PageRenderTime 121ms CodeModel.GetById 14ms app.highlight 94ms RepoModel.GetById 2ms app.codeStats 0ms

/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

http://github.com/mirrors/linux
C | 2667 lines | 1663 code | 380 blank | 624 comment | 411 complexity | 402331e6976d95843b194b1978bfb596 MD5 | raw file

Large files files are truncated, but you can click here to view the full file

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4#include <linux/pci.h>
   5#include <linux/delay.h>
   6#include <linux/iopoll.h>
   7#include <linux/sched.h>
   8
   9#include "ixgbe.h"
  10#include "ixgbe_phy.h"
  11
  12static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  13static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  14static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  15static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  16static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  17static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  18static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  19static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  20static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  21static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  22static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  23static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  24static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  25static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  26static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
  27
  28/**
  29 *  ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  30 *  @hw: pointer to the hardware structure
  31 *  @byte: byte to send
  32 *
  33 *  Returns an error code on error.
  34 **/
  35static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  36{
  37	s32 status;
  38
  39	status = ixgbe_clock_out_i2c_byte(hw, byte);
  40	if (status)
  41		return status;
  42	return ixgbe_get_i2c_ack(hw);
  43}
  44
  45/**
  46 *  ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  47 *  @hw: pointer to the hardware structure
  48 *  @byte: pointer to a u8 to receive the byte
  49 *
  50 *  Returns an error code on error.
  51 **/
  52static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  53{
  54	s32 status;
  55
  56	status = ixgbe_clock_in_i2c_byte(hw, byte);
  57	if (status)
  58		return status;
  59	/* ACK */
  60	return ixgbe_clock_out_i2c_bit(hw, false);
  61}
  62
  63/**
  64 *  ixgbe_ones_comp_byte_add - Perform one's complement addition
  65 *  @add1: addend 1
  66 *  @add2: addend 2
  67 *
  68 *  Returns one's complement 8-bit sum.
  69 **/
  70static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  71{
  72	u16 sum = add1 + add2;
  73
  74	sum = (sum & 0xFF) + (sum >> 8);
  75	return sum & 0xFF;
  76}
  77
  78/**
  79 *  ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
  80 *  @hw: pointer to the hardware structure
  81 *  @addr: I2C bus address to read from
  82 *  @reg: I2C device register to read from
  83 *  @val: pointer to location to receive read value
  84 *  @lock: true if to take and release semaphore
  85 *
  86 *  Returns an error code on error.
  87 */
  88s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
  89					u16 reg, u16 *val, bool lock)
  90{
  91	u32 swfw_mask = hw->phy.phy_semaphore_mask;
  92	int max_retry = 3;
  93	int retry = 0;
  94	u8 csum_byte;
  95	u8 high_bits;
  96	u8 low_bits;
  97	u8 reg_high;
  98	u8 csum;
  99
 100	reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 101	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 102	csum = ~csum;
 103	do {
 104		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 105			return IXGBE_ERR_SWFW_SYNC;
 106		ixgbe_i2c_start(hw);
 107		/* Device Address and write indication */
 108		if (ixgbe_out_i2c_byte_ack(hw, addr))
 109			goto fail;
 110		/* Write bits 14:8 */
 111		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 112			goto fail;
 113		/* Write bits 7:0 */
 114		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 115			goto fail;
 116		/* Write csum */
 117		if (ixgbe_out_i2c_byte_ack(hw, csum))
 118			goto fail;
 119		/* Re-start condition */
 120		ixgbe_i2c_start(hw);
 121		/* Device Address and read indication */
 122		if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 123			goto fail;
 124		/* Get upper bits */
 125		if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 126			goto fail;
 127		/* Get low bits */
 128		if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 129			goto fail;
 130		/* Get csum */
 131		if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 132			goto fail;
 133		/* NACK */
 134		if (ixgbe_clock_out_i2c_bit(hw, false))
 135			goto fail;
 136		ixgbe_i2c_stop(hw);
 137		if (lock)
 138			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 139		*val = (high_bits << 8) | low_bits;
 140		return 0;
 141
 142fail:
 143		ixgbe_i2c_bus_clear(hw);
 144		if (lock)
 145			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 146		retry++;
 147		if (retry < max_retry)
 148			hw_dbg(hw, "I2C byte read combined error - Retry.\n");
 149		else
 150			hw_dbg(hw, "I2C byte read combined error.\n");
 151	} while (retry < max_retry);
 152
 153	return IXGBE_ERR_I2C;
 154}
 155
 156/**
 157 *  ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 158 *  @hw: pointer to the hardware structure
 159 *  @addr: I2C bus address to write to
 160 *  @reg: I2C device register to write to
 161 *  @val: value to write
 162 *  @lock: true if to take and release semaphore
 163 *
 164 *  Returns an error code on error.
 165 */
 166s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 167					 u16 reg, u16 val, bool lock)
 168{
 169	u32 swfw_mask = hw->phy.phy_semaphore_mask;
 170	int max_retry = 1;
 171	int retry = 0;
 172	u8 reg_high;
 173	u8 csum;
 174
 175	reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 176	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 177	csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 178	csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 179	csum = ~csum;
 180	do {
 181		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 182			return IXGBE_ERR_SWFW_SYNC;
 183		ixgbe_i2c_start(hw);
 184		/* Device Address and write indication */
 185		if (ixgbe_out_i2c_byte_ack(hw, addr))
 186			goto fail;
 187		/* Write bits 14:8 */
 188		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 189			goto fail;
 190		/* Write bits 7:0 */
 191		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 192			goto fail;
 193		/* Write data 15:8 */
 194		if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 195			goto fail;
 196		/* Write data 7:0 */
 197		if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 198			goto fail;
 199		/* Write csum */
 200		if (ixgbe_out_i2c_byte_ack(hw, csum))
 201			goto fail;
 202		ixgbe_i2c_stop(hw);
 203		if (lock)
 204			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 205		return 0;
 206
 207fail:
 208		ixgbe_i2c_bus_clear(hw);
 209		if (lock)
 210			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 211		retry++;
 212		if (retry < max_retry)
 213			hw_dbg(hw, "I2C byte write combined error - Retry.\n");
 214		else
 215			hw_dbg(hw, "I2C byte write combined error.\n");
 216	} while (retry < max_retry);
 217
 218	return IXGBE_ERR_I2C;
 219}
 220
 221/**
 222 *  ixgbe_probe_phy - Probe a single address for a PHY
 223 *  @hw: pointer to hardware structure
 224 *  @phy_addr: PHY address to probe
 225 *
 226 *  Returns true if PHY found
 227 **/
 228static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 229{
 230	u16 ext_ability = 0;
 231
 232	hw->phy.mdio.prtad = phy_addr;
 233	if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
 234		return false;
 235
 236	if (ixgbe_get_phy_id(hw))
 237		return false;
 238
 239	hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 240
 241	if (hw->phy.type == ixgbe_phy_unknown) {
 242		hw->phy.ops.read_reg(hw,
 243				     MDIO_PMA_EXTABLE,
 244				     MDIO_MMD_PMAPMD,
 245				     &ext_ability);
 246		if (ext_ability &
 247		    (MDIO_PMA_EXTABLE_10GBT |
 248		     MDIO_PMA_EXTABLE_1000BT))
 249			hw->phy.type = ixgbe_phy_cu_unknown;
 250		else
 251			hw->phy.type = ixgbe_phy_generic;
 252	}
 253
 254	return true;
 255}
 256
 257/**
 258 *  ixgbe_identify_phy_generic - Get physical layer module
 259 *  @hw: pointer to hardware structure
 260 *
 261 *  Determines the physical layer module found on the current adapter.
 262 **/
 263s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 264{
 265	u32 phy_addr;
 266	u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 267
 268	if (!hw->phy.phy_semaphore_mask) {
 269		if (hw->bus.lan_id)
 270			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 271		else
 272			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 273	}
 274
 275	if (hw->phy.type != ixgbe_phy_unknown)
 276		return 0;
 277
 278	if (hw->phy.nw_mng_if_sel) {
 279		phy_addr = (hw->phy.nw_mng_if_sel &
 280			    IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 281			   IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 282		if (ixgbe_probe_phy(hw, phy_addr))
 283			return 0;
 284		else
 285			return IXGBE_ERR_PHY_ADDR_INVALID;
 286	}
 287
 288	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 289		if (ixgbe_probe_phy(hw, phy_addr)) {
 290			status = 0;
 291			break;
 292		}
 293	}
 294
 295	/* Certain media types do not have a phy so an address will not
 296	 * be found and the code will take this path.  Caller has to
 297	 * decide if it is an error or not.
 298	 */
 299	if (status)
 300		hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
 301
 302	return status;
 303}
 304
 305/**
 306 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 307 * @hw: pointer to the hardware structure
 308 *
 309 * This function checks the MMNGC.MNG_VETO bit to see if there are
 310 * any constraints on link from manageability.  For MAC's that don't
 311 * have this bit just return false since the link can not be blocked
 312 * via this method.
 313 **/
 314bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 315{
 316	u32 mmngc;
 317
 318	/* If we don't have this bit, it can't be blocking */
 319	if (hw->mac.type == ixgbe_mac_82598EB)
 320		return false;
 321
 322	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 323	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 324		hw_dbg(hw, "MNG_VETO bit detected.\n");
 325		return true;
 326	}
 327
 328	return false;
 329}
 330
 331/**
 332 *  ixgbe_get_phy_id - Get the phy type
 333 *  @hw: pointer to hardware structure
 334 *
 335 **/
 336static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 337{
 338	s32 status;
 339	u16 phy_id_high = 0;
 340	u16 phy_id_low = 0;
 341
 342	status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 343				      &phy_id_high);
 344
 345	if (!status) {
 346		hw->phy.id = (u32)(phy_id_high << 16);
 347		status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 348					      &phy_id_low);
 349		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 350		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 351	}
 352	return status;
 353}
 354
 355/**
 356 *  ixgbe_get_phy_type_from_id - Get the phy type
 357 *  @phy_id: hardware phy id
 358 *
 359 **/
 360static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 361{
 362	enum ixgbe_phy_type phy_type;
 363
 364	switch (phy_id) {
 365	case TN1010_PHY_ID:
 366		phy_type = ixgbe_phy_tn;
 367		break;
 368	case X550_PHY_ID2:
 369	case X550_PHY_ID3:
 370	case X540_PHY_ID:
 371		phy_type = ixgbe_phy_aq;
 372		break;
 373	case QT2022_PHY_ID:
 374		phy_type = ixgbe_phy_qt;
 375		break;
 376	case ATH_PHY_ID:
 377		phy_type = ixgbe_phy_nl;
 378		break;
 379	case X557_PHY_ID:
 380	case X557_PHY_ID2:
 381		phy_type = ixgbe_phy_x550em_ext_t;
 382		break;
 383	default:
 384		phy_type = ixgbe_phy_unknown;
 385		break;
 386	}
 387
 388	return phy_type;
 389}
 390
 391/**
 392 *  ixgbe_reset_phy_generic - Performs a PHY reset
 393 *  @hw: pointer to hardware structure
 394 **/
 395s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 396{
 397	u32 i;
 398	u16 ctrl = 0;
 399	s32 status = 0;
 400
 401	if (hw->phy.type == ixgbe_phy_unknown)
 402		status = ixgbe_identify_phy_generic(hw);
 403
 404	if (status != 0 || hw->phy.type == ixgbe_phy_none)
 405		return status;
 406
 407	/* Don't reset PHY if it's shut down due to overtemp. */
 408	if (!hw->phy.reset_if_overtemp &&
 409	    (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 410		return 0;
 411
 412	/* Blocked by MNG FW so bail */
 413	if (ixgbe_check_reset_blocked(hw))
 414		return 0;
 415
 416	/*
 417	 * Perform soft PHY reset to the PHY_XS.
 418	 * This will cause a soft reset to the PHY
 419	 */
 420	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 421			      MDIO_MMD_PHYXS,
 422			      MDIO_CTRL1_RESET);
 423
 424	/*
 425	 * Poll for reset bit to self-clear indicating reset is complete.
 426	 * Some PHYs could take up to 3 seconds to complete and need about
 427	 * 1.7 usec delay after the reset is complete.
 428	 */
 429	for (i = 0; i < 30; i++) {
 430		msleep(100);
 431		if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 432			status = hw->phy.ops.read_reg(hw,
 433						  IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 434						  MDIO_MMD_PMAPMD, &ctrl);
 435			if (status)
 436				return status;
 437
 438			if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 439				udelay(2);
 440				break;
 441			}
 442		} else {
 443			status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 444						      MDIO_MMD_PHYXS, &ctrl);
 445			if (status)
 446				return status;
 447
 448			if (!(ctrl & MDIO_CTRL1_RESET)) {
 449				udelay(2);
 450				break;
 451			}
 452		}
 453	}
 454
 455	if (ctrl & MDIO_CTRL1_RESET) {
 456		hw_dbg(hw, "PHY reset polling failed to complete.\n");
 457		return IXGBE_ERR_RESET_FAILED;
 458	}
 459
 460	return 0;
 461}
 462
 463/**
 464 *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 465 *  the SWFW lock
 466 *  @hw: pointer to hardware structure
 467 *  @reg_addr: 32 bit address of PHY register to read
 468 *  @device_type: 5 bit device type
 469 *  @phy_data: Pointer to read data from PHY register
 470 **/
 471s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 472		       u16 *phy_data)
 473{
 474	u32 i, data, command;
 475
 476	/* Setup and write the address cycle command */
 477	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 478		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 479		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 480		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 481
 482	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 483
 484	/* Check every 10 usec to see if the address cycle completed.
 485	 * The MDI Command bit will clear when the operation is
 486	 * complete
 487	 */
 488	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 489		udelay(10);
 490
 491		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 492		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 493				break;
 494	}
 495
 496
 497	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 498		hw_dbg(hw, "PHY address command did not complete.\n");
 499		return IXGBE_ERR_PHY;
 500	}
 501
 502	/* Address cycle complete, setup and write the read
 503	 * command
 504	 */
 505	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 506		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 507		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 508		   (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 509
 510	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 511
 512	/* Check every 10 usec to see if the address cycle
 513	 * completed. The MDI Command bit will clear when the
 514	 * operation is complete
 515	 */
 516	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 517		udelay(10);
 518
 519		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 520		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 521			break;
 522	}
 523
 524	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 525		hw_dbg(hw, "PHY read command didn't complete\n");
 526		return IXGBE_ERR_PHY;
 527	}
 528
 529	/* Read operation is complete.  Get the data
 530	 * from MSRWD
 531	 */
 532	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 533	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 534	*phy_data = (u16)(data);
 535
 536	return 0;
 537}
 538
 539/**
 540 *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 541 *  using the SWFW lock - this function is needed in most cases
 542 *  @hw: pointer to hardware structure
 543 *  @reg_addr: 32 bit address of PHY register to read
 544 *  @device_type: 5 bit device type
 545 *  @phy_data: Pointer to read data from PHY register
 546 **/
 547s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 548			       u32 device_type, u16 *phy_data)
 549{
 550	s32 status;
 551	u32 gssr = hw->phy.phy_semaphore_mask;
 552
 553	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 554		status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 555						phy_data);
 556		hw->mac.ops.release_swfw_sync(hw, gssr);
 557	} else {
 558		return IXGBE_ERR_SWFW_SYNC;
 559	}
 560
 561	return status;
 562}
 563
 564/**
 565 *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 566 *  without SWFW lock
 567 *  @hw: pointer to hardware structure
 568 *  @reg_addr: 32 bit PHY register to write
 569 *  @device_type: 5 bit device type
 570 *  @phy_data: Data to write to the PHY register
 571 **/
 572s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 573				u32 device_type, u16 phy_data)
 574{
 575	u32 i, command;
 576
 577	/* Put the data in the MDI single read and write data register*/
 578	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 579
 580	/* Setup and write the address cycle command */
 581	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 582		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 583		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 584		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 585
 586	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 587
 588	/*
 589	 * Check every 10 usec to see if the address cycle completed.
 590	 * The MDI Command bit will clear when the operation is
 591	 * complete
 592	 */
 593	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 594		udelay(10);
 595
 596		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 597		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 598			break;
 599	}
 600
 601	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 602		hw_dbg(hw, "PHY address cmd didn't complete\n");
 603		return IXGBE_ERR_PHY;
 604	}
 605
 606	/*
 607	 * Address cycle complete, setup and write the write
 608	 * command
 609	 */
 610	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 611		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 612		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 613		   (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 614
 615	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 616
 617	/* Check every 10 usec to see if the address cycle
 618	 * completed. The MDI Command bit will clear when the
 619	 * operation is complete
 620	 */
 621	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 622		udelay(10);
 623
 624		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 625		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 626			break;
 627	}
 628
 629	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 630		hw_dbg(hw, "PHY write cmd didn't complete\n");
 631		return IXGBE_ERR_PHY;
 632	}
 633
 634	return 0;
 635}
 636
 637/**
 638 *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 639 *  using SWFW lock- this function is needed in most cases
 640 *  @hw: pointer to hardware structure
 641 *  @reg_addr: 32 bit PHY register to write
 642 *  @device_type: 5 bit device type
 643 *  @phy_data: Data to write to the PHY register
 644 **/
 645s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 646				u32 device_type, u16 phy_data)
 647{
 648	s32 status;
 649	u32 gssr = hw->phy.phy_semaphore_mask;
 650
 651	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 652		status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 653						 phy_data);
 654		hw->mac.ops.release_swfw_sync(hw, gssr);
 655	} else {
 656		return IXGBE_ERR_SWFW_SYNC;
 657	}
 658
 659	return status;
 660}
 661
 662#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
 663
 664/**
 665 *  ixgbe_msca_cmd - Write the command register and poll for completion/timeout
 666 *  @hw: pointer to hardware structure
 667 *  @cmd: command register value to write
 668 **/
 669static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
 670{
 671	IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
 672
 673	return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
 674				  !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
 675				  10 * IXGBE_MDIO_COMMAND_TIMEOUT);
 676}
 677
 678/**
 679 *  ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags
 680 *  @hw: pointer to hardware structure
 681 *  @addr: address
 682 *  @regnum: register number
 683 *  @gssr: semaphore flags to acquire
 684 **/
 685static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,
 686				      int regnum, u32 gssr)
 687{
 688	u32 hwaddr, cmd;
 689	s32 data;
 690
 691	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 692		return -EBUSY;
 693
 694	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
 695	if (regnum & MII_ADDR_C45) {
 696		hwaddr |= regnum & GENMASK(21, 0);
 697		cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
 698	} else {
 699		hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
 700		cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
 701			IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
 702	}
 703
 704	data = ixgbe_msca_cmd(hw, cmd);
 705	if (data < 0)
 706		goto mii_bus_read_done;
 707
 708	/* For a clause 45 access the address cycle just completed, we still
 709	 * need to do the read command, otherwise just get the data
 710	 */
 711	if (!(regnum & MII_ADDR_C45))
 712		goto do_mii_bus_read;
 713
 714	cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
 715	data = ixgbe_msca_cmd(hw, cmd);
 716	if (data < 0)
 717		goto mii_bus_read_done;
 718
 719do_mii_bus_read:
 720	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 721	data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
 722
 723mii_bus_read_done:
 724	hw->mac.ops.release_swfw_sync(hw, gssr);
 725	return data;
 726}
 727
 728/**
 729 *  ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags
 730 *  @hw: pointer to hardware structure
 731 *  @addr: address
 732 *  @regnum: register number
 733 *  @val: value to write
 734 *  @gssr: semaphore flags to acquire
 735 **/
 736static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,
 737				       int regnum, u16 val, u32 gssr)
 738{
 739	u32 hwaddr, cmd;
 740	s32 err;
 741
 742	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 743		return -EBUSY;
 744
 745	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
 746
 747	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
 748	if (regnum & MII_ADDR_C45) {
 749		hwaddr |= regnum & GENMASK(21, 0);
 750		cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
 751	} else {
 752		hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
 753		cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 754			IXGBE_MSCA_MDI_COMMAND;
 755	}
 756
 757	/* For clause 45 this is an address cycle, for clause 22 this is the
 758	 * entire transaction
 759	 */
 760	err = ixgbe_msca_cmd(hw, cmd);
 761	if (err < 0 || !(regnum & MII_ADDR_C45))
 762		goto mii_bus_write_done;
 763
 764	cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
 765	err = ixgbe_msca_cmd(hw, cmd);
 766
 767mii_bus_write_done:
 768	hw->mac.ops.release_swfw_sync(hw, gssr);
 769	return err;
 770}
 771
 772/**
 773 *  ixgbe_mii_bus_read - Read a clause 22/45 register
 774 *  @hw: pointer to hardware structure
 775 *  @addr: address
 776 *  @regnum: register number
 777 **/
 778static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
 779{
 780	struct ixgbe_adapter *adapter = bus->priv;
 781	struct ixgbe_hw *hw = &adapter->hw;
 782	u32 gssr = hw->phy.phy_semaphore_mask;
 783
 784	return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
 785}
 786
 787/**
 788 *  ixgbe_mii_bus_write - Write a clause 22/45 register
 789 *  @hw: pointer to hardware structure
 790 *  @addr: address
 791 *  @regnum: register number
 792 *  @val: value to write
 793 **/
 794static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,
 795			       u16 val)
 796{
 797	struct ixgbe_adapter *adapter = bus->priv;
 798	struct ixgbe_hw *hw = &adapter->hw;
 799	u32 gssr = hw->phy.phy_semaphore_mask;
 800
 801	return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
 802}
 803
 804/**
 805 *  ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a
 806 *  @hw: pointer to hardware structure
 807 *  @addr: address
 808 *  @regnum: register number
 809 **/
 810static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,
 811				       int regnum)
 812{
 813	struct ixgbe_adapter *adapter = bus->priv;
 814	struct ixgbe_hw *hw = &adapter->hw;
 815	u32 gssr = hw->phy.phy_semaphore_mask;
 816
 817	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
 818	return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
 819}
 820
 821/**
 822 *  ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a
 823 *  @hw: pointer to hardware structure
 824 *  @addr: address
 825 *  @regnum: register number
 826 *  @val: value to write
 827 **/
 828static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,
 829					int regnum, u16 val)
 830{
 831	struct ixgbe_adapter *adapter = bus->priv;
 832	struct ixgbe_hw *hw = &adapter->hw;
 833	u32 gssr = hw->phy.phy_semaphore_mask;
 834
 835	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
 836	return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
 837}
 838
 839/**
 840 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
 841 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
 842 *
 843 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
 844 * on domain 0, bus 0, devfn = 'devfn'
 845 **/
 846static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
 847{
 848	struct pci_dev *rp_pdev;
 849	int bus;
 850
 851	rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
 852	if (rp_pdev && rp_pdev->subordinate) {
 853		bus = rp_pdev->subordinate->number;
 854		return pci_get_domain_bus_and_slot(0, bus, 0);
 855	}
 856
 857	return NULL;
 858}
 859
 860/**
 861 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
 862 * @hw: pointer to hardware structure
 863 *
 864 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
 865 * the SoC.  There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
 866 * but we only want to register one MDIO bus.
 867 **/
 868static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
 869{
 870	struct ixgbe_adapter *adapter = hw->back;
 871	struct pci_dev *pdev = adapter->pdev;
 872	struct pci_dev *func0_pdev;
 873
 874	/* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
 875	 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
 876	 * It's not valid for function 0 to be disabled and function 1 is up,
 877	 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
 878	 * of those two root ports
 879	 */
 880	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
 881	if (func0_pdev) {
 882		if (func0_pdev == pdev)
 883			return true;
 884		else
 885			return false;
 886	}
 887	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
 888	if (func0_pdev == pdev)
 889		return true;
 890
 891	return false;
 892}
 893
 894/**
 895 * ixgbe_mii_bus_init - mii_bus structure setup
 896 * @hw: pointer to hardware structure
 897 *
 898 * Returns 0 on success, negative on failure
 899 *
 900 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
 901 **/
 902s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
 903{
 904	struct ixgbe_adapter *adapter = hw->back;
 905	struct pci_dev *pdev = adapter->pdev;
 906	struct device *dev = &adapter->netdev->dev;
 907	struct mii_bus *bus;
 908	int err = -ENODEV;
 909
 910	bus = devm_mdiobus_alloc(dev);
 911	if (!bus)
 912		return -ENOMEM;
 913
 914	switch (hw->device_id) {
 915	/* C3000 SoCs */
 916	case IXGBE_DEV_ID_X550EM_A_KR:
 917	case IXGBE_DEV_ID_X550EM_A_KR_L:
 918	case IXGBE_DEV_ID_X550EM_A_SFP_N:
 919	case IXGBE_DEV_ID_X550EM_A_SGMII:
 920	case IXGBE_DEV_ID_X550EM_A_SGMII_L:
 921	case IXGBE_DEV_ID_X550EM_A_10G_T:
 922	case IXGBE_DEV_ID_X550EM_A_SFP:
 923	case IXGBE_DEV_ID_X550EM_A_1G_T:
 924	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 925		if (!ixgbe_x550em_a_has_mii(hw))
 926			goto ixgbe_no_mii_bus;
 927		bus->read = &ixgbe_x550em_a_mii_bus_read;
 928		bus->write = &ixgbe_x550em_a_mii_bus_write;
 929		break;
 930	default:
 931		bus->read = &ixgbe_mii_bus_read;
 932		bus->write = &ixgbe_mii_bus_write;
 933		break;
 934	}
 935
 936	/* Use the position of the device in the PCI hierarchy as the id */
 937	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
 938		 pci_name(pdev));
 939
 940	bus->name = "ixgbe-mdio";
 941	bus->priv = adapter;
 942	bus->parent = dev;
 943	bus->phy_mask = GENMASK(31, 0);
 944
 945	/* Support clause 22/45 natively.  ixgbe_probe() sets MDIO_EMULATE_C22
 946	 * unfortunately that causes some clause 22 frames to be sent with
 947	 * clause 45 addressing.  We don't want that.
 948	 */
 949	hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
 950
 951	err = mdiobus_register(bus);
 952	if (!err) {
 953		adapter->mii_bus = bus;
 954		return 0;
 955	}
 956
 957ixgbe_no_mii_bus:
 958	devm_mdiobus_free(dev, bus);
 959	return err;
 960}
 961
 962/**
 963 *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 964 *  @hw: pointer to hardware structure
 965 *
 966 *  Restart autonegotiation and PHY and waits for completion.
 967 **/
 968s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 969{
 970	s32 status = 0;
 971	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 972	bool autoneg = false;
 973	ixgbe_link_speed speed;
 974
 975	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 976
 977	/* Set or unset auto-negotiation 10G advertisement */
 978	hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
 979
 980	autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 981	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 982	    (speed & IXGBE_LINK_SPEED_10GB_FULL))
 983		autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 984
 985	hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
 986
 987	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 988			     MDIO_MMD_AN, &autoneg_reg);
 989
 990	if (hw->mac.type == ixgbe_mac_X550) {
 991		/* Set or unset auto-negotiation 5G advertisement */
 992		autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 993		if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 994		    (speed & IXGBE_LINK_SPEED_5GB_FULL))
 995			autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 996
 997		/* Set or unset auto-negotiation 2.5G advertisement */
 998		autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 999		if ((hw->phy.autoneg_advertised &
1000		     IXGBE_LINK_SPEED_2_5GB_FULL) &&
1001		    (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1002			autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1003	}
1004
1005	/* Set or unset auto-negotiation 1G advertisement */
1006	autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1007	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1008	    (speed & IXGBE_LINK_SPEED_1GB_FULL))
1009		autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1010
1011	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1012			      MDIO_MMD_AN, autoneg_reg);
1013
1014	/* Set or unset auto-negotiation 100M advertisement */
1015	hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1016
1017	autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1018	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1019	    (speed & IXGBE_LINK_SPEED_100_FULL))
1020		autoneg_reg |= ADVERTISE_100FULL;
1021
1022	hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1023
1024	/* Blocked by MNG FW so don't reset PHY */
1025	if (ixgbe_check_reset_blocked(hw))
1026		return 0;
1027
1028	/* Restart PHY autonegotiation and wait for completion */
1029	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1030			     MDIO_MMD_AN, &autoneg_reg);
1031
1032	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1033
1034	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1035			      MDIO_MMD_AN, autoneg_reg);
1036
1037	return status;
1038}
1039
1040/**
1041 *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1042 *  @hw: pointer to hardware structure
1043 *  @speed: new link speed
1044 *  @autoneg_wait_to_complete: unused
1045 **/
1046s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1047				       ixgbe_link_speed speed,
1048				       bool autoneg_wait_to_complete)
1049{
1050	/* Clear autoneg_advertised and set new values based on input link
1051	 * speed.
1052	 */
1053	hw->phy.autoneg_advertised = 0;
1054
1055	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1056		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1057
1058	if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1059		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1060
1061	if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1062		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1063
1064	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1065		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1066
1067	if (speed & IXGBE_LINK_SPEED_100_FULL)
1068		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1069
1070	if (speed & IXGBE_LINK_SPEED_10_FULL)
1071		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1072
1073	/* Setup link based on the new speed settings */
1074	if (hw->phy.ops.setup_link)
1075		hw->phy.ops.setup_link(hw);
1076
1077	return 0;
1078}
1079
1080/**
1081 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1082 * @hw: pointer to hardware structure
1083 *
1084 * Determines the supported link capabilities by reading the PHY auto
1085 * negotiation register.
1086 */
1087static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1088{
1089	u16 speed_ability;
1090	s32 status;
1091
1092	status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1093				      &speed_ability);
1094	if (status)
1095		return status;
1096
1097	if (speed_ability & MDIO_SPEED_10G)
1098		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1099	if (speed_ability & MDIO_PMA_SPEED_1000)
1100		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1101	if (speed_ability & MDIO_PMA_SPEED_100)
1102		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1103
1104	switch (hw->mac.type) {
1105	case ixgbe_mac_X550:
1106		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1107		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1108		break;
1109	case ixgbe_mac_X550EM_x:
1110	case ixgbe_mac_x550em_a:
1111		hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1112		break;
1113	default:
1114		break;
1115	}
1116
1117	return 0;
1118}
1119
1120/**
1121 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1122 * @hw: pointer to hardware structure
1123 * @speed: pointer to link speed
1124 * @autoneg: boolean auto-negotiation value
1125 */
1126s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1127					       ixgbe_link_speed *speed,
1128					       bool *autoneg)
1129{
1130	s32 status = 0;
1131
1132	*autoneg = true;
1133	if (!hw->phy.speeds_supported)
1134		status = ixgbe_get_copper_speeds_supported(hw);
1135
1136	*speed = hw->phy.speeds_supported;
1137	return status;
1138}
1139
1140/**
1141 *  ixgbe_check_phy_link_tnx - Determine link and speed status
1142 *  @hw: pointer to hardware structure
1143 *  @speed: link speed
1144 *  @link_up: status of link
1145 *
1146 *  Reads the VS1 register to determine if link is up and the current speed for
1147 *  the PHY.
1148 **/
1149s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1150			     bool *link_up)
1151{
1152	s32 status;
1153	u32 time_out;
1154	u32 max_time_out = 10;
1155	u16 phy_link = 0;
1156	u16 phy_speed = 0;
1157	u16 phy_data = 0;
1158
1159	/* Initialize speed and link to default case */
1160	*link_up = false;
1161	*speed = IXGBE_LINK_SPEED_10GB_FULL;
1162
1163	/*
1164	 * Check current speed and link status of the PHY register.
1165	 * This is a vendor specific register and may have to
1166	 * be changed for other copper PHYs.
1167	 */
1168	for (time_out = 0; time_out < max_time_out; time_out++) {
1169		udelay(10);
1170		status = hw->phy.ops.read_reg(hw,
1171					      MDIO_STAT1,
1172					      MDIO_MMD_VEND1,
1173					      &phy_data);
1174		phy_link = phy_data &
1175			    IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1176		phy_speed = phy_data &
1177			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1178		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1179			*link_up = true;
1180			if (phy_speed ==
1181			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1182				*speed = IXGBE_LINK_SPEED_1GB_FULL;
1183			break;
1184		}
1185	}
1186
1187	return status;
1188}
1189
1190/**
1191 *	ixgbe_setup_phy_link_tnx - Set and restart autoneg
1192 *	@hw: pointer to hardware structure
1193 *
1194 *	Restart autonegotiation and PHY and waits for completion.
1195 *      This function always returns success, this is nessary since
1196 *	it is called via a function pointer that could call other
1197 *	functions that could return an error.
1198 **/
1199s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1200{
1201	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1202	bool autoneg = false;
1203	ixgbe_link_speed speed;
1204
1205	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1206
1207	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1208		/* Set or unset auto-negotiation 10G advertisement */
1209		hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1210				     MDIO_MMD_AN,
1211				     &autoneg_reg);
1212
1213		autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1214		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1215			autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1216
1217		hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1218				      MDIO_MMD_AN,
1219				      autoneg_reg);
1220	}
1221
1222	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1223		/* Set or unset auto-negotiation 1G advertisement */
1224		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1225				     MDIO_MMD_AN,
1226				     &autoneg_reg);
1227
1228		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1229		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1230			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1231
1232		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1233				      MDIO_MMD_AN,
1234				      autoneg_reg);
1235	}
1236
1237	if (speed & IXGBE_LINK_SPEED_100_FULL) {
1238		/* Set or unset auto-negotiation 100M advertisement */
1239		hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1240				     MDIO_MMD_AN,
1241				     &autoneg_reg);
1242
1243		autoneg_reg &= ~(ADVERTISE_100FULL |
1244				 ADVERTISE_100HALF);
1245		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1246			autoneg_reg |= ADVERTISE_100FULL;
1247
1248		hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1249				      MDIO_MMD_AN,
1250				      autoneg_reg);
1251	}
1252
1253	/* Blocked by MNG FW so don't reset PHY */
1254	if (ixgbe_check_reset_blocked(hw))
1255		return 0;
1256
1257	/* Restart PHY autonegotiation and wait for completion */
1258	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1259			     MDIO_MMD_AN, &autoneg_reg);
1260
1261	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1262
1263	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1264			      MDIO_MMD_AN, autoneg_reg);
1265	return 0;
1266}
1267
1268/**
1269 *  ixgbe_reset_phy_nl - Performs a PHY reset
1270 *  @hw: pointer to hardware structure
1271 **/
1272s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1273{
1274	u16 phy_offset, control, eword, edata, block_crc;
1275	bool end_data = false;
1276	u16 list_offset, data_offset;
1277	u16 phy_data = 0;
1278	s32 ret_val;
1279	u32 i;
1280
1281	/* Blocked by MNG FW so bail */
1282	if (ixgbe_check_reset_blocked(hw))
1283		return 0;
1284
1285	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1286
1287	/* reset the PHY and poll for completion */
1288	hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1289			      (phy_data | MDIO_CTRL1_RESET));
1290
1291	for (i = 0; i < 100; i++) {
1292		hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1293				     &phy_data);
1294		if ((phy_data & MDIO_CTRL1_RESET) == 0)
1295			break;
1296		usleep_range(10000, 20000);
1297	}
1298
1299	if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1300		hw_dbg(hw, "PHY reset did not complete.\n");
1301		return IXGBE_ERR_PHY;
1302	}
1303
1304	/* Get init offsets */
1305	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1306						      &data_offset);
1307	if (ret_val)
1308		return ret_val;
1309
1310	ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1311	data_offset++;
1312	while (!end_data) {
1313		/*
1314		 * Read control word from PHY init contents offset
1315		 */
1316		ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1317		if (ret_val)
1318			goto err_eeprom;
1319		control = (eword & IXGBE_CONTROL_MASK_NL) >>
1320			   IXGBE_CONTROL_SHIFT_NL;
1321		edata = eword & IXGBE_DATA_MASK_NL;
1322		switch (control) {
1323		case IXGBE_DELAY_NL:
1324			data_offset++;
1325			hw_dbg(hw, "DELAY: %d MS\n", edata);
1326			usleep_range(edata * 1000, edata * 2000);
1327			break;
1328		case IXGBE_DATA_NL:
1329			hw_dbg(hw, "DATA:\n");
1330			data_offset++;
1331			ret_val = hw->eeprom.ops.read(hw, data_offset++,
1332						      &phy_offset);
1333			if (ret_val)
1334				goto err_eeprom;
1335			for (i = 0; i < edata; i++) {
1336				ret_val = hw->eeprom.ops.read(hw, data_offset,
1337							      &eword);
1338				if (ret_val)
1339					goto err_eeprom;
1340				hw->phy.ops.write_reg(hw, phy_offset,
1341						      MDIO_MMD_PMAPMD, eword);
1342				hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1343				       phy_offset);
1344				data_offset++;
1345				phy_offset++;
1346			}
1347			break;
1348		case IXGBE_CONTROL_NL:
1349			data_offset++;
1350			hw_dbg(hw, "CONTROL:\n");
1351			if (edata == IXGBE_CONTROL_EOL_NL) {
1352				hw_dbg(hw, "EOL\n");
1353				end_data = true;
1354			} else if (edata == IXGBE_CONTROL_SOL_NL) {
1355				hw_dbg(hw, "SOL\n");
1356			} else {
1357				hw_dbg(hw, "Bad control value\n");
1358				return IXGBE_ERR_PHY;
1359			}
1360			break;
1361		default:
1362			hw_dbg(hw, "Bad control type\n");
1363			return IXGBE_ERR_PHY;
1364		}
1365	}
1366
1367	return ret_val;
1368
1369err_eeprom:
1370	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1371	return IXGBE_ERR_PHY;
1372}
1373
1374/**
1375 *  ixgbe_identify_module_generic - Identifies module type
1376 *  @hw: pointer to hardware structure
1377 *
1378 *  Determines HW type and calls appropriate function.
1379 **/
1380s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1381{
1382	switch (hw->mac.ops.get_media_type(hw)) {
1383	case ixgbe_media_type_fiber:
1384		return ixgbe_identify_sfp_module_generic(hw);
1385	case ixgbe_media_type_fiber_qsfp:
1386		return ixgbe_identify_qsfp_module_generic(hw);
1387	default:
1388		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1389		return IXGBE_ERR_SFP_NOT_PRESENT;
1390	}
1391
1392	return IXGBE_ERR_SFP_NOT_PRESENT;
1393}
1394
1395/**
1396 *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1397 *  @hw: pointer to hardware structure
1398 *
1399 *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1400 **/
1401s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1402{
1403	struct ixgbe_adapter *adapter = hw->back;
1404	s32 status;
1405	u32 vendor_oui = 0;
1406	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1407	u8 identifier = 0;
1408	u8 comp_codes_1g = 0;
1409	u8 comp_codes_10g = 0;
1410	u8 oui_bytes[3] = {0, 0, 0};
1411	u8 cable_tech = 0;
1412	u8 cable_spec = 0;
1413	u16 enforce_sfp = 0;
1414
1415	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1416		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1417		return IXGBE_ERR_SFP_NOT_PRESENT;
1418	}
1419
1420	/* LAN ID is needed for sfp_type determination */
1421	hw->mac.ops.set_lan_id(hw);
1422
1423	status = hw->phy.ops.read_i2c_eeprom(hw,
1424					     IXGBE_SFF_IDENTIFIER,
1425					     &identifier);
1426
1427	if (status)
1428		goto err_read_i2c_eeprom;
1429
1430	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1431		hw->phy.type = ixgbe_phy_sfp_unsupported;
1432		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1433	}
1434	status = hw->phy.ops.read_i2c_eeprom(hw,
1435					     IXGBE_SFF_1GBE_COMP_CODES,
1436					     &comp_codes_1g);
1437
1438	if (status)
1439		goto err_read_i2c_eeprom;
1440
1441	status = hw->phy.ops.read_i2c_eeprom(hw,
1442					     IXGBE_SFF_10GBE_COMP_CODES,
1443					     &comp_codes_10g);
1444
1445	if (status)
1446		goto err_read_i2c_eeprom;
1447	status = hw->phy.ops.read_i2c_eeprom(hw,
1448					     IXGBE_SFF_CABLE_TECHNOLOGY,
1449					     &cable_tech);
1450
1451	if (status)
1452		goto err_read_i2c_eeprom;
1453
1454	 /* ID Module
1455	  * =========
1456	  * 0   SFP_DA_CU
1457	  * 1   SFP_SR
1458	  * 2   SFP_LR
1459	  * 3   SFP_DA_CORE0 - 82599-specific
1460	  * 4   SFP_DA_CORE1 - 82599-specific
1461	  * 5   SFP_SR/LR_CORE0 - 82599-specific
1462	  * 6   SFP_SR/LR_CORE1 - 82599-specific
1463	  * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1464	  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1465	  * 9   SFP_1g_cu_CORE0 - 82599-specific
1466	  * 10  SFP_1g_cu_CORE1 - 82599-specific
1467	  * 11  SFP_1g_sx_CORE0 - 82599-specific
1468	  * 12  SFP_1g_sx_CORE1 - 82599-specific
1469	  */
1470	if (hw->mac.type == ixgbe_mac_82598EB) {
1471		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1472			hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1473		else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1474			hw->phy.sfp_type = ixgbe_sfp_type_sr;
1475		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1476			hw->phy.sfp_type = ixgbe_sfp_type_lr;
1477		else
1478			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1479	} else {
1480		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1481			if (hw->bus.lan_id == 0)
1482				hw->phy.sfp_type =
1483					     ixgbe_sfp_type_da_cu_core0;
1484			else
1485				hw->phy.sfp_type =
1486					     ixgbe_sfp_type_da_cu_core1;
1487		} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1488			hw->phy.ops.read_i2c_eeprom(
1489					hw, IXGBE_SFF_CABLE_SPEC_COMP,
1490					&cable_spec);
1491			if (cable_spec &
1492			    IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1493				if (hw->bus.lan_id == 0)
1494					hw->phy.sfp_type =
1495					ixgbe_sfp_type_da_act_lmt_core0;
1496				else
1497					hw->phy.sfp_type =
1498					ixgbe_sfp_type_da_act_lmt_core1;
1499			} else {
1500				hw->phy.sfp_type =
1501						ixgbe_sfp_type_unknown;
1502			}
1503		} else if (comp_codes_10g &
1504			   (IXGBE_SFF_10GBASESR_CAPABLE |
1505			    IXGBE_SFF_10GBASELR_CAPABLE)) {
1506			if (hw->bus.lan_id == 0)
1507				hw->phy.sfp_type =
1508					      ixgbe_sfp_type_srlr_core0;
1509			else
1510				hw->phy.sfp_type =
1511					      ixgbe_sfp_type_srlr_core1;
1512		} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1513			if (hw->bus.lan_id == 0)
1514				hw->phy.sfp_type =
1515					ixgbe_sfp_type_1g_cu_core0;
1516			else
1517				hw->phy.sfp_type =
1518					ixgbe_sfp_type_1g_cu_core1;
1519		} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1520			if (hw->bus.lan_id == 0)
1521				hw->phy.sfp_type =
1522					ixgbe_sfp_type_1g_sx_core0;
1523			else
1524				hw->phy.sfp_type =
1525					ixgbe_sfp_type_1g_sx_core1;
1526		} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1527			if (hw->bus.lan_id == 0)
1528				hw->phy.sfp_type =
1529					ixgbe_sfp_type_1g_lx_core0;
1530			else
1531				hw->phy.sfp_type =
1532					ixgbe_sfp_type_1g_lx_core1;
1533		} else {
1534			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1535		}
1536	}
1537
1538	if (hw->phy.sfp_type != stored_sfp_type)
1539		hw->phy.sfp_setup_needed = true;
1540
1541	/* Determine if the SFP+ PHY is dual speed or not. */
1542	hw->phy.multispeed_fiber = false;
1543	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1544	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1545	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1546	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1547		hw->phy.multispeed_fiber = true;
1548
1549	/* Determine PHY vendor */
1550	if (hw->phy.type != ixgbe_phy_nl) {
1551		hw->phy.id = identifier;
1552		status = hw->phy.ops.read_i2c_eeprom(hw,
1553					    IXGBE_SFF_VENDOR_OUI_BYTE0,
1554					    &oui_bytes[0]);
1555
1556		if (status != 0)
1557			goto err_read_i2c_eeprom;
1558
1559		status = hw->phy.ops.read_i2c_eeprom(hw,
1560					    IXGBE_SFF_VENDOR_OUI_BYTE1,
1561					    &oui_bytes[1]);
1562
1563		if (status != 0)
1564			goto err_read_i2c_eeprom;
1565
1566		status = hw->phy.ops.read_i2c_eeprom(hw,
1567					    IXGBE_SFF_VENDOR_OUI_BYTE2,
1568					    &oui_bytes[2]);
1569
1570		if (status != 0)
1571			goto err_read_i2c_eeprom;
1572
1573		vendor_oui =
1574		  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1575		   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1576		   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1577
1578		switch (vendor_oui) {
1579		case IXGBE_SFF_VENDOR_OUI_TYCO:
1580			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1581				hw->phy.type =
1582					    ixgbe_phy_sfp_passive_tyco;
1583			break;
1584		case IXGBE_SFF_VENDOR_OUI_FTL:
1585			if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1586				hw->phy.type = ixgbe_phy_sfp_ftl_active;
1587			else
1588				hw->phy.type = ixgbe_phy_sfp_ftl;
1589			break;
1590		case IXGBE_SFF_VENDOR_OUI_AVAGO:
1591			hw->phy.type = ixgbe_phy_sfp_avago;
1592			break;
1593		case IXGBE_SFF_VENDOR_OUI_INTEL:
1594			hw->phy.type = ixgbe_phy_sfp_intel;
1595			break;
1596		default:
1597			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1598				hw->phy.type =
1599					 ixgbe_phy_sfp_passive_unknown;
1600			else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1601				hw->phy.type =
1602					ixgbe_phy_sfp_active_unknown;
1603			else
1604				hw->phy.type = ixgbe_phy_sfp_unknown;
1605			break;
1606		}
1607	}
1608
1609	/* Allow any DA cable vendor */
1610	if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1611	    IXGBE_SFF_DA_ACTIVE_CABLE))
1612		return 0;
1613
1614	/* Verify supported 1G SFP modules */
1615	if (comp_codes_10g == 0 &&
1616	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1617	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1618	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1619	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1620	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1621	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1622		hw->phy.type = ixgbe_phy_sfp_unsupported;
1623		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1624	}
1625
1626	/* Anything else 82598-based is supported */
1627	if (hw->mac.type == ixgbe_mac_82598EB)
1628		return 0;
1629
1630	hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1631	if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1632	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1633	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1634	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1635	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1636	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1637	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1638		/* Make sure we're a supported PHY type */
1639		if (hw->phy.type == ixgbe_phy_sfp_intel)
1640			return 0;
1641		if (hw->allow_unsupported_sfp) {
1642			e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1643			return 0;
1644		}
1645		hw_dbg(hw, "SFP+ module not supported\n");
1646		hw->phy.type = ixgbe_phy_sfp_unsupported;
1647		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1648	}
1649	return 0;
1650
1651err_read_i2c_eeprom:
1652	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1653	if (hw->phy.type != ixgbe_phy_nl) {
1654		hw->phy.id = 0;
1655		hw->phy.type = ixgbe_phy_unknown;
1656	}
1657	return IXGBE_ERR_SFP_NOT_PRESENT;
1658}
1659
1660/**
1661 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1662 * @hw: pointer to hardware structure
1663 *
1664 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1665 **/
1666static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1667{
1668	struct ixgbe_adapter *adapter = hw->back;
1669	s32 status;
1670	u32 vendor_oui = 0;
1671	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1672	u8 identifier = 0;
1673	u8 comp_codes_1g = 0;
1674	u8 comp_codes_10g = 0;
1675	u8 oui_bytes[3] = {0, 0, 0};
1676	u16 enforce_sfp = 0;
1677	u8 connector = 0;
1678	u8 cable_length = 0;
1679	u8 device_tech = 0;
1680	bool active_cable = false;
1681
1682	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1683		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1684		return IXGBE_ERR_SFP_NOT_PRESENT;
1685	}
1686
1687	/* LAN ID is needed for sfp_type determination */
1688	hw->mac.ops.set_lan_id(hw);
1689
1690	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1691					     &identifier);
1692
1693	if (status != 0)
1694		goto err_read_i2c_eeprom;
1695
1696	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1697		hw->phy.type = ixgbe_phy_sfp_unsupported;
1698		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1699	}
1700
1701	hw->phy.id = identifier;
1702
1703	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1704					     &comp_codes_10g);
1705
1706	if (status != 0)
1707		goto err_read_i2c_eeprom;
1708
1709	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1710					     &comp_codes_1g);
1711
1712	if (status != 0)
1713		goto err_read_i2c_eeprom;
1714
1715	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1716		hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1717		if (hw->bus.lan_id == 0)
1718			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1719		else
1720			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1721	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1722				     IXGBE_SFF_10GBASELR_CAPABLE)) {
1723		if (hw->bus.lan_id == 0)
1724			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1725		else
1726			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1727	} else {
1728		if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1729			active_cable = true;
1730
1731		if (!active_cable) {
1732			/* check for active DA cables that pre-date
1733			 * SFF-8436 v3.6
1734			 */
1735			hw->phy.ops.read_i2c_eeprom(hw,
1736					IXGBE_SFF_QSFP_CONNECTOR,
1737					&connector);
1738
1739			hw->phy.ops.read_i2c_eeprom(hw,
1740					IXGBE_SFF_QSFP_CABLE_LENGTH,
1741					&cable_length);
1742
1743			hw->phy.ops.read_i2c_eeprom(hw,
1744					IXGBE_SFF_QSFP_DEVICE_TECH,
1745					&device_tech);
1746
1747			if ((connector ==
1748				     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1749			    (cable_length > 0) &&
1750			    ((device_tech >> 4) ==
1751				     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1752				active_cable = true;
1753		}
1754
1755		if (active_cable) {
1756			hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1757			if (hw->bus.lan_id == 0)
1758				hw->phy.sfp_type =
1759						ixgbe_sfp_type_da_act_lmt_core0;
1760			else
1761				hw->phy.sfp_type =
1762						ixgbe_sfp_type_da_act_lmt_core1;
1763		} else {
1764			/* unsupported module type */
1765			hw->phy.type = ixgbe_phy_sfp_unsupported;
1766			return IXGBE_ERR_SFP_NOT_SUPPORTED;
1767		}
1768	}
1769
1770	if (hw->phy.sfp_type != stored_sfp_type)
1771		hw->phy.sfp_setup_needed = true;
1772
1773	/* Determine if the QSFP+ PHY is dual speed or not. */
1774	hw->phy.multispeed_fiber = false;
1775	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1776	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1777	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1778	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1779		hw->phy.multispeed_fiber = true;
1780
1781	/* Determine PHY vendor for optical modules */
1782	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1783			      IXGBE_SFF_10GBASELR_CAPABLE)) {
1784		status = hw->phy.ops.read_i2c_eeprom(hw,
1785					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1786					&oui_bytes[0]);
1787
1788		if (status != 0)
1789			goto err_read_i2c_eeprom;
1790
1791		status = hw->phy.ops.read_i2c_eeprom(hw,
1792					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1793					&oui_bytes[1]);
1794
1795		if (status != 0)
1796			goto err_read_i2c_eeprom;
1797
1798		status = hw->phy.ops.read_i2c_eeprom(hw,
1799					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1800					&oui_bytes[2]);
1801
1802		if (status != 0)
1803			goto err_read_i2c_eeprom;
1804
1805		vendor_oui =
1806			((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1807			 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1808			 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1809
1810		if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1811			hw->phy.type = ixgbe_phy_qsfp_intel;
1812		else
1813			hw->phy.type = ixgbe_phy_qsfp_unknown;
1814
1815

Large files files are truncated, but you can click here to view the full file