/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
C | 3493 lines | 2747 code | 484 blank | 262 comment | 473 complexity | 2cbe1d3a5380fa647ff589f708c87068 MD5 | raw file
Large files files are truncated, but you can click here to view the full file
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4/* ethtool support for ixgbe */ 5 6#include <linux/interrupt.h> 7#include <linux/types.h> 8#include <linux/module.h> 9#include <linux/slab.h> 10#include <linux/pci.h> 11#include <linux/netdevice.h> 12#include <linux/ethtool.h> 13#include <linux/vmalloc.h> 14#include <linux/highmem.h> 15#include <linux/uaccess.h> 16 17#include "ixgbe.h" 18#include "ixgbe_phy.h" 19 20 21#define IXGBE_ALL_RAR_ENTRIES 16 22 23enum {NETDEV_STATS, IXGBE_STATS}; 24 25struct ixgbe_stats { 26 char stat_string[ETH_GSTRING_LEN]; 27 int type; 28 int sizeof_stat; 29 int stat_offset; 30}; 31 32#define IXGBE_STAT(m) IXGBE_STATS, \ 33 sizeof(((struct ixgbe_adapter *)0)->m), \ 34 offsetof(struct ixgbe_adapter, m) 35#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 36 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 37 offsetof(struct rtnl_link_stats64, m) 38 39static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 40 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 41 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 42 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 43 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 44 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 45 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 46 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 47 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 48 {"lsc_int", IXGBE_STAT(lsc_int)}, 49 {"tx_busy", IXGBE_STAT(tx_busy)}, 50 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 51 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 52 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 53 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 54 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 55 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 56 {"broadcast", IXGBE_STAT(stats.bprc)}, 57 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 58 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 59 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 60 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 61 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 62 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 63 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 64 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 65 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 66 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 67 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 68 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 69 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 70 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 71 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 72 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 73 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 74 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 75 {"rx_length_errors", IXGBE_STAT(stats.rlec)}, 76 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 77 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 78 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 79 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 80 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 81 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 82 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 83 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)}, 84 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 85 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 86 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 87 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 88 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 89 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 90 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 91 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)}, 92 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)}, 93 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)}, 94 {"tx_ipsec", IXGBE_STAT(tx_ipsec)}, 95 {"rx_ipsec", IXGBE_STAT(rx_ipsec)}, 96#ifdef IXGBE_FCOE 97 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 98 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 99 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 100 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 101 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 102 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 103 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 104 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 105#endif /* IXGBE_FCOE */ 106}; 107 108/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 109 * we set the num_rx_queues to evaluate to num_tx_queues. This is 110 * used because we do not have a good way to get the max number of 111 * rx queues with CONFIG_RPS disabled. 112 */ 113#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 114 115#define IXGBE_QUEUE_STATS_LEN ( \ 116 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 117 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 118#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 119#define IXGBE_PB_STATS_LEN ( \ 120 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 121 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 122 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 123 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 124 / sizeof(u64)) 125#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 126 IXGBE_PB_STATS_LEN + \ 127 IXGBE_QUEUE_STATS_LEN) 128 129static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 130 "Register test (offline)", "Eeprom test (offline)", 131 "Interrupt test (offline)", "Loopback test (offline)", 132 "Link test (on/offline)" 133}; 134#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 135 136static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = { 137#define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) 138 "legacy-rx", 139#define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1) 140 "vf-ipsec", 141}; 142 143#define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings) 144 145/* currently supported speeds for 10G */ 146#define ADVRTSD_MSK_10G (SUPPORTED_10000baseT_Full | \ 147 SUPPORTED_10000baseKX4_Full | \ 148 SUPPORTED_10000baseKR_Full) 149 150#define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane) 151 152static u32 ixgbe_get_supported_10gtypes(struct ixgbe_hw *hw) 153{ 154 if (!ixgbe_isbackplane(hw->phy.media_type)) 155 return SUPPORTED_10000baseT_Full; 156 157 switch (hw->device_id) { 158 case IXGBE_DEV_ID_82598: 159 case IXGBE_DEV_ID_82599_KX4: 160 case IXGBE_DEV_ID_82599_KX4_MEZZ: 161 case IXGBE_DEV_ID_X550EM_X_KX4: 162 return SUPPORTED_10000baseKX4_Full; 163 case IXGBE_DEV_ID_82598_BX: 164 case IXGBE_DEV_ID_82599_KR: 165 case IXGBE_DEV_ID_X550EM_X_KR: 166 case IXGBE_DEV_ID_X550EM_X_XFI: 167 return SUPPORTED_10000baseKR_Full; 168 default: 169 return SUPPORTED_10000baseKX4_Full | 170 SUPPORTED_10000baseKR_Full; 171 } 172} 173 174static int ixgbe_get_link_ksettings(struct net_device *netdev, 175 struct ethtool_link_ksettings *cmd) 176{ 177 struct ixgbe_adapter *adapter = netdev_priv(netdev); 178 struct ixgbe_hw *hw = &adapter->hw; 179 ixgbe_link_speed supported_link; 180 bool autoneg = false; 181 u32 supported, advertising; 182 183 ethtool_convert_link_mode_to_legacy_u32(&supported, 184 cmd->link_modes.supported); 185 186 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 187 188 /* set the supported link speeds */ 189 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 190 supported |= ixgbe_get_supported_10gtypes(hw); 191 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 192 supported |= (ixgbe_isbackplane(hw->phy.media_type)) ? 193 SUPPORTED_1000baseKX_Full : 194 SUPPORTED_1000baseT_Full; 195 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 196 supported |= SUPPORTED_100baseT_Full; 197 if (supported_link & IXGBE_LINK_SPEED_10_FULL) 198 supported |= SUPPORTED_10baseT_Full; 199 200 /* default advertised speed if phy.autoneg_advertised isn't set */ 201 advertising = supported; 202 /* set the advertised speeds */ 203 if (hw->phy.autoneg_advertised) { 204 advertising = 0; 205 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) 206 advertising |= ADVERTISED_10baseT_Full; 207 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 208 advertising |= ADVERTISED_100baseT_Full; 209 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 210 advertising |= supported & ADVRTSD_MSK_10G; 211 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 212 if (supported & SUPPORTED_1000baseKX_Full) 213 advertising |= ADVERTISED_1000baseKX_Full; 214 else 215 advertising |= ADVERTISED_1000baseT_Full; 216 } 217 } else { 218 if (hw->phy.multispeed_fiber && !autoneg) { 219 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 220 advertising = ADVERTISED_10000baseT_Full; 221 } 222 } 223 224 if (autoneg) { 225 supported |= SUPPORTED_Autoneg; 226 advertising |= ADVERTISED_Autoneg; 227 cmd->base.autoneg = AUTONEG_ENABLE; 228 } else 229 cmd->base.autoneg = AUTONEG_DISABLE; 230 231 /* Determine the remaining settings based on the PHY type. */ 232 switch (adapter->hw.phy.type) { 233 case ixgbe_phy_tn: 234 case ixgbe_phy_aq: 235 case ixgbe_phy_x550em_ext_t: 236 case ixgbe_phy_fw: 237 case ixgbe_phy_cu_unknown: 238 supported |= SUPPORTED_TP; 239 advertising |= ADVERTISED_TP; 240 cmd->base.port = PORT_TP; 241 break; 242 case ixgbe_phy_qt: 243 supported |= SUPPORTED_FIBRE; 244 advertising |= ADVERTISED_FIBRE; 245 cmd->base.port = PORT_FIBRE; 246 break; 247 case ixgbe_phy_nl: 248 case ixgbe_phy_sfp_passive_tyco: 249 case ixgbe_phy_sfp_passive_unknown: 250 case ixgbe_phy_sfp_ftl: 251 case ixgbe_phy_sfp_avago: 252 case ixgbe_phy_sfp_intel: 253 case ixgbe_phy_sfp_unknown: 254 case ixgbe_phy_qsfp_passive_unknown: 255 case ixgbe_phy_qsfp_active_unknown: 256 case ixgbe_phy_qsfp_intel: 257 case ixgbe_phy_qsfp_unknown: 258 /* SFP+ devices, further checking needed */ 259 switch (adapter->hw.phy.sfp_type) { 260 case ixgbe_sfp_type_da_cu: 261 case ixgbe_sfp_type_da_cu_core0: 262 case ixgbe_sfp_type_da_cu_core1: 263 supported |= SUPPORTED_FIBRE; 264 advertising |= ADVERTISED_FIBRE; 265 cmd->base.port = PORT_DA; 266 break; 267 case ixgbe_sfp_type_sr: 268 case ixgbe_sfp_type_lr: 269 case ixgbe_sfp_type_srlr_core0: 270 case ixgbe_sfp_type_srlr_core1: 271 case ixgbe_sfp_type_1g_sx_core0: 272 case ixgbe_sfp_type_1g_sx_core1: 273 case ixgbe_sfp_type_1g_lx_core0: 274 case ixgbe_sfp_type_1g_lx_core1: 275 supported |= SUPPORTED_FIBRE; 276 advertising |= ADVERTISED_FIBRE; 277 cmd->base.port = PORT_FIBRE; 278 break; 279 case ixgbe_sfp_type_not_present: 280 supported |= SUPPORTED_FIBRE; 281 advertising |= ADVERTISED_FIBRE; 282 cmd->base.port = PORT_NONE; 283 break; 284 case ixgbe_sfp_type_1g_cu_core0: 285 case ixgbe_sfp_type_1g_cu_core1: 286 supported |= SUPPORTED_TP; 287 advertising |= ADVERTISED_TP; 288 cmd->base.port = PORT_TP; 289 break; 290 case ixgbe_sfp_type_unknown: 291 default: 292 supported |= SUPPORTED_FIBRE; 293 advertising |= ADVERTISED_FIBRE; 294 cmd->base.port = PORT_OTHER; 295 break; 296 } 297 break; 298 case ixgbe_phy_xaui: 299 supported |= SUPPORTED_FIBRE; 300 advertising |= ADVERTISED_FIBRE; 301 cmd->base.port = PORT_NONE; 302 break; 303 case ixgbe_phy_unknown: 304 case ixgbe_phy_generic: 305 case ixgbe_phy_sfp_unsupported: 306 default: 307 supported |= SUPPORTED_FIBRE; 308 advertising |= ADVERTISED_FIBRE; 309 cmd->base.port = PORT_OTHER; 310 break; 311 } 312 313 /* Indicate pause support */ 314 supported |= SUPPORTED_Pause; 315 316 switch (hw->fc.requested_mode) { 317 case ixgbe_fc_full: 318 advertising |= ADVERTISED_Pause; 319 break; 320 case ixgbe_fc_rx_pause: 321 advertising |= ADVERTISED_Pause | 322 ADVERTISED_Asym_Pause; 323 break; 324 case ixgbe_fc_tx_pause: 325 advertising |= ADVERTISED_Asym_Pause; 326 break; 327 default: 328 advertising &= ~(ADVERTISED_Pause | 329 ADVERTISED_Asym_Pause); 330 } 331 332 if (netif_carrier_ok(netdev)) { 333 switch (adapter->link_speed) { 334 case IXGBE_LINK_SPEED_10GB_FULL: 335 cmd->base.speed = SPEED_10000; 336 break; 337 case IXGBE_LINK_SPEED_5GB_FULL: 338 cmd->base.speed = SPEED_5000; 339 break; 340 case IXGBE_LINK_SPEED_2_5GB_FULL: 341 cmd->base.speed = SPEED_2500; 342 break; 343 case IXGBE_LINK_SPEED_1GB_FULL: 344 cmd->base.speed = SPEED_1000; 345 break; 346 case IXGBE_LINK_SPEED_100_FULL: 347 cmd->base.speed = SPEED_100; 348 break; 349 case IXGBE_LINK_SPEED_10_FULL: 350 cmd->base.speed = SPEED_10; 351 break; 352 default: 353 break; 354 } 355 cmd->base.duplex = DUPLEX_FULL; 356 } else { 357 cmd->base.speed = SPEED_UNKNOWN; 358 cmd->base.duplex = DUPLEX_UNKNOWN; 359 } 360 361 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 362 supported); 363 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 364 advertising); 365 366 return 0; 367} 368 369static int ixgbe_set_link_ksettings(struct net_device *netdev, 370 const struct ethtool_link_ksettings *cmd) 371{ 372 struct ixgbe_adapter *adapter = netdev_priv(netdev); 373 struct ixgbe_hw *hw = &adapter->hw; 374 u32 advertised, old; 375 s32 err = 0; 376 u32 supported, advertising; 377 378 ethtool_convert_link_mode_to_legacy_u32(&supported, 379 cmd->link_modes.supported); 380 ethtool_convert_link_mode_to_legacy_u32(&advertising, 381 cmd->link_modes.advertising); 382 383 if ((hw->phy.media_type == ixgbe_media_type_copper) || 384 (hw->phy.multispeed_fiber)) { 385 /* 386 * this function does not support duplex forcing, but can 387 * limit the advertising of the adapter to the specified speed 388 */ 389 if (advertising & ~supported) 390 return -EINVAL; 391 392 /* only allow one speed at a time if no autoneg */ 393 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { 394 if (advertising == 395 (ADVERTISED_10000baseT_Full | 396 ADVERTISED_1000baseT_Full)) 397 return -EINVAL; 398 } 399 400 old = hw->phy.autoneg_advertised; 401 advertised = 0; 402 if (advertising & ADVERTISED_10000baseT_Full) 403 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 404 405 if (advertising & ADVERTISED_1000baseT_Full) 406 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 407 408 if (advertising & ADVERTISED_100baseT_Full) 409 advertised |= IXGBE_LINK_SPEED_100_FULL; 410 411 if (advertising & ADVERTISED_10baseT_Full) 412 advertised |= IXGBE_LINK_SPEED_10_FULL; 413 414 if (old == advertised) 415 return err; 416 /* this sets the link speed and restarts auto-neg */ 417 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 418 usleep_range(1000, 2000); 419 420 hw->mac.autotry_restart = true; 421 err = hw->mac.ops.setup_link(hw, advertised, true); 422 if (err) { 423 e_info(probe, "setup link failed with code %d\n", err); 424 hw->mac.ops.setup_link(hw, old, true); 425 } 426 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 427 } else { 428 /* in this case we currently only support 10Gb/FULL */ 429 u32 speed = cmd->base.speed; 430 431 if ((cmd->base.autoneg == AUTONEG_ENABLE) || 432 (advertising != ADVERTISED_10000baseT_Full) || 433 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) 434 return -EINVAL; 435 } 436 437 return err; 438} 439 440static void ixgbe_get_pauseparam(struct net_device *netdev, 441 struct ethtool_pauseparam *pause) 442{ 443 struct ixgbe_adapter *adapter = netdev_priv(netdev); 444 struct ixgbe_hw *hw = &adapter->hw; 445 446 if (ixgbe_device_supports_autoneg_fc(hw) && 447 !hw->fc.disable_fc_autoneg) 448 pause->autoneg = 1; 449 else 450 pause->autoneg = 0; 451 452 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 453 pause->rx_pause = 1; 454 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 455 pause->tx_pause = 1; 456 } else if (hw->fc.current_mode == ixgbe_fc_full) { 457 pause->rx_pause = 1; 458 pause->tx_pause = 1; 459 } 460} 461 462static int ixgbe_set_pauseparam(struct net_device *netdev, 463 struct ethtool_pauseparam *pause) 464{ 465 struct ixgbe_adapter *adapter = netdev_priv(netdev); 466 struct ixgbe_hw *hw = &adapter->hw; 467 struct ixgbe_fc_info fc = hw->fc; 468 469 /* 82598 does no support link flow control with DCB enabled */ 470 if ((hw->mac.type == ixgbe_mac_82598EB) && 471 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 472 return -EINVAL; 473 474 /* some devices do not support autoneg of link flow control */ 475 if ((pause->autoneg == AUTONEG_ENABLE) && 476 !ixgbe_device_supports_autoneg_fc(hw)) 477 return -EINVAL; 478 479 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 480 481 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 482 fc.requested_mode = ixgbe_fc_full; 483 else if (pause->rx_pause && !pause->tx_pause) 484 fc.requested_mode = ixgbe_fc_rx_pause; 485 else if (!pause->rx_pause && pause->tx_pause) 486 fc.requested_mode = ixgbe_fc_tx_pause; 487 else 488 fc.requested_mode = ixgbe_fc_none; 489 490 /* if the thing changed then we'll update and use new autoneg */ 491 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 492 hw->fc = fc; 493 if (netif_running(netdev)) 494 ixgbe_reinit_locked(adapter); 495 else 496 ixgbe_reset(adapter); 497 } 498 499 return 0; 500} 501 502static u32 ixgbe_get_msglevel(struct net_device *netdev) 503{ 504 struct ixgbe_adapter *adapter = netdev_priv(netdev); 505 return adapter->msg_enable; 506} 507 508static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 509{ 510 struct ixgbe_adapter *adapter = netdev_priv(netdev); 511 adapter->msg_enable = data; 512} 513 514static int ixgbe_get_regs_len(struct net_device *netdev) 515{ 516#define IXGBE_REGS_LEN 1145 517 return IXGBE_REGS_LEN * sizeof(u32); 518} 519 520#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 521 522static void ixgbe_get_regs(struct net_device *netdev, 523 struct ethtool_regs *regs, void *p) 524{ 525 struct ixgbe_adapter *adapter = netdev_priv(netdev); 526 struct ixgbe_hw *hw = &adapter->hw; 527 u32 *regs_buff = p; 528 u8 i; 529 530 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 531 532 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 533 hw->device_id; 534 535 /* General Registers */ 536 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 537 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 538 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 539 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 540 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 541 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 542 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 543 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 544 545 /* NVM Register */ 546 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 547 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 548 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 549 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 550 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 551 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 552 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 553 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 554 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 555 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 556 557 /* Interrupt */ 558 /* don't read EICR because it can clear interrupt causes, instead 559 * read EICS which is a shadow but doesn't clear EICR */ 560 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 561 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 562 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 563 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 564 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 565 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 566 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 567 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 568 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 569 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 570 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 571 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 572 573 /* Flow Control */ 574 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 575 for (i = 0; i < 4; i++) 576 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i)); 577 for (i = 0; i < 8; i++) { 578 switch (hw->mac.type) { 579 case ixgbe_mac_82598EB: 580 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 581 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 582 break; 583 case ixgbe_mac_82599EB: 584 case ixgbe_mac_X540: 585 case ixgbe_mac_X550: 586 case ixgbe_mac_X550EM_x: 587 case ixgbe_mac_x550em_a: 588 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 589 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 590 break; 591 default: 592 break; 593 } 594 } 595 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 596 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 597 598 /* Receive DMA */ 599 for (i = 0; i < 64; i++) 600 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 601 for (i = 0; i < 64; i++) 602 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 603 for (i = 0; i < 64; i++) 604 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 605 for (i = 0; i < 64; i++) 606 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 607 for (i = 0; i < 64; i++) 608 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 609 for (i = 0; i < 64; i++) 610 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 611 for (i = 0; i < 16; i++) 612 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 613 for (i = 0; i < 16; i++) 614 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 615 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 616 for (i = 0; i < 8; i++) 617 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 618 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 619 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 620 621 /* Receive */ 622 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 623 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 624 for (i = 0; i < 16; i++) 625 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 626 for (i = 0; i < 16; i++) 627 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 628 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 629 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 630 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 631 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 632 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 633 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 634 for (i = 0; i < 8; i++) 635 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 636 for (i = 0; i < 8; i++) 637 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 638 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 639 640 /* Transmit */ 641 for (i = 0; i < 32; i++) 642 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 643 for (i = 0; i < 32; i++) 644 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 645 for (i = 0; i < 32; i++) 646 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 647 for (i = 0; i < 32; i++) 648 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 649 for (i = 0; i < 32; i++) 650 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 651 for (i = 0; i < 32; i++) 652 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 653 for (i = 0; i < 32; i++) 654 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 655 for (i = 0; i < 32; i++) 656 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 657 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 658 for (i = 0; i < 16; i++) 659 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 660 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 661 for (i = 0; i < 8; i++) 662 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 663 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 664 665 /* Wake Up */ 666 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 667 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 668 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 669 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 670 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 671 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 672 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 673 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 674 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 675 676 /* DCB */ 677 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 678 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 679 680 switch (hw->mac.type) { 681 case ixgbe_mac_82598EB: 682 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 683 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 684 for (i = 0; i < 8; i++) 685 regs_buff[833 + i] = 686 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 687 for (i = 0; i < 8; i++) 688 regs_buff[841 + i] = 689 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 690 for (i = 0; i < 8; i++) 691 regs_buff[849 + i] = 692 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 693 for (i = 0; i < 8; i++) 694 regs_buff[857 + i] = 695 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 696 break; 697 case ixgbe_mac_82599EB: 698 case ixgbe_mac_X540: 699 case ixgbe_mac_X550: 700 case ixgbe_mac_X550EM_x: 701 case ixgbe_mac_x550em_a: 702 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 703 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 704 for (i = 0; i < 8; i++) 705 regs_buff[833 + i] = 706 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 707 for (i = 0; i < 8; i++) 708 regs_buff[841 + i] = 709 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 710 for (i = 0; i < 8; i++) 711 regs_buff[849 + i] = 712 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 713 for (i = 0; i < 8; i++) 714 regs_buff[857 + i] = 715 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 716 break; 717 default: 718 break; 719 } 720 721 for (i = 0; i < 8; i++) 722 regs_buff[865 + i] = 723 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 724 for (i = 0; i < 8; i++) 725 regs_buff[873 + i] = 726 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 727 728 /* Statistics */ 729 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 730 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 731 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 732 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 733 for (i = 0; i < 8; i++) 734 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 735 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 736 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 737 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 738 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 739 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 740 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 741 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 742 for (i = 0; i < 8; i++) 743 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 744 for (i = 0; i < 8; i++) 745 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 746 for (i = 0; i < 8; i++) 747 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 748 for (i = 0; i < 8; i++) 749 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 750 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 751 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 752 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 753 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 754 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 755 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 756 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 757 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 758 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 759 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 760 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc); 761 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32); 762 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc); 763 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32); 764 for (i = 0; i < 8; i++) 765 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 766 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 767 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 768 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 769 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 770 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 771 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 772 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 773 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor); 774 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32); 775 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 776 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 777 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 778 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 779 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 780 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 781 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 782 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 783 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 784 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 785 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 786 for (i = 0; i < 16; i++) 787 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 788 for (i = 0; i < 16; i++) 789 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 790 for (i = 0; i < 16; i++) 791 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 792 for (i = 0; i < 16; i++) 793 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 794 795 /* MAC */ 796 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 797 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 798 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 799 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 800 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 801 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 802 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 803 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 804 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 805 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 806 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 807 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 808 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 809 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 810 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 811 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 812 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 813 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 814 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 815 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 816 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 817 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 818 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 819 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 820 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 821 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 822 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 823 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 824 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 825 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 826 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 827 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 828 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 829 830 /* Diagnostic */ 831 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 832 for (i = 0; i < 8; i++) 833 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 834 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 835 for (i = 0; i < 4; i++) 836 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 837 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 838 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 839 for (i = 0; i < 8; i++) 840 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 841 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 842 for (i = 0; i < 4; i++) 843 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 844 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 845 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 846 for (i = 0; i < 4; i++) 847 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i)); 848 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 849 for (i = 0; i < 4; i++) 850 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i)); 851 for (i = 0; i < 8; i++) 852 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 853 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 854 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 855 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 856 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 857 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 858 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 859 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 860 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 861 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 862 863 /* 82599 X540 specific registers */ 864 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 865 866 /* 82599 X540 specific DCB registers */ 867 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 868 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 869 for (i = 0; i < 4; i++) 870 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 871 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 872 /* same as RTTQCNRM */ 873 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 874 /* same as RTTQCNRR */ 875 876 /* X540 specific DCB registers */ 877 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 878 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 879 880 /* Security config registers */ 881 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 882 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 883 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF); 884 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 885 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 886 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 887} 888 889static int ixgbe_get_eeprom_len(struct net_device *netdev) 890{ 891 struct ixgbe_adapter *adapter = netdev_priv(netdev); 892 return adapter->hw.eeprom.word_size * 2; 893} 894 895static int ixgbe_get_eeprom(struct net_device *netdev, 896 struct ethtool_eeprom *eeprom, u8 *bytes) 897{ 898 struct ixgbe_adapter *adapter = netdev_priv(netdev); 899 struct ixgbe_hw *hw = &adapter->hw; 900 u16 *eeprom_buff; 901 int first_word, last_word, eeprom_len; 902 int ret_val = 0; 903 u16 i; 904 905 if (eeprom->len == 0) 906 return -EINVAL; 907 908 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 909 910 first_word = eeprom->offset >> 1; 911 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 912 eeprom_len = last_word - first_word + 1; 913 914 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL); 915 if (!eeprom_buff) 916 return -ENOMEM; 917 918 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 919 eeprom_buff); 920 921 /* Device's eeprom is always little-endian, word addressable */ 922 for (i = 0; i < eeprom_len; i++) 923 le16_to_cpus(&eeprom_buff[i]); 924 925 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 926 kfree(eeprom_buff); 927 928 return ret_val; 929} 930 931static int ixgbe_set_eeprom(struct net_device *netdev, 932 struct ethtool_eeprom *eeprom, u8 *bytes) 933{ 934 struct ixgbe_adapter *adapter = netdev_priv(netdev); 935 struct ixgbe_hw *hw = &adapter->hw; 936 u16 *eeprom_buff; 937 void *ptr; 938 int max_len, first_word, last_word, ret_val = 0; 939 u16 i; 940 941 if (eeprom->len == 0) 942 return -EINVAL; 943 944 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 945 return -EINVAL; 946 947 max_len = hw->eeprom.word_size * 2; 948 949 first_word = eeprom->offset >> 1; 950 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 951 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 952 if (!eeprom_buff) 953 return -ENOMEM; 954 955 ptr = eeprom_buff; 956 957 if (eeprom->offset & 1) { 958 /* 959 * need read/modify/write of first changed EEPROM word 960 * only the second byte of the word is being modified 961 */ 962 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 963 if (ret_val) 964 goto err; 965 966 ptr++; 967 } 968 if ((eeprom->offset + eeprom->len) & 1) { 969 /* 970 * need read/modify/write of last changed EEPROM word 971 * only the first byte of the word is being modified 972 */ 973 ret_val = hw->eeprom.ops.read(hw, last_word, 974 &eeprom_buff[last_word - first_word]); 975 if (ret_val) 976 goto err; 977 } 978 979 /* Device's eeprom is always little-endian, word addressable */ 980 for (i = 0; i < last_word - first_word + 1; i++) 981 le16_to_cpus(&eeprom_buff[i]); 982 983 memcpy(ptr, bytes, eeprom->len); 984 985 for (i = 0; i < last_word - first_word + 1; i++) 986 cpu_to_le16s(&eeprom_buff[i]); 987 988 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 989 last_word - first_word + 1, 990 eeprom_buff); 991 992 /* Update the checksum */ 993 if (ret_val == 0) 994 hw->eeprom.ops.update_checksum(hw); 995 996err: 997 kfree(eeprom_buff); 998 return ret_val; 999} 1000 1001static void ixgbe_get_drvinfo(struct net_device *netdev, 1002 struct ethtool_drvinfo *drvinfo) 1003{ 1004 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1005 1006 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 1007 strlcpy(drvinfo->version, ixgbe_driver_version, 1008 sizeof(drvinfo->version)); 1009 1010 strlcpy(drvinfo->fw_version, adapter->eeprom_id, 1011 sizeof(drvinfo->fw_version)); 1012 1013 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 1014 sizeof(drvinfo->bus_info)); 1015 1016 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN; 1017} 1018 1019static void ixgbe_get_ringparam(struct net_device *netdev, 1020 struct ethtool_ringparam *ring) 1021{ 1022 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1023 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 1024 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 1025 1026 ring->rx_max_pending = IXGBE_MAX_RXD; 1027 ring->tx_max_pending = IXGBE_MAX_TXD; 1028 ring->rx_pending = rx_ring->count; 1029 ring->tx_pending = tx_ring->count; 1030} 1031 1032static int ixgbe_set_ringparam(struct net_device *netdev, 1033 struct ethtool_ringparam *ring) 1034{ 1035 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1036 struct ixgbe_ring *temp_ring; 1037 int i, j, err = 0; 1038 u32 new_rx_count, new_tx_count; 1039 1040 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 1041 return -EINVAL; 1042 1043 new_tx_count = clamp_t(u32, ring->tx_pending, 1044 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 1045 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 1046 1047 new_rx_count = clamp_t(u32, ring->rx_pending, 1048 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 1049 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 1050 1051 if ((new_tx_count == adapter->tx_ring_count) && 1052 (new_rx_count == adapter->rx_ring_count)) { 1053 /* nothing to do */ 1054 return 0; 1055 } 1056 1057 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 1058 usleep_range(1000, 2000); 1059 1060 if (!netif_running(adapter->netdev)) { 1061 for (i = 0; i < adapter->num_tx_queues; i++) 1062 adapter->tx_ring[i]->count = new_tx_count; 1063 for (i = 0; i < adapter->num_xdp_queues; i++) 1064 adapter->xdp_ring[i]->count = new_tx_count; 1065 for (i = 0; i < adapter->num_rx_queues; i++) 1066 adapter->rx_ring[i]->count = new_rx_count; 1067 adapter->tx_ring_count = new_tx_count; 1068 adapter->xdp_ring_count = new_tx_count; 1069 adapter->rx_ring_count = new_rx_count; 1070 goto clear_reset; 1071 } 1072 1073 /* allocate temporary buffer to store rings in */ 1074 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues, 1075 adapter->num_rx_queues); 1076 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring))); 1077 1078 if (!temp_ring) { 1079 err = -ENOMEM; 1080 goto clear_reset; 1081 } 1082 1083 ixgbe_down(adapter); 1084 1085 /* 1086 * Setup new Tx resources and free the old Tx resources in that order. 1087 * We can then assign the new resources to the rings via a memcpy. 1088 * The advantage to this approach is that we are guaranteed to still 1089 * have resources even in the case of an allocation failure. 1090 */ 1091 if (new_tx_count != adapter->tx_ring_count) { 1092 for (i = 0; i < adapter->num_tx_queues; i++) { 1093 memcpy(&temp_ring[i], adapter->tx_ring[i], 1094 sizeof(struct ixgbe_ring)); 1095 1096 temp_ring[i].count = new_tx_count; 1097 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1098 if (err) { 1099 while (i) { 1100 i--; 1101 ixgbe_free_tx_resources(&temp_ring[i]); 1102 } 1103 goto err_setup; 1104 } 1105 } 1106 1107 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1108 memcpy(&temp_ring[i], adapter->xdp_ring[j], 1109 sizeof(struct ixgbe_ring)); 1110 1111 temp_ring[i].count = new_tx_count; 1112 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1113 if (err) { 1114 while (i) { 1115 i--; 1116 ixgbe_free_tx_resources(&temp_ring[i]); 1117 } 1118 goto err_setup; 1119 } 1120 } 1121 1122 for (i = 0; i < adapter->num_tx_queues; i++) { 1123 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1124 1125 memcpy(adapter->tx_ring[i], &temp_ring[i], 1126 sizeof(struct ixgbe_ring)); 1127 } 1128 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1129 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 1130 1131 memcpy(adapter->xdp_ring[j], &temp_ring[i], 1132 sizeof(struct ixgbe_ring)); 1133 } 1134 1135 adapter->tx_ring_count = new_tx_count; 1136 } 1137 1138 /* Repeat the process for the Rx rings if needed */ 1139 if (new_rx_count != adapter->rx_ring_count) { 1140 for (i = 0; i < adapter->num_rx_queues; i++) { 1141 memcpy(&temp_ring[i], adapter->rx_ring[i], 1142 sizeof(struct ixgbe_ring)); 1143 1144 /* Clear copied XDP RX-queue info */ 1145 memset(&temp_ring[i].xdp_rxq, 0, 1146 sizeof(temp_ring[i].xdp_rxq)); 1147 1148 temp_ring[i].count = new_rx_count; 1149 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]); 1150 if (err) { 1151 while (i) { 1152 i--; 1153 ixgbe_free_rx_resources(&temp_ring[i]); 1154 } 1155 goto err_setup; 1156 } 1157 1158 } 1159 1160 for (i = 0; i < adapter->num_rx_queues; i++) { 1161 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1162 1163 memcpy(adapter->rx_ring[i], &temp_ring[i], 1164 sizeof(struct ixgbe_ring)); 1165 } 1166 1167 adapter->rx_ring_count = new_rx_count; 1168 } 1169 1170err_setup: 1171 ixgbe_up(adapter); 1172 vfree(temp_ring); 1173clear_reset: 1174 clear_bit(__IXGBE_RESETTING, &adapter->state); 1175 return err; 1176} 1177 1178static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1179{ 1180 switch (sset) { 1181 case ETH_SS_TEST: 1182 return IXGBE_TEST_LEN; 1183 case ETH_SS_STATS: 1184 return IXGBE_STATS_LEN; 1185 case ETH_SS_PRIV_FLAGS: 1186 return IXGBE_PRIV_FLAGS_STR_LEN; 1187 default: 1188 return -EOPNOTSUPP; 1189 } 1190} 1191 1192static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1193 struct ethtool_stats *stats, u64 *data) 1194{ 1195 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1196 struct rtnl_link_stats64 temp; 1197 const struct rtnl_link_stats64 *net_stats; 1198 unsigned int start; 1199 struct ixgbe_ring *ring; 1200 int i, j; 1201 char *p = NULL; 1202 1203 ixgbe_update_stats(adapter); 1204 net_stats = dev_get_stats(netdev, &temp); 1205 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1206 switch (ixgbe_gstrings_stats[i].type) { 1207 case NETDEV_STATS: 1208 p = (char *) net_stats + 1209 ixgbe_gstrings_stats[i].stat_offset; 1210 break; 1211 case IXGBE_STATS: 1212 p = (char *) adapter + 1213 ixgbe_gstrings_stats[i].stat_offset; 1214 break; 1215 default: 1216 data[i] = 0; 1217 continue; 1218 } 1219 1220 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1221 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1222 } 1223 for (j = 0; j < netdev->num_tx_queues; j++) { 1224 ring = adapter->tx_ring[j]; 1225 if (!ring) { 1226 data[i] = 0; 1227 data[i+1] = 0; 1228 i += 2; 1229 continue; 1230 } 1231 1232 do { 1233 start = u64_stats_fetch_begin_irq(&ring->syncp); 1234 data[i] = ring->stats.packets; 1235 data[i+1] = ring->stats.bytes; 1236 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1237 i += 2; 1238 } 1239 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1240 ring = adapter->rx_ring[j]; 1241 if (!ring) { 1242 data[i] = 0; 1243 data[i+1] = 0; 1244 i += 2; 1245 continue; 1246 } 1247 1248 do { 1249 start = u64_stats_fetch_begin_irq(&ring->syncp); 1250 data[i] = ring->stats.packets; 1251 data[i+1] = ring->stats.bytes; 1252 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1253 i += 2; 1254 } 1255 1256 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1257 data[i++] = adapter->stats.pxontxc[j]; 1258 data[i++] = adapter->stats.pxofftxc[j]; 1259 } 1260 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1261 data[i++] = adapter->stats.pxonrxc[j]; 1262 data[i++] = adapter->stats.pxoffrxc[j]; 1263 } 1264} 1265 1266static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1267 u8 *data) 1268{ 1269 char *p = (char *)data; 1270 unsigned int i; 1271 1272 switch (stringset) { 1273 case ETH_SS_TEST: 1274 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1275 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1276 data += ETH_GSTRING_LEN; 1277 } 1278 break; 1279 case ETH_SS_STATS: 1280 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1281 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1282 ETH_GSTRING_LEN); 1283 p += ETH_GSTRING_LEN; 1284 } 1285 for (i = 0; i < netdev->num_tx_queues; i++) { 1286 sprintf(p, "tx_queue_%u_packets", i); 1287 p += ETH_GSTRING_LEN; 1288 sprintf(p, "tx_queue_%u_bytes", i); 1289 p += ETH_GSTRING_LEN; 1290 } 1291 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1292 sprintf(p, "rx_queue_%u_packets", i); 1293 p += ETH_GSTRING_LEN; 1294 sprintf(p, "rx_queue_%u_bytes", i); 1295 p += ETH_GSTRING_LEN; 1296 } 1297 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1298 sprintf(p, "tx_pb_%u_pxon", i); 1299 p += ETH_GSTRING_LEN; 1300 sprintf(p, "tx_pb_%u_pxoff", i); 1301 p += ETH_GSTRING_LEN; 1302 } 1303 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1304 sprintf(p, "rx_pb_%u_pxon", i); 1305 p += ETH_GSTRING_LEN; 1306 sprintf(p, "rx_pb_%u_pxoff", i); 1307 p += ETH_GSTRING_LEN; 1308 } 1309 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1310 break; 1311 case ETH_SS_PRIV_FLAGS: 1312 memcpy(data, ixgbe_priv_flags_strings, 1313 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 1314 } 1315} 1316 1317static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1318{ 1319 struct ixgbe_hw *hw = &adapter->hw; 1320 bool link_up; 1321 u32 link_speed = 0; 1322 1323 if (ixgbe_removed(hw->hw_addr)) { 1324 *data = 1; 1325 return 1; 1326 } 1327 *data = 0; 1328 1329 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1330 if (link_up) 1331 return *data; 1332 else 1333 *data = 1; 1334 return *data; 1335} 1336 1337/* ethtool register test data */ 1338struct ixgbe_reg_test { 1339 u16 reg; 1340 u8 array_len; 1341 u8 test_type; 1342 u32 mask; 1343 u32 write; 1344}; 1345 1346/* In the hardware, registers are laid out either singly, in arrays 1347 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1348 * most tests take place on arrays or single registers (handled 1349 * as a single-element array) and special-case the tables. 1350 * Table tests are always pattern tests. 1351 * 1352 * We also make provision for some required setup steps by specifying 1353 * registers to be written without any read-back testing. 1354 */ 1355 1356#define PATTERN_TEST 1 1357#define SET_READ_TEST 2 1358#define WRITE_NO_TEST 3 1359#define TABLE32_TEST 4 1360#define TABLE64_TEST_LO 5 1361#define TABLE64_TEST_HI 6 1362 1363/* default 82599 register test */ 1364static const struct ixgbe_reg_test reg_test_82599[] = { 1365 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1366 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1367 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1368 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1369 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1370 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1371 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1372 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1373 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1374 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1375 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1376 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1377 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1378 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1379 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1380 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1381 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1382 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1383 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1384 { .reg = 0 } 1385}; 1386 1387/* default 82598 register test */ 1388static const struct ixgbe_reg_test reg_test_82598[] = { 1389 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1390 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1391 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1392 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1393 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1394 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1395 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1396 /* Enable all four RX queues before testing. */ 1397 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1398 /* RDH is read-only for 82598, only test RDT. */ 1399 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1400 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1401 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1402 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1403 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1404 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1405 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1406 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1407 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1408 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1409 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1410 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1411 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1412 { .reg = 0 } 1413}; 1414 1415static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1416 u32 mask, u32 write) 1417{ 1418 u32 pat, val, before; 1419 static const u32 test_pattern[] = { 1420 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1421 1422 if (ixgbe_removed(adapter->hw.hw_addr)) { 1423 *data = 1; 1424 return true; 1425 } 1426 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1427 before = ixgbe_read_reg(&adapter->hw, reg); 1428 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1429 val = ixgbe_read_reg(&adapter->hw, reg); 1430 if (val != (test_pattern[pat] & write & mask)) { 1431 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1432 reg, val, (test_pattern[pat] & write & mask)); 1433 *data = reg; 1434 ixgbe_write_reg(&adapter->hw, reg, before); 1435 return true; 1436 } 1437 ixgbe_write_reg(&adapter->hw, reg, before); 1438 } 1439 return false; 1440} 1441 1442static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1443 u32 mask, u32 write) 1444{ 1445 u32 val, before; 1446 1447 if (ixgbe_removed(adapter->hw.hw_addr)) { 1448 *data = 1; 1449 return true; 1450 } 1451 before = ixgbe_read_reg(&adapter->hw, reg); 1452 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1453 val = ixgbe_read_reg(&adapter->hw, reg); 1454 if ((write & mask) != (val & mask)) { 1455 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1456 reg, (val & mask), (write & mask)); 1457 *data = reg; 1458 ixgbe_write_reg(&adapter->hw, reg, before); 1459 return true; 1460 } 1461 ixgbe_write_reg(&adapter->hw, reg, before); 1462 return false; 1463} 1464 1465static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1466{ 1467 const struct ixgbe_reg_test *test; 1468 u32 value, before, after; 1469 u32 i, toggle; 1470 1471 if (ixgbe_removed(adapter->hw.hw_addr)) { 1472 e_err(drv, "Adapter removed - register test blocked\n"); 1473 *data = 1; 1474 return 1; 1475 } 1476 switch (adapter->hw.mac.type) { 1477 case ixgbe_mac_82598EB: 1478 toggle = 0x7FFFF3FF; 1479 test = reg_test_82598; 1480 break; 1481 case ixgbe_mac_82599EB: 1482 case ixgbe_mac_X540: 1483 case ixgbe_mac_X550: 1484 case ixgbe_mac_X550EM_x: 1485 case ixgbe_mac_x550em_a: 1486 toggle = 0x7FFFF30F; 1487 test = reg_test_82599; 1488 break; 1489 default: 1490 *data = 1; 1491 return 1; 1492 } 1493 1494 /* 1495 * Because the status register is such a special case, 1496 * we handle it separately from the rest of the register 1497 * tests. Some bits are read-only, some toggle, and some 1498 * are writeable on newer MACs. 1499 */ 1500 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1501 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1502 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1503 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1504 if (value != after) { 1505 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1506 after, value); 1507 *data = 1; 1508 return 1; 1509 } 1510 /* restore previous status */ 1511 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1512 1513 /* 1514 * Perform the remainder of the register test, looping through 1515 * the test table until we either fail or reach the null entry. 1516 */ 1517 while (test->reg) { 1518 for (i = 0; i < test->array_len; i++) { 1519 bool b = false; 1520 1521 switch (test->test_type) { 1522 case PATTERN_TEST: 1523 b = reg_pattern_test(adapter, data, 1524 test->reg + (i * 0x40), 1525 test->mask, 1526 test->write); 1527 break; 1528 case SET_READ_TEST: 1529 b = reg_set_and_check(adapter, data, 1530 test->reg + (i * 0x40), 1531 test->mask, 1532 test->write); 1533 break; 1534 case WRITE_NO_TEST: 1535 ixgbe_write_reg(&adapter->hw, 1536 test->reg + (i * 0x40), 1537 test->wri…
Large files files are truncated, but you can click here to view the full file