/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

http://github.com/mirrors/linux · C · 498 lines · 333 code · 85 blank · 80 comment · 53 complexity · 0e8b6dff456110c326c23686bf28cddb MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*******************************************************************************
  3. STMMAC Ethernet Driver -- MDIO bus implementation
  4. Provides Bus interface for MII registers
  5. Copyright (C) 2007-2009 STMicroelectronics Ltd
  6. Author: Carl Shaw <carl.shaw@st.com>
  7. Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  8. *******************************************************************************/
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/io.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/mii.h>
  13. #include <linux/of_mdio.h>
  14. #include <linux/phy.h>
  15. #include <linux/property.h>
  16. #include <linux/slab.h>
  17. #include "dwxgmac2.h"
  18. #include "stmmac.h"
  19. #define MII_BUSY 0x00000001
  20. #define MII_WRITE 0x00000002
  21. #define MII_DATA_MASK GENMASK(15, 0)
  22. /* GMAC4 defines */
  23. #define MII_GMAC4_GOC_SHIFT 2
  24. #define MII_GMAC4_REG_ADDR_SHIFT 16
  25. #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
  26. #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
  27. #define MII_GMAC4_C45E BIT(1)
  28. /* XGMAC defines */
  29. #define MII_XGMAC_SADDR BIT(18)
  30. #define MII_XGMAC_CMD_SHIFT 16
  31. #define MII_XGMAC_WRITE (1 << MII_XGMAC_CMD_SHIFT)
  32. #define MII_XGMAC_READ (3 << MII_XGMAC_CMD_SHIFT)
  33. #define MII_XGMAC_BUSY BIT(22)
  34. #define MII_XGMAC_MAX_C22ADDR 3
  35. #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
  36. #define MII_XGMAC_PA_SHIFT 16
  37. #define MII_XGMAC_DA_SHIFT 21
  38. static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
  39. int phyreg, u32 *hw_addr)
  40. {
  41. u32 tmp;
  42. /* Set port as Clause 45 */
  43. tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
  44. tmp &= ~BIT(phyaddr);
  45. writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
  46. *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff);
  47. *hw_addr |= (phyreg >> MII_DEVADDR_C45_SHIFT) << MII_XGMAC_DA_SHIFT;
  48. return 0;
  49. }
  50. static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
  51. int phyreg, u32 *hw_addr)
  52. {
  53. u32 tmp;
  54. /* HW does not support C22 addr >= 4 */
  55. if (phyaddr > MII_XGMAC_MAX_C22ADDR)
  56. return -ENODEV;
  57. /* Set port as Clause 22 */
  58. tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
  59. tmp &= ~MII_XGMAC_C22P_MASK;
  60. tmp |= BIT(phyaddr);
  61. writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
  62. *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f);
  63. return 0;
  64. }
  65. static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
  66. {
  67. struct net_device *ndev = bus->priv;
  68. struct stmmac_priv *priv = netdev_priv(ndev);
  69. unsigned int mii_address = priv->hw->mii.addr;
  70. unsigned int mii_data = priv->hw->mii.data;
  71. u32 tmp, addr, value = MII_XGMAC_BUSY;
  72. int ret;
  73. /* Wait until any existing MII operation is complete */
  74. if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
  75. !(tmp & MII_XGMAC_BUSY), 100, 10000))
  76. return -EBUSY;
  77. if (phyreg & MII_ADDR_C45) {
  78. phyreg &= ~MII_ADDR_C45;
  79. ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
  80. if (ret)
  81. return ret;
  82. } else {
  83. ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
  84. if (ret)
  85. return ret;
  86. value |= MII_XGMAC_SADDR;
  87. }
  88. value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
  89. & priv->hw->mii.clk_csr_mask;
  90. value |= MII_XGMAC_READ;
  91. /* Wait until any existing MII operation is complete */
  92. if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
  93. !(tmp & MII_XGMAC_BUSY), 100, 10000))
  94. return -EBUSY;
  95. /* Set the MII address register to read */
  96. writel(addr, priv->ioaddr + mii_address);
  97. writel(value, priv->ioaddr + mii_data);
  98. /* Wait until any existing MII operation is complete */
  99. if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
  100. !(tmp & MII_XGMAC_BUSY), 100, 10000))
  101. return -EBUSY;
  102. /* Read the data from the MII data register */
  103. return readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
  104. }
  105. static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
  106. int phyreg, u16 phydata)
  107. {
  108. struct net_device *ndev = bus->priv;
  109. struct stmmac_priv *priv = netdev_priv(ndev);
  110. unsigned int mii_address = priv->hw->mii.addr;
  111. unsigned int mii_data = priv->hw->mii.data;
  112. u32 addr, tmp, value = MII_XGMAC_BUSY;
  113. int ret;
  114. /* Wait until any existing MII operation is complete */
  115. if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
  116. !(tmp & MII_XGMAC_BUSY), 100, 10000))
  117. return -EBUSY;
  118. if (phyreg & MII_ADDR_C45) {
  119. phyreg &= ~MII_ADDR_C45;
  120. ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
  121. if (ret)
  122. return ret;
  123. } else {
  124. ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
  125. if (ret)
  126. return ret;
  127. value |= MII_XGMAC_SADDR;
  128. }
  129. value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
  130. & priv->hw->mii.clk_csr_mask;
  131. value |= phydata;
  132. value |= MII_XGMAC_WRITE;
  133. /* Wait until any existing MII operation is complete */
  134. if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
  135. !(tmp & MII_XGMAC_BUSY), 100, 10000))
  136. return -EBUSY;
  137. /* Set the MII address register to write */
  138. writel(addr, priv->ioaddr + mii_address);
  139. writel(value, priv->ioaddr + mii_data);
  140. /* Wait until any existing MII operation is complete */
  141. return readl_poll_timeout(priv->ioaddr + mii_data, tmp,
  142. !(tmp & MII_XGMAC_BUSY), 100, 10000);
  143. }
  144. /**
  145. * stmmac_mdio_read
  146. * @bus: points to the mii_bus structure
  147. * @phyaddr: MII addr
  148. * @phyreg: MII reg
  149. * Description: it reads data from the MII register from within the phy device.
  150. * For the 7111 GMAC, we must set the bit 0 in the MII address register while
  151. * accessing the PHY registers.
  152. * Fortunately, it seems this has no drawback for the 7109 MAC.
  153. */
  154. static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
  155. {
  156. struct net_device *ndev = bus->priv;
  157. struct stmmac_priv *priv = netdev_priv(ndev);
  158. unsigned int mii_address = priv->hw->mii.addr;
  159. unsigned int mii_data = priv->hw->mii.data;
  160. u32 value = MII_BUSY;
  161. int data = 0;
  162. u32 v;
  163. value |= (phyaddr << priv->hw->mii.addr_shift)
  164. & priv->hw->mii.addr_mask;
  165. value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
  166. value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
  167. & priv->hw->mii.clk_csr_mask;
  168. if (priv->plat->has_gmac4) {
  169. value |= MII_GMAC4_READ;
  170. if (phyreg & MII_ADDR_C45) {
  171. value |= MII_GMAC4_C45E;
  172. value &= ~priv->hw->mii.reg_mask;
  173. value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) <<
  174. priv->hw->mii.reg_shift) &
  175. priv->hw->mii.reg_mask;
  176. data |= (phyreg & MII_REGADDR_C45_MASK) <<
  177. MII_GMAC4_REG_ADDR_SHIFT;
  178. }
  179. }
  180. if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
  181. 100, 10000))
  182. return -EBUSY;
  183. writel(data, priv->ioaddr + mii_data);
  184. writel(value, priv->ioaddr + mii_address);
  185. if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
  186. 100, 10000))
  187. return -EBUSY;
  188. /* Read the data from the MII data register */
  189. data = (int)readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
  190. return data;
  191. }
  192. /**
  193. * stmmac_mdio_write
  194. * @bus: points to the mii_bus structure
  195. * @phyaddr: MII addr
  196. * @phyreg: MII reg
  197. * @phydata: phy data
  198. * Description: it writes the data into the MII register from within the device.
  199. */
  200. static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
  201. u16 phydata)
  202. {
  203. struct net_device *ndev = bus->priv;
  204. struct stmmac_priv *priv = netdev_priv(ndev);
  205. unsigned int mii_address = priv->hw->mii.addr;
  206. unsigned int mii_data = priv->hw->mii.data;
  207. u32 value = MII_BUSY;
  208. int data = phydata;
  209. u32 v;
  210. value |= (phyaddr << priv->hw->mii.addr_shift)
  211. & priv->hw->mii.addr_mask;
  212. value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
  213. value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
  214. & priv->hw->mii.clk_csr_mask;
  215. if (priv->plat->has_gmac4) {
  216. value |= MII_GMAC4_WRITE;
  217. if (phyreg & MII_ADDR_C45) {
  218. value |= MII_GMAC4_C45E;
  219. value &= ~priv->hw->mii.reg_mask;
  220. value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) <<
  221. priv->hw->mii.reg_shift) &
  222. priv->hw->mii.reg_mask;
  223. data |= (phyreg & MII_REGADDR_C45_MASK) <<
  224. MII_GMAC4_REG_ADDR_SHIFT;
  225. }
  226. } else {
  227. value |= MII_WRITE;
  228. }
  229. /* Wait until any existing MII operation is complete */
  230. if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
  231. 100, 10000))
  232. return -EBUSY;
  233. /* Set the MII address register to write */
  234. writel(data, priv->ioaddr + mii_data);
  235. writel(value, priv->ioaddr + mii_address);
  236. /* Wait until any existing MII operation is complete */
  237. return readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
  238. 100, 10000);
  239. }
  240. /**
  241. * stmmac_mdio_reset
  242. * @bus: points to the mii_bus structure
  243. * Description: reset the MII bus
  244. */
  245. int stmmac_mdio_reset(struct mii_bus *bus)
  246. {
  247. #if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
  248. struct net_device *ndev = bus->priv;
  249. struct stmmac_priv *priv = netdev_priv(ndev);
  250. unsigned int mii_address = priv->hw->mii.addr;
  251. #ifdef CONFIG_OF
  252. if (priv->device->of_node) {
  253. struct gpio_desc *reset_gpio;
  254. u32 delays[3] = { 0, 0, 0 };
  255. reset_gpio = devm_gpiod_get_optional(priv->device,
  256. "snps,reset",
  257. GPIOD_OUT_LOW);
  258. if (IS_ERR(reset_gpio))
  259. return PTR_ERR(reset_gpio);
  260. device_property_read_u32_array(priv->device,
  261. "snps,reset-delays-us",
  262. delays, ARRAY_SIZE(delays));
  263. if (delays[0])
  264. msleep(DIV_ROUND_UP(delays[0], 1000));
  265. gpiod_set_value_cansleep(reset_gpio, 1);
  266. if (delays[1])
  267. msleep(DIV_ROUND_UP(delays[1], 1000));
  268. gpiod_set_value_cansleep(reset_gpio, 0);
  269. if (delays[2])
  270. msleep(DIV_ROUND_UP(delays[2], 1000));
  271. }
  272. #endif
  273. /* This is a workaround for problems with the STE101P PHY.
  274. * It doesn't complete its reset until at least one clock cycle
  275. * on MDC, so perform a dummy mdio read. To be updated for GMAC4
  276. * if needed.
  277. */
  278. if (!priv->plat->has_gmac4)
  279. writel(0, priv->ioaddr + mii_address);
  280. #endif
  281. return 0;
  282. }
  283. /**
  284. * stmmac_mdio_register
  285. * @ndev: net device structure
  286. * Description: it registers the MII bus
  287. */
  288. int stmmac_mdio_register(struct net_device *ndev)
  289. {
  290. int err = 0;
  291. struct mii_bus *new_bus;
  292. struct stmmac_priv *priv = netdev_priv(ndev);
  293. struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
  294. struct device_node *mdio_node = priv->plat->mdio_node;
  295. struct device *dev = ndev->dev.parent;
  296. int addr, found, max_addr;
  297. if (!mdio_bus_data)
  298. return 0;
  299. new_bus = mdiobus_alloc();
  300. if (!new_bus)
  301. return -ENOMEM;
  302. if (mdio_bus_data->irqs)
  303. memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
  304. new_bus->name = "stmmac";
  305. if (priv->plat->has_xgmac) {
  306. new_bus->read = &stmmac_xgmac2_mdio_read;
  307. new_bus->write = &stmmac_xgmac2_mdio_write;
  308. /* Right now only C22 phys are supported */
  309. max_addr = MII_XGMAC_MAX_C22ADDR + 1;
  310. /* Check if DT specified an unsupported phy addr */
  311. if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
  312. dev_err(dev, "Unsupported phy_addr (max=%d)\n",
  313. MII_XGMAC_MAX_C22ADDR);
  314. } else {
  315. new_bus->read = &stmmac_mdio_read;
  316. new_bus->write = &stmmac_mdio_write;
  317. max_addr = PHY_MAX_ADDR;
  318. }
  319. if (mdio_bus_data->has_xpcs) {
  320. priv->hw->xpcs = mdio_xpcs_get_ops();
  321. if (!priv->hw->xpcs) {
  322. err = -ENODEV;
  323. goto bus_register_fail;
  324. }
  325. }
  326. if (mdio_bus_data->needs_reset)
  327. new_bus->reset = &stmmac_mdio_reset;
  328. snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  329. new_bus->name, priv->plat->bus_id);
  330. new_bus->priv = ndev;
  331. new_bus->phy_mask = mdio_bus_data->phy_mask;
  332. new_bus->parent = priv->device;
  333. err = of_mdiobus_register(new_bus, mdio_node);
  334. if (err != 0) {
  335. dev_err(dev, "Cannot register the MDIO bus\n");
  336. goto bus_register_fail;
  337. }
  338. /* Looks like we need a dummy read for XGMAC only and C45 PHYs */
  339. if (priv->plat->has_xgmac)
  340. stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45);
  341. if (priv->plat->phy_node || mdio_node)
  342. goto bus_register_done;
  343. found = 0;
  344. for (addr = 0; addr < max_addr; addr++) {
  345. struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
  346. if (!phydev)
  347. continue;
  348. /*
  349. * If an IRQ was provided to be assigned after
  350. * the bus probe, do it here.
  351. */
  352. if (!mdio_bus_data->irqs &&
  353. (mdio_bus_data->probed_phy_irq > 0)) {
  354. new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
  355. phydev->irq = mdio_bus_data->probed_phy_irq;
  356. }
  357. /*
  358. * If we're going to bind the MAC to this PHY bus,
  359. * and no PHY number was provided to the MAC,
  360. * use the one probed here.
  361. */
  362. if (priv->plat->phy_addr == -1)
  363. priv->plat->phy_addr = addr;
  364. phy_attached_info(phydev);
  365. found = 1;
  366. }
  367. /* Try to probe the XPCS by scanning all addresses. */
  368. if (priv->hw->xpcs) {
  369. struct mdio_xpcs_args *xpcs = &priv->hw->xpcs_args;
  370. int ret, mode = priv->plat->phy_interface;
  371. max_addr = PHY_MAX_ADDR;
  372. xpcs->bus = new_bus;
  373. for (addr = 0; addr < max_addr; addr++) {
  374. xpcs->addr = addr;
  375. ret = stmmac_xpcs_probe(priv, xpcs, mode);
  376. if (!ret) {
  377. found = 1;
  378. break;
  379. }
  380. }
  381. }
  382. if (!found && !mdio_node) {
  383. dev_warn(dev, "No PHY found\n");
  384. mdiobus_unregister(new_bus);
  385. mdiobus_free(new_bus);
  386. return -ENODEV;
  387. }
  388. bus_register_done:
  389. priv->mii = new_bus;
  390. return 0;
  391. bus_register_fail:
  392. mdiobus_free(new_bus);
  393. return err;
  394. }
  395. /**
  396. * stmmac_mdio_unregister
  397. * @ndev: net device structure
  398. * Description: it unregisters the MII bus
  399. */
  400. int stmmac_mdio_unregister(struct net_device *ndev)
  401. {
  402. struct stmmac_priv *priv = netdev_priv(ndev);
  403. if (!priv->mii)
  404. return 0;
  405. mdiobus_unregister(priv->mii);
  406. priv->mii->priv = NULL;
  407. mdiobus_free(priv->mii);
  408. priv->mii = NULL;
  409. return 0;
  410. }