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/drivers/net/ethernet/mellanox/mlx4/cmd.c

http://github.com/mirrors/linux
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   1/*
   2 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5 *
   6 * This software is available to you under a choice of one of two
   7 * licenses.  You may choose to be licensed under the terms of the GNU
   8 * General Public License (GPL) Version 2, available from the file
   9 * COPYING in the main directory of this source tree, or the
  10 * OpenIB.org BSD license below:
  11 *
  12 *     Redistribution and use in source and binary forms, with or
  13 *     without modification, are permitted provided that the following
  14 *     conditions are met:
  15 *
  16 *      - Redistributions of source code must retain the above
  17 *        copyright notice, this list of conditions and the following
  18 *        disclaimer.
  19 *
  20 *      - Redistributions in binary form must reproduce the above
  21 *        copyright notice, this list of conditions and the following
  22 *        disclaimer in the documentation and/or other materials
  23 *        provided with the distribution.
  24 *
  25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32 * SOFTWARE.
  33 */
  34
  35#include <linux/sched.h>
  36#include <linux/slab.h>
  37#include <linux/export.h>
  38#include <linux/pci.h>
  39#include <linux/errno.h>
  40
  41#include <linux/mlx4/cmd.h>
  42#include <linux/mlx4/device.h>
  43#include <linux/semaphore.h>
  44#include <rdma/ib_smi.h>
  45#include <linux/delay.h>
  46#include <linux/etherdevice.h>
  47
  48#include <asm/io.h>
  49
  50#include "mlx4.h"
  51#include "fw.h"
  52#include "fw_qos.h"
  53#include "mlx4_stats.h"
  54
  55#define CMD_POLL_TOKEN 0xffff
  56#define INBOX_MASK	0xffffffffffffff00ULL
  57
  58#define CMD_CHAN_VER 1
  59#define CMD_CHAN_IF_REV 1
  60
  61enum {
  62	/* command completed successfully: */
  63	CMD_STAT_OK		= 0x00,
  64	/* Internal error (such as a bus error) occurred while processing command: */
  65	CMD_STAT_INTERNAL_ERR	= 0x01,
  66	/* Operation/command not supported or opcode modifier not supported: */
  67	CMD_STAT_BAD_OP		= 0x02,
  68	/* Parameter not supported or parameter out of range: */
  69	CMD_STAT_BAD_PARAM	= 0x03,
  70	/* System not enabled or bad system state: */
  71	CMD_STAT_BAD_SYS_STATE	= 0x04,
  72	/* Attempt to access reserved or unallocaterd resource: */
  73	CMD_STAT_BAD_RESOURCE	= 0x05,
  74	/* Requested resource is currently executing a command, or is otherwise busy: */
  75	CMD_STAT_RESOURCE_BUSY	= 0x06,
  76	/* Required capability exceeds device limits: */
  77	CMD_STAT_EXCEED_LIM	= 0x08,
  78	/* Resource is not in the appropriate state or ownership: */
  79	CMD_STAT_BAD_RES_STATE	= 0x09,
  80	/* Index out of range: */
  81	CMD_STAT_BAD_INDEX	= 0x0a,
  82	/* FW image corrupted: */
  83	CMD_STAT_BAD_NVMEM	= 0x0b,
  84	/* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  85	CMD_STAT_ICM_ERROR	= 0x0c,
  86	/* Attempt to modify a QP/EE which is not in the presumed state: */
  87	CMD_STAT_BAD_QP_STATE   = 0x10,
  88	/* Bad segment parameters (Address/Size): */
  89	CMD_STAT_BAD_SEG_PARAM	= 0x20,
  90	/* Memory Region has Memory Windows bound to: */
  91	CMD_STAT_REG_BOUND	= 0x21,
  92	/* HCA local attached memory not present: */
  93	CMD_STAT_LAM_NOT_PRE	= 0x22,
  94	/* Bad management packet (silently discarded): */
  95	CMD_STAT_BAD_PKT	= 0x30,
  96	/* More outstanding CQEs in CQ than new CQ size: */
  97	CMD_STAT_BAD_SIZE	= 0x40,
  98	/* Multi Function device support required: */
  99	CMD_STAT_MULTI_FUNC_REQ	= 0x50,
 100};
 101
 102enum {
 103	HCR_IN_PARAM_OFFSET	= 0x00,
 104	HCR_IN_MODIFIER_OFFSET	= 0x08,
 105	HCR_OUT_PARAM_OFFSET	= 0x0c,
 106	HCR_TOKEN_OFFSET	= 0x14,
 107	HCR_STATUS_OFFSET	= 0x18,
 108
 109	HCR_OPMOD_SHIFT		= 12,
 110	HCR_T_BIT		= 21,
 111	HCR_E_BIT		= 22,
 112	HCR_GO_BIT		= 23
 113};
 114
 115enum {
 116	GO_BIT_TIMEOUT_MSECS	= 10000
 117};
 118
 119enum mlx4_vlan_transition {
 120	MLX4_VLAN_TRANSITION_VST_VST = 0,
 121	MLX4_VLAN_TRANSITION_VST_VGT = 1,
 122	MLX4_VLAN_TRANSITION_VGT_VST = 2,
 123	MLX4_VLAN_TRANSITION_VGT_VGT = 3,
 124};
 125
 126
 127struct mlx4_cmd_context {
 128	struct completion	done;
 129	int			result;
 130	int			next;
 131	u64			out_param;
 132	u16			token;
 133	u8			fw_status;
 134};
 135
 136static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 137				    struct mlx4_vhcr_cmd *in_vhcr);
 138
 139static int mlx4_status_to_errno(u8 status)
 140{
 141	static const int trans_table[] = {
 142		[CMD_STAT_INTERNAL_ERR]	  = -EIO,
 143		[CMD_STAT_BAD_OP]	  = -EPERM,
 144		[CMD_STAT_BAD_PARAM]	  = -EINVAL,
 145		[CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 146		[CMD_STAT_BAD_RESOURCE]	  = -EBADF,
 147		[CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 148		[CMD_STAT_EXCEED_LIM]	  = -ENOMEM,
 149		[CMD_STAT_BAD_RES_STATE]  = -EBADF,
 150		[CMD_STAT_BAD_INDEX]	  = -EBADF,
 151		[CMD_STAT_BAD_NVMEM]	  = -EFAULT,
 152		[CMD_STAT_ICM_ERROR]	  = -ENFILE,
 153		[CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 154		[CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 155		[CMD_STAT_REG_BOUND]	  = -EBUSY,
 156		[CMD_STAT_LAM_NOT_PRE]	  = -EAGAIN,
 157		[CMD_STAT_BAD_PKT]	  = -EINVAL,
 158		[CMD_STAT_BAD_SIZE]	  = -ENOMEM,
 159		[CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 160	};
 161
 162	if (status >= ARRAY_SIZE(trans_table) ||
 163	    (status != CMD_STAT_OK && trans_table[status] == 0))
 164		return -EIO;
 165
 166	return trans_table[status];
 167}
 168
 169static u8 mlx4_errno_to_status(int errno)
 170{
 171	switch (errno) {
 172	case -EPERM:
 173		return CMD_STAT_BAD_OP;
 174	case -EINVAL:
 175		return CMD_STAT_BAD_PARAM;
 176	case -ENXIO:
 177		return CMD_STAT_BAD_SYS_STATE;
 178	case -EBUSY:
 179		return CMD_STAT_RESOURCE_BUSY;
 180	case -ENOMEM:
 181		return CMD_STAT_EXCEED_LIM;
 182	case -ENFILE:
 183		return CMD_STAT_ICM_ERROR;
 184	default:
 185		return CMD_STAT_INTERNAL_ERR;
 186	}
 187}
 188
 189static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
 190				       u8 op_modifier)
 191{
 192	switch (op) {
 193	case MLX4_CMD_UNMAP_ICM:
 194	case MLX4_CMD_UNMAP_ICM_AUX:
 195	case MLX4_CMD_UNMAP_FA:
 196	case MLX4_CMD_2RST_QP:
 197	case MLX4_CMD_HW2SW_EQ:
 198	case MLX4_CMD_HW2SW_CQ:
 199	case MLX4_CMD_HW2SW_SRQ:
 200	case MLX4_CMD_HW2SW_MPT:
 201	case MLX4_CMD_CLOSE_HCA:
 202	case MLX4_QP_FLOW_STEERING_DETACH:
 203	case MLX4_CMD_FREE_RES:
 204	case MLX4_CMD_CLOSE_PORT:
 205		return CMD_STAT_OK;
 206
 207	case MLX4_CMD_QP_ATTACH:
 208		/* On Detach case return success */
 209		if (op_modifier == 0)
 210			return CMD_STAT_OK;
 211		return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 212
 213	default:
 214		return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 215	}
 216}
 217
 218static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
 219{
 220	/* Any error during the closing commands below is considered fatal */
 221	if (op == MLX4_CMD_CLOSE_HCA ||
 222	    op == MLX4_CMD_HW2SW_EQ ||
 223	    op == MLX4_CMD_HW2SW_CQ ||
 224	    op == MLX4_CMD_2RST_QP ||
 225	    op == MLX4_CMD_HW2SW_SRQ ||
 226	    op == MLX4_CMD_SYNC_TPT ||
 227	    op == MLX4_CMD_UNMAP_ICM ||
 228	    op == MLX4_CMD_UNMAP_ICM_AUX ||
 229	    op == MLX4_CMD_UNMAP_FA)
 230		return 1;
 231	/* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
 232	  * CMD_STAT_REG_BOUND.
 233	  * This status indicates that memory region has memory windows bound to it
 234	  * which may result from invalid user space usage and is not fatal.
 235	  */
 236	if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
 237		return 1;
 238	return 0;
 239}
 240
 241static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
 242			       int err)
 243{
 244	/* Only if reset flow is really active return code is based on
 245	  * command, otherwise current error code is returned.
 246	  */
 247	if (mlx4_internal_err_reset) {
 248		mlx4_enter_error_state(dev->persist);
 249		err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 250	}
 251
 252	return err;
 253}
 254
 255static int comm_pending(struct mlx4_dev *dev)
 256{
 257	struct mlx4_priv *priv = mlx4_priv(dev);
 258	u32 status = readl(&priv->mfunc.comm->slave_read);
 259
 260	return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 261}
 262
 263static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 264{
 265	struct mlx4_priv *priv = mlx4_priv(dev);
 266	u32 val;
 267
 268	/* To avoid writing to unknown addresses after the device state was
 269	 * changed to internal error and the function was rest,
 270	 * check the INTERNAL_ERROR flag which is updated under
 271	 * device_state_mutex lock.
 272	 */
 273	mutex_lock(&dev->persist->device_state_mutex);
 274
 275	if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 276		mutex_unlock(&dev->persist->device_state_mutex);
 277		return -EIO;
 278	}
 279
 280	priv->cmd.comm_toggle ^= 1;
 281	val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 282	__raw_writel((__force u32) cpu_to_be32(val),
 283		     &priv->mfunc.comm->slave_write);
 284	mutex_unlock(&dev->persist->device_state_mutex);
 285	return 0;
 286}
 287
 288static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 289		       unsigned long timeout)
 290{
 291	struct mlx4_priv *priv = mlx4_priv(dev);
 292	unsigned long end;
 293	int err = 0;
 294	int ret_from_pending = 0;
 295
 296	/* First, verify that the master reports correct status */
 297	if (comm_pending(dev)) {
 298		mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
 299			  priv->cmd.comm_toggle, cmd);
 300		return -EAGAIN;
 301	}
 302
 303	/* Write command */
 304	down(&priv->cmd.poll_sem);
 305	if (mlx4_comm_cmd_post(dev, cmd, param)) {
 306		/* Only in case the device state is INTERNAL_ERROR,
 307		 * mlx4_comm_cmd_post returns with an error
 308		 */
 309		err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 310		goto out;
 311	}
 312
 313	end = msecs_to_jiffies(timeout) + jiffies;
 314	while (comm_pending(dev) && time_before(jiffies, end))
 315		cond_resched();
 316	ret_from_pending = comm_pending(dev);
 317	if (ret_from_pending) {
 318		/* check if the slave is trying to boot in the middle of
 319		 * FLR process. The only non-zero result in the RESET command
 320		 * is MLX4_DELAY_RESET_SLAVE*/
 321		if ((MLX4_COMM_CMD_RESET == cmd)) {
 322			err = MLX4_DELAY_RESET_SLAVE;
 323			goto out;
 324		} else {
 325			mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
 326				  cmd);
 327			err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 328		}
 329	}
 330
 331	if (err)
 332		mlx4_enter_error_state(dev->persist);
 333out:
 334	up(&priv->cmd.poll_sem);
 335	return err;
 336}
 337
 338static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
 339			      u16 param, u16 op, unsigned long timeout)
 340{
 341	struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 342	struct mlx4_cmd_context *context;
 343	unsigned long end;
 344	int err = 0;
 345
 346	down(&cmd->event_sem);
 347
 348	spin_lock(&cmd->context_lock);
 349	BUG_ON(cmd->free_head < 0);
 350	context = &cmd->context[cmd->free_head];
 351	context->token += cmd->token_mask + 1;
 352	cmd->free_head = context->next;
 353	spin_unlock(&cmd->context_lock);
 354
 355	reinit_completion(&context->done);
 356
 357	if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
 358		/* Only in case the device state is INTERNAL_ERROR,
 359		 * mlx4_comm_cmd_post returns with an error
 360		 */
 361		err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 362		goto out;
 363	}
 364
 365	if (!wait_for_completion_timeout(&context->done,
 366					 msecs_to_jiffies(timeout))) {
 367		mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
 368			  vhcr_cmd, op);
 369		goto out_reset;
 370	}
 371
 372	err = context->result;
 373	if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 374		mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 375			 vhcr_cmd, context->fw_status);
 376		if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 377			goto out_reset;
 378	}
 379
 380	/* wait for comm channel ready
 381	 * this is necessary for prevention the race
 382	 * when switching between event to polling mode
 383	 * Skipping this section in case the device is in FATAL_ERROR state,
 384	 * In this state, no commands are sent via the comm channel until
 385	 * the device has returned from reset.
 386	 */
 387	if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 388		end = msecs_to_jiffies(timeout) + jiffies;
 389		while (comm_pending(dev) && time_before(jiffies, end))
 390			cond_resched();
 391	}
 392	goto out;
 393
 394out_reset:
 395	err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 396	mlx4_enter_error_state(dev->persist);
 397out:
 398	spin_lock(&cmd->context_lock);
 399	context->next = cmd->free_head;
 400	cmd->free_head = context - cmd->context;
 401	spin_unlock(&cmd->context_lock);
 402
 403	up(&cmd->event_sem);
 404	return err;
 405}
 406
 407int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 408		  u16 op, unsigned long timeout)
 409{
 410	if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 411		return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
 412
 413	if (mlx4_priv(dev)->cmd.use_events)
 414		return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
 415	return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 416}
 417
 418static int cmd_pending(struct mlx4_dev *dev)
 419{
 420	u32 status;
 421
 422	if (pci_channel_offline(dev->persist->pdev))
 423		return -EIO;
 424
 425	status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 426
 427	return (status & swab32(1 << HCR_GO_BIT)) ||
 428		(mlx4_priv(dev)->cmd.toggle ==
 429		 !!(status & swab32(1 << HCR_T_BIT)));
 430}
 431
 432static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 433			 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 434			 int event)
 435{
 436	struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 437	u32 __iomem *hcr = cmd->hcr;
 438	int ret = -EIO;
 439	unsigned long end;
 440
 441	mutex_lock(&dev->persist->device_state_mutex);
 442	/* To avoid writing to unknown addresses after the device state was
 443	  * changed to internal error and the chip was reset,
 444	  * check the INTERNAL_ERROR flag which is updated under
 445	  * device_state_mutex lock.
 446	  */
 447	if (pci_channel_offline(dev->persist->pdev) ||
 448	    (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
 449		/*
 450		 * Device is going through error recovery
 451		 * and cannot accept commands.
 452		 */
 453		goto out;
 454	}
 455
 456	end = jiffies;
 457	if (event)
 458		end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 459
 460	while (cmd_pending(dev)) {
 461		if (pci_channel_offline(dev->persist->pdev)) {
 462			/*
 463			 * Device is going through error recovery
 464			 * and cannot accept commands.
 465			 */
 466			goto out;
 467		}
 468
 469		if (time_after_eq(jiffies, end)) {
 470			mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 471			goto out;
 472		}
 473		cond_resched();
 474	}
 475
 476	/*
 477	 * We use writel (instead of something like memcpy_toio)
 478	 * because writes of less than 32 bits to the HCR don't work
 479	 * (and some architectures such as ia64 implement memcpy_toio
 480	 * in terms of writeb).
 481	 */
 482	__raw_writel((__force u32) cpu_to_be32(in_param >> 32),		  hcr + 0);
 483	__raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 484	__raw_writel((__force u32) cpu_to_be32(in_modifier),		  hcr + 2);
 485	__raw_writel((__force u32) cpu_to_be32(out_param >> 32),	  hcr + 3);
 486	__raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 487	__raw_writel((__force u32) cpu_to_be32(token << 16),		  hcr + 5);
 488
 489	/* __raw_writel may not order writes. */
 490	wmb();
 491
 492	__raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)		|
 493					       (cmd->toggle << HCR_T_BIT)	|
 494					       (event ? (1 << HCR_E_BIT) : 0)	|
 495					       (op_modifier << HCR_OPMOD_SHIFT) |
 496					       op), hcr + 6);
 497
 498	cmd->toggle = cmd->toggle ^ 1;
 499
 500	ret = 0;
 501
 502out:
 503	if (ret)
 504		mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
 505			  op, ret, in_param, in_modifier, op_modifier);
 506	mutex_unlock(&dev->persist->device_state_mutex);
 507
 508	return ret;
 509}
 510
 511static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 512			  int out_is_imm, u32 in_modifier, u8 op_modifier,
 513			  u16 op, unsigned long timeout)
 514{
 515	struct mlx4_priv *priv = mlx4_priv(dev);
 516	struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 517	int ret;
 518
 519	mutex_lock(&priv->cmd.slave_cmd_mutex);
 520
 521	vhcr->in_param = cpu_to_be64(in_param);
 522	vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 523	vhcr->in_modifier = cpu_to_be32(in_modifier);
 524	vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 525	vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 526	vhcr->status = 0;
 527	vhcr->flags = !!(priv->cmd.use_events) << 6;
 528
 529	if (mlx4_is_master(dev)) {
 530		ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 531		if (!ret) {
 532			if (out_is_imm) {
 533				if (out_param)
 534					*out_param =
 535						be64_to_cpu(vhcr->out_param);
 536				else {
 537					mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 538						 op);
 539					vhcr->status = CMD_STAT_BAD_PARAM;
 540				}
 541			}
 542			ret = mlx4_status_to_errno(vhcr->status);
 543		}
 544		if (ret &&
 545		    dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 546			ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
 547	} else {
 548		ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
 549				    MLX4_COMM_TIME + timeout);
 550		if (!ret) {
 551			if (out_is_imm) {
 552				if (out_param)
 553					*out_param =
 554						be64_to_cpu(vhcr->out_param);
 555				else {
 556					mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 557						 op);
 558					vhcr->status = CMD_STAT_BAD_PARAM;
 559				}
 560			}
 561			ret = mlx4_status_to_errno(vhcr->status);
 562		} else {
 563			if (dev->persist->state &
 564			    MLX4_DEVICE_STATE_INTERNAL_ERROR)
 565				ret = mlx4_internal_err_ret_value(dev, op,
 566								  op_modifier);
 567			else
 568				mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
 569		}
 570	}
 571
 572	mutex_unlock(&priv->cmd.slave_cmd_mutex);
 573	return ret;
 574}
 575
 576static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 577			 int out_is_imm, u32 in_modifier, u8 op_modifier,
 578			 u16 op, unsigned long timeout)
 579{
 580	struct mlx4_priv *priv = mlx4_priv(dev);
 581	void __iomem *hcr = priv->cmd.hcr;
 582	int err = 0;
 583	unsigned long end;
 584	u32 stat;
 585
 586	down(&priv->cmd.poll_sem);
 587
 588	if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 589		/*
 590		 * Device is going through error recovery
 591		 * and cannot accept commands.
 592		 */
 593		err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 594		goto out;
 595	}
 596
 597	if (out_is_imm && !out_param) {
 598		mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 599			 op);
 600		err = -EINVAL;
 601		goto out;
 602	}
 603
 604	err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 605			    in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 606	if (err)
 607		goto out_reset;
 608
 609	end = msecs_to_jiffies(timeout) + jiffies;
 610	while (cmd_pending(dev) && time_before(jiffies, end)) {
 611		if (pci_channel_offline(dev->persist->pdev)) {
 612			/*
 613			 * Device is going through error recovery
 614			 * and cannot accept commands.
 615			 */
 616			err = -EIO;
 617			goto out_reset;
 618		}
 619
 620		if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
 621			err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 622			goto out;
 623		}
 624
 625		cond_resched();
 626	}
 627
 628	if (cmd_pending(dev)) {
 629		mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 630			  op);
 631		err = -EIO;
 632		goto out_reset;
 633	}
 634
 635	if (out_is_imm)
 636		*out_param =
 637			(u64) be32_to_cpu((__force __be32)
 638					  __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 639			(u64) be32_to_cpu((__force __be32)
 640					  __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 641	stat = be32_to_cpu((__force __be32)
 642			   __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 643	err = mlx4_status_to_errno(stat);
 644	if (err) {
 645		mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 646			 op, stat);
 647		if (mlx4_closing_cmd_fatal_error(op, stat))
 648			goto out_reset;
 649		goto out;
 650	}
 651
 652out_reset:
 653	if (err)
 654		err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 655out:
 656	up(&priv->cmd.poll_sem);
 657	return err;
 658}
 659
 660void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 661{
 662	struct mlx4_priv *priv = mlx4_priv(dev);
 663	struct mlx4_cmd_context *context =
 664		&priv->cmd.context[token & priv->cmd.token_mask];
 665
 666	/* previously timed out command completing at long last */
 667	if (token != context->token)
 668		return;
 669
 670	context->fw_status = status;
 671	context->result    = mlx4_status_to_errno(status);
 672	context->out_param = out_param;
 673
 674	complete(&context->done);
 675}
 676
 677static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 678			 int out_is_imm, u32 in_modifier, u8 op_modifier,
 679			 u16 op, unsigned long timeout)
 680{
 681	struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 682	struct mlx4_cmd_context *context;
 683	long ret_wait;
 684	int err = 0;
 685
 686	down(&cmd->event_sem);
 687
 688	spin_lock(&cmd->context_lock);
 689	BUG_ON(cmd->free_head < 0);
 690	context = &cmd->context[cmd->free_head];
 691	context->token += cmd->token_mask + 1;
 692	cmd->free_head = context->next;
 693	spin_unlock(&cmd->context_lock);
 694
 695	if (out_is_imm && !out_param) {
 696		mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
 697			 op);
 698		err = -EINVAL;
 699		goto out;
 700	}
 701
 702	reinit_completion(&context->done);
 703
 704	err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 705			    in_modifier, op_modifier, op, context->token, 1);
 706	if (err)
 707		goto out_reset;
 708
 709	if (op == MLX4_CMD_SENSE_PORT) {
 710		ret_wait =
 711			wait_for_completion_interruptible_timeout(&context->done,
 712								  msecs_to_jiffies(timeout));
 713		if (ret_wait < 0) {
 714			context->fw_status = 0;
 715			context->out_param = 0;
 716			context->result = 0;
 717		}
 718	} else {
 719		ret_wait = (long)wait_for_completion_timeout(&context->done,
 720							     msecs_to_jiffies(timeout));
 721	}
 722	if (!ret_wait) {
 723		mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
 724			  op);
 725		if (op == MLX4_CMD_NOP) {
 726			err = -EBUSY;
 727			goto out;
 728		} else {
 729			err = -EIO;
 730			goto out_reset;
 731		}
 732	}
 733
 734	err = context->result;
 735	if (err) {
 736		/* Since we do not want to have this error message always
 737		 * displayed at driver start when there are ConnectX2 HCAs
 738		 * on the host, we deprecate the error message for this
 739		 * specific command/input_mod/opcode_mod/fw-status to be debug.
 740		 */
 741		if (op == MLX4_CMD_SET_PORT &&
 742		    (in_modifier == 1 || in_modifier == 2) &&
 743		    op_modifier == MLX4_SET_PORT_IB_OPCODE &&
 744		    context->fw_status == CMD_STAT_BAD_SIZE)
 745			mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
 746				 op, context->fw_status);
 747		else
 748			mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 749				 op, context->fw_status);
 750		if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 751			err = mlx4_internal_err_ret_value(dev, op, op_modifier);
 752		else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
 753			goto out_reset;
 754
 755		goto out;
 756	}
 757
 758	if (out_is_imm)
 759		*out_param = context->out_param;
 760
 761out_reset:
 762	if (err)
 763		err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
 764out:
 765	spin_lock(&cmd->context_lock);
 766	context->next = cmd->free_head;
 767	cmd->free_head = context - cmd->context;
 768	spin_unlock(&cmd->context_lock);
 769
 770	up(&cmd->event_sem);
 771	return err;
 772}
 773
 774int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 775	       int out_is_imm, u32 in_modifier, u8 op_modifier,
 776	       u16 op, unsigned long timeout, int native)
 777{
 778	if (pci_channel_offline(dev->persist->pdev))
 779		return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
 780
 781	if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 782		int ret;
 783
 784		if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
 785			return mlx4_internal_err_ret_value(dev, op,
 786							  op_modifier);
 787		down_read(&mlx4_priv(dev)->cmd.switch_sem);
 788		if (mlx4_priv(dev)->cmd.use_events)
 789			ret = mlx4_cmd_wait(dev, in_param, out_param,
 790					    out_is_imm, in_modifier,
 791					    op_modifier, op, timeout);
 792		else
 793			ret = mlx4_cmd_poll(dev, in_param, out_param,
 794					    out_is_imm, in_modifier,
 795					    op_modifier, op, timeout);
 796
 797		up_read(&mlx4_priv(dev)->cmd.switch_sem);
 798		return ret;
 799	}
 800	return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 801			      in_modifier, op_modifier, op, timeout);
 802}
 803EXPORT_SYMBOL_GPL(__mlx4_cmd);
 804
 805
 806int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 807{
 808	return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 809			MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 810}
 811
 812static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 813			   int slave, u64 slave_addr,
 814			   int size, int is_read)
 815{
 816	u64 in_param;
 817	u64 out_param;
 818
 819	if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 820	    (slave & ~0x7f) | (size & 0xff)) {
 821		mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
 822			 slave_addr, master_addr, slave, size);
 823		return -EINVAL;
 824	}
 825
 826	if (is_read) {
 827		in_param = (u64) slave | slave_addr;
 828		out_param = (u64) dev->caps.function | master_addr;
 829	} else {
 830		in_param = (u64) dev->caps.function | master_addr;
 831		out_param = (u64) slave | slave_addr;
 832	}
 833
 834	return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 835			    MLX4_CMD_ACCESS_MEM,
 836			    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 837}
 838
 839static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 840			       struct mlx4_cmd_mailbox *inbox,
 841			       struct mlx4_cmd_mailbox *outbox)
 842{
 843	struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 844	struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 845	int err;
 846	int i;
 847
 848	if (index & 0x1f)
 849		return -EINVAL;
 850
 851	in_mad->attr_mod = cpu_to_be32(index / 32);
 852
 853	err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 854			   MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 855			   MLX4_CMD_NATIVE);
 856	if (err)
 857		return err;
 858
 859	for (i = 0; i < 32; ++i)
 860		pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 861
 862	return err;
 863}
 864
 865static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 866			       struct mlx4_cmd_mailbox *inbox,
 867			       struct mlx4_cmd_mailbox *outbox)
 868{
 869	int i;
 870	int err;
 871
 872	for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 873		err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 874		if (err)
 875			return err;
 876	}
 877
 878	return 0;
 879}
 880#define PORT_CAPABILITY_LOCATION_IN_SMP 20
 881#define PORT_STATE_OFFSET 32
 882
 883static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 884{
 885	if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 886		return IB_PORT_ACTIVE;
 887	else
 888		return IB_PORT_DOWN;
 889}
 890
 891static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 892				struct mlx4_vhcr *vhcr,
 893				struct mlx4_cmd_mailbox *inbox,
 894				struct mlx4_cmd_mailbox *outbox,
 895				struct mlx4_cmd_info *cmd)
 896{
 897	struct ib_smp *smp = inbox->buf;
 898	u32 index;
 899	u8 port, slave_port;
 900	u8 opcode_modifier;
 901	u16 *table;
 902	int err;
 903	int vidx, pidx;
 904	int network_view;
 905	struct mlx4_priv *priv = mlx4_priv(dev);
 906	struct ib_smp *outsmp = outbox->buf;
 907	__be16 *outtab = (__be16 *)(outsmp->data);
 908	__be32 slave_cap_mask;
 909	__be64 slave_node_guid;
 910
 911	slave_port = vhcr->in_modifier;
 912	port = mlx4_slave_convert_port(dev, slave, slave_port);
 913
 914	/* network-view bit is for driver use only, and should not be passed to FW */
 915	opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
 916	network_view = !!(vhcr->op_modifier & 0x8);
 917
 918	if (smp->base_version == 1 &&
 919	    smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 920	    smp->class_version == 1) {
 921		/* host view is paravirtualized */
 922		if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
 923			if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 924				index = be32_to_cpu(smp->attr_mod);
 925				if (port < 1 || port > dev->caps.num_ports)
 926					return -EINVAL;
 927				table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
 928						sizeof(*table) * 32, GFP_KERNEL);
 929
 930				if (!table)
 931					return -ENOMEM;
 932				/* need to get the full pkey table because the paravirtualized
 933				 * pkeys may be scattered among several pkey blocks.
 934				 */
 935				err = get_full_pkey_table(dev, port, table, inbox, outbox);
 936				if (!err) {
 937					for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 938						pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 939						outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 940					}
 941				}
 942				kfree(table);
 943				return err;
 944			}
 945			if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 946				/*get the slave specific caps:*/
 947				/*do the command */
 948				smp->attr_mod = cpu_to_be32(port);
 949				err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 950					    port, opcode_modifier,
 951					    vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 952				/* modify the response for slaves */
 953				if (!err && slave != mlx4_master_func_num(dev)) {
 954					u8 *state = outsmp->data + PORT_STATE_OFFSET;
 955
 956					*state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 957					slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 958					memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 959				}
 960				return err;
 961			}
 962			if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 963				__be64 guid = mlx4_get_admin_guid(dev, slave,
 964								  port);
 965
 966				/* set the PF admin guid to the FW/HW burned
 967				 * GUID, if it wasn't yet set
 968				 */
 969				if (slave == 0 && guid == 0) {
 970					smp->attr_mod = 0;
 971					err = mlx4_cmd_box(dev,
 972							   inbox->dma,
 973							   outbox->dma,
 974							   vhcr->in_modifier,
 975							   opcode_modifier,
 976							   vhcr->op,
 977							   MLX4_CMD_TIME_CLASS_C,
 978							   MLX4_CMD_NATIVE);
 979					if (err)
 980						return err;
 981					mlx4_set_admin_guid(dev,
 982							    *(__be64 *)outsmp->
 983							    data, slave, port);
 984				} else {
 985					memcpy(outsmp->data, &guid, 8);
 986				}
 987
 988				/* clean all other gids */
 989				memset(outsmp->data + 8, 0, 56);
 990				return 0;
 991			}
 992			if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 993				err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 994					     port, opcode_modifier,
 995					     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 996				if (!err) {
 997					slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 998					memcpy(outsmp->data + 12, &slave_node_guid, 8);
 999				}
1000				return err;
1001			}
1002		}
1003	}
1004
1005	/* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
1006	 * These are the MADs used by ib verbs (such as ib_query_gids).
1007	 */
1008	if (slave != mlx4_master_func_num(dev) &&
1009	    !mlx4_vf_smi_enabled(dev, slave, port)) {
1010		if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
1011		      smp->method == IB_MGMT_METHOD_GET) || network_view) {
1012			mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
1013				 slave, smp->mgmt_class, smp->method,
1014				 network_view ? "Network" : "Host",
1015				 be16_to_cpu(smp->attr_id));
1016			return -EPERM;
1017		}
1018	}
1019
1020	return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
1021				    vhcr->in_modifier, opcode_modifier,
1022				    vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1023}
1024
1025static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
1026		     struct mlx4_vhcr *vhcr,
1027		     struct mlx4_cmd_mailbox *inbox,
1028		     struct mlx4_cmd_mailbox *outbox,
1029		     struct mlx4_cmd_info *cmd)
1030{
1031	return -EPERM;
1032}
1033
1034int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1035		     struct mlx4_vhcr *vhcr,
1036		     struct mlx4_cmd_mailbox *inbox,
1037		     struct mlx4_cmd_mailbox *outbox,
1038		     struct mlx4_cmd_info *cmd)
1039{
1040	u64 in_param;
1041	u64 out_param;
1042	int err;
1043
1044	in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1045	out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1046	if (cmd->encode_slave_id) {
1047		in_param &= 0xffffffffffffff00ll;
1048		in_param |= slave;
1049	}
1050
1051	err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1052			 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1053			 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1054
1055	if (cmd->out_is_imm)
1056		vhcr->out_param = out_param;
1057
1058	return err;
1059}
1060
1061static struct mlx4_cmd_info cmd_info[] = {
1062	{
1063		.opcode = MLX4_CMD_QUERY_FW,
1064		.has_inbox = false,
1065		.has_outbox = true,
1066		.out_is_imm = false,
1067		.encode_slave_id = false,
1068		.verify = NULL,
1069		.wrapper = mlx4_QUERY_FW_wrapper
1070	},
1071	{
1072		.opcode = MLX4_CMD_QUERY_HCA,
1073		.has_inbox = false,
1074		.has_outbox = true,
1075		.out_is_imm = false,
1076		.encode_slave_id = false,
1077		.verify = NULL,
1078		.wrapper = NULL
1079	},
1080	{
1081		.opcode = MLX4_CMD_QUERY_DEV_CAP,
1082		.has_inbox = false,
1083		.has_outbox = true,
1084		.out_is_imm = false,
1085		.encode_slave_id = false,
1086		.verify = NULL,
1087		.wrapper = mlx4_QUERY_DEV_CAP_wrapper
1088	},
1089	{
1090		.opcode = MLX4_CMD_QUERY_FUNC_CAP,
1091		.has_inbox = false,
1092		.has_outbox = true,
1093		.out_is_imm = false,
1094		.encode_slave_id = false,
1095		.verify = NULL,
1096		.wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1097	},
1098	{
1099		.opcode = MLX4_CMD_QUERY_ADAPTER,
1100		.has_inbox = false,
1101		.has_outbox = true,
1102		.out_is_imm = false,
1103		.encode_slave_id = false,
1104		.verify = NULL,
1105		.wrapper = NULL
1106	},
1107	{
1108		.opcode = MLX4_CMD_INIT_PORT,
1109		.has_inbox = false,
1110		.has_outbox = false,
1111		.out_is_imm = false,
1112		.encode_slave_id = false,
1113		.verify = NULL,
1114		.wrapper = mlx4_INIT_PORT_wrapper
1115	},
1116	{
1117		.opcode = MLX4_CMD_CLOSE_PORT,
1118		.has_inbox = false,
1119		.has_outbox = false,
1120		.out_is_imm  = false,
1121		.encode_slave_id = false,
1122		.verify = NULL,
1123		.wrapper = mlx4_CLOSE_PORT_wrapper
1124	},
1125	{
1126		.opcode = MLX4_CMD_QUERY_PORT,
1127		.has_inbox = false,
1128		.has_outbox = true,
1129		.out_is_imm = false,
1130		.encode_slave_id = false,
1131		.verify = NULL,
1132		.wrapper = mlx4_QUERY_PORT_wrapper
1133	},
1134	{
1135		.opcode = MLX4_CMD_SET_PORT,
1136		.has_inbox = true,
1137		.has_outbox = false,
1138		.out_is_imm = false,
1139		.encode_slave_id = false,
1140		.verify = NULL,
1141		.wrapper = mlx4_SET_PORT_wrapper
1142	},
1143	{
1144		.opcode = MLX4_CMD_MAP_EQ,
1145		.has_inbox = false,
1146		.has_outbox = false,
1147		.out_is_imm = false,
1148		.encode_slave_id = false,
1149		.verify = NULL,
1150		.wrapper = mlx4_MAP_EQ_wrapper
1151	},
1152	{
1153		.opcode = MLX4_CMD_SW2HW_EQ,
1154		.has_inbox = true,
1155		.has_outbox = false,
1156		.out_is_imm = false,
1157		.encode_slave_id = true,
1158		.verify = NULL,
1159		.wrapper = mlx4_SW2HW_EQ_wrapper
1160	},
1161	{
1162		.opcode = MLX4_CMD_HW_HEALTH_CHECK,
1163		.has_inbox = false,
1164		.has_outbox = false,
1165		.out_is_imm = false,
1166		.encode_slave_id = false,
1167		.verify = NULL,
1168		.wrapper = NULL
1169	},
1170	{
1171		.opcode = MLX4_CMD_NOP,
1172		.has_inbox = false,
1173		.has_outbox = false,
1174		.out_is_imm = false,
1175		.encode_slave_id = false,
1176		.verify = NULL,
1177		.wrapper = NULL
1178	},
1179	{
1180		.opcode = MLX4_CMD_CONFIG_DEV,
1181		.has_inbox = false,
1182		.has_outbox = true,
1183		.out_is_imm = false,
1184		.encode_slave_id = false,
1185		.verify = NULL,
1186		.wrapper = mlx4_CONFIG_DEV_wrapper
1187	},
1188	{
1189		.opcode = MLX4_CMD_ALLOC_RES,
1190		.has_inbox = false,
1191		.has_outbox = false,
1192		.out_is_imm = true,
1193		.encode_slave_id = false,
1194		.verify = NULL,
1195		.wrapper = mlx4_ALLOC_RES_wrapper
1196	},
1197	{
1198		.opcode = MLX4_CMD_FREE_RES,
1199		.has_inbox = false,
1200		.has_outbox = false,
1201		.out_is_imm = false,
1202		.encode_slave_id = false,
1203		.verify = NULL,
1204		.wrapper = mlx4_FREE_RES_wrapper
1205	},
1206	{
1207		.opcode = MLX4_CMD_SW2HW_MPT,
1208		.has_inbox = true,
1209		.has_outbox = false,
1210		.out_is_imm = false,
1211		.encode_slave_id = true,
1212		.verify = NULL,
1213		.wrapper = mlx4_SW2HW_MPT_wrapper
1214	},
1215	{
1216		.opcode = MLX4_CMD_QUERY_MPT,
1217		.has_inbox = false,
1218		.has_outbox = true,
1219		.out_is_imm = false,
1220		.encode_slave_id = false,
1221		.verify = NULL,
1222		.wrapper = mlx4_QUERY_MPT_wrapper
1223	},
1224	{
1225		.opcode = MLX4_CMD_HW2SW_MPT,
1226		.has_inbox = false,
1227		.has_outbox = false,
1228		.out_is_imm = false,
1229		.encode_slave_id = false,
1230		.verify = NULL,
1231		.wrapper = mlx4_HW2SW_MPT_wrapper
1232	},
1233	{
1234		.opcode = MLX4_CMD_READ_MTT,
1235		.has_inbox = false,
1236		.has_outbox = true,
1237		.out_is_imm = false,
1238		.encode_slave_id = false,
1239		.verify = NULL,
1240		.wrapper = NULL
1241	},
1242	{
1243		.opcode = MLX4_CMD_WRITE_MTT,
1244		.has_inbox = true,
1245		.has_outbox = false,
1246		.out_is_imm = false,
1247		.encode_slave_id = false,
1248		.verify = NULL,
1249		.wrapper = mlx4_WRITE_MTT_wrapper
1250	},
1251	{
1252		.opcode = MLX4_CMD_SYNC_TPT,
1253		.has_inbox = true,
1254		.has_outbox = false,
1255		.out_is_imm = false,
1256		.encode_slave_id = false,
1257		.verify = NULL,
1258		.wrapper = NULL
1259	},
1260	{
1261		.opcode = MLX4_CMD_HW2SW_EQ,
1262		.has_inbox = false,
1263		.has_outbox = false,
1264		.out_is_imm = false,
1265		.encode_slave_id = true,
1266		.verify = NULL,
1267		.wrapper = mlx4_HW2SW_EQ_wrapper
1268	},
1269	{
1270		.opcode = MLX4_CMD_QUERY_EQ,
1271		.has_inbox = false,
1272		.has_outbox = true,
1273		.out_is_imm = false,
1274		.encode_slave_id = true,
1275		.verify = NULL,
1276		.wrapper = mlx4_QUERY_EQ_wrapper
1277	},
1278	{
1279		.opcode = MLX4_CMD_SW2HW_CQ,
1280		.has_inbox = true,
1281		.has_outbox = false,
1282		.out_is_imm = false,
1283		.encode_slave_id = true,
1284		.verify = NULL,
1285		.wrapper = mlx4_SW2HW_CQ_wrapper
1286	},
1287	{
1288		.opcode = MLX4_CMD_HW2SW_CQ,
1289		.has_inbox = false,
1290		.has_outbox = false,
1291		.out_is_imm = false,
1292		.encode_slave_id = false,
1293		.verify = NULL,
1294		.wrapper = mlx4_HW2SW_CQ_wrapper
1295	},
1296	{
1297		.opcode = MLX4_CMD_QUERY_CQ,
1298		.has_inbox = false,
1299		.has_outbox = true,
1300		.out_is_imm = false,
1301		.encode_slave_id = false,
1302		.verify = NULL,
1303		.wrapper = mlx4_QUERY_CQ_wrapper
1304	},
1305	{
1306		.opcode = MLX4_CMD_MODIFY_CQ,
1307		.has_inbox = true,
1308		.has_outbox = false,
1309		.out_is_imm = true,
1310		.encode_slave_id = false,
1311		.verify = NULL,
1312		.wrapper = mlx4_MODIFY_CQ_wrapper
1313	},
1314	{
1315		.opcode = MLX4_CMD_SW2HW_SRQ,
1316		.has_inbox = true,
1317		.has_outbox = false,
1318		.out_is_imm = false,
1319		.encode_slave_id = true,
1320		.verify = NULL,
1321		.wrapper = mlx4_SW2HW_SRQ_wrapper
1322	},
1323	{
1324		.opcode = MLX4_CMD_HW2SW_SRQ,
1325		.has_inbox = false,
1326		.has_outbox = false,
1327		.out_is_imm = false,
1328		.encode_slave_id = false,
1329		.verify = NULL,
1330		.wrapper = mlx4_HW2SW_SRQ_wrapper
1331	},
1332	{
1333		.opcode = MLX4_CMD_QUERY_SRQ,
1334		.has_inbox = false,
1335		.has_outbox = true,
1336		.out_is_imm = false,
1337		.encode_slave_id = false,
1338		.verify = NULL,
1339		.wrapper = mlx4_QUERY_SRQ_wrapper
1340	},
1341	{
1342		.opcode = MLX4_CMD_ARM_SRQ,
1343		.has_inbox = false,
1344		.has_outbox = false,
1345		.out_is_imm = false,
1346		.encode_slave_id = false,
1347		.verify = NULL,
1348		.wrapper = mlx4_ARM_SRQ_wrapper
1349	},
1350	{
1351		.opcode = MLX4_CMD_RST2INIT_QP,
1352		.has_inbox = true,
1353		.has_outbox = false,
1354		.out_is_imm = false,
1355		.encode_slave_id = true,
1356		.verify = NULL,
1357		.wrapper = mlx4_RST2INIT_QP_wrapper
1358	},
1359	{
1360		.opcode = MLX4_CMD_INIT2INIT_QP,
1361		.has_inbox = true,
1362		.has_outbox = false,
1363		.out_is_imm = false,
1364		.encode_slave_id = false,
1365		.verify = NULL,
1366		.wrapper = mlx4_INIT2INIT_QP_wrapper
1367	},
1368	{
1369		.opcode = MLX4_CMD_INIT2RTR_QP,
1370		.has_inbox = true,
1371		.has_outbox = false,
1372		.out_is_imm = false,
1373		.encode_slave_id = false,
1374		.verify = NULL,
1375		.wrapper = mlx4_INIT2RTR_QP_wrapper
1376	},
1377	{
1378		.opcode = MLX4_CMD_RTR2RTS_QP,
1379		.has_inbox = true,
1380		.has_outbox = false,
1381		.out_is_imm = false,
1382		.encode_slave_id = false,
1383		.verify = NULL,
1384		.wrapper = mlx4_RTR2RTS_QP_wrapper
1385	},
1386	{
1387		.opcode = MLX4_CMD_RTS2RTS_QP,
1388		.has_inbox = true,
1389		.has_outbox = false,
1390		.out_is_imm = false,
1391		.encode_slave_id = false,
1392		.verify = NULL,
1393		.wrapper = mlx4_RTS2RTS_QP_wrapper
1394	},
1395	{
1396		.opcode = MLX4_CMD_SQERR2RTS_QP,
1397		.has_inbox = true,
1398		.has_outbox = false,
1399		.out_is_imm = false,
1400		.encode_slave_id = false,
1401		.verify = NULL,
1402		.wrapper = mlx4_SQERR2RTS_QP_wrapper
1403	},
1404	{
1405		.opcode = MLX4_CMD_2ERR_QP,
1406		.has_inbox = false,
1407		.has_outbox = false,
1408		.out_is_imm = false,
1409		.encode_slave_id = false,
1410		.verify = NULL,
1411		.wrapper = mlx4_GEN_QP_wrapper
1412	},
1413	{
1414		.opcode = MLX4_CMD_RTS2SQD_QP,
1415		.has_inbox = false,
1416		.has_outbox = false,
1417		.out_is_imm = false,
1418		.encode_slave_id = false,
1419		.verify = NULL,
1420		.wrapper = mlx4_GEN_QP_wrapper
1421	},
1422	{
1423		.opcode = MLX4_CMD_SQD2SQD_QP,
1424		.has_inbox = true,
1425		.has_outbox = false,
1426		.out_is_imm = false,
1427		.encode_slave_id = false,
1428		.verify = NULL,
1429		.wrapper = mlx4_SQD2SQD_QP_wrapper
1430	},
1431	{
1432		.opcode = MLX4_CMD_SQD2RTS_QP,
1433		.has_inbox = true,
1434		.has_outbox = false,
1435		.out_is_imm = false,
1436		.encode_slave_id = false,
1437		.verify = NULL,
1438		.wrapper = mlx4_SQD2RTS_QP_wrapper
1439	},
1440	{
1441		.opcode = MLX4_CMD_2RST_QP,
1442		.has_inbox = false,
1443		.has_outbox = false,
1444		.out_is_imm = false,
1445		.encode_slave_id = false,
1446		.verify = NULL,
1447		.wrapper = mlx4_2RST_QP_wrapper
1448	},
1449	{
1450		.opcode = MLX4_CMD_QUERY_QP,
1451		.has_inbox = false,
1452		.has_outbox = true,
1453		.out_is_imm = false,
1454		.encode_slave_id = false,
1455		.verify = NULL,
1456		.wrapper = mlx4_GEN_QP_wrapper
1457	},
1458	{
1459		.opcode = MLX4_CMD_SUSPEND_QP,
1460		.has_inbox = false,
1461		.has_outbox = false,
1462		.out_is_imm = false,
1463		.encode_slave_id = false,
1464		.verify = NULL,
1465		.wrapper = mlx4_GEN_QP_wrapper
1466	},
1467	{
1468		.opcode = MLX4_CMD_UNSUSPEND_QP,
1469		.has_inbox = false,
1470		.has_outbox = false,
1471		.out_is_imm = false,
1472		.encode_slave_id = false,
1473		.verify = NULL,
1474		.wrapper = mlx4_GEN_QP_wrapper
1475	},
1476	{
1477		.opcode = MLX4_CMD_UPDATE_QP,
1478		.has_inbox = true,
1479		.has_outbox = false,
1480		.out_is_imm = false,
1481		.encode_slave_id = false,
1482		.verify = NULL,
1483		.wrapper = mlx4_UPDATE_QP_wrapper
1484	},
1485	{
1486		.opcode = MLX4_CMD_GET_OP_REQ,
1487		.has_inbox = false,
1488		.has_outbox = false,
1489		.out_is_imm = false,
1490		.encode_slave_id = false,
1491		.verify = NULL,
1492		.wrapper = mlx4_CMD_EPERM_wrapper,
1493	},
1494	{
1495		.opcode = MLX4_CMD_ALLOCATE_VPP,
1496		.has_inbox = false,
1497		.has_outbox = true,
1498		.out_is_imm = false,
1499		.encode_slave_id = false,
1500		.verify = NULL,
1501		.wrapper = mlx4_CMD_EPERM_wrapper,
1502	},
1503	{
1504		.opcode = MLX4_CMD_SET_VPORT_QOS,
1505		.has_inbox = false,
1506		.has_outbox = true,
1507		.out_is_imm = false,
1508		.encode_slave_id = false,
1509		.verify = NULL,
1510		.wrapper = mlx4_CMD_EPERM_wrapper,
1511	},
1512	{
1513		.opcode = MLX4_CMD_CONF_SPECIAL_QP,
1514		.has_inbox = false,
1515		.has_outbox = false,
1516		.out_is_imm = false,
1517		.encode_slave_id = false,
1518		.verify = NULL, /* XXX verify: only demux can do this */
1519		.wrapper = NULL
1520	},
1521	{
1522		.opcode = MLX4_CMD_MAD_IFC,
1523		.has_inbox = true,
1524		.has_outbox = true,
1525		.out_is_imm = false,
1526		.encode_slave_id = false,
1527		.verify = NULL,
1528		.wrapper = mlx4_MAD_IFC_wrapper
1529	},
1530	{
1531		.opcode = MLX4_CMD_MAD_DEMUX,
1532		.has_inbox = false,
1533		.has_outbox = false,
1534		.out_is_imm = false,
1535		.encode_slave_id = false,
1536		.verify = NULL,
1537		.wrapper = mlx4_CMD_EPERM_wrapper
1538	},
1539	{
1540		.opcode = MLX4_CMD_QUERY_IF_STAT,
1541		.has_inbox = false,
1542		.has_outbox = true,
1543		.out_is_imm = false,
1544		.encode_slave_id = false,
1545		.verify = NULL,
1546		.wrapper = mlx4_QUERY_IF_STAT_wrapper
1547	},
1548	{
1549		.opcode = MLX4_CMD_ACCESS_REG,
1550		.has_inbox = true,
1551		.has_outbox = true,
1552		.out_is_imm = false,
1553		.encode_slave_id = false,
1554		.verify = NULL,
1555		.wrapper = mlx4_ACCESS_REG_wrapper,
1556	},
1557	{
1558		.opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1559		.has_inbox = false,
1560		.has_outbox = false,
1561		.out_is_imm = false,
1562		.encode_slave_id = false,
1563		.verify = NULL,
1564		.wrapper = mlx4_CMD_EPERM_wrapper,
1565	},
1566	/* Native multicast commands are not available for guests */
1567	{
1568		.opcode = MLX4_CMD_QP_ATTACH,
1569		.has_inbox = true,
1570		.has_outbox = false,
1571		.out_is_imm = false,
1572		.encode_slave_id = false,
1573		.verify = NULL,
1574		.wrapper = mlx4_QP_ATTACH_wrapper
1575	},
1576	{
1577		.opcode = MLX4_CMD_PROMISC,
1578		.has_inbox = false,
1579		.has_outbox = false,
1580		.out_is_imm = false,
1581		.encode_slave_id = false,
1582		.verify = NULL,
1583		.wrapper = mlx4_PROMISC_wrapper
1584	},
1585	/* Ethernet specific commands */
1586	{
1587		.opcode = MLX4_CMD_SET_VLAN_FLTR,
1588		.has_inbox = true,
1589		.has_outbox = false,
1590		.out_is_imm = false,
1591		.encode_slave_id = false,
1592		.verify = NULL,
1593		.wrapper = mlx4_SET_VLAN_FLTR_wrapper
1594	},
1595	{
1596		.opcode = MLX4_CMD_SET_MCAST_FLTR,
1597		.has_inbox = false,
1598		.has_outbox = false,
1599		.out_is_imm = false,
1600		.encode_slave_id = false,
1601		.verify = NULL,
1602		.wrapper = mlx4_SET_MCAST_FLTR_wrapper
1603	},
1604	{
1605		.opcode = MLX4_CMD_DUMP_ETH_STATS,
1606		.has_inbox = false,
1607		.has_outbox = true,
1608		.out_is_imm = false,
1609		.encode_slave_id = false,
1610		.verify = NULL,
1611		.wrapper = mlx4_DUMP_ETH_STATS_wrapper
1612	},
1613	{
1614		.opcode = MLX4_CMD_INFORM_FLR_DONE,
1615		.has_inbox = false,
1616		.has_outbox = false,
1617		.out_is_imm = false,
1618		.encode_slave_id = false,
1619		.verify = NULL,
1620		.wrapper = NULL
1621	},
1622	/* flow steering commands */
1623	{
1624		.opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1625		.has_inbox = true,
1626		.has_outbox = false,
1627		.out_is_imm = true,
1628		.encode_slave_id = false,
1629		.verify = NULL,
1630		.wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1631	},
1632	{
1633		.opcode = MLX4_QP_FLOW_STEERING_DETACH,
1634		.has_inbox = false,
1635		.has_outbox = false,
1636		.out_is_imm = false,
1637		.encode_slave_id = false,
1638		.verify = NULL,
1639		.wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1640	},
1641	{
1642		.opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1643		.has_inbox = false,
1644		.has_outbox = false,
1645		.out_is_imm = false,
1646		.encode_slave_id = false,
1647		.verify = NULL,
1648		.wrapper = mlx4_CMD_EPERM_wrapper
1649	},
1650	{
1651		.opcode = MLX4_CMD_VIRT_PORT_MAP,
1652		.has_inbox = false,
1653		.has_outbox = false,
1654		.out_is_imm = false,
1655		.encode_slave_id = false,
1656		.verify = NULL,
1657		.wrapper = mlx4_CMD_EPERM_wrapper
1658	},
1659};
1660
1661static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1662				    struct mlx4_vhcr_cmd *in_vhcr)
1663{
1664	struct mlx4_priv *priv = mlx4_priv(dev);
1665	struct mlx4_cmd_info *cmd = NULL;
1666	struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1667	struct mlx4_vhcr *vhcr;
1668	struct mlx4_cmd_mailbox *inbox = NULL;
1669	struct mlx4_cmd_mailbox *outbox = NULL;
1670	u64 in_param;
1671	u64 out_param;
1672	int ret = 0;
1673	int i;
1674	int err = 0;
1675
1676	/* Create sw representation of Virtual HCR */
1677	vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1678	if (!vhcr)
1679		return -ENOMEM;
1680
1681	/* DMA in the vHCR */
1682	if (!in_vhcr) {
1683		ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1684				      priv->mfunc.master.slave_state[slave].vhcr_dma,
1685				      ALIGN(sizeof(struct mlx4_vhcr_cmd),
1686					    MLX4_ACCESS_MEM_ALIGN), 1);
1687		if (ret) {
1688			if (!(dev->persist->state &
1689			    MLX4_DEVICE_STATE_INTERNAL_ERROR))
1690				mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1691					 __func__, ret);
1692			kfree(vhcr);
1693			return ret;
1694		}
1695	}
1696
1697	/* Fill SW VHCR fields */
1698	vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1699	vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1700	vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1701	vhcr->token = be16_to_cpu(vhcr_cmd->token);
1702	vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1703	vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1704	vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1705
1706	/* Lookup command */
1707	for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1708		if (vhcr->op == cmd_info[i].opcode) {
1709			cmd = &cmd_info[i];
1710			break;
1711		}
1712	}
1713	if (!cmd) {
1714		mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1715			 vhcr->op, slave);
1716		vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1717		goto out_status;
1718	}
1719
1720	/* Read inbox */
1721	if (cmd->has_inbox) {
1722		vhcr->in_param &= INBOX_MASK;
1723		inbox = mlx4_alloc_cmd_mailbox(dev);
1724		if (IS_ERR(inbox)) {
1725			vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1726			inbox = NULL;
1727			goto out_status;
1728		}
1729
1730		ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1731				      vhcr->in_param,
1732				      MLX4_MAILBOX_SIZE, 1);
1733		if (ret) {
1734			if (!(dev->persist->state &
1735			    MLX4_DEVICE_STATE_INTERNAL_ERROR))
1736				mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1737					 __func__, cmd->opcode);
1738			vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1739			goto out_status;
1740		}
1741	}
1742
1743	/* Apply permission and bound checks if applicable */
1744	if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1745		mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1746			  vhcr->op, slave, vhcr->in_modifier);
1747		vhcr_cmd->status = CMD_STAT_BAD_OP;
1748		goto out_status;
1749	}
1750
1751	/* Allocate outbox */
1752	if (cmd->has_outbox) {
1753		outbox = mlx4_alloc_cmd_mailbox(dev);
1754		if (IS_ERR(outbox)) {
1755			vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1756			outbox = NULL;
1757			goto out_status;
1758		}
1759	}
1760
1761	/* Execute the command! */
1762	if (cmd->wrapper) {
1763		err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1764				   cmd);
1765		if (cmd->out_is_imm)
1766			vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1767	} else {
1768		in_param = cmd->has_inbox ? (u64) inbox->dma :
1769			vhcr->in_param;
1770		out_param = cmd->has_outbox ? (u64) outbox->dma :
1771			vhcr->out_param;
1772		err = __mlx4_cmd(dev, in_param, &out_param,
1773				 cmd->out_is_imm, vhcr->in_modifier,
1774				 vhcr->op_modifier, vhcr->op,
1775				 MLX4_CMD_TIME_CLASS_A,
1776				 MLX4_CMD_NATIVE);
1777
1778		if (cmd->out_is_imm) {
1779			vhcr->out_param = out_param;
1780			vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1781		}
1782	}
1783
1784	if (err) {
1785		if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
1786			if (vhcr->op == MLX4_CMD_ALLOC_RES &&
1787			    (vhcr->in_modifier & 0xff) == RES_COUNTER &&
1788			    err == -EDQUOT)
1789				mlx4_dbg(dev,
1790					 "Unable to allocate counter for slave %d (%d)\n",
1791					 slave, err);
1792			else
1793				mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1794					  vhcr->op, slave, vhcr->errno, err);
1795		}
1796		vhcr_cmd->status = mlx4_errno_to_status(err);
1797		goto out_status;
1798	}
1799
1800
1801	/* Write outbox if command completed successfully */
1802	if (cmd->has_outbox && !vhcr_cmd->status) {
1803		ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1804				      vhcr->out_param,
1805				      MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1806		if (ret) {
1807			/* If we failed to write back the outbox after the
1808			 *command was successfully executed, we must fail this
1809			 * slave, as it is now in undefined state */
1810			if (!(dev->persist->state &
1811			    MLX4_DEVICE_STATE_INTERNAL_ERROR))
1812				mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1813			goto out;
1814		}
1815	}
1816
1817out_status:
1818	/* DMA back vhcr result */
1819	if (!in_vhcr) {
1820		ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1821				      priv->mfunc.master.slave_state[slave].vhcr_dma,
1822				      ALIGN(sizeof(struct mlx4_vhcr),
1823					    MLX4_ACCESS_MEM_ALIGN),
1824				      MLX4_CMD_WRAPPED);
1825		if (ret)
1826			mlx4_err(dev, "%s:Failed writing vhcr result\n",
1827				 __func__);
1828		else if (vhcr->e_bit &&
1829			 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1830				mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1831					  slave);
1832	}
1833
1834out:
1835	kfree(vhcr);
1836	mlx4_free_cmd_mailbox(dev, inbox);
1837	mlx4_free_cmd_mailbox(dev, outbox);
1838	return ret;
1839}
1840
1841static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1842					    int slave, int port)
1843{
1844	struct mlx4_vport_oper_state *vp_oper;
1845	struct mlx4_vport_state *vp_admin;
1846	struct mlx4_vf_immed_vlan_work *work;
1847	struct mlx4_dev *dev = &(priv->dev);
1848	int err;
1849	int admin_vlan_ix = NO_INDX;
1850
1851	vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1852	vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1853
1854	if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1855	    vp_oper->state.default_qos == vp_admin->default_qos &&
1856	    vp_oper->state.vlan_proto == vp_admin->vlan_proto &&
1857	    vp_oper->state.link_state == vp_admin->link_state &&
1858	    vp_oper->state.qos_vport == vp_admin->qos_vport)
1859		return 0;
1860
1861	if (!(priv->mfunc.master.slave_state[slave].active &&
1862	      dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1863		/* even if the UPDATE_QP command isn't supported, we still want
1864		 * to set this VF link according to the admin directive
1865		 */
1866		vp_oper->state.link_state = vp_admin->link_state;
1867		return -1;
1868	}
1869
1870	mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1871		 slave, port);
1872	mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1873		 vp_admin->default_vlan, vp_admin->default_qos,
1874		 vp_admin->link_state);
1875
1876	work = kzalloc(sizeof(*work), GFP_KERNEL);
1877	if (!work)
1878		return -ENOMEM;
1879
1880	if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1881		if (MLX4_VGT != vp_admin->default_vlan) {
1882			err = __mlx4_register_vlan(&priv->dev, port,
1883						   vp_admin->default_vlan,
1884						   &admin_vlan_ix);
1885			if (err) {
1886				kfree(work);
1887				mlx4_warn(&priv->dev,
1888					  "No vlan resources slave %d, port %d\n",
1889					  slave, port);
1890				return err;
1891			}
1892		} else {
1893			admin_vlan_ix = NO_INDX;
1894		}
1895		work->flags |= MLX4_VF_IMMED_VLAN_FLAG_V

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