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/drivers/net/ethernet/micrel/ksz884x.c

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   1// SPDX-License-Identifier: GPL-2.0-only
   2/**
   3 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
   4 *
   5 * Copyright (c) 2009-2010 Micrel, Inc.
   6 * 	Tristram Ha <Tristram.Ha@micrel.com>
   7 */
   8
   9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11#include <linux/init.h>
  12#include <linux/interrupt.h>
  13#include <linux/kernel.h>
  14#include <linux/module.h>
  15#include <linux/ioport.h>
  16#include <linux/pci.h>
  17#include <linux/proc_fs.h>
  18#include <linux/mii.h>
  19#include <linux/platform_device.h>
  20#include <linux/ethtool.h>
  21#include <linux/etherdevice.h>
  22#include <linux/in.h>
  23#include <linux/ip.h>
  24#include <linux/if_vlan.h>
  25#include <linux/crc32.h>
  26#include <linux/sched.h>
  27#include <linux/slab.h>
  28
  29
  30/* DMA Registers */
  31
  32#define KS_DMA_TX_CTRL			0x0000
  33#define DMA_TX_ENABLE			0x00000001
  34#define DMA_TX_CRC_ENABLE		0x00000002
  35#define DMA_TX_PAD_ENABLE		0x00000004
  36#define DMA_TX_LOOPBACK			0x00000100
  37#define DMA_TX_FLOW_ENABLE		0x00000200
  38#define DMA_TX_CSUM_IP			0x00010000
  39#define DMA_TX_CSUM_TCP			0x00020000
  40#define DMA_TX_CSUM_UDP			0x00040000
  41#define DMA_TX_BURST_SIZE		0x3F000000
  42
  43#define KS_DMA_RX_CTRL			0x0004
  44#define DMA_RX_ENABLE			0x00000001
  45#define KS884X_DMA_RX_MULTICAST		0x00000002
  46#define DMA_RX_PROMISCUOUS		0x00000004
  47#define DMA_RX_ERROR			0x00000008
  48#define DMA_RX_UNICAST			0x00000010
  49#define DMA_RX_ALL_MULTICAST		0x00000020
  50#define DMA_RX_BROADCAST		0x00000040
  51#define DMA_RX_FLOW_ENABLE		0x00000200
  52#define DMA_RX_CSUM_IP			0x00010000
  53#define DMA_RX_CSUM_TCP			0x00020000
  54#define DMA_RX_CSUM_UDP			0x00040000
  55#define DMA_RX_BURST_SIZE		0x3F000000
  56
  57#define DMA_BURST_SHIFT			24
  58#define DMA_BURST_DEFAULT		8
  59
  60#define KS_DMA_TX_START			0x0008
  61#define KS_DMA_RX_START			0x000C
  62#define DMA_START			0x00000001
  63
  64#define KS_DMA_TX_ADDR			0x0010
  65#define KS_DMA_RX_ADDR			0x0014
  66
  67#define DMA_ADDR_LIST_MASK		0xFFFFFFFC
  68#define DMA_ADDR_LIST_SHIFT		2
  69
  70/* MTR0 */
  71#define KS884X_MULTICAST_0_OFFSET	0x0020
  72#define KS884X_MULTICAST_1_OFFSET	0x0021
  73#define KS884X_MULTICAST_2_OFFSET	0x0022
  74#define KS884x_MULTICAST_3_OFFSET	0x0023
  75/* MTR1 */
  76#define KS884X_MULTICAST_4_OFFSET	0x0024
  77#define KS884X_MULTICAST_5_OFFSET	0x0025
  78#define KS884X_MULTICAST_6_OFFSET	0x0026
  79#define KS884X_MULTICAST_7_OFFSET	0x0027
  80
  81/* Interrupt Registers */
  82
  83/* INTEN */
  84#define KS884X_INTERRUPTS_ENABLE	0x0028
  85/* INTST */
  86#define KS884X_INTERRUPTS_STATUS	0x002C
  87
  88#define KS884X_INT_RX_STOPPED		0x02000000
  89#define KS884X_INT_TX_STOPPED		0x04000000
  90#define KS884X_INT_RX_OVERRUN		0x08000000
  91#define KS884X_INT_TX_EMPTY		0x10000000
  92#define KS884X_INT_RX			0x20000000
  93#define KS884X_INT_TX			0x40000000
  94#define KS884X_INT_PHY			0x80000000
  95
  96#define KS884X_INT_RX_MASK		\
  97	(KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
  98#define KS884X_INT_TX_MASK		\
  99	(KS884X_INT_TX | KS884X_INT_TX_EMPTY)
 100#define KS884X_INT_MASK	(KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
 101
 102/* MAC Additional Station Address */
 103
 104/* MAAL0 */
 105#define KS_ADD_ADDR_0_LO		0x0080
 106/* MAAH0 */
 107#define KS_ADD_ADDR_0_HI		0x0084
 108/* MAAL1 */
 109#define KS_ADD_ADDR_1_LO		0x0088
 110/* MAAH1 */
 111#define KS_ADD_ADDR_1_HI		0x008C
 112/* MAAL2 */
 113#define KS_ADD_ADDR_2_LO		0x0090
 114/* MAAH2 */
 115#define KS_ADD_ADDR_2_HI		0x0094
 116/* MAAL3 */
 117#define KS_ADD_ADDR_3_LO		0x0098
 118/* MAAH3 */
 119#define KS_ADD_ADDR_3_HI		0x009C
 120/* MAAL4 */
 121#define KS_ADD_ADDR_4_LO		0x00A0
 122/* MAAH4 */
 123#define KS_ADD_ADDR_4_HI		0x00A4
 124/* MAAL5 */
 125#define KS_ADD_ADDR_5_LO		0x00A8
 126/* MAAH5 */
 127#define KS_ADD_ADDR_5_HI		0x00AC
 128/* MAAL6 */
 129#define KS_ADD_ADDR_6_LO		0x00B0
 130/* MAAH6 */
 131#define KS_ADD_ADDR_6_HI		0x00B4
 132/* MAAL7 */
 133#define KS_ADD_ADDR_7_LO		0x00B8
 134/* MAAH7 */
 135#define KS_ADD_ADDR_7_HI		0x00BC
 136/* MAAL8 */
 137#define KS_ADD_ADDR_8_LO		0x00C0
 138/* MAAH8 */
 139#define KS_ADD_ADDR_8_HI		0x00C4
 140/* MAAL9 */
 141#define KS_ADD_ADDR_9_LO		0x00C8
 142/* MAAH9 */
 143#define KS_ADD_ADDR_9_HI		0x00CC
 144/* MAAL10 */
 145#define KS_ADD_ADDR_A_LO		0x00D0
 146/* MAAH10 */
 147#define KS_ADD_ADDR_A_HI		0x00D4
 148/* MAAL11 */
 149#define KS_ADD_ADDR_B_LO		0x00D8
 150/* MAAH11 */
 151#define KS_ADD_ADDR_B_HI		0x00DC
 152/* MAAL12 */
 153#define KS_ADD_ADDR_C_LO		0x00E0
 154/* MAAH12 */
 155#define KS_ADD_ADDR_C_HI		0x00E4
 156/* MAAL13 */
 157#define KS_ADD_ADDR_D_LO		0x00E8
 158/* MAAH13 */
 159#define KS_ADD_ADDR_D_HI		0x00EC
 160/* MAAL14 */
 161#define KS_ADD_ADDR_E_LO		0x00F0
 162/* MAAH14 */
 163#define KS_ADD_ADDR_E_HI		0x00F4
 164/* MAAL15 */
 165#define KS_ADD_ADDR_F_LO		0x00F8
 166/* MAAH15 */
 167#define KS_ADD_ADDR_F_HI		0x00FC
 168
 169#define ADD_ADDR_HI_MASK		0x0000FFFF
 170#define ADD_ADDR_ENABLE			0x80000000
 171#define ADD_ADDR_INCR			8
 172
 173/* Miscellaneous Registers */
 174
 175/* MARL */
 176#define KS884X_ADDR_0_OFFSET		0x0200
 177#define KS884X_ADDR_1_OFFSET		0x0201
 178/* MARM */
 179#define KS884X_ADDR_2_OFFSET		0x0202
 180#define KS884X_ADDR_3_OFFSET		0x0203
 181/* MARH */
 182#define KS884X_ADDR_4_OFFSET		0x0204
 183#define KS884X_ADDR_5_OFFSET		0x0205
 184
 185/* OBCR */
 186#define KS884X_BUS_CTRL_OFFSET		0x0210
 187
 188#define BUS_SPEED_125_MHZ		0x0000
 189#define BUS_SPEED_62_5_MHZ		0x0001
 190#define BUS_SPEED_41_66_MHZ		0x0002
 191#define BUS_SPEED_25_MHZ		0x0003
 192
 193/* EEPCR */
 194#define KS884X_EEPROM_CTRL_OFFSET	0x0212
 195
 196#define EEPROM_CHIP_SELECT		0x0001
 197#define EEPROM_SERIAL_CLOCK		0x0002
 198#define EEPROM_DATA_OUT			0x0004
 199#define EEPROM_DATA_IN			0x0008
 200#define EEPROM_ACCESS_ENABLE		0x0010
 201
 202/* MBIR */
 203#define KS884X_MEM_INFO_OFFSET		0x0214
 204
 205#define RX_MEM_TEST_FAILED		0x0008
 206#define RX_MEM_TEST_FINISHED		0x0010
 207#define TX_MEM_TEST_FAILED		0x0800
 208#define TX_MEM_TEST_FINISHED		0x1000
 209
 210/* GCR */
 211#define KS884X_GLOBAL_CTRL_OFFSET	0x0216
 212#define GLOBAL_SOFTWARE_RESET		0x0001
 213
 214#define KS8841_POWER_MANAGE_OFFSET	0x0218
 215
 216/* WFCR */
 217#define KS8841_WOL_CTRL_OFFSET		0x021A
 218#define KS8841_WOL_MAGIC_ENABLE		0x0080
 219#define KS8841_WOL_FRAME3_ENABLE	0x0008
 220#define KS8841_WOL_FRAME2_ENABLE	0x0004
 221#define KS8841_WOL_FRAME1_ENABLE	0x0002
 222#define KS8841_WOL_FRAME0_ENABLE	0x0001
 223
 224/* WF0 */
 225#define KS8841_WOL_FRAME_CRC_OFFSET	0x0220
 226#define KS8841_WOL_FRAME_BYTE0_OFFSET	0x0224
 227#define KS8841_WOL_FRAME_BYTE2_OFFSET	0x0228
 228
 229/* IACR */
 230#define KS884X_IACR_P			0x04A0
 231#define KS884X_IACR_OFFSET		KS884X_IACR_P
 232
 233/* IADR1 */
 234#define KS884X_IADR1_P			0x04A2
 235#define KS884X_IADR2_P			0x04A4
 236#define KS884X_IADR3_P			0x04A6
 237#define KS884X_IADR4_P			0x04A8
 238#define KS884X_IADR5_P			0x04AA
 239
 240#define KS884X_ACC_CTRL_SEL_OFFSET	KS884X_IACR_P
 241#define KS884X_ACC_CTRL_INDEX_OFFSET	(KS884X_ACC_CTRL_SEL_OFFSET + 1)
 242
 243#define KS884X_ACC_DATA_0_OFFSET	KS884X_IADR4_P
 244#define KS884X_ACC_DATA_1_OFFSET	(KS884X_ACC_DATA_0_OFFSET + 1)
 245#define KS884X_ACC_DATA_2_OFFSET	KS884X_IADR5_P
 246#define KS884X_ACC_DATA_3_OFFSET	(KS884X_ACC_DATA_2_OFFSET + 1)
 247#define KS884X_ACC_DATA_4_OFFSET	KS884X_IADR2_P
 248#define KS884X_ACC_DATA_5_OFFSET	(KS884X_ACC_DATA_4_OFFSET + 1)
 249#define KS884X_ACC_DATA_6_OFFSET	KS884X_IADR3_P
 250#define KS884X_ACC_DATA_7_OFFSET	(KS884X_ACC_DATA_6_OFFSET + 1)
 251#define KS884X_ACC_DATA_8_OFFSET	KS884X_IADR1_P
 252
 253/* P1MBCR */
 254#define KS884X_P1MBCR_P			0x04D0
 255#define KS884X_P1MBSR_P			0x04D2
 256#define KS884X_PHY1ILR_P		0x04D4
 257#define KS884X_PHY1IHR_P		0x04D6
 258#define KS884X_P1ANAR_P			0x04D8
 259#define KS884X_P1ANLPR_P		0x04DA
 260
 261/* P2MBCR */
 262#define KS884X_P2MBCR_P			0x04E0
 263#define KS884X_P2MBSR_P			0x04E2
 264#define KS884X_PHY2ILR_P		0x04E4
 265#define KS884X_PHY2IHR_P		0x04E6
 266#define KS884X_P2ANAR_P			0x04E8
 267#define KS884X_P2ANLPR_P		0x04EA
 268
 269#define KS884X_PHY_1_CTRL_OFFSET	KS884X_P1MBCR_P
 270#define PHY_CTRL_INTERVAL		(KS884X_P2MBCR_P - KS884X_P1MBCR_P)
 271
 272#define KS884X_PHY_CTRL_OFFSET		0x00
 273
 274/* Mode Control Register */
 275#define PHY_REG_CTRL			0
 276
 277#define PHY_RESET			0x8000
 278#define PHY_LOOPBACK			0x4000
 279#define PHY_SPEED_100MBIT		0x2000
 280#define PHY_AUTO_NEG_ENABLE		0x1000
 281#define PHY_POWER_DOWN			0x0800
 282#define PHY_MII_DISABLE			0x0400
 283#define PHY_AUTO_NEG_RESTART		0x0200
 284#define PHY_FULL_DUPLEX			0x0100
 285#define PHY_COLLISION_TEST		0x0080
 286#define PHY_HP_MDIX			0x0020
 287#define PHY_FORCE_MDIX			0x0010
 288#define PHY_AUTO_MDIX_DISABLE		0x0008
 289#define PHY_REMOTE_FAULT_DISABLE	0x0004
 290#define PHY_TRANSMIT_DISABLE		0x0002
 291#define PHY_LED_DISABLE			0x0001
 292
 293#define KS884X_PHY_STATUS_OFFSET	0x02
 294
 295/* Mode Status Register */
 296#define PHY_REG_STATUS			1
 297
 298#define PHY_100BT4_CAPABLE		0x8000
 299#define PHY_100BTX_FD_CAPABLE		0x4000
 300#define PHY_100BTX_CAPABLE		0x2000
 301#define PHY_10BT_FD_CAPABLE		0x1000
 302#define PHY_10BT_CAPABLE		0x0800
 303#define PHY_MII_SUPPRESS_CAPABLE	0x0040
 304#define PHY_AUTO_NEG_ACKNOWLEDGE	0x0020
 305#define PHY_REMOTE_FAULT		0x0010
 306#define PHY_AUTO_NEG_CAPABLE		0x0008
 307#define PHY_LINK_STATUS			0x0004
 308#define PHY_JABBER_DETECT		0x0002
 309#define PHY_EXTENDED_CAPABILITY		0x0001
 310
 311#define KS884X_PHY_ID_1_OFFSET		0x04
 312#define KS884X_PHY_ID_2_OFFSET		0x06
 313
 314/* PHY Identifier Registers */
 315#define PHY_REG_ID_1			2
 316#define PHY_REG_ID_2			3
 317
 318#define KS884X_PHY_AUTO_NEG_OFFSET	0x08
 319
 320/* Auto-Negotiation Advertisement Register */
 321#define PHY_REG_AUTO_NEGOTIATION	4
 322
 323#define PHY_AUTO_NEG_NEXT_PAGE		0x8000
 324#define PHY_AUTO_NEG_REMOTE_FAULT	0x2000
 325/* Not supported. */
 326#define PHY_AUTO_NEG_ASYM_PAUSE		0x0800
 327#define PHY_AUTO_NEG_SYM_PAUSE		0x0400
 328#define PHY_AUTO_NEG_100BT4		0x0200
 329#define PHY_AUTO_NEG_100BTX_FD		0x0100
 330#define PHY_AUTO_NEG_100BTX		0x0080
 331#define PHY_AUTO_NEG_10BT_FD		0x0040
 332#define PHY_AUTO_NEG_10BT		0x0020
 333#define PHY_AUTO_NEG_SELECTOR		0x001F
 334#define PHY_AUTO_NEG_802_3		0x0001
 335
 336#define PHY_AUTO_NEG_PAUSE  (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
 337
 338#define KS884X_PHY_REMOTE_CAP_OFFSET	0x0A
 339
 340/* Auto-Negotiation Link Partner Ability Register */
 341#define PHY_REG_REMOTE_CAPABILITY	5
 342
 343#define PHY_REMOTE_NEXT_PAGE		0x8000
 344#define PHY_REMOTE_ACKNOWLEDGE		0x4000
 345#define PHY_REMOTE_REMOTE_FAULT		0x2000
 346#define PHY_REMOTE_SYM_PAUSE		0x0400
 347#define PHY_REMOTE_100BTX_FD		0x0100
 348#define PHY_REMOTE_100BTX		0x0080
 349#define PHY_REMOTE_10BT_FD		0x0040
 350#define PHY_REMOTE_10BT			0x0020
 351
 352/* P1VCT */
 353#define KS884X_P1VCT_P			0x04F0
 354#define KS884X_P1PHYCTRL_P		0x04F2
 355
 356/* P2VCT */
 357#define KS884X_P2VCT_P			0x04F4
 358#define KS884X_P2PHYCTRL_P		0x04F6
 359
 360#define KS884X_PHY_SPECIAL_OFFSET	KS884X_P1VCT_P
 361#define PHY_SPECIAL_INTERVAL		(KS884X_P2VCT_P - KS884X_P1VCT_P)
 362
 363#define KS884X_PHY_LINK_MD_OFFSET	0x00
 364
 365#define PHY_START_CABLE_DIAG		0x8000
 366#define PHY_CABLE_DIAG_RESULT		0x6000
 367#define PHY_CABLE_STAT_NORMAL		0x0000
 368#define PHY_CABLE_STAT_OPEN		0x2000
 369#define PHY_CABLE_STAT_SHORT		0x4000
 370#define PHY_CABLE_STAT_FAILED		0x6000
 371#define PHY_CABLE_10M_SHORT		0x1000
 372#define PHY_CABLE_FAULT_COUNTER		0x01FF
 373
 374#define KS884X_PHY_PHY_CTRL_OFFSET	0x02
 375
 376#define PHY_STAT_REVERSED_POLARITY	0x0020
 377#define PHY_STAT_MDIX			0x0010
 378#define PHY_FORCE_LINK			0x0008
 379#define PHY_POWER_SAVING_DISABLE	0x0004
 380#define PHY_REMOTE_LOOPBACK		0x0002
 381
 382/* SIDER */
 383#define KS884X_SIDER_P			0x0400
 384#define KS884X_CHIP_ID_OFFSET		KS884X_SIDER_P
 385#define KS884X_FAMILY_ID_OFFSET		(KS884X_CHIP_ID_OFFSET + 1)
 386
 387#define REG_FAMILY_ID			0x88
 388
 389#define REG_CHIP_ID_41			0x8810
 390#define REG_CHIP_ID_42			0x8800
 391
 392#define KS884X_CHIP_ID_MASK_41		0xFF10
 393#define KS884X_CHIP_ID_MASK		0xFFF0
 394#define KS884X_CHIP_ID_SHIFT		4
 395#define KS884X_REVISION_MASK		0x000E
 396#define KS884X_REVISION_SHIFT		1
 397#define KS8842_START			0x0001
 398
 399#define CHIP_IP_41_M			0x8810
 400#define CHIP_IP_42_M			0x8800
 401#define CHIP_IP_61_M			0x8890
 402#define CHIP_IP_62_M			0x8880
 403
 404#define CHIP_IP_41_P			0x8850
 405#define CHIP_IP_42_P			0x8840
 406#define CHIP_IP_61_P			0x88D0
 407#define CHIP_IP_62_P			0x88C0
 408
 409/* SGCR1 */
 410#define KS8842_SGCR1_P			0x0402
 411#define KS8842_SWITCH_CTRL_1_OFFSET	KS8842_SGCR1_P
 412
 413#define SWITCH_PASS_ALL			0x8000
 414#define SWITCH_TX_FLOW_CTRL		0x2000
 415#define SWITCH_RX_FLOW_CTRL		0x1000
 416#define SWITCH_CHECK_LENGTH		0x0800
 417#define SWITCH_AGING_ENABLE		0x0400
 418#define SWITCH_FAST_AGING		0x0200
 419#define SWITCH_AGGR_BACKOFF		0x0100
 420#define SWITCH_PASS_PAUSE		0x0008
 421#define SWITCH_LINK_AUTO_AGING		0x0001
 422
 423/* SGCR2 */
 424#define KS8842_SGCR2_P			0x0404
 425#define KS8842_SWITCH_CTRL_2_OFFSET	KS8842_SGCR2_P
 426
 427#define SWITCH_VLAN_ENABLE		0x8000
 428#define SWITCH_IGMP_SNOOP		0x4000
 429#define IPV6_MLD_SNOOP_ENABLE		0x2000
 430#define IPV6_MLD_SNOOP_OPTION		0x1000
 431#define PRIORITY_SCHEME_SELECT		0x0800
 432#define SWITCH_MIRROR_RX_TX		0x0100
 433#define UNICAST_VLAN_BOUNDARY		0x0080
 434#define MULTICAST_STORM_DISABLE		0x0040
 435#define SWITCH_BACK_PRESSURE		0x0020
 436#define FAIR_FLOW_CTRL			0x0010
 437#define NO_EXC_COLLISION_DROP		0x0008
 438#define SWITCH_HUGE_PACKET		0x0004
 439#define SWITCH_LEGAL_PACKET		0x0002
 440#define SWITCH_BUF_RESERVE		0x0001
 441
 442/* SGCR3 */
 443#define KS8842_SGCR3_P			0x0406
 444#define KS8842_SWITCH_CTRL_3_OFFSET	KS8842_SGCR3_P
 445
 446#define BROADCAST_STORM_RATE_LO		0xFF00
 447#define SWITCH_REPEATER			0x0080
 448#define SWITCH_HALF_DUPLEX		0x0040
 449#define SWITCH_FLOW_CTRL		0x0020
 450#define SWITCH_10_MBIT			0x0010
 451#define SWITCH_REPLACE_NULL_VID		0x0008
 452#define BROADCAST_STORM_RATE_HI		0x0007
 453
 454#define BROADCAST_STORM_RATE		0x07FF
 455
 456/* SGCR4 */
 457#define KS8842_SGCR4_P			0x0408
 458
 459/* SGCR5 */
 460#define KS8842_SGCR5_P			0x040A
 461#define KS8842_SWITCH_CTRL_5_OFFSET	KS8842_SGCR5_P
 462
 463#define LED_MODE			0x8200
 464#define LED_SPEED_DUPLEX_ACT		0x0000
 465#define LED_SPEED_DUPLEX_LINK_ACT	0x8000
 466#define LED_DUPLEX_10_100		0x0200
 467
 468/* SGCR6 */
 469#define KS8842_SGCR6_P			0x0410
 470#define KS8842_SWITCH_CTRL_6_OFFSET	KS8842_SGCR6_P
 471
 472#define KS8842_PRIORITY_MASK		3
 473#define KS8842_PRIORITY_SHIFT		2
 474
 475/* SGCR7 */
 476#define KS8842_SGCR7_P			0x0412
 477#define KS8842_SWITCH_CTRL_7_OFFSET	KS8842_SGCR7_P
 478
 479#define SWITCH_UNK_DEF_PORT_ENABLE	0x0008
 480#define SWITCH_UNK_DEF_PORT_3		0x0004
 481#define SWITCH_UNK_DEF_PORT_2		0x0002
 482#define SWITCH_UNK_DEF_PORT_1		0x0001
 483
 484/* MACAR1 */
 485#define KS8842_MACAR1_P			0x0470
 486#define KS8842_MACAR2_P			0x0472
 487#define KS8842_MACAR3_P			0x0474
 488#define KS8842_MAC_ADDR_1_OFFSET	KS8842_MACAR1_P
 489#define KS8842_MAC_ADDR_0_OFFSET	(KS8842_MAC_ADDR_1_OFFSET + 1)
 490#define KS8842_MAC_ADDR_3_OFFSET	KS8842_MACAR2_P
 491#define KS8842_MAC_ADDR_2_OFFSET	(KS8842_MAC_ADDR_3_OFFSET + 1)
 492#define KS8842_MAC_ADDR_5_OFFSET	KS8842_MACAR3_P
 493#define KS8842_MAC_ADDR_4_OFFSET	(KS8842_MAC_ADDR_5_OFFSET + 1)
 494
 495/* TOSR1 */
 496#define KS8842_TOSR1_P			0x0480
 497#define KS8842_TOSR2_P			0x0482
 498#define KS8842_TOSR3_P			0x0484
 499#define KS8842_TOSR4_P			0x0486
 500#define KS8842_TOSR5_P			0x0488
 501#define KS8842_TOSR6_P			0x048A
 502#define KS8842_TOSR7_P			0x0490
 503#define KS8842_TOSR8_P			0x0492
 504#define KS8842_TOS_1_OFFSET		KS8842_TOSR1_P
 505#define KS8842_TOS_2_OFFSET		KS8842_TOSR2_P
 506#define KS8842_TOS_3_OFFSET		KS8842_TOSR3_P
 507#define KS8842_TOS_4_OFFSET		KS8842_TOSR4_P
 508#define KS8842_TOS_5_OFFSET		KS8842_TOSR5_P
 509#define KS8842_TOS_6_OFFSET		KS8842_TOSR6_P
 510
 511#define KS8842_TOS_7_OFFSET		KS8842_TOSR7_P
 512#define KS8842_TOS_8_OFFSET		KS8842_TOSR8_P
 513
 514/* P1CR1 */
 515#define KS8842_P1CR1_P			0x0500
 516#define KS8842_P1CR2_P			0x0502
 517#define KS8842_P1VIDR_P			0x0504
 518#define KS8842_P1CR3_P			0x0506
 519#define KS8842_P1IRCR_P			0x0508
 520#define KS8842_P1ERCR_P			0x050A
 521#define KS884X_P1SCSLMD_P		0x0510
 522#define KS884X_P1CR4_P			0x0512
 523#define KS884X_P1SR_P			0x0514
 524
 525/* P2CR1 */
 526#define KS8842_P2CR1_P			0x0520
 527#define KS8842_P2CR2_P			0x0522
 528#define KS8842_P2VIDR_P			0x0524
 529#define KS8842_P2CR3_P			0x0526
 530#define KS8842_P2IRCR_P			0x0528
 531#define KS8842_P2ERCR_P			0x052A
 532#define KS884X_P2SCSLMD_P		0x0530
 533#define KS884X_P2CR4_P			0x0532
 534#define KS884X_P2SR_P			0x0534
 535
 536/* P3CR1 */
 537#define KS8842_P3CR1_P			0x0540
 538#define KS8842_P3CR2_P			0x0542
 539#define KS8842_P3VIDR_P			0x0544
 540#define KS8842_P3CR3_P			0x0546
 541#define KS8842_P3IRCR_P			0x0548
 542#define KS8842_P3ERCR_P			0x054A
 543
 544#define KS8842_PORT_1_CTRL_1		KS8842_P1CR1_P
 545#define KS8842_PORT_2_CTRL_1		KS8842_P2CR1_P
 546#define KS8842_PORT_3_CTRL_1		KS8842_P3CR1_P
 547
 548#define PORT_CTRL_ADDR(port, addr)		\
 549	(addr = KS8842_PORT_1_CTRL_1 + (port) *	\
 550		(KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
 551
 552#define KS8842_PORT_CTRL_1_OFFSET	0x00
 553
 554#define PORT_BROADCAST_STORM		0x0080
 555#define PORT_DIFFSERV_ENABLE		0x0040
 556#define PORT_802_1P_ENABLE		0x0020
 557#define PORT_BASED_PRIORITY_MASK	0x0018
 558#define PORT_BASED_PRIORITY_BASE	0x0003
 559#define PORT_BASED_PRIORITY_SHIFT	3
 560#define PORT_BASED_PRIORITY_0		0x0000
 561#define PORT_BASED_PRIORITY_1		0x0008
 562#define PORT_BASED_PRIORITY_2		0x0010
 563#define PORT_BASED_PRIORITY_3		0x0018
 564#define PORT_INSERT_TAG			0x0004
 565#define PORT_REMOVE_TAG			0x0002
 566#define PORT_PRIO_QUEUE_ENABLE		0x0001
 567
 568#define KS8842_PORT_CTRL_2_OFFSET	0x02
 569
 570#define PORT_INGRESS_VLAN_FILTER	0x4000
 571#define PORT_DISCARD_NON_VID		0x2000
 572#define PORT_FORCE_FLOW_CTRL		0x1000
 573#define PORT_BACK_PRESSURE		0x0800
 574#define PORT_TX_ENABLE			0x0400
 575#define PORT_RX_ENABLE			0x0200
 576#define PORT_LEARN_DISABLE		0x0100
 577#define PORT_MIRROR_SNIFFER		0x0080
 578#define PORT_MIRROR_RX			0x0040
 579#define PORT_MIRROR_TX			0x0020
 580#define PORT_USER_PRIORITY_CEILING	0x0008
 581#define PORT_VLAN_MEMBERSHIP		0x0007
 582
 583#define KS8842_PORT_CTRL_VID_OFFSET	0x04
 584
 585#define PORT_DEFAULT_VID		0x0001
 586
 587#define KS8842_PORT_CTRL_3_OFFSET	0x06
 588
 589#define PORT_INGRESS_LIMIT_MODE		0x000C
 590#define PORT_INGRESS_ALL		0x0000
 591#define PORT_INGRESS_UNICAST		0x0004
 592#define PORT_INGRESS_MULTICAST		0x0008
 593#define PORT_INGRESS_BROADCAST		0x000C
 594#define PORT_COUNT_IFG			0x0002
 595#define PORT_COUNT_PREAMBLE		0x0001
 596
 597#define KS8842_PORT_IN_RATE_OFFSET	0x08
 598#define KS8842_PORT_OUT_RATE_OFFSET	0x0A
 599
 600#define PORT_PRIORITY_RATE		0x0F
 601#define PORT_PRIORITY_RATE_SHIFT	4
 602
 603#define KS884X_PORT_LINK_MD		0x10
 604
 605#define PORT_CABLE_10M_SHORT		0x8000
 606#define PORT_CABLE_DIAG_RESULT		0x6000
 607#define PORT_CABLE_STAT_NORMAL		0x0000
 608#define PORT_CABLE_STAT_OPEN		0x2000
 609#define PORT_CABLE_STAT_SHORT		0x4000
 610#define PORT_CABLE_STAT_FAILED		0x6000
 611#define PORT_START_CABLE_DIAG		0x1000
 612#define PORT_FORCE_LINK			0x0800
 613#define PORT_POWER_SAVING_DISABLE	0x0400
 614#define PORT_PHY_REMOTE_LOOPBACK	0x0200
 615#define PORT_CABLE_FAULT_COUNTER	0x01FF
 616
 617#define KS884X_PORT_CTRL_4_OFFSET	0x12
 618
 619#define PORT_LED_OFF			0x8000
 620#define PORT_TX_DISABLE			0x4000
 621#define PORT_AUTO_NEG_RESTART		0x2000
 622#define PORT_REMOTE_FAULT_DISABLE	0x1000
 623#define PORT_POWER_DOWN			0x0800
 624#define PORT_AUTO_MDIX_DISABLE		0x0400
 625#define PORT_FORCE_MDIX			0x0200
 626#define PORT_LOOPBACK			0x0100
 627#define PORT_AUTO_NEG_ENABLE		0x0080
 628#define PORT_FORCE_100_MBIT		0x0040
 629#define PORT_FORCE_FULL_DUPLEX		0x0020
 630#define PORT_AUTO_NEG_SYM_PAUSE		0x0010
 631#define PORT_AUTO_NEG_100BTX_FD		0x0008
 632#define PORT_AUTO_NEG_100BTX		0x0004
 633#define PORT_AUTO_NEG_10BT_FD		0x0002
 634#define PORT_AUTO_NEG_10BT		0x0001
 635
 636#define KS884X_PORT_STATUS_OFFSET	0x14
 637
 638#define PORT_HP_MDIX			0x8000
 639#define PORT_REVERSED_POLARITY		0x2000
 640#define PORT_RX_FLOW_CTRL		0x0800
 641#define PORT_TX_FLOW_CTRL		0x1000
 642#define PORT_STATUS_SPEED_100MBIT	0x0400
 643#define PORT_STATUS_FULL_DUPLEX		0x0200
 644#define PORT_REMOTE_FAULT		0x0100
 645#define PORT_MDIX_STATUS		0x0080
 646#define PORT_AUTO_NEG_COMPLETE		0x0040
 647#define PORT_STATUS_LINK_GOOD		0x0020
 648#define PORT_REMOTE_SYM_PAUSE		0x0010
 649#define PORT_REMOTE_100BTX_FD		0x0008
 650#define PORT_REMOTE_100BTX		0x0004
 651#define PORT_REMOTE_10BT_FD		0x0002
 652#define PORT_REMOTE_10BT		0x0001
 653
 654/*
 655#define STATIC_MAC_TABLE_ADDR		00-0000FFFF-FFFFFFFF
 656#define STATIC_MAC_TABLE_FWD_PORTS	00-00070000-00000000
 657#define STATIC_MAC_TABLE_VALID		00-00080000-00000000
 658#define STATIC_MAC_TABLE_OVERRIDE	00-00100000-00000000
 659#define STATIC_MAC_TABLE_USE_FID	00-00200000-00000000
 660#define STATIC_MAC_TABLE_FID		00-03C00000-00000000
 661*/
 662
 663#define STATIC_MAC_TABLE_ADDR		0x0000FFFF
 664#define STATIC_MAC_TABLE_FWD_PORTS	0x00070000
 665#define STATIC_MAC_TABLE_VALID		0x00080000
 666#define STATIC_MAC_TABLE_OVERRIDE	0x00100000
 667#define STATIC_MAC_TABLE_USE_FID	0x00200000
 668#define STATIC_MAC_TABLE_FID		0x03C00000
 669
 670#define STATIC_MAC_FWD_PORTS_SHIFT	16
 671#define STATIC_MAC_FID_SHIFT		22
 672
 673/*
 674#define VLAN_TABLE_VID			00-00000000-00000FFF
 675#define VLAN_TABLE_FID			00-00000000-0000F000
 676#define VLAN_TABLE_MEMBERSHIP		00-00000000-00070000
 677#define VLAN_TABLE_VALID		00-00000000-00080000
 678*/
 679
 680#define VLAN_TABLE_VID			0x00000FFF
 681#define VLAN_TABLE_FID			0x0000F000
 682#define VLAN_TABLE_MEMBERSHIP		0x00070000
 683#define VLAN_TABLE_VALID		0x00080000
 684
 685#define VLAN_TABLE_FID_SHIFT		12
 686#define VLAN_TABLE_MEMBERSHIP_SHIFT	16
 687
 688/*
 689#define DYNAMIC_MAC_TABLE_ADDR		00-0000FFFF-FFFFFFFF
 690#define DYNAMIC_MAC_TABLE_FID		00-000F0000-00000000
 691#define DYNAMIC_MAC_TABLE_SRC_PORT	00-00300000-00000000
 692#define DYNAMIC_MAC_TABLE_TIMESTAMP	00-00C00000-00000000
 693#define DYNAMIC_MAC_TABLE_ENTRIES	03-FF000000-00000000
 694#define DYNAMIC_MAC_TABLE_MAC_EMPTY	04-00000000-00000000
 695#define DYNAMIC_MAC_TABLE_RESERVED	78-00000000-00000000
 696#define DYNAMIC_MAC_TABLE_NOT_READY	80-00000000-00000000
 697*/
 698
 699#define DYNAMIC_MAC_TABLE_ADDR		0x0000FFFF
 700#define DYNAMIC_MAC_TABLE_FID		0x000F0000
 701#define DYNAMIC_MAC_TABLE_SRC_PORT	0x00300000
 702#define DYNAMIC_MAC_TABLE_TIMESTAMP	0x00C00000
 703#define DYNAMIC_MAC_TABLE_ENTRIES	0xFF000000
 704
 705#define DYNAMIC_MAC_TABLE_ENTRIES_H	0x03
 706#define DYNAMIC_MAC_TABLE_MAC_EMPTY	0x04
 707#define DYNAMIC_MAC_TABLE_RESERVED	0x78
 708#define DYNAMIC_MAC_TABLE_NOT_READY	0x80
 709
 710#define DYNAMIC_MAC_FID_SHIFT		16
 711#define DYNAMIC_MAC_SRC_PORT_SHIFT	20
 712#define DYNAMIC_MAC_TIMESTAMP_SHIFT	22
 713#define DYNAMIC_MAC_ENTRIES_SHIFT	24
 714#define DYNAMIC_MAC_ENTRIES_H_SHIFT	8
 715
 716/*
 717#define MIB_COUNTER_VALUE		00-00000000-3FFFFFFF
 718#define MIB_COUNTER_VALID		00-00000000-40000000
 719#define MIB_COUNTER_OVERFLOW		00-00000000-80000000
 720*/
 721
 722#define MIB_COUNTER_VALUE		0x3FFFFFFF
 723#define MIB_COUNTER_VALID		0x40000000
 724#define MIB_COUNTER_OVERFLOW		0x80000000
 725
 726#define MIB_PACKET_DROPPED		0x0000FFFF
 727
 728#define KS_MIB_PACKET_DROPPED_TX_0	0x100
 729#define KS_MIB_PACKET_DROPPED_TX_1	0x101
 730#define KS_MIB_PACKET_DROPPED_TX	0x102
 731#define KS_MIB_PACKET_DROPPED_RX_0	0x103
 732#define KS_MIB_PACKET_DROPPED_RX_1	0x104
 733#define KS_MIB_PACKET_DROPPED_RX	0x105
 734
 735/* Change default LED mode. */
 736#define SET_DEFAULT_LED			LED_SPEED_DUPLEX_ACT
 737
 738#define MAC_ADDR_ORDER(i)		(ETH_ALEN - 1 - (i))
 739
 740#define MAX_ETHERNET_BODY_SIZE		1500
 741#define ETHERNET_HEADER_SIZE		(14 + VLAN_HLEN)
 742
 743#define MAX_ETHERNET_PACKET_SIZE	\
 744	(MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
 745
 746#define REGULAR_RX_BUF_SIZE		(MAX_ETHERNET_PACKET_SIZE + 4)
 747#define MAX_RX_BUF_SIZE			(1912 + 4)
 748
 749#define ADDITIONAL_ENTRIES		16
 750#define MAX_MULTICAST_LIST		32
 751
 752#define HW_MULTICAST_SIZE		8
 753
 754#define HW_TO_DEV_PORT(port)		(port - 1)
 755
 756enum {
 757	media_connected,
 758	media_disconnected
 759};
 760
 761enum {
 762	OID_COUNTER_UNKOWN,
 763
 764	OID_COUNTER_FIRST,
 765
 766	/* total transmit errors */
 767	OID_COUNTER_XMIT_ERROR,
 768
 769	/* total receive errors */
 770	OID_COUNTER_RCV_ERROR,
 771
 772	OID_COUNTER_LAST
 773};
 774
 775/*
 776 * Hardware descriptor definitions
 777 */
 778
 779#define DESC_ALIGNMENT			16
 780#define BUFFER_ALIGNMENT		8
 781
 782#define NUM_OF_RX_DESC			64
 783#define NUM_OF_TX_DESC			64
 784
 785#define KS_DESC_RX_FRAME_LEN		0x000007FF
 786#define KS_DESC_RX_FRAME_TYPE		0x00008000
 787#define KS_DESC_RX_ERROR_CRC		0x00010000
 788#define KS_DESC_RX_ERROR_RUNT		0x00020000
 789#define KS_DESC_RX_ERROR_TOO_LONG	0x00040000
 790#define KS_DESC_RX_ERROR_PHY		0x00080000
 791#define KS884X_DESC_RX_PORT_MASK	0x00300000
 792#define KS_DESC_RX_MULTICAST		0x01000000
 793#define KS_DESC_RX_ERROR		0x02000000
 794#define KS_DESC_RX_ERROR_CSUM_UDP	0x04000000
 795#define KS_DESC_RX_ERROR_CSUM_TCP	0x08000000
 796#define KS_DESC_RX_ERROR_CSUM_IP	0x10000000
 797#define KS_DESC_RX_LAST			0x20000000
 798#define KS_DESC_RX_FIRST		0x40000000
 799#define KS_DESC_RX_ERROR_COND		\
 800	(KS_DESC_RX_ERROR_CRC |		\
 801	KS_DESC_RX_ERROR_RUNT |		\
 802	KS_DESC_RX_ERROR_PHY |		\
 803	KS_DESC_RX_ERROR_TOO_LONG)
 804
 805#define KS_DESC_HW_OWNED		0x80000000
 806
 807#define KS_DESC_BUF_SIZE		0x000007FF
 808#define KS884X_DESC_TX_PORT_MASK	0x00300000
 809#define KS_DESC_END_OF_RING		0x02000000
 810#define KS_DESC_TX_CSUM_GEN_UDP		0x04000000
 811#define KS_DESC_TX_CSUM_GEN_TCP		0x08000000
 812#define KS_DESC_TX_CSUM_GEN_IP		0x10000000
 813#define KS_DESC_TX_LAST			0x20000000
 814#define KS_DESC_TX_FIRST		0x40000000
 815#define KS_DESC_TX_INTERRUPT		0x80000000
 816
 817#define KS_DESC_PORT_SHIFT		20
 818
 819#define KS_DESC_RX_MASK			(KS_DESC_BUF_SIZE)
 820
 821#define KS_DESC_TX_MASK			\
 822	(KS_DESC_TX_INTERRUPT |		\
 823	KS_DESC_TX_FIRST |		\
 824	KS_DESC_TX_LAST |		\
 825	KS_DESC_TX_CSUM_GEN_IP |	\
 826	KS_DESC_TX_CSUM_GEN_TCP |	\
 827	KS_DESC_TX_CSUM_GEN_UDP |	\
 828	KS_DESC_BUF_SIZE)
 829
 830struct ksz_desc_rx_stat {
 831#ifdef __BIG_ENDIAN_BITFIELD
 832	u32 hw_owned:1;
 833	u32 first_desc:1;
 834	u32 last_desc:1;
 835	u32 csum_err_ip:1;
 836	u32 csum_err_tcp:1;
 837	u32 csum_err_udp:1;
 838	u32 error:1;
 839	u32 multicast:1;
 840	u32 src_port:4;
 841	u32 err_phy:1;
 842	u32 err_too_long:1;
 843	u32 err_runt:1;
 844	u32 err_crc:1;
 845	u32 frame_type:1;
 846	u32 reserved1:4;
 847	u32 frame_len:11;
 848#else
 849	u32 frame_len:11;
 850	u32 reserved1:4;
 851	u32 frame_type:1;
 852	u32 err_crc:1;
 853	u32 err_runt:1;
 854	u32 err_too_long:1;
 855	u32 err_phy:1;
 856	u32 src_port:4;
 857	u32 multicast:1;
 858	u32 error:1;
 859	u32 csum_err_udp:1;
 860	u32 csum_err_tcp:1;
 861	u32 csum_err_ip:1;
 862	u32 last_desc:1;
 863	u32 first_desc:1;
 864	u32 hw_owned:1;
 865#endif
 866};
 867
 868struct ksz_desc_tx_stat {
 869#ifdef __BIG_ENDIAN_BITFIELD
 870	u32 hw_owned:1;
 871	u32 reserved1:31;
 872#else
 873	u32 reserved1:31;
 874	u32 hw_owned:1;
 875#endif
 876};
 877
 878struct ksz_desc_rx_buf {
 879#ifdef __BIG_ENDIAN_BITFIELD
 880	u32 reserved4:6;
 881	u32 end_of_ring:1;
 882	u32 reserved3:14;
 883	u32 buf_size:11;
 884#else
 885	u32 buf_size:11;
 886	u32 reserved3:14;
 887	u32 end_of_ring:1;
 888	u32 reserved4:6;
 889#endif
 890};
 891
 892struct ksz_desc_tx_buf {
 893#ifdef __BIG_ENDIAN_BITFIELD
 894	u32 intr:1;
 895	u32 first_seg:1;
 896	u32 last_seg:1;
 897	u32 csum_gen_ip:1;
 898	u32 csum_gen_tcp:1;
 899	u32 csum_gen_udp:1;
 900	u32 end_of_ring:1;
 901	u32 reserved4:1;
 902	u32 dest_port:4;
 903	u32 reserved3:9;
 904	u32 buf_size:11;
 905#else
 906	u32 buf_size:11;
 907	u32 reserved3:9;
 908	u32 dest_port:4;
 909	u32 reserved4:1;
 910	u32 end_of_ring:1;
 911	u32 csum_gen_udp:1;
 912	u32 csum_gen_tcp:1;
 913	u32 csum_gen_ip:1;
 914	u32 last_seg:1;
 915	u32 first_seg:1;
 916	u32 intr:1;
 917#endif
 918};
 919
 920union desc_stat {
 921	struct ksz_desc_rx_stat rx;
 922	struct ksz_desc_tx_stat tx;
 923	u32 data;
 924};
 925
 926union desc_buf {
 927	struct ksz_desc_rx_buf rx;
 928	struct ksz_desc_tx_buf tx;
 929	u32 data;
 930};
 931
 932/**
 933 * struct ksz_hw_desc - Hardware descriptor data structure
 934 * @ctrl:	Descriptor control value.
 935 * @buf:	Descriptor buffer value.
 936 * @addr:	Physical address of memory buffer.
 937 * @next:	Pointer to next hardware descriptor.
 938 */
 939struct ksz_hw_desc {
 940	union desc_stat ctrl;
 941	union desc_buf buf;
 942	u32 addr;
 943	u32 next;
 944};
 945
 946/**
 947 * struct ksz_sw_desc - Software descriptor data structure
 948 * @ctrl:	Descriptor control value.
 949 * @buf:	Descriptor buffer value.
 950 * @buf_size:	Current buffers size value in hardware descriptor.
 951 */
 952struct ksz_sw_desc {
 953	union desc_stat ctrl;
 954	union desc_buf buf;
 955	u32 buf_size;
 956};
 957
 958/**
 959 * struct ksz_dma_buf - OS dependent DMA buffer data structure
 960 * @skb:	Associated socket buffer.
 961 * @dma:	Associated physical DMA address.
 962 * len:		Actual len used.
 963 */
 964struct ksz_dma_buf {
 965	struct sk_buff *skb;
 966	dma_addr_t dma;
 967	int len;
 968};
 969
 970/**
 971 * struct ksz_desc - Descriptor structure
 972 * @phw:	Hardware descriptor pointer to uncached physical memory.
 973 * @sw:		Cached memory to hold hardware descriptor values for
 974 * 		manipulation.
 975 * @dma_buf:	Operating system dependent data structure to hold physical
 976 * 		memory buffer allocation information.
 977 */
 978struct ksz_desc {
 979	struct ksz_hw_desc *phw;
 980	struct ksz_sw_desc sw;
 981	struct ksz_dma_buf dma_buf;
 982};
 983
 984#define DMA_BUFFER(desc)  ((struct ksz_dma_buf *)(&(desc)->dma_buf))
 985
 986/**
 987 * struct ksz_desc_info - Descriptor information data structure
 988 * @ring:	First descriptor in the ring.
 989 * @cur:	Current descriptor being manipulated.
 990 * @ring_virt:	First hardware descriptor in the ring.
 991 * @ring_phys:	The physical address of the first descriptor of the ring.
 992 * @size:	Size of hardware descriptor.
 993 * @alloc:	Number of descriptors allocated.
 994 * @avail:	Number of descriptors available for use.
 995 * @last:	Index for last descriptor released to hardware.
 996 * @next:	Index for next descriptor available for use.
 997 * @mask:	Mask for index wrapping.
 998 */
 999struct ksz_desc_info {
1000	struct ksz_desc *ring;
1001	struct ksz_desc *cur;
1002	struct ksz_hw_desc *ring_virt;
1003	u32 ring_phys;
1004	int size;
1005	int alloc;
1006	int avail;
1007	int last;
1008	int next;
1009	int mask;
1010};
1011
1012/*
1013 * KSZ8842 switch definitions
1014 */
1015
1016enum {
1017	TABLE_STATIC_MAC = 0,
1018	TABLE_VLAN,
1019	TABLE_DYNAMIC_MAC,
1020	TABLE_MIB
1021};
1022
1023#define LEARNED_MAC_TABLE_ENTRIES	1024
1024#define STATIC_MAC_TABLE_ENTRIES	8
1025
1026/**
1027 * struct ksz_mac_table - Static MAC table data structure
1028 * @mac_addr:	MAC address to filter.
1029 * @vid:	VID value.
1030 * @fid:	FID value.
1031 * @ports:	Port membership.
1032 * @override:	Override setting.
1033 * @use_fid:	FID use setting.
1034 * @valid:	Valid setting indicating the entry is being used.
1035 */
1036struct ksz_mac_table {
1037	u8 mac_addr[ETH_ALEN];
1038	u16 vid;
1039	u8 fid;
1040	u8 ports;
1041	u8 override:1;
1042	u8 use_fid:1;
1043	u8 valid:1;
1044};
1045
1046#define VLAN_TABLE_ENTRIES		16
1047
1048/**
1049 * struct ksz_vlan_table - VLAN table data structure
1050 * @vid:	VID value.
1051 * @fid:	FID value.
1052 * @member:	Port membership.
1053 */
1054struct ksz_vlan_table {
1055	u16 vid;
1056	u8 fid;
1057	u8 member;
1058};
1059
1060#define DIFFSERV_ENTRIES		64
1061#define PRIO_802_1P_ENTRIES		8
1062#define PRIO_QUEUES			4
1063
1064#define SWITCH_PORT_NUM			2
1065#define TOTAL_PORT_NUM			(SWITCH_PORT_NUM + 1)
1066#define HOST_MASK			(1 << SWITCH_PORT_NUM)
1067#define PORT_MASK			7
1068
1069#define MAIN_PORT			0
1070#define OTHER_PORT			1
1071#define HOST_PORT			SWITCH_PORT_NUM
1072
1073#define PORT_COUNTER_NUM		0x20
1074#define TOTAL_PORT_COUNTER_NUM		(PORT_COUNTER_NUM + 2)
1075
1076#define MIB_COUNTER_RX_LO_PRIORITY	0x00
1077#define MIB_COUNTER_RX_HI_PRIORITY	0x01
1078#define MIB_COUNTER_RX_UNDERSIZE	0x02
1079#define MIB_COUNTER_RX_FRAGMENT		0x03
1080#define MIB_COUNTER_RX_OVERSIZE		0x04
1081#define MIB_COUNTER_RX_JABBER		0x05
1082#define MIB_COUNTER_RX_SYMBOL_ERR	0x06
1083#define MIB_COUNTER_RX_CRC_ERR		0x07
1084#define MIB_COUNTER_RX_ALIGNMENT_ERR	0x08
1085#define MIB_COUNTER_RX_CTRL_8808	0x09
1086#define MIB_COUNTER_RX_PAUSE		0x0A
1087#define MIB_COUNTER_RX_BROADCAST	0x0B
1088#define MIB_COUNTER_RX_MULTICAST	0x0C
1089#define MIB_COUNTER_RX_UNICAST		0x0D
1090#define MIB_COUNTER_RX_OCTET_64		0x0E
1091#define MIB_COUNTER_RX_OCTET_65_127	0x0F
1092#define MIB_COUNTER_RX_OCTET_128_255	0x10
1093#define MIB_COUNTER_RX_OCTET_256_511	0x11
1094#define MIB_COUNTER_RX_OCTET_512_1023	0x12
1095#define MIB_COUNTER_RX_OCTET_1024_1522	0x13
1096#define MIB_COUNTER_TX_LO_PRIORITY	0x14
1097#define MIB_COUNTER_TX_HI_PRIORITY	0x15
1098#define MIB_COUNTER_TX_LATE_COLLISION	0x16
1099#define MIB_COUNTER_TX_PAUSE		0x17
1100#define MIB_COUNTER_TX_BROADCAST	0x18
1101#define MIB_COUNTER_TX_MULTICAST	0x19
1102#define MIB_COUNTER_TX_UNICAST		0x1A
1103#define MIB_COUNTER_TX_DEFERRED		0x1B
1104#define MIB_COUNTER_TX_TOTAL_COLLISION	0x1C
1105#define MIB_COUNTER_TX_EXCESS_COLLISION	0x1D
1106#define MIB_COUNTER_TX_SINGLE_COLLISION	0x1E
1107#define MIB_COUNTER_TX_MULTI_COLLISION	0x1F
1108
1109#define MIB_COUNTER_RX_DROPPED_PACKET	0x20
1110#define MIB_COUNTER_TX_DROPPED_PACKET	0x21
1111
1112/**
1113 * struct ksz_port_mib - Port MIB data structure
1114 * @cnt_ptr:	Current pointer to MIB counter index.
1115 * @link_down:	Indication the link has just gone down.
1116 * @state:	Connection status of the port.
1117 * @mib_start:	The starting counter index.  Some ports do not start at 0.
1118 * @counter:	64-bit MIB counter value.
1119 * @dropped:	Temporary buffer to remember last read packet dropped values.
1120 *
1121 * MIB counters needs to be read periodically so that counters do not get
1122 * overflowed and give incorrect values.  A right balance is needed to
1123 * satisfy this condition and not waste too much CPU time.
1124 *
1125 * It is pointless to read MIB counters when the port is disconnected.  The
1126 * @state provides the connection status so that MIB counters are read only
1127 * when the port is connected.  The @link_down indicates the port is just
1128 * disconnected so that all MIB counters are read one last time to update the
1129 * information.
1130 */
1131struct ksz_port_mib {
1132	u8 cnt_ptr;
1133	u8 link_down;
1134	u8 state;
1135	u8 mib_start;
1136
1137	u64 counter[TOTAL_PORT_COUNTER_NUM];
1138	u32 dropped[2];
1139};
1140
1141/**
1142 * struct ksz_port_cfg - Port configuration data structure
1143 * @vid:	VID value.
1144 * @member:	Port membership.
1145 * @port_prio:	Port priority.
1146 * @rx_rate:	Receive priority rate.
1147 * @tx_rate:	Transmit priority rate.
1148 * @stp_state:	Current Spanning Tree Protocol state.
1149 */
1150struct ksz_port_cfg {
1151	u16 vid;
1152	u8 member;
1153	u8 port_prio;
1154	u32 rx_rate[PRIO_QUEUES];
1155	u32 tx_rate[PRIO_QUEUES];
1156	int stp_state;
1157};
1158
1159/**
1160 * struct ksz_switch - KSZ8842 switch data structure
1161 * @mac_table:	MAC table entries information.
1162 * @vlan_table:	VLAN table entries information.
1163 * @port_cfg:	Port configuration information.
1164 * @diffserv:	DiffServ priority settings.  Possible values from 6-bit of ToS
1165 * 		(bit7 ~ bit2) field.
1166 * @p_802_1p:	802.1P priority settings.  Possible values from 3-bit of 802.1p
1167 * 		Tag priority field.
1168 * @br_addr:	Bridge address.  Used for STP.
1169 * @other_addr:	Other MAC address.  Used for multiple network device mode.
1170 * @broad_per:	Broadcast storm percentage.
1171 * @member:	Current port membership.  Used for STP.
1172 */
1173struct ksz_switch {
1174	struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1175	struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1176	struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1177
1178	u8 diffserv[DIFFSERV_ENTRIES];
1179	u8 p_802_1p[PRIO_802_1P_ENTRIES];
1180
1181	u8 br_addr[ETH_ALEN];
1182	u8 other_addr[ETH_ALEN];
1183
1184	u8 broad_per;
1185	u8 member;
1186};
1187
1188#define TX_RATE_UNIT			10000
1189
1190/**
1191 * struct ksz_port_info - Port information data structure
1192 * @state:	Connection status of the port.
1193 * @tx_rate:	Transmit rate divided by 10000 to get Mbit.
1194 * @duplex:	Duplex mode.
1195 * @advertised:	Advertised auto-negotiation setting.  Used to determine link.
1196 * @partner:	Auto-negotiation partner setting.  Used to determine link.
1197 * @port_id:	Port index to access actual hardware register.
1198 * @pdev:	Pointer to OS dependent network device.
1199 */
1200struct ksz_port_info {
1201	uint state;
1202	uint tx_rate;
1203	u8 duplex;
1204	u8 advertised;
1205	u8 partner;
1206	u8 port_id;
1207	void *pdev;
1208};
1209
1210#define MAX_TX_HELD_SIZE		52000
1211
1212/* Hardware features and bug fixes. */
1213#define LINK_INT_WORKING		(1 << 0)
1214#define SMALL_PACKET_TX_BUG		(1 << 1)
1215#define HALF_DUPLEX_SIGNAL_BUG		(1 << 2)
1216#define RX_HUGE_FRAME			(1 << 4)
1217#define STP_SUPPORT			(1 << 8)
1218
1219/* Software overrides. */
1220#define PAUSE_FLOW_CTRL			(1 << 0)
1221#define FAST_AGING			(1 << 1)
1222
1223/**
1224 * struct ksz_hw - KSZ884X hardware data structure
1225 * @io:			Virtual address assigned.
1226 * @ksz_switch:		Pointer to KSZ8842 switch.
1227 * @port_info:		Port information.
1228 * @port_mib:		Port MIB information.
1229 * @dev_count:		Number of network devices this hardware supports.
1230 * @dst_ports:		Destination ports in switch for transmission.
1231 * @id:			Hardware ID.  Used for display only.
1232 * @mib_cnt:		Number of MIB counters this hardware has.
1233 * @mib_port_cnt:	Number of ports with MIB counters.
1234 * @tx_cfg:		Cached transmit control settings.
1235 * @rx_cfg:		Cached receive control settings.
1236 * @intr_mask:		Current interrupt mask.
1237 * @intr_set:		Current interrup set.
1238 * @intr_blocked:	Interrupt blocked.
1239 * @rx_desc_info:	Receive descriptor information.
1240 * @tx_desc_info:	Transmit descriptor information.
1241 * @tx_int_cnt:		Transmit interrupt count.  Used for TX optimization.
1242 * @tx_int_mask:	Transmit interrupt mask.  Used for TX optimization.
1243 * @tx_size:		Transmit data size.  Used for TX optimization.
1244 * 			The maximum is defined by MAX_TX_HELD_SIZE.
1245 * @perm_addr:		Permanent MAC address.
1246 * @override_addr:	Overridden MAC address.
1247 * @address:		Additional MAC address entries.
1248 * @addr_list_size:	Additional MAC address list size.
1249 * @mac_override:	Indication of MAC address overridden.
1250 * @promiscuous:	Counter to keep track of promiscuous mode set.
1251 * @all_multi:		Counter to keep track of all multicast mode set.
1252 * @multi_list:		Multicast address entries.
1253 * @multi_bits:		Cached multicast hash table settings.
1254 * @multi_list_size:	Multicast address list size.
1255 * @enabled:		Indication of hardware enabled.
1256 * @rx_stop:		Indication of receive process stop.
1257 * @features:		Hardware features to enable.
1258 * @overrides:		Hardware features to override.
1259 * @parent:		Pointer to parent, network device private structure.
1260 */
1261struct ksz_hw {
1262	void __iomem *io;
1263
1264	struct ksz_switch *ksz_switch;
1265	struct ksz_port_info port_info[SWITCH_PORT_NUM];
1266	struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1267	int dev_count;
1268	int dst_ports;
1269	int id;
1270	int mib_cnt;
1271	int mib_port_cnt;
1272
1273	u32 tx_cfg;
1274	u32 rx_cfg;
1275	u32 intr_mask;
1276	u32 intr_set;
1277	uint intr_blocked;
1278
1279	struct ksz_desc_info rx_desc_info;
1280	struct ksz_desc_info tx_desc_info;
1281
1282	int tx_int_cnt;
1283	int tx_int_mask;
1284	int tx_size;
1285
1286	u8 perm_addr[ETH_ALEN];
1287	u8 override_addr[ETH_ALEN];
1288	u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1289	u8 addr_list_size;
1290	u8 mac_override;
1291	u8 promiscuous;
1292	u8 all_multi;
1293	u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1294	u8 multi_bits[HW_MULTICAST_SIZE];
1295	u8 multi_list_size;
1296
1297	u8 enabled;
1298	u8 rx_stop;
1299	u8 reserved2[1];
1300
1301	uint features;
1302	uint overrides;
1303
1304	void *parent;
1305};
1306
1307enum {
1308	PHY_NO_FLOW_CTRL,
1309	PHY_FLOW_CTRL,
1310	PHY_TX_ONLY,
1311	PHY_RX_ONLY
1312};
1313
1314/**
1315 * struct ksz_port - Virtual port data structure
1316 * @duplex:		Duplex mode setting.  1 for half duplex, 2 for full
1317 * 			duplex, and 0 for auto, which normally results in full
1318 * 			duplex.
1319 * @speed:		Speed setting.  10 for 10 Mbit, 100 for 100 Mbit, and
1320 * 			0 for auto, which normally results in 100 Mbit.
1321 * @force_link:		Force link setting.  0 for auto-negotiation, and 1 for
1322 * 			force.
1323 * @flow_ctrl:		Flow control setting.  PHY_NO_FLOW_CTRL for no flow
1324 * 			control, and PHY_FLOW_CTRL for flow control.
1325 * 			PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1326 * 			Mbit PHY.
1327 * @first_port:		Index of first port this port supports.
1328 * @mib_port_cnt:	Number of ports with MIB counters.
1329 * @port_cnt:		Number of ports this port supports.
1330 * @counter:		Port statistics counter.
1331 * @hw:			Pointer to hardware structure.
1332 * @linked:		Pointer to port information linked to this port.
1333 */
1334struct ksz_port {
1335	u8 duplex;
1336	u8 speed;
1337	u8 force_link;
1338	u8 flow_ctrl;
1339
1340	int first_port;
1341	int mib_port_cnt;
1342	int port_cnt;
1343	u64 counter[OID_COUNTER_LAST];
1344
1345	struct ksz_hw *hw;
1346	struct ksz_port_info *linked;
1347};
1348
1349/**
1350 * struct ksz_timer_info - Timer information data structure
1351 * @timer:	Kernel timer.
1352 * @cnt:	Running timer counter.
1353 * @max:	Number of times to run timer; -1 for infinity.
1354 * @period:	Timer period in jiffies.
1355 */
1356struct ksz_timer_info {
1357	struct timer_list timer;
1358	int cnt;
1359	int max;
1360	int period;
1361};
1362
1363/**
1364 * struct ksz_shared_mem - OS dependent shared memory data structure
1365 * @dma_addr:	Physical DMA address allocated.
1366 * @alloc_size:	Allocation size.
1367 * @phys:	Actual physical address used.
1368 * @alloc_virt:	Virtual address allocated.
1369 * @virt:	Actual virtual address used.
1370 */
1371struct ksz_shared_mem {
1372	dma_addr_t dma_addr;
1373	uint alloc_size;
1374	uint phys;
1375	u8 *alloc_virt;
1376	u8 *virt;
1377};
1378
1379/**
1380 * struct ksz_counter_info - OS dependent counter information data structure
1381 * @counter:	Wait queue to wakeup after counters are read.
1382 * @time:	Next time in jiffies to read counter.
1383 * @read:	Indication of counters read in full or not.
1384 */
1385struct ksz_counter_info {
1386	wait_queue_head_t counter;
1387	unsigned long time;
1388	int read;
1389};
1390
1391/**
1392 * struct dev_info - Network device information data structure
1393 * @dev:		Pointer to network device.
1394 * @pdev:		Pointer to PCI device.
1395 * @hw:			Hardware structure.
1396 * @desc_pool:		Physical memory used for descriptor pool.
1397 * @hwlock:		Spinlock to prevent hardware from accessing.
1398 * @lock:		Mutex lock to prevent device from accessing.
1399 * @dev_rcv:		Receive process function used.
1400 * @last_skb:		Socket buffer allocated for descriptor rx fragments.
1401 * @skb_index:		Buffer index for receiving fragments.
1402 * @skb_len:		Buffer length for receiving fragments.
1403 * @mib_read:		Workqueue to read MIB counters.
1404 * @mib_timer_info:	Timer to read MIB counters.
1405 * @counter:		Used for MIB reading.
1406 * @mtu:		Current MTU used.  The default is REGULAR_RX_BUF_SIZE;
1407 * 			the maximum is MAX_RX_BUF_SIZE.
1408 * @opened:		Counter to keep track of device open.
1409 * @rx_tasklet:		Receive processing tasklet.
1410 * @tx_tasklet:		Transmit processing tasklet.
1411 * @wol_enable:		Wake-on-LAN enable set by ethtool.
1412 * @wol_support:	Wake-on-LAN support used by ethtool.
1413 * @pme_wait:		Used for KSZ8841 power management.
1414 */
1415struct dev_info {
1416	struct net_device *dev;
1417	struct pci_dev *pdev;
1418
1419	struct ksz_hw hw;
1420	struct ksz_shared_mem desc_pool;
1421
1422	spinlock_t hwlock;
1423	struct mutex lock;
1424
1425	int (*dev_rcv)(struct dev_info *);
1426
1427	struct sk_buff *last_skb;
1428	int skb_index;
1429	int skb_len;
1430
1431	struct work_struct mib_read;
1432	struct ksz_timer_info mib_timer_info;
1433	struct ksz_counter_info counter[TOTAL_PORT_NUM];
1434
1435	int mtu;
1436	int opened;
1437
1438	struct tasklet_struct rx_tasklet;
1439	struct tasklet_struct tx_tasklet;
1440
1441	int wol_enable;
1442	int wol_support;
1443	unsigned long pme_wait;
1444};
1445
1446/**
1447 * struct dev_priv - Network device private data structure
1448 * @adapter:		Adapter device information.
1449 * @port:		Port information.
1450 * @monitor_time_info:	Timer to monitor ports.
1451 * @proc_sem:		Semaphore for proc accessing.
1452 * @id:			Device ID.
1453 * @mii_if:		MII interface information.
1454 * @advertising:	Temporary variable to store advertised settings.
1455 * @msg_enable:		The message flags controlling driver output.
1456 * @media_state:	The connection status of the device.
1457 * @multicast:		The all multicast state of the device.
1458 * @promiscuous:	The promiscuous state of the device.
1459 */
1460struct dev_priv {
1461	struct dev_info *adapter;
1462	struct ksz_port port;
1463	struct ksz_timer_info monitor_timer_info;
1464
1465	struct semaphore proc_sem;
1466	int id;
1467
1468	struct mii_if_info mii_if;
1469	u32 advertising;
1470
1471	u32 msg_enable;
1472	int media_state;
1473	int multicast;
1474	int promiscuous;
1475};
1476
1477#define DRV_NAME		"KSZ884X PCI"
1478#define DEVICE_NAME		"KSZ884x PCI"
1479#define DRV_VERSION		"1.0.0"
1480#define DRV_RELDATE		"Feb 8, 2010"
1481
1482static char version[] =
1483	"Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1484
1485static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1486
1487/*
1488 * Interrupt processing primary routines
1489 */
1490
1491static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1492{
1493	writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1494}
1495
1496static inline void hw_dis_intr(struct ksz_hw *hw)
1497{
1498	hw->intr_blocked = hw->intr_mask;
1499	writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1500	hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1501}
1502
1503static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1504{
1505	hw->intr_set = interrupt;
1506	writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1507}
1508
1509static inline void hw_ena_intr(struct ksz_hw *hw)
1510{
1511	hw->intr_blocked = 0;
1512	hw_set_intr(hw, hw->intr_mask);
1513}
1514
1515static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1516{
1517	hw->intr_mask &= ~(bit);
1518}
1519
1520static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1521{
1522	u32 read_intr;
1523
1524	read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1525	hw->intr_set = read_intr & ~interrupt;
1526	writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1527	hw_dis_intr_bit(hw, interrupt);
1528}
1529
1530/**
1531 * hw_turn_on_intr - turn on specified interrupts
1532 * @hw: 	The hardware instance.
1533 * @bit:	The interrupt bits to be on.
1534 *
1535 * This routine turns on the specified interrupts in the interrupt mask so that
1536 * those interrupts will be enabled.
1537 */
1538static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1539{
1540	hw->intr_mask |= bit;
1541
1542	if (!hw->intr_blocked)
1543		hw_set_intr(hw, hw->intr_mask);
1544}
1545
1546static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1547{
1548	u32 read_intr;
1549
1550	read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1551	hw->intr_set = read_intr | interrupt;
1552	writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1553}
1554
1555static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1556{
1557	*status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1558	*status = *status & hw->intr_set;
1559}
1560
1561static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1562{
1563	if (interrupt)
1564		hw_ena_intr(hw);
1565}
1566
1567/**
1568 * hw_block_intr - block hardware interrupts
1569 *
1570 * This function blocks all interrupts of the hardware and returns the current
1571 * interrupt enable mask so that interrupts can be restored later.
1572 *
1573 * Return the current interrupt enable mask.
1574 */
1575static uint hw_block_intr(struct ksz_hw *hw)
1576{
1577	uint interrupt = 0;
1578
1579	if (!hw->intr_blocked) {
1580		hw_dis_intr(hw);
1581		interrupt = hw->intr_blocked;
1582	}
1583	return interrupt;
1584}
1585
1586/*
1587 * Hardware descriptor routines
1588 */
1589
1590static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1591{
1592	status.rx.hw_owned = 0;
1593	desc->phw->ctrl.data = cpu_to_le32(status.data);
1594}
1595
1596static inline void release_desc(struct ksz_desc *desc)
1597{
1598	desc->sw.ctrl.tx.hw_owned = 1;
1599	if (desc->sw.buf_size != desc->sw.buf.data) {
1600		desc->sw.buf_size = desc->sw.buf.data;
1601		desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1602	}
1603	desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1604}
1605
1606static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1607{
1608	*desc = &info->ring[info->last];
1609	info->last++;
1610	info->last &= info->mask;
1611	info->avail--;
1612	(*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1613}
1614
1615static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1616{
1617	desc->phw->addr = cpu_to_le32(addr);
1618}
1619
1620static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1621{
1622	desc->sw.buf.rx.buf_size = len;
1623}
1624
1625static inline void get_tx_pkt(struct ksz_desc_info *info,
1626	struct ksz_desc **desc)
1627{
1628	*desc = &info->ring[info->next];
1629	info->next++;
1630	info->next &= info->mask;
1631	info->avail--;
1632	(*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1633}
1634
1635static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1636{
1637	desc->phw->addr = cpu_to_le32(addr);
1638}
1639
1640static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1641{
1642	desc->sw.buf.tx.buf_size = len;
1643}
1644
1645/* Switch functions */
1646
1647#define TABLE_READ			0x10
1648#define TABLE_SEL_SHIFT			2
1649
1650#define HW_DELAY(hw, reg)			\
1651	do {					\
1652		u16 dummy;			\
1653		dummy = readw(hw->io + reg);	\
1654	} while (0)
1655
1656/**
1657 * sw_r_table - read 4 bytes of data from switch table
1658 * @hw:		The hardware instance.
1659 * @table:	The table selector.
1660 * @addr:	The address of the table entry.
1661 * @data:	Buffer to store the read data.
1662 *
1663 * This routine reads 4 bytes of data from the table of the switch.
1664 * Hardware interrupts are disabled to minimize corruption of read data.
1665 */
1666static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1667{
1668	u16 ctrl_addr;
1669	uint interrupt;
1670
1671	ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1672
1673	interrupt = hw_block_intr(hw);
1674
1675	writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1676	HW_DELAY(hw, KS884X_IACR_OFFSET);
1677	*data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1678
1679	hw_restore_intr(hw, interrupt);
1680}
1681
1682/**
1683 * sw_w_table_64 - write 8 bytes of data to the switch table
1684 * @hw:		The hardware instance.
1685 * @table:	The table selector.
1686 * @addr:	The address of the table entry.
1687 * @data_hi:	The high part of data to be written (bit63 ~ bit32).
1688 * @data_lo:	The low part of data to be written (bit31 ~ bit0).
1689 *
1690 * This routine writes 8 bytes of data to the table of the switch.
1691 * Hardware interrupts are disabled to minimize corruption of written data.
1692 */
1693static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1694	u32 data_lo)
1695{
1696	u16 ctrl_addr;
1697	uint interrupt;
1698
1699	ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1700
1701	interrupt = hw_block_intr(hw);
1702
1703	writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1704	writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1705
1706	writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1707	HW_DELAY(hw, KS884X_IACR_OFFSET);
1708
1709	hw_restore_intr(hw, interrupt);
1710}
1711
1712/**
1713 * sw_w_sta_mac_table - write to the static MAC table
1714 * @hw: 	The hardware instance.
1715 * @addr:	The address of the table entry.
1716 * @mac_addr:	The MAC address.
1717 * @ports:	The port members.
1718 * @override:	The flag to override the port receive/transmit settings.
1719 * @valid:	The flag to indicate entry is valid.
1720 * @use_fid:	The flag to indicate the FID is valid.
1721 * @fid:	The FID value.
1722 *
1723 * This routine writes an entry of the static MAC table of the switch.  It
1724 * calls sw_w_table_64() to write the data.
1725 */
1726static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1727	u8 ports, int override, int valid, int use_fid, u8 fid)
1728{
1729	u32 data_hi;
1730	u32 data_lo;
1731
1732	data_lo = ((u32) mac_addr[2] << 24) |
1733		((u32) mac_addr[3] << 16) |
1734		((u32) mac_addr[4] << 8) | mac_addr[5];
1735	data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1736	data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1737
1738	if (override)
1739		data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1740	if (use_fid) {
1741		data_hi |= STATIC_MAC_TABLE_USE_FID;
1742		data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1743	}
1744	if (valid)
1745		data_hi |= STATIC_MAC_TABLE_VALID;
1746
1747	sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1748}
1749
1750/**
1751 * sw_r_vlan_table - read from the VLAN table
1752 * @hw: 	The hardware instance.
1753 * @addr:	The address of the table entry.
1754 * @vid:	Buffer to store the VID.
1755 * @fid:	Buffer to store the VID.
1756 * @member:	Buffer to store the port membership.
1757 *
1758 * This function reads an entry of the VLAN table of the switch.  It calls
1759 * sw_r_table() to get the data.
1760 *
1761 * Return 0 if the entry is valid; otherwise -1.
1762 */
1763static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1764	u8 *member)
1765{
1766	u32 data;
1767
1768	sw_r_table(hw, TABLE_VLAN, addr, &data);
1769	if (data & VLAN_TABLE_VALID) {
1770		*vid = (u16)(data & VLAN_TABLE_VID);
1771		*fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1772		*member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1773			VLAN_TABLE_MEMBERSHIP_SHIFT);
1774		return 0;
1775	}
1776	return -1;
1777}
1778
1779/**
1780 * port_r_mib_cnt - read MIB counter
1781 * @hw: 	The hardware instance.
1782 * @port:	The port index.
1783 * @addr:	The address of the counter.
1784 * @cnt:	Buffer to store the counter.
1785 *
1786 * This routine reads a MIB counter of the port.
1787 * Hardware interrupts are disabled to minimize corruption of read data.
1788 */
1789static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1790{
1791	u32 data;
1792	u16 ctrl_addr;
1793	uint interrupt;
1794	int timeout;
1795
1796	ctrl_addr = addr + PORT_COUNTER_NUM * port;
1797
1798	interrupt = hw_block_intr(hw);
1799
1800	ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1801	writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1802	HW_DELAY(hw, KS884X_IACR_OFFSET);
1803
1804	for (timeout = 100; timeout > 0; timeout--) {
1805		data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1806
1807		if (data & MIB_COUNTER_VALID) {
1808			if (data & MIB_COUNTER_OVERFLOW)
1809				*cnt += MIB_COUNTER_VALUE + 1;
1810			*cnt += data & MIB_COUNTER_VALUE;
1811			break;
1812		}
1813	}
1814
1815	hw_restore_intr(hw, interrupt);
1816}
1817
1818/**
1819 * port_r_mib_pkt - read dropped packet counts
1820 * @hw: 	The hardware instance.
1821 * @port:	The port index.
1822 * @cnt:	Buffer to store the receive and transmit dropped packet counts.
1823 *
1824 * This routine reads the dropped packet counts of the port.
1825 * Hardware interrupts are disabled to minimize corruption of read data.
1826 */
1827static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1828{
1829	u32 cur;
1830	u32 data;
1831	u16 ctrl_addr;
1832	uint interrupt;
1833	int index;
1834
1835	index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1836	do {
1837		interrupt = hw_block_intr(hw);
1838
1839		ctrl_addr = (u16) index;
1840		ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | T

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