/drivers/net/ethernet/sgi/ioc3-eth.c

http://github.com/mirrors/linux · C · 1284 lines · 940 code · 230 blank · 114 comment · 109 complexity · ff63435f56f3c3b75afc136fa4eb56e0 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
  3. *
  4. * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
  5. * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
  6. *
  7. * References:
  8. * o IOC3 ASIC specification 4.51, 1996-04-18
  9. * o IEEE 802.3 specification, 2000 edition
  10. * o DP38840A Specification, National Semiconductor, March 1997
  11. *
  12. * To do:
  13. *
  14. * o Use prefetching for large packets. What is a good lower limit for
  15. * prefetching?
  16. * o Use hardware checksums.
  17. * o Which PHYs might possibly be attached to the IOC3 in real live,
  18. * which workarounds are required for them? Do we ever have Lucent's?
  19. * o For the 2.5 branch kill the mii-tool ioctls.
  20. */
  21. #define IOC3_NAME "ioc3-eth"
  22. #define IOC3_VERSION "2.6.3-4"
  23. #include <linux/delay.h>
  24. #include <linux/kernel.h>
  25. #include <linux/mm.h>
  26. #include <linux/errno.h>
  27. #include <linux/module.h>
  28. #include <linux/init.h>
  29. #include <linux/crc16.h>
  30. #include <linux/crc32.h>
  31. #include <linux/mii.h>
  32. #include <linux/in.h>
  33. #include <linux/io.h>
  34. #include <linux/ip.h>
  35. #include <linux/tcp.h>
  36. #include <linux/udp.h>
  37. #include <linux/gfp.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/ethtool.h>
  41. #include <linux/skbuff.h>
  42. #include <linux/dma-mapping.h>
  43. #include <linux/platform_device.h>
  44. #include <linux/nvmem-consumer.h>
  45. #include <net/ip.h>
  46. #include <asm/sn/ioc3.h>
  47. #include <asm/pci/bridge.h>
  48. #define CRC16_INIT 0
  49. #define CRC16_VALID 0xb001
  50. /* Number of RX buffers. This is tunable in the range of 16 <= x < 512.
  51. * The value must be a power of two.
  52. */
  53. #define RX_BUFFS 64
  54. #define RX_RING_ENTRIES 512 /* fixed in hardware */
  55. #define RX_RING_MASK (RX_RING_ENTRIES - 1)
  56. #define RX_RING_SIZE (RX_RING_ENTRIES * sizeof(u64))
  57. /* 128 TX buffers (not tunable) */
  58. #define TX_RING_ENTRIES 128
  59. #define TX_RING_MASK (TX_RING_ENTRIES - 1)
  60. #define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct ioc3_etxd))
  61. /* IOC3 does dma transfers in 128 byte blocks */
  62. #define IOC3_DMA_XFER_LEN 128UL
  63. /* Every RX buffer starts with 8 byte descriptor data */
  64. #define RX_OFFSET (sizeof(struct ioc3_erxbuf) + NET_IP_ALIGN)
  65. #define RX_BUF_SIZE (13 * IOC3_DMA_XFER_LEN)
  66. #define ETCSR_FD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21)
  67. #define ETCSR_HD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21)
  68. /* Private per NIC data of the driver. */
  69. struct ioc3_private {
  70. struct ioc3_ethregs *regs;
  71. struct device *dma_dev;
  72. u32 *ssram;
  73. unsigned long *rxr; /* pointer to receiver ring */
  74. void *tx_ring;
  75. struct ioc3_etxd *txr;
  76. dma_addr_t rxr_dma;
  77. dma_addr_t txr_dma;
  78. struct sk_buff *rx_skbs[RX_RING_ENTRIES];
  79. struct sk_buff *tx_skbs[TX_RING_ENTRIES];
  80. int rx_ci; /* RX consumer index */
  81. int rx_pi; /* RX producer index */
  82. int tx_ci; /* TX consumer index */
  83. int tx_pi; /* TX producer index */
  84. int txqlen;
  85. u32 emcr, ehar_h, ehar_l;
  86. spinlock_t ioc3_lock;
  87. struct mii_if_info mii;
  88. /* Members used by autonegotiation */
  89. struct timer_list ioc3_timer;
  90. };
  91. static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  92. static void ioc3_set_multicast_list(struct net_device *dev);
  93. static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
  94. static void ioc3_timeout(struct net_device *dev, unsigned int txqueue);
  95. static inline unsigned int ioc3_hash(const unsigned char *addr);
  96. static void ioc3_start(struct ioc3_private *ip);
  97. static inline void ioc3_stop(struct ioc3_private *ip);
  98. static void ioc3_init(struct net_device *dev);
  99. static int ioc3_alloc_rx_bufs(struct net_device *dev);
  100. static void ioc3_free_rx_bufs(struct ioc3_private *ip);
  101. static inline void ioc3_clean_tx_ring(struct ioc3_private *ip);
  102. static const struct ethtool_ops ioc3_ethtool_ops;
  103. static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
  104. {
  105. return (~addr + 1) & (IOC3_DMA_XFER_LEN - 1UL);
  106. }
  107. static inline int ioc3_alloc_skb(struct ioc3_private *ip, struct sk_buff **skb,
  108. struct ioc3_erxbuf **rxb, dma_addr_t *rxb_dma)
  109. {
  110. struct sk_buff *new_skb;
  111. dma_addr_t d;
  112. int offset;
  113. new_skb = alloc_skb(RX_BUF_SIZE + IOC3_DMA_XFER_LEN - 1, GFP_ATOMIC);
  114. if (!new_skb)
  115. return -ENOMEM;
  116. /* ensure buffer is aligned to IOC3_DMA_XFER_LEN */
  117. offset = aligned_rx_skb_addr((unsigned long)new_skb->data);
  118. if (offset)
  119. skb_reserve(new_skb, offset);
  120. d = dma_map_single(ip->dma_dev, new_skb->data,
  121. RX_BUF_SIZE, DMA_FROM_DEVICE);
  122. if (dma_mapping_error(ip->dma_dev, d)) {
  123. dev_kfree_skb_any(new_skb);
  124. return -ENOMEM;
  125. }
  126. *rxb_dma = d;
  127. *rxb = (struct ioc3_erxbuf *)new_skb->data;
  128. skb_reserve(new_skb, RX_OFFSET);
  129. *skb = new_skb;
  130. return 0;
  131. }
  132. #ifdef CONFIG_PCI_XTALK_BRIDGE
  133. static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
  134. {
  135. return (addr & ~PCI64_ATTR_BAR) | attr;
  136. }
  137. #define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT)
  138. #else
  139. static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
  140. {
  141. return addr;
  142. }
  143. #define ERBAR_VAL 0
  144. #endif
  145. static int ioc3eth_nvmem_match(struct device *dev, const void *data)
  146. {
  147. const char *name = dev_name(dev);
  148. const char *prefix = data;
  149. int prefix_len;
  150. prefix_len = strlen(prefix);
  151. if (strlen(name) < (prefix_len + 3))
  152. return 0;
  153. if (memcmp(prefix, name, prefix_len) != 0)
  154. return 0;
  155. /* found nvmem device which is attached to our ioc3
  156. * now check for one wire family code 09, 89 and 91
  157. */
  158. if (memcmp(name + prefix_len, "09-", 3) == 0)
  159. return 1;
  160. if (memcmp(name + prefix_len, "89-", 3) == 0)
  161. return 1;
  162. if (memcmp(name + prefix_len, "91-", 3) == 0)
  163. return 1;
  164. return 0;
  165. }
  166. static int ioc3eth_get_mac_addr(struct resource *res, u8 mac_addr[6])
  167. {
  168. struct nvmem_device *nvmem;
  169. char prefix[24];
  170. u8 prom[16];
  171. int ret;
  172. int i;
  173. snprintf(prefix, sizeof(prefix), "ioc3-%012llx-",
  174. res->start & ~0xffff);
  175. nvmem = nvmem_device_find(prefix, ioc3eth_nvmem_match);
  176. if (IS_ERR(nvmem))
  177. return PTR_ERR(nvmem);
  178. ret = nvmem_device_read(nvmem, 0, 16, prom);
  179. nvmem_device_put(nvmem);
  180. if (ret < 0)
  181. return ret;
  182. /* check, if content is valid */
  183. if (prom[0] != 0x0a ||
  184. crc16(CRC16_INIT, prom, 13) != CRC16_VALID)
  185. return -EINVAL;
  186. for (i = 0; i < 6; i++)
  187. mac_addr[i] = prom[10 - i];
  188. return 0;
  189. }
  190. static void __ioc3_set_mac_address(struct net_device *dev)
  191. {
  192. struct ioc3_private *ip = netdev_priv(dev);
  193. writel((dev->dev_addr[5] << 8) |
  194. dev->dev_addr[4],
  195. &ip->regs->emar_h);
  196. writel((dev->dev_addr[3] << 24) |
  197. (dev->dev_addr[2] << 16) |
  198. (dev->dev_addr[1] << 8) |
  199. dev->dev_addr[0],
  200. &ip->regs->emar_l);
  201. }
  202. static int ioc3_set_mac_address(struct net_device *dev, void *addr)
  203. {
  204. struct ioc3_private *ip = netdev_priv(dev);
  205. struct sockaddr *sa = addr;
  206. memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
  207. spin_lock_irq(&ip->ioc3_lock);
  208. __ioc3_set_mac_address(dev);
  209. spin_unlock_irq(&ip->ioc3_lock);
  210. return 0;
  211. }
  212. /* Caller must hold the ioc3_lock ever for MII readers. This is also
  213. * used to protect the transmitter side but it's low contention.
  214. */
  215. static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
  216. {
  217. struct ioc3_private *ip = netdev_priv(dev);
  218. struct ioc3_ethregs *regs = ip->regs;
  219. while (readl(&regs->micr) & MICR_BUSY)
  220. ;
  221. writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG,
  222. &regs->micr);
  223. while (readl(&regs->micr) & MICR_BUSY)
  224. ;
  225. return readl(&regs->midr_r) & MIDR_DATA_MASK;
  226. }
  227. static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
  228. {
  229. struct ioc3_private *ip = netdev_priv(dev);
  230. struct ioc3_ethregs *regs = ip->regs;
  231. while (readl(&regs->micr) & MICR_BUSY)
  232. ;
  233. writel(data, &regs->midr_w);
  234. writel((phy << MICR_PHYADDR_SHIFT) | reg, &regs->micr);
  235. while (readl(&regs->micr) & MICR_BUSY)
  236. ;
  237. }
  238. static int ioc3_mii_init(struct ioc3_private *ip);
  239. static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
  240. {
  241. struct ioc3_private *ip = netdev_priv(dev);
  242. struct ioc3_ethregs *regs = ip->regs;
  243. dev->stats.collisions += readl(&regs->etcdc) & ETCDC_COLLCNT_MASK;
  244. return &dev->stats;
  245. }
  246. static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)
  247. {
  248. struct ethhdr *eh = eth_hdr(skb);
  249. unsigned int proto;
  250. unsigned char *cp;
  251. struct iphdr *ih;
  252. u32 csum, ehsum;
  253. u16 *ew;
  254. /* Did hardware handle the checksum at all? The cases we can handle
  255. * are:
  256. *
  257. * - TCP and UDP checksums of IPv4 only.
  258. * - IPv6 would be doable but we keep that for later ...
  259. * - Only unfragmented packets. Did somebody already tell you
  260. * fragmentation is evil?
  261. * - don't care about packet size. Worst case when processing a
  262. * malformed packet we'll try to access the packet at ip header +
  263. * 64 bytes which is still inside the skb. Even in the unlikely
  264. * case where the checksum is right the higher layers will still
  265. * drop the packet as appropriate.
  266. */
  267. if (eh->h_proto != htons(ETH_P_IP))
  268. return;
  269. ih = (struct iphdr *)((char *)eh + ETH_HLEN);
  270. if (ip_is_fragment(ih))
  271. return;
  272. proto = ih->protocol;
  273. if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
  274. return;
  275. /* Same as tx - compute csum of pseudo header */
  276. csum = hwsum +
  277. (ih->tot_len - (ih->ihl << 2)) +
  278. htons((u16)ih->protocol) +
  279. (ih->saddr >> 16) + (ih->saddr & 0xffff) +
  280. (ih->daddr >> 16) + (ih->daddr & 0xffff);
  281. /* Sum up ethernet dest addr, src addr and protocol */
  282. ew = (u16 *)eh;
  283. ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
  284. ehsum = (ehsum & 0xffff) + (ehsum >> 16);
  285. ehsum = (ehsum & 0xffff) + (ehsum >> 16);
  286. csum += 0xffff ^ ehsum;
  287. /* In the next step we also subtract the 1's complement
  288. * checksum of the trailing ethernet CRC.
  289. */
  290. cp = (char *)eh + len; /* points at trailing CRC */
  291. if (len & 1) {
  292. csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]);
  293. csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]);
  294. } else {
  295. csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]);
  296. csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]);
  297. }
  298. csum = (csum & 0xffff) + (csum >> 16);
  299. csum = (csum & 0xffff) + (csum >> 16);
  300. if (csum == 0xffff)
  301. skb->ip_summed = CHECKSUM_UNNECESSARY;
  302. }
  303. static inline void ioc3_rx(struct net_device *dev)
  304. {
  305. struct ioc3_private *ip = netdev_priv(dev);
  306. struct sk_buff *skb, *new_skb;
  307. int rx_entry, n_entry, len;
  308. struct ioc3_erxbuf *rxb;
  309. unsigned long *rxr;
  310. dma_addr_t d;
  311. u32 w0, err;
  312. rxr = ip->rxr; /* Ring base */
  313. rx_entry = ip->rx_ci; /* RX consume index */
  314. n_entry = ip->rx_pi;
  315. skb = ip->rx_skbs[rx_entry];
  316. rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
  317. w0 = be32_to_cpu(rxb->w0);
  318. while (w0 & ERXBUF_V) {
  319. err = be32_to_cpu(rxb->err); /* It's valid ... */
  320. if (err & ERXBUF_GOODPKT) {
  321. len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
  322. skb_put(skb, len);
  323. skb->protocol = eth_type_trans(skb, dev);
  324. if (ioc3_alloc_skb(ip, &new_skb, &rxb, &d)) {
  325. /* Ouch, drop packet and just recycle packet
  326. * to keep the ring filled.
  327. */
  328. dev->stats.rx_dropped++;
  329. new_skb = skb;
  330. d = rxr[rx_entry];
  331. goto next;
  332. }
  333. if (likely(dev->features & NETIF_F_RXCSUM))
  334. ioc3_tcpudp_checksum(skb,
  335. w0 & ERXBUF_IPCKSUM_MASK,
  336. len);
  337. dma_unmap_single(ip->dma_dev, rxr[rx_entry],
  338. RX_BUF_SIZE, DMA_FROM_DEVICE);
  339. netif_rx(skb);
  340. ip->rx_skbs[rx_entry] = NULL; /* Poison */
  341. dev->stats.rx_packets++; /* Statistics */
  342. dev->stats.rx_bytes += len;
  343. } else {
  344. /* The frame is invalid and the skb never
  345. * reached the network layer so we can just
  346. * recycle it.
  347. */
  348. new_skb = skb;
  349. d = rxr[rx_entry];
  350. dev->stats.rx_errors++;
  351. }
  352. if (err & ERXBUF_CRCERR) /* Statistics */
  353. dev->stats.rx_crc_errors++;
  354. if (err & ERXBUF_FRAMERR)
  355. dev->stats.rx_frame_errors++;
  356. next:
  357. ip->rx_skbs[n_entry] = new_skb;
  358. rxr[n_entry] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
  359. rxb->w0 = 0; /* Clear valid flag */
  360. n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */
  361. /* Now go on to the next ring entry. */
  362. rx_entry = (rx_entry + 1) & RX_RING_MASK;
  363. skb = ip->rx_skbs[rx_entry];
  364. rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
  365. w0 = be32_to_cpu(rxb->w0);
  366. }
  367. writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir);
  368. ip->rx_pi = n_entry;
  369. ip->rx_ci = rx_entry;
  370. }
  371. static inline void ioc3_tx(struct net_device *dev)
  372. {
  373. struct ioc3_private *ip = netdev_priv(dev);
  374. struct ioc3_ethregs *regs = ip->regs;
  375. unsigned long packets, bytes;
  376. int tx_entry, o_entry;
  377. struct sk_buff *skb;
  378. u32 etcir;
  379. spin_lock(&ip->ioc3_lock);
  380. etcir = readl(&regs->etcir);
  381. tx_entry = (etcir >> 7) & TX_RING_MASK;
  382. o_entry = ip->tx_ci;
  383. packets = 0;
  384. bytes = 0;
  385. while (o_entry != tx_entry) {
  386. packets++;
  387. skb = ip->tx_skbs[o_entry];
  388. bytes += skb->len;
  389. dev_consume_skb_irq(skb);
  390. ip->tx_skbs[o_entry] = NULL;
  391. o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */
  392. etcir = readl(&regs->etcir); /* More pkts sent? */
  393. tx_entry = (etcir >> 7) & TX_RING_MASK;
  394. }
  395. dev->stats.tx_packets += packets;
  396. dev->stats.tx_bytes += bytes;
  397. ip->txqlen -= packets;
  398. if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES)
  399. netif_wake_queue(dev);
  400. ip->tx_ci = o_entry;
  401. spin_unlock(&ip->ioc3_lock);
  402. }
  403. /* Deal with fatal IOC3 errors. This condition might be caused by a hard or
  404. * software problems, so we should try to recover
  405. * more gracefully if this ever happens. In theory we might be flooded
  406. * with such error interrupts if something really goes wrong, so we might
  407. * also consider to take the interface down.
  408. */
  409. static void ioc3_error(struct net_device *dev, u32 eisr)
  410. {
  411. struct ioc3_private *ip = netdev_priv(dev);
  412. spin_lock(&ip->ioc3_lock);
  413. if (eisr & EISR_RXOFLO)
  414. net_err_ratelimited("%s: RX overflow.\n", dev->name);
  415. if (eisr & EISR_RXBUFOFLO)
  416. net_err_ratelimited("%s: RX buffer overflow.\n", dev->name);
  417. if (eisr & EISR_RXMEMERR)
  418. net_err_ratelimited("%s: RX PCI error.\n", dev->name);
  419. if (eisr & EISR_RXPARERR)
  420. net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name);
  421. if (eisr & EISR_TXBUFUFLO)
  422. net_err_ratelimited("%s: TX buffer underflow.\n", dev->name);
  423. if (eisr & EISR_TXMEMERR)
  424. net_err_ratelimited("%s: TX PCI error.\n", dev->name);
  425. ioc3_stop(ip);
  426. ioc3_free_rx_bufs(ip);
  427. ioc3_clean_tx_ring(ip);
  428. ioc3_init(dev);
  429. if (ioc3_alloc_rx_bufs(dev)) {
  430. netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
  431. spin_unlock(&ip->ioc3_lock);
  432. return;
  433. }
  434. ioc3_start(ip);
  435. ioc3_mii_init(ip);
  436. netif_wake_queue(dev);
  437. spin_unlock(&ip->ioc3_lock);
  438. }
  439. /* The interrupt handler does all of the Rx thread work and cleans up
  440. * after the Tx thread.
  441. */
  442. static irqreturn_t ioc3_interrupt(int irq, void *dev_id)
  443. {
  444. struct ioc3_private *ip = netdev_priv(dev_id);
  445. struct ioc3_ethregs *regs = ip->regs;
  446. u32 eisr;
  447. eisr = readl(&regs->eisr);
  448. writel(eisr, &regs->eisr);
  449. readl(&regs->eisr); /* Flush */
  450. if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
  451. EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
  452. ioc3_error(dev_id, eisr);
  453. if (eisr & EISR_RXTIMERINT)
  454. ioc3_rx(dev_id);
  455. if (eisr & EISR_TXEXPLICIT)
  456. ioc3_tx(dev_id);
  457. return IRQ_HANDLED;
  458. }
  459. static inline void ioc3_setup_duplex(struct ioc3_private *ip)
  460. {
  461. struct ioc3_ethregs *regs = ip->regs;
  462. spin_lock_irq(&ip->ioc3_lock);
  463. if (ip->mii.full_duplex) {
  464. writel(ETCSR_FD, &regs->etcsr);
  465. ip->emcr |= EMCR_DUPLEX;
  466. } else {
  467. writel(ETCSR_HD, &regs->etcsr);
  468. ip->emcr &= ~EMCR_DUPLEX;
  469. }
  470. writel(ip->emcr, &regs->emcr);
  471. spin_unlock_irq(&ip->ioc3_lock);
  472. }
  473. static void ioc3_timer(struct timer_list *t)
  474. {
  475. struct ioc3_private *ip = from_timer(ip, t, ioc3_timer);
  476. /* Print the link status if it has changed */
  477. mii_check_media(&ip->mii, 1, 0);
  478. ioc3_setup_duplex(ip);
  479. ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */
  480. add_timer(&ip->ioc3_timer);
  481. }
  482. /* Try to find a PHY. There is no apparent relation between the MII addresses
  483. * in the SGI documentation and what we find in reality, so we simply probe
  484. * for the PHY.
  485. */
  486. static int ioc3_mii_init(struct ioc3_private *ip)
  487. {
  488. u16 word;
  489. int i;
  490. for (i = 0; i < 32; i++) {
  491. word = ioc3_mdio_read(ip->mii.dev, i, MII_PHYSID1);
  492. if (word != 0xffff && word != 0x0000) {
  493. ip->mii.phy_id = i;
  494. return 0;
  495. }
  496. }
  497. ip->mii.phy_id = -1;
  498. return -ENODEV;
  499. }
  500. static void ioc3_mii_start(struct ioc3_private *ip)
  501. {
  502. ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */
  503. add_timer(&ip->ioc3_timer);
  504. }
  505. static inline void ioc3_tx_unmap(struct ioc3_private *ip, int entry)
  506. {
  507. struct ioc3_etxd *desc;
  508. u32 cmd, bufcnt, len;
  509. desc = &ip->txr[entry];
  510. cmd = be32_to_cpu(desc->cmd);
  511. bufcnt = be32_to_cpu(desc->bufcnt);
  512. if (cmd & ETXD_B1V) {
  513. len = (bufcnt & ETXD_B1CNT_MASK) >> ETXD_B1CNT_SHIFT;
  514. dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p1),
  515. len, DMA_TO_DEVICE);
  516. }
  517. if (cmd & ETXD_B2V) {
  518. len = (bufcnt & ETXD_B2CNT_MASK) >> ETXD_B2CNT_SHIFT;
  519. dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p2),
  520. len, DMA_TO_DEVICE);
  521. }
  522. }
  523. static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
  524. {
  525. struct sk_buff *skb;
  526. int i;
  527. for (i = 0; i < TX_RING_ENTRIES; i++) {
  528. skb = ip->tx_skbs[i];
  529. if (skb) {
  530. ioc3_tx_unmap(ip, i);
  531. ip->tx_skbs[i] = NULL;
  532. dev_kfree_skb_any(skb);
  533. }
  534. ip->txr[i].cmd = 0;
  535. }
  536. ip->tx_pi = 0;
  537. ip->tx_ci = 0;
  538. }
  539. static void ioc3_free_rx_bufs(struct ioc3_private *ip)
  540. {
  541. int rx_entry, n_entry;
  542. struct sk_buff *skb;
  543. n_entry = ip->rx_ci;
  544. rx_entry = ip->rx_pi;
  545. while (n_entry != rx_entry) {
  546. skb = ip->rx_skbs[n_entry];
  547. if (skb) {
  548. dma_unmap_single(ip->dma_dev,
  549. be64_to_cpu(ip->rxr[n_entry]),
  550. RX_BUF_SIZE, DMA_FROM_DEVICE);
  551. dev_kfree_skb_any(skb);
  552. }
  553. n_entry = (n_entry + 1) & RX_RING_MASK;
  554. }
  555. }
  556. static int ioc3_alloc_rx_bufs(struct net_device *dev)
  557. {
  558. struct ioc3_private *ip = netdev_priv(dev);
  559. struct ioc3_erxbuf *rxb;
  560. dma_addr_t d;
  561. int i;
  562. /* Now the rx buffers. The RX ring may be larger but
  563. * we only allocate 16 buffers for now. Need to tune
  564. * this for performance and memory later.
  565. */
  566. for (i = 0; i < RX_BUFFS; i++) {
  567. if (ioc3_alloc_skb(ip, &ip->rx_skbs[i], &rxb, &d))
  568. return -ENOMEM;
  569. rxb->w0 = 0; /* Clear valid flag */
  570. ip->rxr[i] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
  571. }
  572. ip->rx_ci = 0;
  573. ip->rx_pi = RX_BUFFS;
  574. return 0;
  575. }
  576. static inline void ioc3_ssram_disc(struct ioc3_private *ip)
  577. {
  578. struct ioc3_ethregs *regs = ip->regs;
  579. u32 *ssram0 = &ip->ssram[0x0000];
  580. u32 *ssram1 = &ip->ssram[0x4000];
  581. u32 pattern = 0x5555;
  582. /* Assume the larger size SSRAM and enable parity checking */
  583. writel(readl(&regs->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), &regs->emcr);
  584. readl(&regs->emcr); /* Flush */
  585. writel(pattern, ssram0);
  586. writel(~pattern & IOC3_SSRAM_DM, ssram1);
  587. if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern ||
  588. (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
  589. /* set ssram size to 64 KB */
  590. ip->emcr |= EMCR_RAMPAR;
  591. writel(readl(&regs->emcr) & ~EMCR_BUFSIZ, &regs->emcr);
  592. } else {
  593. ip->emcr |= EMCR_BUFSIZ | EMCR_RAMPAR;
  594. }
  595. }
  596. static void ioc3_init(struct net_device *dev)
  597. {
  598. struct ioc3_private *ip = netdev_priv(dev);
  599. struct ioc3_ethregs *regs = ip->regs;
  600. del_timer_sync(&ip->ioc3_timer); /* Kill if running */
  601. writel(EMCR_RST, &regs->emcr); /* Reset */
  602. readl(&regs->emcr); /* Flush WB */
  603. udelay(4); /* Give it time ... */
  604. writel(0, &regs->emcr);
  605. readl(&regs->emcr);
  606. /* Misc registers */
  607. writel(ERBAR_VAL, &regs->erbar);
  608. readl(&regs->etcdc); /* Clear on read */
  609. writel(15, &regs->ercsr); /* RX low watermark */
  610. writel(0, &regs->ertr); /* Interrupt immediately */
  611. __ioc3_set_mac_address(dev);
  612. writel(ip->ehar_h, &regs->ehar_h);
  613. writel(ip->ehar_l, &regs->ehar_l);
  614. writel(42, &regs->ersr); /* XXX should be random */
  615. }
  616. static void ioc3_start(struct ioc3_private *ip)
  617. {
  618. struct ioc3_ethregs *regs = ip->regs;
  619. unsigned long ring;
  620. /* Now the rx ring base, consume & produce registers. */
  621. ring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC);
  622. writel(ring >> 32, &regs->erbr_h);
  623. writel(ring & 0xffffffff, &regs->erbr_l);
  624. writel(ip->rx_ci << 3, &regs->ercir);
  625. writel((ip->rx_pi << 3) | ERPIR_ARM, &regs->erpir);
  626. ring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC);
  627. ip->txqlen = 0; /* nothing queued */
  628. /* Now the tx ring base, consume & produce registers. */
  629. writel(ring >> 32, &regs->etbr_h);
  630. writel(ring & 0xffffffff, &regs->etbr_l);
  631. writel(ip->tx_pi << 7, &regs->etpir);
  632. writel(ip->tx_ci << 7, &regs->etcir);
  633. readl(&regs->etcir); /* Flush */
  634. ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
  635. EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
  636. writel(ip->emcr, &regs->emcr);
  637. writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
  638. EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
  639. EISR_TXEXPLICIT | EISR_TXMEMERR, &regs->eier);
  640. readl(&regs->eier);
  641. }
  642. static inline void ioc3_stop(struct ioc3_private *ip)
  643. {
  644. struct ioc3_ethregs *regs = ip->regs;
  645. writel(0, &regs->emcr); /* Shutup */
  646. writel(0, &regs->eier); /* Disable interrupts */
  647. readl(&regs->eier); /* Flush */
  648. }
  649. static int ioc3_open(struct net_device *dev)
  650. {
  651. struct ioc3_private *ip = netdev_priv(dev);
  652. ip->ehar_h = 0;
  653. ip->ehar_l = 0;
  654. ioc3_init(dev);
  655. if (ioc3_alloc_rx_bufs(dev)) {
  656. netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
  657. return -ENOMEM;
  658. }
  659. ioc3_start(ip);
  660. ioc3_mii_start(ip);
  661. netif_start_queue(dev);
  662. return 0;
  663. }
  664. static int ioc3_close(struct net_device *dev)
  665. {
  666. struct ioc3_private *ip = netdev_priv(dev);
  667. del_timer_sync(&ip->ioc3_timer);
  668. netif_stop_queue(dev);
  669. ioc3_stop(ip);
  670. ioc3_free_rx_bufs(ip);
  671. ioc3_clean_tx_ring(ip);
  672. return 0;
  673. }
  674. static const struct net_device_ops ioc3_netdev_ops = {
  675. .ndo_open = ioc3_open,
  676. .ndo_stop = ioc3_close,
  677. .ndo_start_xmit = ioc3_start_xmit,
  678. .ndo_tx_timeout = ioc3_timeout,
  679. .ndo_get_stats = ioc3_get_stats,
  680. .ndo_set_rx_mode = ioc3_set_multicast_list,
  681. .ndo_do_ioctl = ioc3_ioctl,
  682. .ndo_validate_addr = eth_validate_addr,
  683. .ndo_set_mac_address = ioc3_set_mac_address,
  684. };
  685. static int ioc3eth_probe(struct platform_device *pdev)
  686. {
  687. u32 sw_physid1, sw_physid2, vendor, model, rev;
  688. struct ioc3_private *ip;
  689. struct net_device *dev;
  690. struct resource *regs;
  691. u8 mac_addr[6];
  692. int err;
  693. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  694. /* get mac addr from one wire prom */
  695. if (ioc3eth_get_mac_addr(regs, mac_addr))
  696. return -EPROBE_DEFER; /* not available yet */
  697. dev = alloc_etherdev(sizeof(struct ioc3_private));
  698. if (!dev)
  699. return -ENOMEM;
  700. SET_NETDEV_DEV(dev, &pdev->dev);
  701. ip = netdev_priv(dev);
  702. ip->dma_dev = pdev->dev.parent;
  703. ip->regs = devm_platform_ioremap_resource(pdev, 0);
  704. if (!ip->regs) {
  705. err = -ENOMEM;
  706. goto out_free;
  707. }
  708. ip->ssram = devm_platform_ioremap_resource(pdev, 1);
  709. if (!ip->ssram) {
  710. err = -ENOMEM;
  711. goto out_free;
  712. }
  713. dev->irq = platform_get_irq(pdev, 0);
  714. if (dev->irq < 0) {
  715. err = dev->irq;
  716. goto out_free;
  717. }
  718. if (devm_request_irq(&pdev->dev, dev->irq, ioc3_interrupt,
  719. IRQF_SHARED, "ioc3-eth", dev)) {
  720. dev_err(&pdev->dev, "Can't get irq %d\n", dev->irq);
  721. err = -ENODEV;
  722. goto out_free;
  723. }
  724. spin_lock_init(&ip->ioc3_lock);
  725. timer_setup(&ip->ioc3_timer, ioc3_timer, 0);
  726. ioc3_stop(ip);
  727. /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */
  728. ip->rxr = dma_alloc_coherent(ip->dma_dev, RX_RING_SIZE, &ip->rxr_dma,
  729. GFP_KERNEL);
  730. if (!ip->rxr) {
  731. pr_err("ioc3-eth: rx ring allocation failed\n");
  732. err = -ENOMEM;
  733. goto out_stop;
  734. }
  735. /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */
  736. ip->tx_ring = dma_alloc_coherent(ip->dma_dev, TX_RING_SIZE + SZ_16K - 1,
  737. &ip->txr_dma, GFP_KERNEL);
  738. if (!ip->tx_ring) {
  739. pr_err("ioc3-eth: tx ring allocation failed\n");
  740. err = -ENOMEM;
  741. goto out_stop;
  742. }
  743. /* Align TX ring */
  744. ip->txr = PTR_ALIGN(ip->tx_ring, SZ_16K);
  745. ip->txr_dma = ALIGN(ip->txr_dma, SZ_16K);
  746. ioc3_init(dev);
  747. ip->mii.phy_id_mask = 0x1f;
  748. ip->mii.reg_num_mask = 0x1f;
  749. ip->mii.dev = dev;
  750. ip->mii.mdio_read = ioc3_mdio_read;
  751. ip->mii.mdio_write = ioc3_mdio_write;
  752. ioc3_mii_init(ip);
  753. if (ip->mii.phy_id == -1) {
  754. netdev_err(dev, "Didn't find a PHY, goodbye.\n");
  755. err = -ENODEV;
  756. goto out_stop;
  757. }
  758. ioc3_mii_start(ip);
  759. ioc3_ssram_disc(ip);
  760. memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
  761. /* The IOC3-specific entries in the device structure. */
  762. dev->watchdog_timeo = 5 * HZ;
  763. dev->netdev_ops = &ioc3_netdev_ops;
  764. dev->ethtool_ops = &ioc3_ethtool_ops;
  765. dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  766. dev->features = NETIF_F_IP_CSUM | NETIF_F_HIGHDMA;
  767. sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
  768. sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
  769. err = register_netdev(dev);
  770. if (err)
  771. goto out_stop;
  772. mii_check_media(&ip->mii, 1, 1);
  773. ioc3_setup_duplex(ip);
  774. vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
  775. model = (sw_physid2 >> 4) & 0x3f;
  776. rev = sw_physid2 & 0xf;
  777. netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n",
  778. ip->mii.phy_id, vendor, model, rev);
  779. netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n",
  780. ip->emcr & EMCR_BUFSIZ ? 128 : 64);
  781. return 0;
  782. out_stop:
  783. del_timer_sync(&ip->ioc3_timer);
  784. if (ip->rxr)
  785. dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr,
  786. ip->rxr_dma);
  787. if (ip->tx_ring)
  788. dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->tx_ring,
  789. ip->txr_dma);
  790. out_free:
  791. free_netdev(dev);
  792. return err;
  793. }
  794. static int ioc3eth_remove(struct platform_device *pdev)
  795. {
  796. struct net_device *dev = platform_get_drvdata(pdev);
  797. struct ioc3_private *ip = netdev_priv(dev);
  798. dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, ip->rxr_dma);
  799. dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->tx_ring, ip->txr_dma);
  800. unregister_netdev(dev);
  801. del_timer_sync(&ip->ioc3_timer);
  802. free_netdev(dev);
  803. return 0;
  804. }
  805. static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  806. {
  807. struct ioc3_private *ip = netdev_priv(dev);
  808. struct ioc3_etxd *desc;
  809. unsigned long data;
  810. unsigned int len;
  811. int produce;
  812. u32 w0 = 0;
  813. /* IOC3 has a fairly simple minded checksumming hardware which simply
  814. * adds up the 1's complement checksum for the entire packet and
  815. * inserts it at an offset which can be specified in the descriptor
  816. * into the transmit packet. This means we have to compensate for the
  817. * MAC header which should not be summed and the TCP/UDP pseudo headers
  818. * manually.
  819. */
  820. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  821. const struct iphdr *ih = ip_hdr(skb);
  822. const int proto = ntohs(ih->protocol);
  823. unsigned int csoff;
  824. u32 csum, ehsum;
  825. u16 *eh;
  826. /* The MAC header. skb->mac seem the logic approach
  827. * to find the MAC header - except it's a NULL pointer ...
  828. */
  829. eh = (u16 *)skb->data;
  830. /* Sum up dest addr, src addr and protocol */
  831. ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
  832. /* Skip IP header; it's sum is always zero and was
  833. * already filled in by ip_output.c
  834. */
  835. csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
  836. ih->tot_len - (ih->ihl << 2),
  837. proto, csum_fold(ehsum));
  838. csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
  839. csum = (csum & 0xffff) + (csum >> 16);
  840. csoff = ETH_HLEN + (ih->ihl << 2);
  841. if (proto == IPPROTO_UDP) {
  842. csoff += offsetof(struct udphdr, check);
  843. udp_hdr(skb)->check = csum;
  844. }
  845. if (proto == IPPROTO_TCP) {
  846. csoff += offsetof(struct tcphdr, check);
  847. tcp_hdr(skb)->check = csum;
  848. }
  849. w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
  850. }
  851. spin_lock_irq(&ip->ioc3_lock);
  852. data = (unsigned long)skb->data;
  853. len = skb->len;
  854. produce = ip->tx_pi;
  855. desc = &ip->txr[produce];
  856. if (len <= 104) {
  857. /* Short packet, let's copy it directly into the ring. */
  858. skb_copy_from_linear_data(skb, desc->data, skb->len);
  859. if (len < ETH_ZLEN) {
  860. /* Very short packet, pad with zeros at the end. */
  861. memset(desc->data + len, 0, ETH_ZLEN - len);
  862. len = ETH_ZLEN;
  863. }
  864. desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
  865. desc->bufcnt = cpu_to_be32(len);
  866. } else if ((data ^ (data + len - 1)) & 0x4000) {
  867. unsigned long b2 = (data | 0x3fffUL) + 1UL;
  868. unsigned long s1 = b2 - data;
  869. unsigned long s2 = data + len - b2;
  870. dma_addr_t d1, d2;
  871. desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
  872. ETXD_B1V | ETXD_B2V | w0);
  873. desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
  874. (s2 << ETXD_B2CNT_SHIFT));
  875. d1 = dma_map_single(ip->dma_dev, skb->data, s1, DMA_TO_DEVICE);
  876. if (dma_mapping_error(ip->dma_dev, d1))
  877. goto drop_packet;
  878. d2 = dma_map_single(ip->dma_dev, (void *)b2, s1, DMA_TO_DEVICE);
  879. if (dma_mapping_error(ip->dma_dev, d2)) {
  880. dma_unmap_single(ip->dma_dev, d1, len, DMA_TO_DEVICE);
  881. goto drop_packet;
  882. }
  883. desc->p1 = cpu_to_be64(ioc3_map(d1, PCI64_ATTR_PREF));
  884. desc->p2 = cpu_to_be64(ioc3_map(d2, PCI64_ATTR_PREF));
  885. } else {
  886. dma_addr_t d;
  887. /* Normal sized packet that doesn't cross a page boundary. */
  888. desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
  889. desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
  890. d = dma_map_single(ip->dma_dev, skb->data, len, DMA_TO_DEVICE);
  891. if (dma_mapping_error(ip->dma_dev, d))
  892. goto drop_packet;
  893. desc->p1 = cpu_to_be64(ioc3_map(d, PCI64_ATTR_PREF));
  894. }
  895. mb(); /* make sure all descriptor changes are visible */
  896. ip->tx_skbs[produce] = skb; /* Remember skb */
  897. produce = (produce + 1) & TX_RING_MASK;
  898. ip->tx_pi = produce;
  899. writel(produce << 7, &ip->regs->etpir); /* Fire ... */
  900. ip->txqlen++;
  901. if (ip->txqlen >= (TX_RING_ENTRIES - 1))
  902. netif_stop_queue(dev);
  903. spin_unlock_irq(&ip->ioc3_lock);
  904. return NETDEV_TX_OK;
  905. drop_packet:
  906. dev_kfree_skb_any(skb);
  907. dev->stats.tx_dropped++;
  908. spin_unlock_irq(&ip->ioc3_lock);
  909. return NETDEV_TX_OK;
  910. }
  911. static void ioc3_timeout(struct net_device *dev, unsigned int txqueue)
  912. {
  913. struct ioc3_private *ip = netdev_priv(dev);
  914. netdev_err(dev, "transmit timed out, resetting\n");
  915. spin_lock_irq(&ip->ioc3_lock);
  916. ioc3_stop(ip);
  917. ioc3_free_rx_bufs(ip);
  918. ioc3_clean_tx_ring(ip);
  919. ioc3_init(dev);
  920. if (ioc3_alloc_rx_bufs(dev)) {
  921. netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
  922. spin_unlock_irq(&ip->ioc3_lock);
  923. return;
  924. }
  925. ioc3_start(ip);
  926. ioc3_mii_init(ip);
  927. ioc3_mii_start(ip);
  928. spin_unlock_irq(&ip->ioc3_lock);
  929. netif_wake_queue(dev);
  930. }
  931. /* Given a multicast ethernet address, this routine calculates the
  932. * address's bit index in the logical address filter mask
  933. */
  934. static inline unsigned int ioc3_hash(const unsigned char *addr)
  935. {
  936. unsigned int temp = 0;
  937. int bits;
  938. u32 crc;
  939. crc = ether_crc_le(ETH_ALEN, addr);
  940. crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
  941. for (bits = 6; --bits >= 0; ) {
  942. temp <<= 1;
  943. temp |= (crc & 0x1);
  944. crc >>= 1;
  945. }
  946. return temp;
  947. }
  948. static void ioc3_get_drvinfo(struct net_device *dev,
  949. struct ethtool_drvinfo *info)
  950. {
  951. strlcpy(info->driver, IOC3_NAME, sizeof(info->driver));
  952. strlcpy(info->version, IOC3_VERSION, sizeof(info->version));
  953. strlcpy(info->bus_info, pci_name(to_pci_dev(dev->dev.parent)),
  954. sizeof(info->bus_info));
  955. }
  956. static int ioc3_get_link_ksettings(struct net_device *dev,
  957. struct ethtool_link_ksettings *cmd)
  958. {
  959. struct ioc3_private *ip = netdev_priv(dev);
  960. spin_lock_irq(&ip->ioc3_lock);
  961. mii_ethtool_get_link_ksettings(&ip->mii, cmd);
  962. spin_unlock_irq(&ip->ioc3_lock);
  963. return 0;
  964. }
  965. static int ioc3_set_link_ksettings(struct net_device *dev,
  966. const struct ethtool_link_ksettings *cmd)
  967. {
  968. struct ioc3_private *ip = netdev_priv(dev);
  969. int rc;
  970. spin_lock_irq(&ip->ioc3_lock);
  971. rc = mii_ethtool_set_link_ksettings(&ip->mii, cmd);
  972. spin_unlock_irq(&ip->ioc3_lock);
  973. return rc;
  974. }
  975. static int ioc3_nway_reset(struct net_device *dev)
  976. {
  977. struct ioc3_private *ip = netdev_priv(dev);
  978. int rc;
  979. spin_lock_irq(&ip->ioc3_lock);
  980. rc = mii_nway_restart(&ip->mii);
  981. spin_unlock_irq(&ip->ioc3_lock);
  982. return rc;
  983. }
  984. static u32 ioc3_get_link(struct net_device *dev)
  985. {
  986. struct ioc3_private *ip = netdev_priv(dev);
  987. int rc;
  988. spin_lock_irq(&ip->ioc3_lock);
  989. rc = mii_link_ok(&ip->mii);
  990. spin_unlock_irq(&ip->ioc3_lock);
  991. return rc;
  992. }
  993. static const struct ethtool_ops ioc3_ethtool_ops = {
  994. .get_drvinfo = ioc3_get_drvinfo,
  995. .nway_reset = ioc3_nway_reset,
  996. .get_link = ioc3_get_link,
  997. .get_link_ksettings = ioc3_get_link_ksettings,
  998. .set_link_ksettings = ioc3_set_link_ksettings,
  999. };
  1000. static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1001. {
  1002. struct ioc3_private *ip = netdev_priv(dev);
  1003. int rc;
  1004. spin_lock_irq(&ip->ioc3_lock);
  1005. rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
  1006. spin_unlock_irq(&ip->ioc3_lock);
  1007. return rc;
  1008. }
  1009. static void ioc3_set_multicast_list(struct net_device *dev)
  1010. {
  1011. struct ioc3_private *ip = netdev_priv(dev);
  1012. struct ioc3_ethregs *regs = ip->regs;
  1013. struct netdev_hw_addr *ha;
  1014. u64 ehar = 0;
  1015. spin_lock_irq(&ip->ioc3_lock);
  1016. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  1017. ip->emcr |= EMCR_PROMISC;
  1018. writel(ip->emcr, &regs->emcr);
  1019. readl(&regs->emcr);
  1020. } else {
  1021. ip->emcr &= ~EMCR_PROMISC;
  1022. writel(ip->emcr, &regs->emcr); /* Clear promiscuous. */
  1023. readl(&regs->emcr);
  1024. if ((dev->flags & IFF_ALLMULTI) ||
  1025. (netdev_mc_count(dev) > 64)) {
  1026. /* Too many for hashing to make sense or we want all
  1027. * multicast packets anyway, so skip computing all the
  1028. * hashes and just accept all packets.
  1029. */
  1030. ip->ehar_h = 0xffffffff;
  1031. ip->ehar_l = 0xffffffff;
  1032. } else {
  1033. netdev_for_each_mc_addr(ha, dev) {
  1034. ehar |= (1UL << ioc3_hash(ha->addr));
  1035. }
  1036. ip->ehar_h = ehar >> 32;
  1037. ip->ehar_l = ehar & 0xffffffff;
  1038. }
  1039. writel(ip->ehar_h, &regs->ehar_h);
  1040. writel(ip->ehar_l, &regs->ehar_l);
  1041. }
  1042. spin_unlock_irq(&ip->ioc3_lock);
  1043. }
  1044. static struct platform_driver ioc3eth_driver = {
  1045. .probe = ioc3eth_probe,
  1046. .remove = ioc3eth_remove,
  1047. .driver = {
  1048. .name = "ioc3-eth",
  1049. }
  1050. };
  1051. module_platform_driver(ioc3eth_driver);
  1052. MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
  1053. MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
  1054. MODULE_LICENSE("GPL");