/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c

http://github.com/mirrors/linux · C · 1430 lines · 1195 code · 209 blank · 26 comment · 209 complexity · 8df8f4aa8e9ebef0080b3c6fe763bef8 MD5 · raw file

  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
  9. {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
  10. {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  11. {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
  12. {QLCNIC_CMD_DESTROY_TX_CTX, 3, 1},
  13. {QLCNIC_CMD_INTRPT_TEST, 4, 1},
  14. {QLCNIC_CMD_SET_MTU, 4, 1},
  15. {QLCNIC_CMD_READ_PHY, 4, 2},
  16. {QLCNIC_CMD_WRITE_PHY, 5, 1},
  17. {QLCNIC_CMD_READ_HW_REG, 4, 1},
  18. {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  19. {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  20. {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  21. {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  22. {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  23. {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
  24. {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
  25. {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
  26. {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  27. {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  28. {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  29. {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  30. {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  31. {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
  32. {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  33. {QLCNIC_CMD_GET_ESWITCH_STATS, 4, 1},
  34. {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  35. {QLCNIC_CMD_TEMP_SIZE, 4, 4},
  36. {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
  37. {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
  38. {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
  39. {QLCNIC_CMD_MQ_TX_CONFIG_INTR, 2, 3},
  40. {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  41. {QLCNIC_CMD_DCB_QUERY_PARAM, 4, 1},
  42. };
  43. static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
  44. {
  45. return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
  46. (0xcafe << 16);
  47. }
  48. /* Allocate mailbox registers */
  49. int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
  50. struct qlcnic_adapter *adapter, u32 type)
  51. {
  52. int i, size;
  53. const struct qlcnic_mailbox_metadata *mbx_tbl;
  54. mbx_tbl = qlcnic_mbx_tbl;
  55. size = ARRAY_SIZE(qlcnic_mbx_tbl);
  56. for (i = 0; i < size; i++) {
  57. if (type == mbx_tbl[i].cmd) {
  58. mbx->req.num = mbx_tbl[i].in_args;
  59. mbx->rsp.num = mbx_tbl[i].out_args;
  60. mbx->req.arg = kcalloc(mbx->req.num,
  61. sizeof(u32), GFP_ATOMIC);
  62. if (!mbx->req.arg)
  63. return -ENOMEM;
  64. mbx->rsp.arg = kcalloc(mbx->rsp.num,
  65. sizeof(u32), GFP_ATOMIC);
  66. if (!mbx->rsp.arg) {
  67. kfree(mbx->req.arg);
  68. mbx->req.arg = NULL;
  69. return -ENOMEM;
  70. }
  71. mbx->req.arg[0] = type;
  72. break;
  73. }
  74. }
  75. return 0;
  76. }
  77. /* Free up mailbox registers */
  78. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
  79. {
  80. kfree(cmd->req.arg);
  81. cmd->req.arg = NULL;
  82. kfree(cmd->rsp.arg);
  83. cmd->rsp.arg = NULL;
  84. }
  85. static u32
  86. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  87. {
  88. u32 rsp;
  89. int timeout = 0, err = 0;
  90. do {
  91. /* give atleast 1ms for firmware to respond */
  92. mdelay(1);
  93. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  94. return QLCNIC_CDRP_RSP_TIMEOUT;
  95. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
  96. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  97. return rsp;
  98. }
  99. int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
  100. struct qlcnic_cmd_args *cmd)
  101. {
  102. int i, err = 0;
  103. u32 rsp;
  104. u32 signature;
  105. struct pci_dev *pdev = adapter->pdev;
  106. struct qlcnic_hardware_context *ahw = adapter->ahw;
  107. const char *fmt;
  108. signature = qlcnic_get_cmd_signature(ahw);
  109. /* Acquire semaphore before accessing CRB */
  110. if (qlcnic_api_lock(adapter)) {
  111. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  112. return cmd->rsp.arg[0];
  113. }
  114. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  115. for (i = 1; i < cmd->req.num; i++)
  116. QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
  117. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
  118. QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
  119. rsp = qlcnic_poll_rsp(adapter);
  120. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  121. dev_err(&pdev->dev, "command timeout, response = 0x%x\n", rsp);
  122. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  123. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  124. cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
  125. switch (cmd->rsp.arg[0]) {
  126. case QLCNIC_RCODE_INVALID_ARGS:
  127. fmt = "CDRP invalid args: [%d]\n";
  128. break;
  129. case QLCNIC_RCODE_NOT_SUPPORTED:
  130. case QLCNIC_RCODE_NOT_IMPL:
  131. fmt = "CDRP command not supported: [%d]\n";
  132. break;
  133. case QLCNIC_RCODE_NOT_PERMITTED:
  134. fmt = "CDRP requested action not permitted: [%d]\n";
  135. break;
  136. case QLCNIC_RCODE_INVALID:
  137. fmt = "CDRP invalid or unknown cmd received: [%d]\n";
  138. break;
  139. case QLCNIC_RCODE_TIMEOUT:
  140. fmt = "CDRP command timeout: [%d]\n";
  141. break;
  142. default:
  143. fmt = "CDRP command failed: [%d]\n";
  144. break;
  145. }
  146. dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
  147. qlcnic_dump_mbx(adapter, cmd);
  148. } else if (rsp == QLCNIC_CDRP_RSP_OK)
  149. cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
  150. for (i = 1; i < cmd->rsp.num; i++)
  151. cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
  152. /* Release semaphore */
  153. qlcnic_api_unlock(adapter);
  154. return cmd->rsp.arg[0];
  155. }
  156. int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
  157. {
  158. struct qlcnic_cmd_args cmd;
  159. u32 arg1, arg2, arg3;
  160. char drv_string[12];
  161. int err = 0;
  162. memset(drv_string, 0, sizeof(drv_string));
  163. snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
  164. _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
  165. _QLCNIC_LINUX_SUBVERSION);
  166. err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
  167. if (err)
  168. return err;
  169. memcpy(&arg1, drv_string, sizeof(u32));
  170. memcpy(&arg2, drv_string + 4, sizeof(u32));
  171. memcpy(&arg3, drv_string + 8, sizeof(u32));
  172. cmd.req.arg[1] = arg1;
  173. cmd.req.arg[2] = arg2;
  174. cmd.req.arg[3] = arg3;
  175. err = qlcnic_issue_cmd(adapter, &cmd);
  176. if (err) {
  177. dev_info(&adapter->pdev->dev,
  178. "Failed to set driver version in firmware\n");
  179. err = -EIO;
  180. }
  181. qlcnic_free_mbx_args(&cmd);
  182. return err;
  183. }
  184. int
  185. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  186. {
  187. int err = 0;
  188. struct qlcnic_cmd_args cmd;
  189. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  190. if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
  191. return err;
  192. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
  193. if (err)
  194. return err;
  195. cmd.req.arg[1] = recv_ctx->context_id;
  196. cmd.req.arg[2] = mtu;
  197. err = qlcnic_issue_cmd(adapter, &cmd);
  198. if (err) {
  199. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  200. err = -EIO;
  201. }
  202. qlcnic_free_mbx_args(&cmd);
  203. return err;
  204. }
  205. int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  206. {
  207. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  208. struct qlcnic_hardware_context *ahw = adapter->ahw;
  209. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  210. struct net_device *netdev = adapter->netdev;
  211. u32 temp_intr_crb_mode, temp_rds_crb_mode;
  212. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  213. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  214. struct qlcnic_hostrq_rds_ring *prq_rds;
  215. struct qlcnic_hostrq_sds_ring *prq_sds;
  216. struct qlcnic_host_rds_ring *rds_ring;
  217. struct qlcnic_host_sds_ring *sds_ring;
  218. struct qlcnic_cardrsp_rx_ctx *prsp;
  219. struct qlcnic_hostrq_rx_ctx *prq;
  220. u8 i, nrds_rings, nsds_rings;
  221. struct qlcnic_cmd_args cmd;
  222. size_t rq_size, rsp_size;
  223. u32 cap, reg, val, reg2;
  224. u64 phys_addr;
  225. u16 temp_u16;
  226. void *addr;
  227. int err;
  228. nrds_rings = adapter->max_rds_rings;
  229. nsds_rings = adapter->drv_sds_rings;
  230. rq_size = SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  231. nsds_rings);
  232. rsp_size = SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  233. nsds_rings);
  234. addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  235. &hostrq_phys_addr, GFP_KERNEL);
  236. if (addr == NULL)
  237. return -ENOMEM;
  238. prq = addr;
  239. addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  240. &cardrsp_phys_addr, GFP_KERNEL);
  241. if (addr == NULL) {
  242. err = -ENOMEM;
  243. goto out_free_rq;
  244. }
  245. prsp = addr;
  246. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  247. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  248. | QLCNIC_CAP0_VALIDOFF);
  249. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  250. if (qlcnic_check_multi_tx(adapter) &&
  251. !adapter->ahw->diag_test) {
  252. cap |= QLCNIC_CAP0_TX_MULTI;
  253. } else {
  254. temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
  255. prq->valid_field_offset = cpu_to_le16(temp_u16);
  256. prq->txrx_sds_binding = nsds_rings - 1;
  257. temp_intr_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  258. prq->host_int_crb_mode = cpu_to_le32(temp_intr_crb_mode);
  259. temp_rds_crb_mode = QLCNIC_HOST_RDS_CRB_MODE_UNIQUE;
  260. prq->host_rds_crb_mode = cpu_to_le32(temp_rds_crb_mode);
  261. }
  262. prq->capabilities[0] = cpu_to_le32(cap);
  263. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  264. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  265. prq->rds_ring_offset = 0;
  266. val = le32_to_cpu(prq->rds_ring_offset) +
  267. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  268. prq->sds_ring_offset = cpu_to_le32(val);
  269. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  270. le32_to_cpu(prq->rds_ring_offset));
  271. for (i = 0; i < nrds_rings; i++) {
  272. rds_ring = &recv_ctx->rds_rings[i];
  273. rds_ring->producer = 0;
  274. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  275. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  276. prq_rds[i].ring_kind = cpu_to_le32(i);
  277. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  278. }
  279. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  280. le32_to_cpu(prq->sds_ring_offset));
  281. for (i = 0; i < nsds_rings; i++) {
  282. sds_ring = &recv_ctx->sds_rings[i];
  283. sds_ring->consumer = 0;
  284. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  285. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  286. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  287. if (qlcnic_check_multi_tx(adapter) &&
  288. !adapter->ahw->diag_test)
  289. prq_sds[i].msi_index = cpu_to_le16(ahw->intr_tbl[i].id);
  290. else
  291. prq_sds[i].msi_index = cpu_to_le16(i);
  292. }
  293. phys_addr = hostrq_phys_addr;
  294. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
  295. if (err)
  296. goto out_free_rsp;
  297. cmd.req.arg[1] = MSD(phys_addr);
  298. cmd.req.arg[2] = LSD(phys_addr);
  299. cmd.req.arg[3] = rq_size;
  300. err = qlcnic_issue_cmd(adapter, &cmd);
  301. if (err) {
  302. dev_err(&adapter->pdev->dev,
  303. "Failed to create rx ctx in firmware%d\n", err);
  304. goto out_free_rsp;
  305. }
  306. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  307. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  308. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  309. rds_ring = &recv_ctx->rds_rings[i];
  310. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  311. rds_ring->crb_rcv_producer = ahw->pci_base0 + reg;
  312. }
  313. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  314. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  315. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  316. sds_ring = &recv_ctx->sds_rings[i];
  317. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  318. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  319. reg2 = ahw->intr_tbl[i].src;
  320. else
  321. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  322. sds_ring->crb_intr_mask = ahw->pci_base0 + reg2;
  323. sds_ring->crb_sts_consumer = ahw->pci_base0 + reg;
  324. }
  325. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  326. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  327. recv_ctx->virt_port = prsp->virt_port;
  328. netdev_info(netdev, "Rx Context[%d] Created, state 0x%x\n",
  329. recv_ctx->context_id, recv_ctx->state);
  330. qlcnic_free_mbx_args(&cmd);
  331. out_free_rsp:
  332. dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
  333. cardrsp_phys_addr);
  334. out_free_rq:
  335. dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
  336. return err;
  337. }
  338. void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
  339. {
  340. int err;
  341. struct qlcnic_cmd_args cmd;
  342. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  343. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
  344. if (err)
  345. return;
  346. cmd.req.arg[1] = recv_ctx->context_id;
  347. err = qlcnic_issue_cmd(adapter, &cmd);
  348. if (err)
  349. dev_err(&adapter->pdev->dev,
  350. "Failed to destroy rx ctx in firmware\n");
  351. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  352. qlcnic_free_mbx_args(&cmd);
  353. }
  354. int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
  355. struct qlcnic_host_tx_ring *tx_ring,
  356. int ring)
  357. {
  358. struct qlcnic_hardware_context *ahw = adapter->ahw;
  359. struct net_device *netdev = adapter->netdev;
  360. struct qlcnic_hostrq_tx_ctx *prq;
  361. struct qlcnic_hostrq_cds_ring *prq_cds;
  362. struct qlcnic_cardrsp_tx_ctx *prsp;
  363. struct qlcnic_cmd_args cmd;
  364. u32 temp, intr_mask, temp_int_crb_mode;
  365. dma_addr_t rq_phys_addr, rsp_phys_addr;
  366. int temp_nsds_rings, index, err;
  367. void *rq_addr, *rsp_addr;
  368. size_t rq_size, rsp_size;
  369. u64 phys_addr;
  370. u16 msix_id;
  371. /* reset host resources */
  372. tx_ring->producer = 0;
  373. tx_ring->sw_consumer = 0;
  374. *(tx_ring->hw_consumer) = 0;
  375. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  376. rq_addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  377. &rq_phys_addr, GFP_KERNEL);
  378. if (!rq_addr)
  379. return -ENOMEM;
  380. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  381. rsp_addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  382. &rsp_phys_addr, GFP_KERNEL);
  383. if (!rsp_addr) {
  384. err = -ENOMEM;
  385. goto out_free_rq;
  386. }
  387. prq = rq_addr;
  388. prsp = rsp_addr;
  389. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  390. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  391. QLCNIC_CAP0_LSO);
  392. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  393. temp |= QLCNIC_CAP0_TX_MULTI;
  394. prq->capabilities[0] = cpu_to_le32(temp);
  395. if (qlcnic_check_multi_tx(adapter) &&
  396. !adapter->ahw->diag_test) {
  397. temp_nsds_rings = adapter->drv_sds_rings;
  398. index = temp_nsds_rings + ring;
  399. msix_id = ahw->intr_tbl[index].id;
  400. prq->msi_index = cpu_to_le16(msix_id);
  401. } else {
  402. temp_int_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  403. prq->host_int_crb_mode = cpu_to_le32(temp_int_crb_mode);
  404. prq->msi_index = 0;
  405. }
  406. prq->interrupt_ctl = 0;
  407. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  408. prq_cds = &prq->cds_ring;
  409. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  410. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  411. phys_addr = rq_phys_addr;
  412. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
  413. if (err)
  414. goto out_free_rsp;
  415. cmd.req.arg[1] = MSD(phys_addr);
  416. cmd.req.arg[2] = LSD(phys_addr);
  417. cmd.req.arg[3] = rq_size;
  418. err = qlcnic_issue_cmd(adapter, &cmd);
  419. if (err == QLCNIC_RCODE_SUCCESS) {
  420. tx_ring->state = le32_to_cpu(prsp->host_ctx_state);
  421. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  422. tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
  423. tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
  424. if (qlcnic_check_multi_tx(adapter) &&
  425. !adapter->ahw->diag_test &&
  426. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  427. index = adapter->drv_sds_rings + ring;
  428. intr_mask = ahw->intr_tbl[index].src;
  429. tx_ring->crb_intr_mask = ahw->pci_base0 + intr_mask;
  430. }
  431. netdev_info(netdev, "Tx Context[0x%x] Created, state 0x%x\n",
  432. tx_ring->ctx_id, tx_ring->state);
  433. } else {
  434. netdev_err(netdev, "Failed to create tx ctx in firmware%d\n",
  435. err);
  436. err = -EIO;
  437. }
  438. qlcnic_free_mbx_args(&cmd);
  439. out_free_rsp:
  440. dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
  441. rsp_phys_addr);
  442. out_free_rq:
  443. dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
  444. return err;
  445. }
  446. void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
  447. struct qlcnic_host_tx_ring *tx_ring)
  448. {
  449. struct qlcnic_cmd_args cmd;
  450. int ret;
  451. ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
  452. if (ret)
  453. return;
  454. cmd.req.arg[1] = tx_ring->ctx_id;
  455. if (qlcnic_issue_cmd(adapter, &cmd))
  456. dev_err(&adapter->pdev->dev,
  457. "Failed to destroy tx ctx in firmware\n");
  458. qlcnic_free_mbx_args(&cmd);
  459. }
  460. int
  461. qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
  462. {
  463. int err;
  464. struct qlcnic_cmd_args cmd;
  465. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
  466. if (err)
  467. return err;
  468. cmd.req.arg[1] = config;
  469. err = qlcnic_issue_cmd(adapter, &cmd);
  470. qlcnic_free_mbx_args(&cmd);
  471. return err;
  472. }
  473. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  474. {
  475. void *addr;
  476. int err, ring;
  477. struct qlcnic_recv_context *recv_ctx;
  478. struct qlcnic_host_rds_ring *rds_ring;
  479. struct qlcnic_host_sds_ring *sds_ring;
  480. struct qlcnic_host_tx_ring *tx_ring;
  481. __le32 *ptr;
  482. struct pci_dev *pdev = adapter->pdev;
  483. recv_ctx = adapter->recv_ctx;
  484. for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
  485. tx_ring = &adapter->tx_ring[ring];
  486. ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
  487. &tx_ring->hw_cons_phys_addr,
  488. GFP_KERNEL);
  489. if (ptr == NULL) {
  490. err = -ENOMEM;
  491. goto err_out_free;
  492. }
  493. tx_ring->hw_consumer = ptr;
  494. /* cmd desc ring */
  495. addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
  496. &tx_ring->phys_addr,
  497. GFP_KERNEL);
  498. if (addr == NULL) {
  499. err = -ENOMEM;
  500. goto err_out_free;
  501. }
  502. tx_ring->desc_head = addr;
  503. }
  504. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  505. rds_ring = &recv_ctx->rds_rings[ring];
  506. addr = dma_alloc_coherent(&adapter->pdev->dev,
  507. RCV_DESC_RINGSIZE(rds_ring),
  508. &rds_ring->phys_addr, GFP_KERNEL);
  509. if (addr == NULL) {
  510. err = -ENOMEM;
  511. goto err_out_free;
  512. }
  513. rds_ring->desc_head = addr;
  514. }
  515. for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
  516. sds_ring = &recv_ctx->sds_rings[ring];
  517. addr = dma_alloc_coherent(&adapter->pdev->dev,
  518. STATUS_DESC_RINGSIZE(sds_ring),
  519. &sds_ring->phys_addr, GFP_KERNEL);
  520. if (addr == NULL) {
  521. err = -ENOMEM;
  522. goto err_out_free;
  523. }
  524. sds_ring->desc_head = addr;
  525. }
  526. return 0;
  527. err_out_free:
  528. qlcnic_free_hw_resources(adapter);
  529. return err;
  530. }
  531. int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
  532. {
  533. int i, err, ring;
  534. if (dev->flags & QLCNIC_NEED_FLR) {
  535. pci_reset_function(dev->pdev);
  536. dev->flags &= ~QLCNIC_NEED_FLR;
  537. }
  538. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  539. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
  540. err = qlcnic_83xx_config_intrpt(dev, 1);
  541. if (err)
  542. return err;
  543. }
  544. }
  545. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  546. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test) {
  547. err = qlcnic_82xx_mq_intrpt(dev, 1);
  548. if (err)
  549. return err;
  550. }
  551. err = qlcnic_fw_cmd_create_rx_ctx(dev);
  552. if (err)
  553. goto err_out;
  554. for (ring = 0; ring < dev->drv_tx_rings; ring++) {
  555. err = qlcnic_fw_cmd_create_tx_ctx(dev,
  556. &dev->tx_ring[ring],
  557. ring);
  558. if (err) {
  559. qlcnic_fw_cmd_del_rx_ctx(dev);
  560. if (ring == 0)
  561. goto err_out;
  562. for (i = 0; i < ring; i++)
  563. qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
  564. goto err_out;
  565. }
  566. }
  567. set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
  568. return 0;
  569. err_out:
  570. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  571. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test)
  572. qlcnic_82xx_config_intrpt(dev, 0);
  573. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  574. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  575. qlcnic_83xx_config_intrpt(dev, 0);
  576. }
  577. return err;
  578. }
  579. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  580. {
  581. int ring;
  582. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  583. qlcnic_fw_cmd_del_rx_ctx(adapter);
  584. for (ring = 0; ring < adapter->drv_tx_rings; ring++)
  585. qlcnic_fw_cmd_del_tx_ctx(adapter,
  586. &adapter->tx_ring[ring]);
  587. if (qlcnic_82xx_check(adapter) &&
  588. (adapter->flags & QLCNIC_MSIX_ENABLED) &&
  589. qlcnic_check_multi_tx(adapter) &&
  590. !adapter->ahw->diag_test)
  591. qlcnic_82xx_config_intrpt(adapter, 0);
  592. if (qlcnic_83xx_check(adapter) &&
  593. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  594. if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  595. qlcnic_83xx_config_intrpt(adapter, 0);
  596. }
  597. /* Allow dma queues to drain after context reset */
  598. mdelay(20);
  599. }
  600. }
  601. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  602. {
  603. struct qlcnic_recv_context *recv_ctx;
  604. struct qlcnic_host_rds_ring *rds_ring;
  605. struct qlcnic_host_sds_ring *sds_ring;
  606. struct qlcnic_host_tx_ring *tx_ring;
  607. int ring;
  608. recv_ctx = adapter->recv_ctx;
  609. for (ring = 0; ring < adapter->drv_tx_rings; ring++) {
  610. tx_ring = &adapter->tx_ring[ring];
  611. if (tx_ring->hw_consumer != NULL) {
  612. dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
  613. tx_ring->hw_consumer,
  614. tx_ring->hw_cons_phys_addr);
  615. tx_ring->hw_consumer = NULL;
  616. }
  617. if (tx_ring->desc_head != NULL) {
  618. dma_free_coherent(&adapter->pdev->dev,
  619. TX_DESC_RINGSIZE(tx_ring),
  620. tx_ring->desc_head,
  621. tx_ring->phys_addr);
  622. tx_ring->desc_head = NULL;
  623. }
  624. }
  625. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  626. rds_ring = &recv_ctx->rds_rings[ring];
  627. if (rds_ring->desc_head != NULL) {
  628. dma_free_coherent(&adapter->pdev->dev,
  629. RCV_DESC_RINGSIZE(rds_ring),
  630. rds_ring->desc_head,
  631. rds_ring->phys_addr);
  632. rds_ring->desc_head = NULL;
  633. }
  634. }
  635. for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
  636. sds_ring = &recv_ctx->sds_rings[ring];
  637. if (sds_ring->desc_head != NULL) {
  638. dma_free_coherent(&adapter->pdev->dev,
  639. STATUS_DESC_RINGSIZE(sds_ring),
  640. sds_ring->desc_head,
  641. sds_ring->phys_addr);
  642. sds_ring->desc_head = NULL;
  643. }
  644. }
  645. }
  646. int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *adapter, u8 op_type)
  647. {
  648. struct qlcnic_hardware_context *ahw = adapter->ahw;
  649. struct net_device *netdev = adapter->netdev;
  650. struct qlcnic_cmd_args cmd;
  651. u32 type, val;
  652. int i, err = 0;
  653. for (i = 0; i < ahw->num_msix; i++) {
  654. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  655. QLCNIC_CMD_MQ_TX_CONFIG_INTR);
  656. if (err)
  657. return err;
  658. type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
  659. val = type | (ahw->intr_tbl[i].type << 4);
  660. if (ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
  661. val |= (ahw->intr_tbl[i].id << 16);
  662. cmd.req.arg[1] = val;
  663. err = qlcnic_issue_cmd(adapter, &cmd);
  664. if (err) {
  665. netdev_err(netdev, "Failed to %s interrupts %d\n",
  666. op_type == QLCNIC_INTRPT_ADD ? "Add" :
  667. "Delete", err);
  668. qlcnic_free_mbx_args(&cmd);
  669. return err;
  670. }
  671. val = cmd.rsp.arg[1];
  672. if (LSB(val)) {
  673. netdev_info(netdev,
  674. "failed to configure interrupt for %d\n",
  675. ahw->intr_tbl[i].id);
  676. continue;
  677. }
  678. if (op_type) {
  679. ahw->intr_tbl[i].id = MSW(val);
  680. ahw->intr_tbl[i].enabled = 1;
  681. ahw->intr_tbl[i].src = cmd.rsp.arg[2];
  682. } else {
  683. ahw->intr_tbl[i].id = i;
  684. ahw->intr_tbl[i].enabled = 0;
  685. ahw->intr_tbl[i].src = 0;
  686. }
  687. qlcnic_free_mbx_args(&cmd);
  688. }
  689. return err;
  690. }
  691. int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
  692. u8 function)
  693. {
  694. int err, i;
  695. struct qlcnic_cmd_args cmd;
  696. u32 mac_low, mac_high;
  697. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
  698. if (err)
  699. return err;
  700. cmd.req.arg[1] = function | BIT_8;
  701. err = qlcnic_issue_cmd(adapter, &cmd);
  702. if (err == QLCNIC_RCODE_SUCCESS) {
  703. mac_low = cmd.rsp.arg[1];
  704. mac_high = cmd.rsp.arg[2];
  705. for (i = 0; i < 2; i++)
  706. mac[i] = (u8) (mac_high >> ((1 - i) * 8));
  707. for (i = 2; i < 6; i++)
  708. mac[i] = (u8) (mac_low >> ((5 - i) * 8));
  709. } else {
  710. dev_err(&adapter->pdev->dev,
  711. "Failed to get mac address%d\n", err);
  712. err = -EIO;
  713. }
  714. qlcnic_free_mbx_args(&cmd);
  715. return err;
  716. }
  717. /* Get info of a NIC partition */
  718. int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
  719. struct qlcnic_info *npar_info, u8 func_id)
  720. {
  721. int err;
  722. dma_addr_t nic_dma_t;
  723. const struct qlcnic_info_le *nic_info;
  724. void *nic_info_addr;
  725. struct qlcnic_cmd_args cmd;
  726. size_t nic_size = sizeof(struct qlcnic_info_le);
  727. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  728. &nic_dma_t, GFP_KERNEL);
  729. if (!nic_info_addr)
  730. return -ENOMEM;
  731. nic_info = nic_info_addr;
  732. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
  733. if (err)
  734. goto out_free_dma;
  735. cmd.req.arg[1] = MSD(nic_dma_t);
  736. cmd.req.arg[2] = LSD(nic_dma_t);
  737. cmd.req.arg[3] = (func_id << 16 | nic_size);
  738. err = qlcnic_issue_cmd(adapter, &cmd);
  739. if (err != QLCNIC_RCODE_SUCCESS) {
  740. dev_err(&adapter->pdev->dev,
  741. "Failed to get nic info%d\n", err);
  742. err = -EIO;
  743. } else {
  744. npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
  745. npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
  746. npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  747. npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  748. npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
  749. npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
  750. npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  751. npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  752. npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
  753. npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
  754. }
  755. qlcnic_free_mbx_args(&cmd);
  756. out_free_dma:
  757. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  758. nic_dma_t);
  759. return err;
  760. }
  761. /* Configure a NIC partition */
  762. int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
  763. struct qlcnic_info *nic)
  764. {
  765. int err = -EIO;
  766. dma_addr_t nic_dma_t;
  767. void *nic_info_addr;
  768. struct qlcnic_cmd_args cmd;
  769. struct qlcnic_info_le *nic_info;
  770. size_t nic_size = sizeof(struct qlcnic_info_le);
  771. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  772. return err;
  773. nic_info_addr = dma_alloc_coherent(&adapter->pdev->dev, nic_size,
  774. &nic_dma_t, GFP_KERNEL);
  775. if (!nic_info_addr)
  776. return -ENOMEM;
  777. nic_info = nic_info_addr;
  778. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  779. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  780. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  781. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  782. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  783. nic_info->max_mac_filters = nic->max_mac_filters;
  784. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  785. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  786. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  787. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  788. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
  789. if (err)
  790. goto out_free_dma;
  791. cmd.req.arg[1] = MSD(nic_dma_t);
  792. cmd.req.arg[2] = LSD(nic_dma_t);
  793. cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
  794. err = qlcnic_issue_cmd(adapter, &cmd);
  795. if (err != QLCNIC_RCODE_SUCCESS) {
  796. dev_err(&adapter->pdev->dev,
  797. "Failed to set nic info%d\n", err);
  798. err = -EIO;
  799. }
  800. qlcnic_free_mbx_args(&cmd);
  801. out_free_dma:
  802. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  803. nic_dma_t);
  804. return err;
  805. }
  806. /* Get PCI Info of a partition */
  807. int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
  808. struct qlcnic_pci_info *pci_info)
  809. {
  810. struct qlcnic_hardware_context *ahw = adapter->ahw;
  811. size_t npar_size = sizeof(struct qlcnic_pci_info_le);
  812. size_t pci_size = npar_size * ahw->max_vnic_func;
  813. u16 nic = 0, fcoe = 0, iscsi = 0;
  814. struct qlcnic_pci_info_le *npar;
  815. struct qlcnic_cmd_args cmd;
  816. dma_addr_t pci_info_dma_t;
  817. void *pci_info_addr;
  818. int err = 0, i;
  819. pci_info_addr = dma_alloc_coherent(&adapter->pdev->dev, pci_size,
  820. &pci_info_dma_t, GFP_KERNEL);
  821. if (!pci_info_addr)
  822. return -ENOMEM;
  823. npar = pci_info_addr;
  824. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
  825. if (err)
  826. goto out_free_dma;
  827. cmd.req.arg[1] = MSD(pci_info_dma_t);
  828. cmd.req.arg[2] = LSD(pci_info_dma_t);
  829. cmd.req.arg[3] = pci_size;
  830. err = qlcnic_issue_cmd(adapter, &cmd);
  831. ahw->total_nic_func = 0;
  832. if (err == QLCNIC_RCODE_SUCCESS) {
  833. for (i = 0; i < ahw->max_vnic_func; i++, npar++, pci_info++) {
  834. pci_info->id = le16_to_cpu(npar->id);
  835. pci_info->active = le16_to_cpu(npar->active);
  836. if (!pci_info->active)
  837. continue;
  838. pci_info->type = le16_to_cpu(npar->type);
  839. err = qlcnic_get_pci_func_type(adapter, pci_info->type,
  840. &nic, &fcoe, &iscsi);
  841. pci_info->default_port =
  842. le16_to_cpu(npar->default_port);
  843. pci_info->tx_min_bw =
  844. le16_to_cpu(npar->tx_min_bw);
  845. pci_info->tx_max_bw =
  846. le16_to_cpu(npar->tx_max_bw);
  847. memcpy(pci_info->mac, npar->mac, ETH_ALEN);
  848. }
  849. } else {
  850. dev_err(&adapter->pdev->dev,
  851. "Failed to get PCI Info%d\n", err);
  852. err = -EIO;
  853. }
  854. ahw->total_nic_func = nic;
  855. ahw->total_pci_func = nic + fcoe + iscsi;
  856. if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
  857. dev_err(&adapter->pdev->dev,
  858. "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
  859. __func__, ahw->total_nic_func, ahw->total_pci_func);
  860. err = -EIO;
  861. }
  862. qlcnic_free_mbx_args(&cmd);
  863. out_free_dma:
  864. dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
  865. pci_info_dma_t);
  866. return err;
  867. }
  868. /* Configure eSwitch for port mirroring */
  869. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  870. u8 enable_mirroring, u8 pci_func)
  871. {
  872. struct device *dev = &adapter->pdev->dev;
  873. struct qlcnic_cmd_args cmd;
  874. int err = -EIO;
  875. u32 arg1;
  876. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
  877. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE)) {
  878. dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
  879. __func__);
  880. return err;
  881. }
  882. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  883. arg1 |= pci_func << 8;
  884. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  885. QLCNIC_CMD_SET_PORTMIRRORING);
  886. if (err)
  887. return err;
  888. cmd.req.arg[1] = arg1;
  889. err = qlcnic_issue_cmd(adapter, &cmd);
  890. if (err != QLCNIC_RCODE_SUCCESS)
  891. dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
  892. pci_func, id);
  893. else
  894. dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
  895. pci_func, id);
  896. qlcnic_free_mbx_args(&cmd);
  897. return err;
  898. }
  899. int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
  900. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  901. size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
  902. struct qlcnic_esw_stats_le *stats;
  903. dma_addr_t stats_dma_t;
  904. void *stats_addr;
  905. u32 arg1;
  906. struct qlcnic_cmd_args cmd;
  907. int err;
  908. if (esw_stats == NULL)
  909. return -ENOMEM;
  910. if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
  911. (func != adapter->ahw->pci_func)) {
  912. dev_err(&adapter->pdev->dev,
  913. "Not privilege to query stats for func=%d", func);
  914. return -EIO;
  915. }
  916. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  917. &stats_dma_t, GFP_KERNEL);
  918. if (!stats_addr)
  919. return -ENOMEM;
  920. arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
  921. arg1 |= rx_tx << 15 | stats_size << 16;
  922. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  923. QLCNIC_CMD_GET_ESWITCH_STATS);
  924. if (err)
  925. goto out_free_dma;
  926. cmd.req.arg[1] = arg1;
  927. cmd.req.arg[2] = MSD(stats_dma_t);
  928. cmd.req.arg[3] = LSD(stats_dma_t);
  929. err = qlcnic_issue_cmd(adapter, &cmd);
  930. if (!err) {
  931. stats = stats_addr;
  932. esw_stats->context_id = le16_to_cpu(stats->context_id);
  933. esw_stats->version = le16_to_cpu(stats->version);
  934. esw_stats->size = le16_to_cpu(stats->size);
  935. esw_stats->multicast_frames =
  936. le64_to_cpu(stats->multicast_frames);
  937. esw_stats->broadcast_frames =
  938. le64_to_cpu(stats->broadcast_frames);
  939. esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
  940. esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
  941. esw_stats->local_frames = le64_to_cpu(stats->local_frames);
  942. esw_stats->errors = le64_to_cpu(stats->errors);
  943. esw_stats->numbytes = le64_to_cpu(stats->numbytes);
  944. }
  945. qlcnic_free_mbx_args(&cmd);
  946. out_free_dma:
  947. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  948. stats_dma_t);
  949. return err;
  950. }
  951. /* This routine will retrieve the MAC statistics from firmware */
  952. int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
  953. struct qlcnic_mac_statistics *mac_stats)
  954. {
  955. struct qlcnic_mac_statistics_le *stats;
  956. struct qlcnic_cmd_args cmd;
  957. size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
  958. dma_addr_t stats_dma_t;
  959. void *stats_addr;
  960. int err;
  961. if (mac_stats == NULL)
  962. return -ENOMEM;
  963. stats_addr = dma_alloc_coherent(&adapter->pdev->dev, stats_size,
  964. &stats_dma_t, GFP_KERNEL);
  965. if (!stats_addr)
  966. return -ENOMEM;
  967. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
  968. if (err)
  969. goto out_free_dma;
  970. cmd.req.arg[1] = stats_size << 16;
  971. cmd.req.arg[2] = MSD(stats_dma_t);
  972. cmd.req.arg[3] = LSD(stats_dma_t);
  973. err = qlcnic_issue_cmd(adapter, &cmd);
  974. if (!err) {
  975. stats = stats_addr;
  976. mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
  977. mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
  978. mac_stats->mac_tx_mcast_pkts =
  979. le64_to_cpu(stats->mac_tx_mcast_pkts);
  980. mac_stats->mac_tx_bcast_pkts =
  981. le64_to_cpu(stats->mac_tx_bcast_pkts);
  982. mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
  983. mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
  984. mac_stats->mac_rx_mcast_pkts =
  985. le64_to_cpu(stats->mac_rx_mcast_pkts);
  986. mac_stats->mac_rx_length_error =
  987. le64_to_cpu(stats->mac_rx_length_error);
  988. mac_stats->mac_rx_length_small =
  989. le64_to_cpu(stats->mac_rx_length_small);
  990. mac_stats->mac_rx_length_large =
  991. le64_to_cpu(stats->mac_rx_length_large);
  992. mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
  993. mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
  994. mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
  995. } else {
  996. dev_err(&adapter->pdev->dev,
  997. "%s: Get mac stats failed, err=%d.\n", __func__, err);
  998. }
  999. qlcnic_free_mbx_args(&cmd);
  1000. out_free_dma:
  1001. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  1002. stats_dma_t);
  1003. return err;
  1004. }
  1005. int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
  1006. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  1007. struct __qlcnic_esw_statistics port_stats;
  1008. u8 i;
  1009. int ret = -EIO;
  1010. if (esw_stats == NULL)
  1011. return -ENOMEM;
  1012. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1013. return -EIO;
  1014. if (adapter->npars == NULL)
  1015. return -EIO;
  1016. memset(esw_stats, 0, sizeof(u64));
  1017. esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1018. esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1019. esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
  1020. esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
  1021. esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
  1022. esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
  1023. esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
  1024. esw_stats->context_id = eswitch;
  1025. for (i = 0; i < adapter->ahw->total_nic_func; i++) {
  1026. if (adapter->npars[i].phy_port != eswitch)
  1027. continue;
  1028. memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
  1029. if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
  1030. rx_tx, &port_stats))
  1031. continue;
  1032. esw_stats->size = port_stats.size;
  1033. esw_stats->version = port_stats.version;
  1034. QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
  1035. port_stats.unicast_frames);
  1036. QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
  1037. port_stats.multicast_frames);
  1038. QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
  1039. port_stats.broadcast_frames);
  1040. QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
  1041. port_stats.dropped_frames);
  1042. QLCNIC_ADD_ESW_STATS(esw_stats->errors,
  1043. port_stats.errors);
  1044. QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
  1045. port_stats.local_frames);
  1046. QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
  1047. port_stats.numbytes);
  1048. ret = 0;
  1049. }
  1050. return ret;
  1051. }
  1052. int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
  1053. const u8 port, const u8 rx_tx)
  1054. {
  1055. struct qlcnic_hardware_context *ahw = adapter->ahw;
  1056. struct qlcnic_cmd_args cmd;
  1057. int err;
  1058. u32 arg1;
  1059. if (ahw->op_mode != QLCNIC_MGMT_FUNC)
  1060. return -EIO;
  1061. if (func_esw == QLCNIC_STATS_PORT) {
  1062. if (port >= ahw->max_vnic_func)
  1063. goto err_ret;
  1064. } else if (func_esw == QLCNIC_STATS_ESWITCH) {
  1065. if (port >= QLCNIC_NIU_MAX_XG_PORTS)
  1066. goto err_ret;
  1067. } else {
  1068. goto err_ret;
  1069. }
  1070. if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
  1071. goto err_ret;
  1072. arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
  1073. arg1 |= BIT_14 | rx_tx << 15;
  1074. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1075. QLCNIC_CMD_GET_ESWITCH_STATS);
  1076. if (err)
  1077. return err;
  1078. cmd.req.arg[1] = arg1;
  1079. err = qlcnic_issue_cmd(adapter, &cmd);
  1080. qlcnic_free_mbx_args(&cmd);
  1081. return err;
  1082. err_ret:
  1083. dev_err(&adapter->pdev->dev,
  1084. "Invalid args func_esw %d port %d rx_ctx %d\n",
  1085. func_esw, port, rx_tx);
  1086. return -EIO;
  1087. }
  1088. static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1089. u32 *arg1, u32 *arg2)
  1090. {
  1091. struct device *dev = &adapter->pdev->dev;
  1092. struct qlcnic_cmd_args cmd;
  1093. u8 pci_func = *arg1 >> 8;
  1094. int err;
  1095. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1096. QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
  1097. if (err)
  1098. return err;
  1099. cmd.req.arg[1] = *arg1;
  1100. err = qlcnic_issue_cmd(adapter, &cmd);
  1101. *arg1 = cmd.rsp.arg[1];
  1102. *arg2 = cmd.rsp.arg[2];
  1103. qlcnic_free_mbx_args(&cmd);
  1104. if (err == QLCNIC_RCODE_SUCCESS)
  1105. dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
  1106. pci_func);
  1107. else
  1108. dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
  1109. pci_func);
  1110. return err;
  1111. }
  1112. /* Configure eSwitch port
  1113. op_mode = 0 for setting default port behavior
  1114. op_mode = 1 for setting vlan id
  1115. op_mode = 2 for deleting vlan id
  1116. op_type = 0 for vlan_id
  1117. op_type = 1 for port vlan_id
  1118. */
  1119. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
  1120. struct qlcnic_esw_func_cfg *esw_cfg)
  1121. {
  1122. struct device *dev = &adapter->pdev->dev;
  1123. struct qlcnic_cmd_args cmd;
  1124. int err = -EIO, index;
  1125. u32 arg1, arg2 = 0;
  1126. u8 pci_func;
  1127. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
  1128. dev_err(&adapter->pdev->dev, "%s: Not a management function\n",
  1129. __func__);
  1130. return err;
  1131. }
  1132. pci_func = esw_cfg->pci_func;
  1133. index = qlcnic_is_valid_nic_func(adapter, pci_func);
  1134. if (index < 0)
  1135. return err;
  1136. arg1 = (adapter->npars[index].phy_port & BIT_0);
  1137. arg1 |= (pci_func << 8);
  1138. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1139. return err;
  1140. arg1 &= ~(0x0ff << 8);
  1141. arg1 |= (pci_func << 8);
  1142. arg1 &= ~(BIT_2 | BIT_3);
  1143. switch (esw_cfg->op_mode) {
  1144. case QLCNIC_PORT_DEFAULTS:
  1145. arg1 |= (BIT_4 | BIT_6 | BIT_7);
  1146. arg2 |= (BIT_0 | BIT_1);
  1147. if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
  1148. arg2 |= (BIT_2 | BIT_3);
  1149. if (!(esw_cfg->discard_tagged))
  1150. arg1 &= ~BIT_4;
  1151. if (!(esw_cfg->promisc_mode))
  1152. arg1 &= ~BIT_6;
  1153. if (!(esw_cfg->mac_override))
  1154. arg1 &= ~BIT_7;
  1155. if (!(esw_cfg->mac_anti_spoof))
  1156. arg2 &= ~BIT_0;
  1157. if (!(esw_cfg->offload_flags & BIT_0))
  1158. arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
  1159. if (!(esw_cfg->offload_flags & BIT_1))
  1160. arg2 &= ~BIT_2;
  1161. if (!(esw_cfg->offload_flags & BIT_2))
  1162. arg2 &= ~BIT_3;
  1163. break;
  1164. case QLCNIC_ADD_VLAN:
  1165. arg1 &= ~(0x0ffff << 16);
  1166. arg1 |= (BIT_2 | BIT_5);
  1167. arg1 |= (esw_cfg->vlan_id << 16);
  1168. break;
  1169. case QLCNIC_DEL_VLAN:
  1170. arg1 |= (BIT_3 | BIT_5);
  1171. arg1 &= ~(0x0ffff << 16);
  1172. break;
  1173. default:
  1174. dev_err(&adapter->pdev->dev, "%s: Invalid opmode 0x%x\n",
  1175. __func__, esw_cfg->op_mode);
  1176. return err;
  1177. }
  1178. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1179. QLCNIC_CMD_CONFIGURE_ESWITCH);
  1180. if (err)
  1181. return err;
  1182. cmd.req.arg[1] = arg1;
  1183. cmd.req.arg[2] = arg2;
  1184. err = qlcnic_issue_cmd(adapter, &cmd);
  1185. qlcnic_free_mbx_args(&cmd);
  1186. if (err != QLCNIC_RCODE_SUCCESS)
  1187. dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
  1188. pci_func);
  1189. else
  1190. dev_info(dev, "Configured eSwitch for vNIC function %d\n",
  1191. pci_func);
  1192. return err;
  1193. }
  1194. int
  1195. qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1196. struct qlcnic_esw_func_cfg *esw_cfg)
  1197. {
  1198. u32 arg1, arg2;
  1199. int index;
  1200. u8 phy_port;
  1201. if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
  1202. index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
  1203. if (index < 0)
  1204. return -EIO;
  1205. phy_port = adapter->npars[index].phy_port;
  1206. } else {
  1207. phy_port = adapter->ahw->physical_port;
  1208. }
  1209. arg1 = phy_port;
  1210. arg1 |= (esw_cfg->pci_func << 8);
  1211. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1212. return -EIO;
  1213. esw_cfg->discard_tagged = !!(arg1 & BIT_4);
  1214. esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
  1215. esw_cfg->promisc_mode = !!(arg1 & BIT_6);
  1216. esw_cfg->mac_override = !!(arg1 & BIT_7);
  1217. esw_cfg->vlan_id = LSW(arg1 >> 16);
  1218. esw_cfg->mac_anti_spoof = (arg2 & 0x1);
  1219. esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
  1220. return 0;
  1221. }