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/drivers/net/ethernet/smsc/smsc9420.h

http://github.com/mirrors/linux
C Header | 263 lines | 192 code | 50 blank | 21 comment | 0 complexity | b41d16f0ad0332ab100a838d32e65db8 MD5 | raw file
  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2 /***************************************************************************
  3 *
  4 * Copyright (C) 2007,2008  SMSC
  5 *
  6 ***************************************************************************
  7 */
  8
  9#ifndef _SMSC9420_H
 10#define _SMSC9420_H
 11
 12#define TX_RING_SIZE			(32)
 13#define RX_RING_SIZE			(128)
 14
 15/* interrupt deassertion in multiples of 10us */
 16#define INT_DEAS_TIME			(50)
 17
 18#define NAPI_WEIGHT			(64)
 19#define SMSC_BAR			(3)
 20
 21#ifdef __BIG_ENDIAN
 22/* Register set is duplicated for BE at an offset of 0x200 */
 23#define LAN9420_CPSR_ENDIAN_OFFSET	(0x200)
 24#else
 25#define LAN9420_CPSR_ENDIAN_OFFSET	(0)
 26#endif
 27
 28#define PCI_VENDOR_ID_9420		(0x1055)
 29#define PCI_DEVICE_ID_9420		(0xE420)
 30
 31#define LAN_REGISTER_EXTENT		(0x400)
 32
 33#define SMSC9420_EEPROM_SIZE		((u32)11)
 34#define SMSC9420_EEPROM_MAGIC		(0x9420)
 35
 36#define PKT_BUF_SZ			(VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4)
 37
 38/***********************************************/
 39/* DMA Controller Control and Status Registers */
 40/***********************************************/
 41#define BUS_MODE			(0x00)
 42#define BUS_MODE_SWR_			(BIT(0))
 43#define BUS_MODE_DMA_BURST_LENGTH_1	(BIT(8))
 44#define BUS_MODE_DMA_BURST_LENGTH_2	(BIT(9))
 45#define BUS_MODE_DMA_BURST_LENGTH_4	(BIT(10))
 46#define BUS_MODE_DMA_BURST_LENGTH_8	(BIT(11))
 47#define BUS_MODE_DMA_BURST_LENGTH_16	(BIT(12))
 48#define BUS_MODE_DMA_BURST_LENGTH_32	(BIT(13))
 49#define BUS_MODE_DBO_			(BIT(20))
 50
 51#define TX_POLL_DEMAND			(0x04)
 52
 53#define RX_POLL_DEMAND			(0x08)
 54
 55#define RX_BASE_ADDR			(0x0C)
 56
 57#define TX_BASE_ADDR			(0x10)
 58
 59#define DMAC_STATUS			(0x14)
 60#define DMAC_STS_TS_			(7 << 20)
 61#define DMAC_STS_RS_ 			(7 << 17)
 62#define DMAC_STS_NIS_			(BIT(16))
 63#define DMAC_STS_AIS_			(BIT(15))
 64#define DMAC_STS_RWT_			(BIT(9))
 65#define DMAC_STS_RXPS_			(BIT(8))
 66#define DMAC_STS_RXBU_			(BIT(7))
 67#define DMAC_STS_RX_			(BIT(6))
 68#define DMAC_STS_TXUNF_			(BIT(5))
 69#define DMAC_STS_TXBU_			(BIT(2))
 70#define DMAC_STS_TXPS_			(BIT(1))
 71#define DMAC_STS_TX_			(BIT(0))
 72
 73#define DMAC_CONTROL			(0x18)
 74#define DMAC_CONTROL_TTM_		(BIT(22))
 75#define DMAC_CONTROL_SF_		(BIT(21))
 76#define DMAC_CONTROL_ST_		(BIT(13))
 77#define DMAC_CONTROL_OSF_		(BIT(2))
 78#define DMAC_CONTROL_SR_		(BIT(1))
 79
 80#define DMAC_INTR_ENA			(0x1C)
 81#define DMAC_INTR_ENA_NIS_		(BIT(16))
 82#define DMAC_INTR_ENA_AIS_		(BIT(15))
 83#define DMAC_INTR_ENA_RWT_		(BIT(9))
 84#define DMAC_INTR_ENA_RXPS_		(BIT(8))
 85#define DMAC_INTR_ENA_RXBU_		(BIT(7))
 86#define DMAC_INTR_ENA_RX_		(BIT(6))
 87#define DMAC_INTR_ENA_TXBU_		(BIT(2))
 88#define DMAC_INTR_ENA_TXPS_		(BIT(1))
 89#define DMAC_INTR_ENA_TX_		(BIT(0))
 90
 91#define MISS_FRAME_CNTR			(0x20)
 92
 93#define TX_BUFF_ADDR			(0x50)
 94
 95#define RX_BUFF_ADDR			(0x54)
 96
 97/* Transmit Descriptor Bit Defs */
 98#define TDES0_OWN_			(0x80000000)
 99#define TDES0_ERROR_SUMMARY_		(0x00008000)
100#define TDES0_LOSS_OF_CARRIER_		(0x00000800)
101#define TDES0_NO_CARRIER_		(0x00000400)
102#define TDES0_LATE_COLLISION_		(0x00000200)
103#define TDES0_EXCESSIVE_COLLISIONS_	(0x00000100)
104#define TDES0_HEARTBEAT_FAIL_		(0x00000080)
105#define TDES0_COLLISION_COUNT_MASK_	(0x00000078)
106#define TDES0_COLLISION_COUNT_SHFT_	(3)
107#define TDES0_EXCESSIVE_DEFERRAL_	(0x00000004)
108#define TDES0_DEFERRED_			(0x00000001)
109
110#define TDES1_IC_			0x80000000
111#define TDES1_LS_			0x40000000
112#define TDES1_FS_			0x20000000
113#define TDES1_TXCSEN_			0x08000000
114#define TDES1_TER_			(BIT(25))
115#define TDES1_TCH_			0x01000000
116
117/* Receive Descriptor 0 Bit Defs */
118#define RDES0_OWN_			(0x80000000)
119#define RDES0_FRAME_LENGTH_MASK_	(0x07FF0000)
120#define RDES0_FRAME_LENGTH_SHFT_	(16)
121#define RDES0_ERROR_SUMMARY_		(0x00008000)
122#define RDES0_DESCRIPTOR_ERROR_		(0x00004000)
123#define RDES0_LENGTH_ERROR_		(0x00001000)
124#define RDES0_RUNT_FRAME_		(0x00000800)
125#define RDES0_MULTICAST_FRAME_		(0x00000400)
126#define RDES0_FIRST_DESCRIPTOR_		(0x00000200)
127#define RDES0_LAST_DESCRIPTOR_		(0x00000100)
128#define RDES0_FRAME_TOO_LONG_		(0x00000080)
129#define RDES0_COLLISION_SEEN_		(0x00000040)
130#define RDES0_FRAME_TYPE_		(0x00000020)
131#define RDES0_WATCHDOG_TIMEOUT_		(0x00000010)
132#define RDES0_MII_ERROR_		(0x00000008)
133#define RDES0_DRIBBLING_BIT_		(0x00000004)
134#define RDES0_CRC_ERROR_		(0x00000002)
135
136/* Receive Descriptor 1 Bit Defs */
137#define RDES1_RER_			(0x02000000)
138
139/***********************************************/
140/*       MAC Control and Status Registers      */
141/***********************************************/
142#define MAC_CR				(0x80)
143#define MAC_CR_RXALL_			(0x80000000)
144#define MAC_CR_DIS_RXOWN_		(0x00800000)
145#define MAC_CR_LOOPBK_			(0x00200000)
146#define MAC_CR_FDPX_			(0x00100000)
147#define MAC_CR_MCPAS_			(0x00080000)
148#define MAC_CR_PRMS_			(0x00040000)
149#define MAC_CR_INVFILT_			(0x00020000)
150#define MAC_CR_PASSBAD_			(0x00010000)
151#define MAC_CR_HFILT_			(0x00008000)
152#define MAC_CR_HPFILT_			(0x00002000)
153#define MAC_CR_LCOLL_			(0x00001000)
154#define MAC_CR_DIS_BCAST_		(0x00000800)
155#define MAC_CR_DIS_RTRY_		(0x00000400)
156#define MAC_CR_PADSTR_			(0x00000100)
157#define MAC_CR_BOLMT_MSK		(0x000000C0)
158#define MAC_CR_MFCHK_			(0x00000020)
159#define MAC_CR_TXEN_			(0x00000008)
160#define MAC_CR_RXEN_			(0x00000004)
161
162#define ADDRH				(0x84)
163
164#define ADDRL				(0x88)
165
166#define HASHH				(0x8C)
167
168#define HASHL				(0x90)
169
170#define MII_ACCESS			(0x94)
171#define MII_ACCESS_MII_BUSY_		(0x00000001)
172#define MII_ACCESS_MII_WRITE_		(0x00000002)
173#define MII_ACCESS_MII_READ_		(0x00000000)
174#define MII_ACCESS_INDX_MSK_		(0x000007C0)
175#define MII_ACCESS_PHYADDR_MSK_		(0x0000F8C0)
176#define MII_ACCESS_INDX_SHFT_CNT	(6)
177#define MII_ACCESS_PHYADDR_SHFT_CNT	(11)
178
179#define MII_DATA			(0x98)
180
181#define FLOW				(0x9C)
182
183#define VLAN1				(0xA0)
184
185#define VLAN2				(0xA4)
186
187#define WUFF				(0xA8)
188
189#define WUCSR				(0xAC)
190
191#define COE_CR				(0xB0)
192#define TX_COE_EN			(0x00010000)
193#define RX_COE_MODE			(0x00000002)
194#define RX_COE_EN			(0x00000001)
195
196/***********************************************/
197/*     System Control and Status Registers     */
198/***********************************************/
199#define ID_REV				(0xC0)
200
201#define INT_CTL				(0xC4)
202#define INT_CTL_SW_INT_EN_		(0x00008000)
203#define INT_CTL_SBERR_INT_EN_		(1 << 12)
204#define INT_CTL_MBERR_INT_EN_		(1 << 13)
205#define INT_CTL_GPT_INT_EN_		(0x00000008)
206#define INT_CTL_PHY_INT_EN_		(0x00000004)
207#define INT_CTL_WAKE_INT_EN_		(0x00000002)
208
209#define INT_STAT			(0xC8)
210#define INT_STAT_SW_INT_		(1 << 15)
211#define INT_STAT_MBERR_INT_		(1 << 13)
212#define INT_STAT_SBERR_INT_		(1 << 12)
213#define INT_STAT_GPT_INT_		(1 << 3)
214#define INT_STAT_PHY_INT_		(0x00000004)
215#define INT_STAT_WAKE_INT_		(0x00000002)
216#define INT_STAT_DMAC_INT_		(0x00000001)
217
218#define INT_CFG				(0xCC)
219#define INT_CFG_IRQ_INT_		(0x00080000)
220#define INT_CFG_IRQ_EN_			(0x00040000)
221#define INT_CFG_INT_DEAS_CLR_		(0x00000200)
222#define INT_CFG_INT_DEAS_MASK		(0x000000FF)
223
224#define GPIO_CFG			(0xD0)
225#define GPIO_CFG_LED_3_			(0x40000000)
226#define GPIO_CFG_LED_2_			(0x20000000)
227#define GPIO_CFG_LED_1_			(0x10000000)
228#define GPIO_CFG_EEPR_EN_		(0x00700000)
229
230#define GPT_CFG				(0xD4)
231#define GPT_CFG_TIMER_EN_		(0x20000000)
232
233#define GPT_CNT				(0xD8)
234
235#define BUS_CFG				(0xDC)
236#define BUS_CFG_RXTXWEIGHT_1_1		(0 << 25)
237#define BUS_CFG_RXTXWEIGHT_2_1		(1 << 25)
238#define BUS_CFG_RXTXWEIGHT_3_1		(2 << 25)
239#define BUS_CFG_RXTXWEIGHT_4_1		(3 << 25)
240
241#define PMT_CTRL			(0xE0)
242
243#define FREE_RUN			(0xF4)
244
245#define E2P_CMD				(0xF8)
246#define E2P_CMD_EPC_BUSY_		(0x80000000)
247#define E2P_CMD_EPC_CMD_		(0x70000000)
248#define E2P_CMD_EPC_CMD_READ_		(0x00000000)
249#define E2P_CMD_EPC_CMD_EWDS_		(0x10000000)
250#define E2P_CMD_EPC_CMD_EWEN_		(0x20000000)
251#define E2P_CMD_EPC_CMD_WRITE_		(0x30000000)
252#define E2P_CMD_EPC_CMD_WRAL_		(0x40000000)
253#define E2P_CMD_EPC_CMD_ERASE_		(0x50000000)
254#define E2P_CMD_EPC_CMD_ERAL_		(0x60000000)
255#define E2P_CMD_EPC_CMD_RELOAD_		(0x70000000)
256#define E2P_CMD_EPC_TIMEOUT_		(0x00000200)
257#define E2P_CMD_MAC_ADDR_LOADED_	(0x00000100)
258#define E2P_CMD_EPC_ADDR_		(0x000000FF)
259
260#define E2P_DATA			(0xFC)
261#define E2P_DATA_EEPROM_DATA_		(0x000000FF)
262
263#endif /* _SMSC9420_H */