/drivers/net/ethernet/toshiba/tc35815.c

http://github.com/mirrors/linux · C · 2153 lines · 1692 code · 228 blank · 233 comment · 228 complexity · ff01004d0cf5182b5f322008ba48d689 MD5 · raw file

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  1. /*
  2. * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
  3. *
  4. * Based on skelton.c by Donald Becker.
  5. *
  6. * This driver is a replacement of older and less maintained version.
  7. * This is a header of the older version:
  8. * -----<snip>-----
  9. * Copyright 2001 MontaVista Software Inc.
  10. * Author: MontaVista Software, Inc.
  11. * ahennessy@mvista.com
  12. * Copyright (C) 2000-2001 Toshiba Corporation
  13. * static const char *version =
  14. * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
  15. * -----<snip>-----
  16. *
  17. * This file is subject to the terms and conditions of the GNU General Public
  18. * License. See the file "COPYING" in the main directory of this archive
  19. * for more details.
  20. *
  21. * (C) Copyright TOSHIBA CORPORATION 2004-2005
  22. * All Rights Reserved.
  23. */
  24. #define DRV_VERSION "1.39"
  25. static const char version[] = "tc35815.c:v" DRV_VERSION "\n";
  26. #define MODNAME "tc35815"
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/types.h>
  30. #include <linux/fcntl.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/ioport.h>
  33. #include <linux/in.h>
  34. #include <linux/if_vlan.h>
  35. #include <linux/slab.h>
  36. #include <linux/string.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/errno.h>
  39. #include <linux/netdevice.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/skbuff.h>
  42. #include <linux/delay.h>
  43. #include <linux/pci.h>
  44. #include <linux/phy.h>
  45. #include <linux/workqueue.h>
  46. #include <linux/platform_device.h>
  47. #include <linux/prefetch.h>
  48. #include <asm/io.h>
  49. #include <asm/byteorder.h>
  50. enum tc35815_chiptype {
  51. TC35815CF = 0,
  52. TC35815_NWU,
  53. TC35815_TX4939,
  54. };
  55. /* indexed by tc35815_chiptype, above */
  56. static const struct {
  57. const char *name;
  58. } chip_info[] = {
  59. { "TOSHIBA TC35815CF 10/100BaseTX" },
  60. { "TOSHIBA TC35815 with Wake on LAN" },
  61. { "TOSHIBA TC35815/TX4939" },
  62. };
  63. static const struct pci_device_id tc35815_pci_tbl[] = {
  64. {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
  65. {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
  66. {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
  67. {0,}
  68. };
  69. MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
  70. /* see MODULE_PARM_DESC */
  71. static struct tc35815_options {
  72. int speed;
  73. int duplex;
  74. } options;
  75. /*
  76. * Registers
  77. */
  78. struct tc35815_regs {
  79. __u32 DMA_Ctl; /* 0x00 */
  80. __u32 TxFrmPtr;
  81. __u32 TxThrsh;
  82. __u32 TxPollCtr;
  83. __u32 BLFrmPtr;
  84. __u32 RxFragSize;
  85. __u32 Int_En;
  86. __u32 FDA_Bas;
  87. __u32 FDA_Lim; /* 0x20 */
  88. __u32 Int_Src;
  89. __u32 unused0[2];
  90. __u32 PauseCnt;
  91. __u32 RemPauCnt;
  92. __u32 TxCtlFrmStat;
  93. __u32 unused1;
  94. __u32 MAC_Ctl; /* 0x40 */
  95. __u32 CAM_Ctl;
  96. __u32 Tx_Ctl;
  97. __u32 Tx_Stat;
  98. __u32 Rx_Ctl;
  99. __u32 Rx_Stat;
  100. __u32 MD_Data;
  101. __u32 MD_CA;
  102. __u32 CAM_Adr; /* 0x60 */
  103. __u32 CAM_Data;
  104. __u32 CAM_Ena;
  105. __u32 PROM_Ctl;
  106. __u32 PROM_Data;
  107. __u32 Algn_Cnt;
  108. __u32 CRC_Cnt;
  109. __u32 Miss_Cnt;
  110. };
  111. /*
  112. * Bit assignments
  113. */
  114. /* DMA_Ctl bit assign ------------------------------------------------------- */
  115. #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
  116. #define DMA_RxAlign_1 0x00400000
  117. #define DMA_RxAlign_2 0x00800000
  118. #define DMA_RxAlign_3 0x00c00000
  119. #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
  120. #define DMA_IntMask 0x00040000 /* 1:Interrupt mask */
  121. #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
  122. #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
  123. #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
  124. #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
  125. #define DMA_TestMode 0x00002000 /* 1:Test Mode */
  126. #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
  127. #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
  128. /* RxFragSize bit assign ---------------------------------------------------- */
  129. #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
  130. #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
  131. /* MAC_Ctl bit assign ------------------------------------------------------- */
  132. #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
  133. #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
  134. #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
  135. #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
  136. #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
  137. #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
  138. #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
  139. #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
  140. #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
  141. #define MAC_Reset 0x00000004 /* 1:Software Reset */
  142. #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
  143. #define MAC_HaltReq 0x00000001 /* 1:Halt request */
  144. /* PROM_Ctl bit assign ------------------------------------------------------ */
  145. #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
  146. #define PROM_Read 0x00004000 /*10:Read operation */
  147. #define PROM_Write 0x00002000 /*01:Write operation */
  148. #define PROM_Erase 0x00006000 /*11:Erase operation */
  149. /*00:Enable or Disable Writting, */
  150. /* as specified in PROM_Addr. */
  151. #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
  152. /*00xxxx: disable */
  153. /* CAM_Ctl bit assign ------------------------------------------------------- */
  154. #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
  155. #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
  156. /* accept other */
  157. #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
  158. #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
  159. #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
  160. /* CAM_Ena bit assign ------------------------------------------------------- */
  161. #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
  162. #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
  163. #define CAM_Ena_Bit(index) (1 << (index))
  164. #define CAM_ENTRY_DESTINATION 0
  165. #define CAM_ENTRY_SOURCE 1
  166. #define CAM_ENTRY_MACCTL 20
  167. /* Tx_Ctl bit assign -------------------------------------------------------- */
  168. #define Tx_En 0x00000001 /* 1:Transmit enable */
  169. #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
  170. #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
  171. #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
  172. #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
  173. #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
  174. #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
  175. #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
  176. #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
  177. #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
  178. #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
  179. #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
  180. /* Tx_Stat bit assign ------------------------------------------------------- */
  181. #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
  182. #define Tx_ExColl 0x00000010 /* Excessive Collision */
  183. #define Tx_TXDefer 0x00000020 /* Transmit Defered */
  184. #define Tx_Paused 0x00000040 /* Transmit Paused */
  185. #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
  186. #define Tx_Under 0x00000100 /* Underrun */
  187. #define Tx_Defer 0x00000200 /* Deferral */
  188. #define Tx_NCarr 0x00000400 /* No Carrier */
  189. #define Tx_10Stat 0x00000800 /* 10Mbps Status */
  190. #define Tx_LateColl 0x00001000 /* Late Collision */
  191. #define Tx_TxPar 0x00002000 /* Tx Parity Error */
  192. #define Tx_Comp 0x00004000 /* Completion */
  193. #define Tx_Halted 0x00008000 /* Tx Halted */
  194. #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
  195. /* Rx_Ctl bit assign -------------------------------------------------------- */
  196. #define Rx_EnGood 0x00004000 /* 1:Enable Good */
  197. #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
  198. #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
  199. #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
  200. #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
  201. #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
  202. #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
  203. #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
  204. #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
  205. #define Rx_LongEn 0x00000004 /* 1:Long Enable */
  206. #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
  207. #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
  208. /* Rx_Stat bit assign ------------------------------------------------------- */
  209. #define Rx_Halted 0x00008000 /* Rx Halted */
  210. #define Rx_Good 0x00004000 /* Rx Good */
  211. #define Rx_RxPar 0x00002000 /* Rx Parity Error */
  212. #define Rx_TypePkt 0x00001000 /* Rx Type Packet */
  213. #define Rx_LongErr 0x00000800 /* Rx Long Error */
  214. #define Rx_Over 0x00000400 /* Rx Overflow */
  215. #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
  216. #define Rx_Align 0x00000100 /* Rx Alignment Error */
  217. #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
  218. #define Rx_IntRx 0x00000040 /* Rx Interrupt */
  219. #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
  220. #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
  221. #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
  222. /* Int_En bit assign -------------------------------------------------------- */
  223. #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
  224. #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
  225. #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
  226. #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
  227. #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
  228. #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
  229. #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
  230. #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
  231. #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
  232. #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
  233. #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
  234. #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
  235. /* Exhausted Enable */
  236. /* Int_Src bit assign ------------------------------------------------------- */
  237. #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
  238. #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
  239. #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
  240. #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
  241. #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
  242. #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
  243. #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
  244. #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
  245. #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
  246. #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
  247. #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
  248. #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
  249. #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
  250. #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
  251. #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
  252. /* MD_CA bit assign --------------------------------------------------------- */
  253. #define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */
  254. #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
  255. #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
  256. /*
  257. * Descriptors
  258. */
  259. /* Frame descriptor */
  260. struct FDesc {
  261. volatile __u32 FDNext;
  262. volatile __u32 FDSystem;
  263. volatile __u32 FDStat;
  264. volatile __u32 FDCtl;
  265. };
  266. /* Buffer descriptor */
  267. struct BDesc {
  268. volatile __u32 BuffData;
  269. volatile __u32 BDCtl;
  270. };
  271. #define FD_ALIGN 16
  272. /* Frame Descriptor bit assign ---------------------------------------------- */
  273. #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
  274. #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
  275. #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
  276. #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
  277. #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
  278. #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
  279. #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
  280. #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
  281. #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
  282. #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
  283. #define FD_BDCnt_SHIFT 16
  284. /* Buffer Descriptor bit assign --------------------------------------------- */
  285. #define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */
  286. #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
  287. #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
  288. #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
  289. #define BD_RxBDID_SHIFT 16
  290. #define BD_RxBDSeqN_SHIFT 24
  291. /* Some useful constants. */
  292. #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
  293. Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
  294. Tx_En) /* maybe 0x7b01 */
  295. /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
  296. #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
  297. | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
  298. #define INT_EN_CMD (Int_NRAbtEn | \
  299. Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
  300. Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
  301. Int_STargAbtEn | \
  302. Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
  303. #define DMA_CTL_CMD DMA_BURST_SIZE
  304. #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
  305. /* Tuning parameters */
  306. #define DMA_BURST_SIZE 32
  307. #define TX_THRESHOLD 1024
  308. /* used threshold with packet max byte for low pci transfer ability.*/
  309. #define TX_THRESHOLD_MAX 1536
  310. /* setting threshold max value when overrun error occurred this count. */
  311. #define TX_THRESHOLD_KEEP_LIMIT 10
  312. /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
  313. #define FD_PAGE_NUM 4
  314. #define RX_BUF_NUM 128 /* < 256 */
  315. #define RX_FD_NUM 256 /* >= 32 */
  316. #define TX_FD_NUM 128
  317. #if RX_CTL_CMD & Rx_LongEn
  318. #define RX_BUF_SIZE PAGE_SIZE
  319. #elif RX_CTL_CMD & Rx_StripCRC
  320. #define RX_BUF_SIZE \
  321. L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
  322. #else
  323. #define RX_BUF_SIZE \
  324. L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
  325. #endif
  326. #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
  327. #define NAPI_WEIGHT 16
  328. struct TxFD {
  329. struct FDesc fd;
  330. struct BDesc bd;
  331. struct BDesc unused;
  332. };
  333. struct RxFD {
  334. struct FDesc fd;
  335. struct BDesc bd[]; /* variable length */
  336. };
  337. struct FrFD {
  338. struct FDesc fd;
  339. struct BDesc bd[RX_BUF_NUM];
  340. };
  341. #define tc_readl(addr) ioread32(addr)
  342. #define tc_writel(d, addr) iowrite32(d, addr)
  343. #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
  344. /* Information that need to be kept for each controller. */
  345. struct tc35815_local {
  346. struct pci_dev *pci_dev;
  347. struct net_device *dev;
  348. struct napi_struct napi;
  349. /* statistics */
  350. struct {
  351. int max_tx_qlen;
  352. int tx_ints;
  353. int rx_ints;
  354. int tx_underrun;
  355. } lstats;
  356. /* Tx control lock. This protects the transmit buffer ring
  357. * state along with the "tx full" state of the driver. This
  358. * means all netif_queue flow control actions are protected
  359. * by this lock as well.
  360. */
  361. spinlock_t lock;
  362. spinlock_t rx_lock;
  363. struct mii_bus *mii_bus;
  364. int duplex;
  365. int speed;
  366. int link;
  367. struct work_struct restart_work;
  368. /*
  369. * Transmitting: Batch Mode.
  370. * 1 BD in 1 TxFD.
  371. * Receiving: Non-Packing Mode.
  372. * 1 circular FD for Free Buffer List.
  373. * RX_BUF_NUM BD in Free Buffer FD.
  374. * One Free Buffer BD has ETH_FRAME_LEN data buffer.
  375. */
  376. void *fd_buf; /* for TxFD, RxFD, FrFD */
  377. dma_addr_t fd_buf_dma;
  378. struct TxFD *tfd_base;
  379. unsigned int tfd_start;
  380. unsigned int tfd_end;
  381. struct RxFD *rfd_base;
  382. struct RxFD *rfd_limit;
  383. struct RxFD *rfd_cur;
  384. struct FrFD *fbl_ptr;
  385. unsigned int fbl_count;
  386. struct {
  387. struct sk_buff *skb;
  388. dma_addr_t skb_dma;
  389. } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
  390. u32 msg_enable;
  391. enum tc35815_chiptype chiptype;
  392. };
  393. static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
  394. {
  395. return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
  396. }
  397. #ifdef DEBUG
  398. static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
  399. {
  400. return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
  401. }
  402. #endif
  403. static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
  404. struct pci_dev *hwdev,
  405. dma_addr_t *dma_handle)
  406. {
  407. struct sk_buff *skb;
  408. skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
  409. if (!skb)
  410. return NULL;
  411. *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
  412. PCI_DMA_FROMDEVICE);
  413. if (pci_dma_mapping_error(hwdev, *dma_handle)) {
  414. dev_kfree_skb_any(skb);
  415. return NULL;
  416. }
  417. skb_reserve(skb, 2); /* make IP header 4byte aligned */
  418. return skb;
  419. }
  420. static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
  421. {
  422. pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
  423. PCI_DMA_FROMDEVICE);
  424. dev_kfree_skb_any(skb);
  425. }
  426. /* Index to functions, as function prototypes. */
  427. static int tc35815_open(struct net_device *dev);
  428. static netdev_tx_t tc35815_send_packet(struct sk_buff *skb,
  429. struct net_device *dev);
  430. static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
  431. static int tc35815_rx(struct net_device *dev, int limit);
  432. static int tc35815_poll(struct napi_struct *napi, int budget);
  433. static void tc35815_txdone(struct net_device *dev);
  434. static int tc35815_close(struct net_device *dev);
  435. static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
  436. static void tc35815_set_multicast_list(struct net_device *dev);
  437. static void tc35815_tx_timeout(struct net_device *dev, unsigned int txqueue);
  438. #ifdef CONFIG_NET_POLL_CONTROLLER
  439. static void tc35815_poll_controller(struct net_device *dev);
  440. #endif
  441. static const struct ethtool_ops tc35815_ethtool_ops;
  442. /* Example routines you must write ;->. */
  443. static void tc35815_chip_reset(struct net_device *dev);
  444. static void tc35815_chip_init(struct net_device *dev);
  445. #ifdef DEBUG
  446. static void panic_queues(struct net_device *dev);
  447. #endif
  448. static void tc35815_restart_work(struct work_struct *work);
  449. static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  450. {
  451. struct net_device *dev = bus->priv;
  452. struct tc35815_regs __iomem *tr =
  453. (struct tc35815_regs __iomem *)dev->base_addr;
  454. unsigned long timeout = jiffies + HZ;
  455. tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
  456. udelay(12); /* it takes 32 x 400ns at least */
  457. while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
  458. if (time_after(jiffies, timeout))
  459. return -EIO;
  460. cpu_relax();
  461. }
  462. return tc_readl(&tr->MD_Data) & 0xffff;
  463. }
  464. static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
  465. {
  466. struct net_device *dev = bus->priv;
  467. struct tc35815_regs __iomem *tr =
  468. (struct tc35815_regs __iomem *)dev->base_addr;
  469. unsigned long timeout = jiffies + HZ;
  470. tc_writel(val, &tr->MD_Data);
  471. tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
  472. &tr->MD_CA);
  473. udelay(12); /* it takes 32 x 400ns at least */
  474. while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
  475. if (time_after(jiffies, timeout))
  476. return -EIO;
  477. cpu_relax();
  478. }
  479. return 0;
  480. }
  481. static void tc_handle_link_change(struct net_device *dev)
  482. {
  483. struct tc35815_local *lp = netdev_priv(dev);
  484. struct phy_device *phydev = dev->phydev;
  485. unsigned long flags;
  486. int status_change = 0;
  487. spin_lock_irqsave(&lp->lock, flags);
  488. if (phydev->link &&
  489. (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
  490. struct tc35815_regs __iomem *tr =
  491. (struct tc35815_regs __iomem *)dev->base_addr;
  492. u32 reg;
  493. reg = tc_readl(&tr->MAC_Ctl);
  494. reg |= MAC_HaltReq;
  495. tc_writel(reg, &tr->MAC_Ctl);
  496. if (phydev->duplex == DUPLEX_FULL)
  497. reg |= MAC_FullDup;
  498. else
  499. reg &= ~MAC_FullDup;
  500. tc_writel(reg, &tr->MAC_Ctl);
  501. reg &= ~MAC_HaltReq;
  502. tc_writel(reg, &tr->MAC_Ctl);
  503. /*
  504. * TX4939 PCFG.SPEEDn bit will be changed on
  505. * NETDEV_CHANGE event.
  506. */
  507. /*
  508. * WORKAROUND: enable LostCrS only if half duplex
  509. * operation.
  510. * (TX4939 does not have EnLCarr)
  511. */
  512. if (phydev->duplex == DUPLEX_HALF &&
  513. lp->chiptype != TC35815_TX4939)
  514. tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
  515. &tr->Tx_Ctl);
  516. lp->speed = phydev->speed;
  517. lp->duplex = phydev->duplex;
  518. status_change = 1;
  519. }
  520. if (phydev->link != lp->link) {
  521. if (phydev->link) {
  522. /* delayed promiscuous enabling */
  523. if (dev->flags & IFF_PROMISC)
  524. tc35815_set_multicast_list(dev);
  525. } else {
  526. lp->speed = 0;
  527. lp->duplex = -1;
  528. }
  529. lp->link = phydev->link;
  530. status_change = 1;
  531. }
  532. spin_unlock_irqrestore(&lp->lock, flags);
  533. if (status_change && netif_msg_link(lp)) {
  534. phy_print_status(phydev);
  535. pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
  536. dev->name,
  537. phy_read(phydev, MII_BMCR),
  538. phy_read(phydev, MII_BMSR),
  539. phy_read(phydev, MII_LPA));
  540. }
  541. }
  542. static int tc_mii_probe(struct net_device *dev)
  543. {
  544. __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
  545. struct tc35815_local *lp = netdev_priv(dev);
  546. struct phy_device *phydev;
  547. phydev = phy_find_first(lp->mii_bus);
  548. if (!phydev) {
  549. printk(KERN_ERR "%s: no PHY found\n", dev->name);
  550. return -ENODEV;
  551. }
  552. /* attach the mac to the phy */
  553. phydev = phy_connect(dev, phydev_name(phydev),
  554. &tc_handle_link_change,
  555. lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
  556. if (IS_ERR(phydev)) {
  557. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  558. return PTR_ERR(phydev);
  559. }
  560. phy_attached_info(phydev);
  561. /* mask with MAC supported features */
  562. phy_set_max_speed(phydev, SPEED_100);
  563. if (options.speed == 10) {
  564. linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
  565. linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
  566. } else if (options.speed == 100) {
  567. linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask);
  568. linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask);
  569. }
  570. if (options.duplex == 1) {
  571. linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask);
  572. linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
  573. } else if (options.duplex == 2) {
  574. linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask);
  575. linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
  576. }
  577. linkmode_andnot(phydev->supported, phydev->supported, mask);
  578. linkmode_copy(phydev->advertising, phydev->supported);
  579. lp->link = 0;
  580. lp->speed = 0;
  581. lp->duplex = -1;
  582. return 0;
  583. }
  584. static int tc_mii_init(struct net_device *dev)
  585. {
  586. struct tc35815_local *lp = netdev_priv(dev);
  587. int err;
  588. lp->mii_bus = mdiobus_alloc();
  589. if (lp->mii_bus == NULL) {
  590. err = -ENOMEM;
  591. goto err_out;
  592. }
  593. lp->mii_bus->name = "tc35815_mii_bus";
  594. lp->mii_bus->read = tc_mdio_read;
  595. lp->mii_bus->write = tc_mdio_write;
  596. snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
  597. (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
  598. lp->mii_bus->priv = dev;
  599. lp->mii_bus->parent = &lp->pci_dev->dev;
  600. err = mdiobus_register(lp->mii_bus);
  601. if (err)
  602. goto err_out_free_mii_bus;
  603. err = tc_mii_probe(dev);
  604. if (err)
  605. goto err_out_unregister_bus;
  606. return 0;
  607. err_out_unregister_bus:
  608. mdiobus_unregister(lp->mii_bus);
  609. err_out_free_mii_bus:
  610. mdiobus_free(lp->mii_bus);
  611. err_out:
  612. return err;
  613. }
  614. #ifdef CONFIG_CPU_TX49XX
  615. /*
  616. * Find a platform_device providing a MAC address. The platform code
  617. * should provide a "tc35815-mac" device with a MAC address in its
  618. * platform_data.
  619. */
  620. static int tc35815_mac_match(struct device *dev, const void *data)
  621. {
  622. struct platform_device *plat_dev = to_platform_device(dev);
  623. const struct pci_dev *pci_dev = data;
  624. unsigned int id = pci_dev->irq;
  625. return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
  626. }
  627. static int tc35815_read_plat_dev_addr(struct net_device *dev)
  628. {
  629. struct tc35815_local *lp = netdev_priv(dev);
  630. struct device *pd = bus_find_device(&platform_bus_type, NULL,
  631. lp->pci_dev, tc35815_mac_match);
  632. if (pd) {
  633. if (pd->platform_data)
  634. memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
  635. put_device(pd);
  636. return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
  637. }
  638. return -ENODEV;
  639. }
  640. #else
  641. static int tc35815_read_plat_dev_addr(struct net_device *dev)
  642. {
  643. return -ENODEV;
  644. }
  645. #endif
  646. static int tc35815_init_dev_addr(struct net_device *dev)
  647. {
  648. struct tc35815_regs __iomem *tr =
  649. (struct tc35815_regs __iomem *)dev->base_addr;
  650. int i;
  651. while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
  652. ;
  653. for (i = 0; i < 6; i += 2) {
  654. unsigned short data;
  655. tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
  656. while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
  657. ;
  658. data = tc_readl(&tr->PROM_Data);
  659. dev->dev_addr[i] = data & 0xff;
  660. dev->dev_addr[i+1] = data >> 8;
  661. }
  662. if (!is_valid_ether_addr(dev->dev_addr))
  663. return tc35815_read_plat_dev_addr(dev);
  664. return 0;
  665. }
  666. static const struct net_device_ops tc35815_netdev_ops = {
  667. .ndo_open = tc35815_open,
  668. .ndo_stop = tc35815_close,
  669. .ndo_start_xmit = tc35815_send_packet,
  670. .ndo_get_stats = tc35815_get_stats,
  671. .ndo_set_rx_mode = tc35815_set_multicast_list,
  672. .ndo_tx_timeout = tc35815_tx_timeout,
  673. .ndo_do_ioctl = phy_do_ioctl_running,
  674. .ndo_validate_addr = eth_validate_addr,
  675. .ndo_set_mac_address = eth_mac_addr,
  676. #ifdef CONFIG_NET_POLL_CONTROLLER
  677. .ndo_poll_controller = tc35815_poll_controller,
  678. #endif
  679. };
  680. static int tc35815_init_one(struct pci_dev *pdev,
  681. const struct pci_device_id *ent)
  682. {
  683. void __iomem *ioaddr = NULL;
  684. struct net_device *dev;
  685. struct tc35815_local *lp;
  686. int rc;
  687. static int printed_version;
  688. if (!printed_version++) {
  689. printk(version);
  690. dev_printk(KERN_DEBUG, &pdev->dev,
  691. "speed:%d duplex:%d\n",
  692. options.speed, options.duplex);
  693. }
  694. if (!pdev->irq) {
  695. dev_warn(&pdev->dev, "no IRQ assigned.\n");
  696. return -ENODEV;
  697. }
  698. /* dev zeroed in alloc_etherdev */
  699. dev = alloc_etherdev(sizeof(*lp));
  700. if (dev == NULL)
  701. return -ENOMEM;
  702. SET_NETDEV_DEV(dev, &pdev->dev);
  703. lp = netdev_priv(dev);
  704. lp->dev = dev;
  705. /* enable device (incl. PCI PM wakeup), and bus-mastering */
  706. rc = pcim_enable_device(pdev);
  707. if (rc)
  708. goto err_out;
  709. rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
  710. if (rc)
  711. goto err_out;
  712. pci_set_master(pdev);
  713. ioaddr = pcim_iomap_table(pdev)[1];
  714. /* Initialize the device structure. */
  715. dev->netdev_ops = &tc35815_netdev_ops;
  716. dev->ethtool_ops = &tc35815_ethtool_ops;
  717. dev->watchdog_timeo = TC35815_TX_TIMEOUT;
  718. netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
  719. dev->irq = pdev->irq;
  720. dev->base_addr = (unsigned long)ioaddr;
  721. INIT_WORK(&lp->restart_work, tc35815_restart_work);
  722. spin_lock_init(&lp->lock);
  723. spin_lock_init(&lp->rx_lock);
  724. lp->pci_dev = pdev;
  725. lp->chiptype = ent->driver_data;
  726. lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
  727. pci_set_drvdata(pdev, dev);
  728. /* Soft reset the chip. */
  729. tc35815_chip_reset(dev);
  730. /* Retrieve the ethernet address. */
  731. if (tc35815_init_dev_addr(dev)) {
  732. dev_warn(&pdev->dev, "not valid ether addr\n");
  733. eth_hw_addr_random(dev);
  734. }
  735. rc = register_netdev(dev);
  736. if (rc)
  737. goto err_out;
  738. printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
  739. dev->name,
  740. chip_info[ent->driver_data].name,
  741. dev->base_addr,
  742. dev->dev_addr,
  743. dev->irq);
  744. rc = tc_mii_init(dev);
  745. if (rc)
  746. goto err_out_unregister;
  747. return 0;
  748. err_out_unregister:
  749. unregister_netdev(dev);
  750. err_out:
  751. free_netdev(dev);
  752. return rc;
  753. }
  754. static void tc35815_remove_one(struct pci_dev *pdev)
  755. {
  756. struct net_device *dev = pci_get_drvdata(pdev);
  757. struct tc35815_local *lp = netdev_priv(dev);
  758. phy_disconnect(dev->phydev);
  759. mdiobus_unregister(lp->mii_bus);
  760. mdiobus_free(lp->mii_bus);
  761. unregister_netdev(dev);
  762. free_netdev(dev);
  763. }
  764. static int
  765. tc35815_init_queues(struct net_device *dev)
  766. {
  767. struct tc35815_local *lp = netdev_priv(dev);
  768. int i;
  769. unsigned long fd_addr;
  770. if (!lp->fd_buf) {
  771. BUG_ON(sizeof(struct FDesc) +
  772. sizeof(struct BDesc) * RX_BUF_NUM +
  773. sizeof(struct FDesc) * RX_FD_NUM +
  774. sizeof(struct TxFD) * TX_FD_NUM >
  775. PAGE_SIZE * FD_PAGE_NUM);
  776. lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
  777. PAGE_SIZE * FD_PAGE_NUM,
  778. &lp->fd_buf_dma);
  779. if (!lp->fd_buf)
  780. return -ENOMEM;
  781. for (i = 0; i < RX_BUF_NUM; i++) {
  782. lp->rx_skbs[i].skb =
  783. alloc_rxbuf_skb(dev, lp->pci_dev,
  784. &lp->rx_skbs[i].skb_dma);
  785. if (!lp->rx_skbs[i].skb) {
  786. while (--i >= 0) {
  787. free_rxbuf_skb(lp->pci_dev,
  788. lp->rx_skbs[i].skb,
  789. lp->rx_skbs[i].skb_dma);
  790. lp->rx_skbs[i].skb = NULL;
  791. }
  792. pci_free_consistent(lp->pci_dev,
  793. PAGE_SIZE * FD_PAGE_NUM,
  794. lp->fd_buf,
  795. lp->fd_buf_dma);
  796. lp->fd_buf = NULL;
  797. return -ENOMEM;
  798. }
  799. }
  800. printk(KERN_DEBUG "%s: FD buf %p DataBuf",
  801. dev->name, lp->fd_buf);
  802. printk("\n");
  803. } else {
  804. for (i = 0; i < FD_PAGE_NUM; i++)
  805. clear_page((void *)((unsigned long)lp->fd_buf +
  806. i * PAGE_SIZE));
  807. }
  808. fd_addr = (unsigned long)lp->fd_buf;
  809. /* Free Descriptors (for Receive) */
  810. lp->rfd_base = (struct RxFD *)fd_addr;
  811. fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
  812. for (i = 0; i < RX_FD_NUM; i++)
  813. lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
  814. lp->rfd_cur = lp->rfd_base;
  815. lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
  816. /* Transmit Descriptors */
  817. lp->tfd_base = (struct TxFD *)fd_addr;
  818. fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
  819. for (i = 0; i < TX_FD_NUM; i++) {
  820. lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
  821. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
  822. lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
  823. }
  824. lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
  825. lp->tfd_start = 0;
  826. lp->tfd_end = 0;
  827. /* Buffer List (for Receive) */
  828. lp->fbl_ptr = (struct FrFD *)fd_addr;
  829. lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
  830. lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
  831. /*
  832. * move all allocated skbs to head of rx_skbs[] array.
  833. * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
  834. * tc35815_rx() had failed.
  835. */
  836. lp->fbl_count = 0;
  837. for (i = 0; i < RX_BUF_NUM; i++) {
  838. if (lp->rx_skbs[i].skb) {
  839. if (i != lp->fbl_count) {
  840. lp->rx_skbs[lp->fbl_count].skb =
  841. lp->rx_skbs[i].skb;
  842. lp->rx_skbs[lp->fbl_count].skb_dma =
  843. lp->rx_skbs[i].skb_dma;
  844. }
  845. lp->fbl_count++;
  846. }
  847. }
  848. for (i = 0; i < RX_BUF_NUM; i++) {
  849. if (i >= lp->fbl_count) {
  850. lp->fbl_ptr->bd[i].BuffData = 0;
  851. lp->fbl_ptr->bd[i].BDCtl = 0;
  852. continue;
  853. }
  854. lp->fbl_ptr->bd[i].BuffData =
  855. cpu_to_le32(lp->rx_skbs[i].skb_dma);
  856. /* BDID is index of FrFD.bd[] */
  857. lp->fbl_ptr->bd[i].BDCtl =
  858. cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
  859. RX_BUF_SIZE);
  860. }
  861. printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
  862. dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
  863. return 0;
  864. }
  865. static void
  866. tc35815_clear_queues(struct net_device *dev)
  867. {
  868. struct tc35815_local *lp = netdev_priv(dev);
  869. int i;
  870. for (i = 0; i < TX_FD_NUM; i++) {
  871. u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
  872. struct sk_buff *skb =
  873. fdsystem != 0xffffffff ?
  874. lp->tx_skbs[fdsystem].skb : NULL;
  875. #ifdef DEBUG
  876. if (lp->tx_skbs[i].skb != skb) {
  877. printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
  878. panic_queues(dev);
  879. }
  880. #else
  881. BUG_ON(lp->tx_skbs[i].skb != skb);
  882. #endif
  883. if (skb) {
  884. pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
  885. lp->tx_skbs[i].skb = NULL;
  886. lp->tx_skbs[i].skb_dma = 0;
  887. dev_kfree_skb_any(skb);
  888. }
  889. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
  890. }
  891. tc35815_init_queues(dev);
  892. }
  893. static void
  894. tc35815_free_queues(struct net_device *dev)
  895. {
  896. struct tc35815_local *lp = netdev_priv(dev);
  897. int i;
  898. if (lp->tfd_base) {
  899. for (i = 0; i < TX_FD_NUM; i++) {
  900. u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
  901. struct sk_buff *skb =
  902. fdsystem != 0xffffffff ?
  903. lp->tx_skbs[fdsystem].skb : NULL;
  904. #ifdef DEBUG
  905. if (lp->tx_skbs[i].skb != skb) {
  906. printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
  907. panic_queues(dev);
  908. }
  909. #else
  910. BUG_ON(lp->tx_skbs[i].skb != skb);
  911. #endif
  912. if (skb) {
  913. pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
  914. dev_kfree_skb(skb);
  915. lp->tx_skbs[i].skb = NULL;
  916. lp->tx_skbs[i].skb_dma = 0;
  917. }
  918. lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
  919. }
  920. }
  921. lp->rfd_base = NULL;
  922. lp->rfd_limit = NULL;
  923. lp->rfd_cur = NULL;
  924. lp->fbl_ptr = NULL;
  925. for (i = 0; i < RX_BUF_NUM; i++) {
  926. if (lp->rx_skbs[i].skb) {
  927. free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
  928. lp->rx_skbs[i].skb_dma);
  929. lp->rx_skbs[i].skb = NULL;
  930. }
  931. }
  932. if (lp->fd_buf) {
  933. pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
  934. lp->fd_buf, lp->fd_buf_dma);
  935. lp->fd_buf = NULL;
  936. }
  937. }
  938. static void
  939. dump_txfd(struct TxFD *fd)
  940. {
  941. printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
  942. le32_to_cpu(fd->fd.FDNext),
  943. le32_to_cpu(fd->fd.FDSystem),
  944. le32_to_cpu(fd->fd.FDStat),
  945. le32_to_cpu(fd->fd.FDCtl));
  946. printk("BD: ");
  947. printk(" %08x %08x",
  948. le32_to_cpu(fd->bd.BuffData),
  949. le32_to_cpu(fd->bd.BDCtl));
  950. printk("\n");
  951. }
  952. static int
  953. dump_rxfd(struct RxFD *fd)
  954. {
  955. int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
  956. if (bd_count > 8)
  957. bd_count = 8;
  958. printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
  959. le32_to_cpu(fd->fd.FDNext),
  960. le32_to_cpu(fd->fd.FDSystem),
  961. le32_to_cpu(fd->fd.FDStat),
  962. le32_to_cpu(fd->fd.FDCtl));
  963. if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
  964. return 0;
  965. printk("BD: ");
  966. for (i = 0; i < bd_count; i++)
  967. printk(" %08x %08x",
  968. le32_to_cpu(fd->bd[i].BuffData),
  969. le32_to_cpu(fd->bd[i].BDCtl));
  970. printk("\n");
  971. return bd_count;
  972. }
  973. #ifdef DEBUG
  974. static void
  975. dump_frfd(struct FrFD *fd)
  976. {
  977. int i;
  978. printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
  979. le32_to_cpu(fd->fd.FDNext),
  980. le32_to_cpu(fd->fd.FDSystem),
  981. le32_to_cpu(fd->fd.FDStat),
  982. le32_to_cpu(fd->fd.FDCtl));
  983. printk("BD: ");
  984. for (i = 0; i < RX_BUF_NUM; i++)
  985. printk(" %08x %08x",
  986. le32_to_cpu(fd->bd[i].BuffData),
  987. le32_to_cpu(fd->bd[i].BDCtl));
  988. printk("\n");
  989. }
  990. static void
  991. panic_queues(struct net_device *dev)
  992. {
  993. struct tc35815_local *lp = netdev_priv(dev);
  994. int i;
  995. printk("TxFD base %p, start %u, end %u\n",
  996. lp->tfd_base, lp->tfd_start, lp->tfd_end);
  997. printk("RxFD base %p limit %p cur %p\n",
  998. lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
  999. printk("FrFD %p\n", lp->fbl_ptr);
  1000. for (i = 0; i < TX_FD_NUM; i++)
  1001. dump_txfd(&lp->tfd_base[i]);
  1002. for (i = 0; i < RX_FD_NUM; i++) {
  1003. int bd_count = dump_rxfd(&lp->rfd_base[i]);
  1004. i += (bd_count + 1) / 2; /* skip BDs */
  1005. }
  1006. dump_frfd(lp->fbl_ptr);
  1007. panic("%s: Illegal queue state.", dev->name);
  1008. }
  1009. #endif
  1010. static void print_eth(const u8 *add)
  1011. {
  1012. printk(KERN_DEBUG "print_eth(%p)\n", add);
  1013. printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
  1014. add + 6, add, add[12], add[13]);
  1015. }
  1016. static int tc35815_tx_full(struct net_device *dev)
  1017. {
  1018. struct tc35815_local *lp = netdev_priv(dev);
  1019. return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
  1020. }
  1021. static void tc35815_restart(struct net_device *dev)
  1022. {
  1023. struct tc35815_local *lp = netdev_priv(dev);
  1024. int ret;
  1025. if (dev->phydev) {
  1026. ret = phy_init_hw(dev->phydev);
  1027. if (ret)
  1028. printk(KERN_ERR "%s: PHY init failed.\n", dev->name);
  1029. }
  1030. spin_lock_bh(&lp->rx_lock);
  1031. spin_lock_irq(&lp->lock);
  1032. tc35815_chip_reset(dev);
  1033. tc35815_clear_queues(dev);
  1034. tc35815_chip_init(dev);
  1035. /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
  1036. tc35815_set_multicast_list(dev);
  1037. spin_unlock_irq(&lp->lock);
  1038. spin_unlock_bh(&lp->rx_lock);
  1039. netif_wake_queue(dev);
  1040. }
  1041. static void tc35815_restart_work(struct work_struct *work)
  1042. {
  1043. struct tc35815_local *lp =
  1044. container_of(work, struct tc35815_local, restart_work);
  1045. struct net_device *dev = lp->dev;
  1046. tc35815_restart(dev);
  1047. }
  1048. static void tc35815_schedule_restart(struct net_device *dev)
  1049. {
  1050. struct tc35815_local *lp = netdev_priv(dev);
  1051. struct tc35815_regs __iomem *tr =
  1052. (struct tc35815_regs __iomem *)dev->base_addr;
  1053. unsigned long flags;
  1054. /* disable interrupts */
  1055. spin_lock_irqsave(&lp->lock, flags);
  1056. tc_writel(0, &tr->Int_En);
  1057. tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
  1058. schedule_work(&lp->restart_work);
  1059. spin_unlock_irqrestore(&lp->lock, flags);
  1060. }
  1061. static void tc35815_tx_timeout(struct net_device *dev, unsigned int txqueue)
  1062. {
  1063. struct tc35815_regs __iomem *tr =
  1064. (struct tc35815_regs __iomem *)dev->base_addr;
  1065. printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
  1066. dev->name, tc_readl(&tr->Tx_Stat));
  1067. /* Try to restart the adaptor. */
  1068. tc35815_schedule_restart(dev);
  1069. dev->stats.tx_errors++;
  1070. }
  1071. /*
  1072. * Open/initialize the controller. This is called (in the current kernel)
  1073. * sometime after booting when the 'ifconfig' program is run.
  1074. *
  1075. * This routine should set everything up anew at each open, even
  1076. * registers that "should" only need to be set once at boot, so that
  1077. * there is non-reboot way to recover if something goes wrong.
  1078. */
  1079. static int
  1080. tc35815_open(struct net_device *dev)
  1081. {
  1082. struct tc35815_local *lp = netdev_priv(dev);
  1083. /*
  1084. * This is used if the interrupt line can turned off (shared).
  1085. * See 3c503.c for an example of selecting the IRQ at config-time.
  1086. */
  1087. if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
  1088. dev->name, dev))
  1089. return -EAGAIN;
  1090. tc35815_chip_reset(dev);
  1091. if (tc35815_init_queues(dev) != 0) {
  1092. free_irq(dev->irq, dev);
  1093. return -EAGAIN;
  1094. }
  1095. napi_enable(&lp->napi);
  1096. /* Reset the hardware here. Don't forget to set the station address. */
  1097. spin_lock_irq(&lp->lock);
  1098. tc35815_chip_init(dev);
  1099. spin_unlock_irq(&lp->lock);
  1100. netif_carrier_off(dev);
  1101. /* schedule a link state check */
  1102. phy_start(dev->phydev);
  1103. /* We are now ready to accept transmit requeusts from
  1104. * the queueing layer of the networking.
  1105. */
  1106. netif_start_queue(dev);
  1107. return 0;
  1108. }
  1109. /* This will only be invoked if your driver is _not_ in XOFF state.
  1110. * What this means is that you need not check it, and that this
  1111. * invariant will hold if you make sure that the netif_*_queue()
  1112. * calls are done at the proper times.
  1113. */
  1114. static netdev_tx_t
  1115. tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
  1116. {
  1117. struct tc35815_local *lp = netdev_priv(dev);
  1118. struct TxFD *txfd;
  1119. unsigned long flags;
  1120. /* If some error occurs while trying to transmit this
  1121. * packet, you should return '1' from this function.
  1122. * In such a case you _may not_ do anything to the
  1123. * SKB, it is still owned by the network queueing
  1124. * layer when an error is returned. This means you
  1125. * may not modify any SKB fields, you may not free
  1126. * the SKB, etc.
  1127. */
  1128. /* This is the most common case for modern hardware.
  1129. * The spinlock protects this code from the TX complete
  1130. * hardware interrupt handler. Queue flow control is
  1131. * thus managed under this lock as well.
  1132. */
  1133. spin_lock_irqsave(&lp->lock, flags);
  1134. /* failsafe... (handle txdone now if half of FDs are used) */
  1135. if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
  1136. TX_FD_NUM / 2)
  1137. tc35815_txdone(dev);
  1138. if (netif_msg_pktdata(lp))
  1139. print_eth(skb->data);
  1140. #ifdef DEBUG
  1141. if (lp->tx_skbs[lp->tfd_start].skb) {
  1142. printk("%s: tx_skbs conflict.\n", dev->name);
  1143. panic_queues(dev);
  1144. }
  1145. #else
  1146. BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
  1147. #endif
  1148. lp->tx_skbs[lp->tfd_start].skb = skb;
  1149. lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
  1150. /*add to ring */
  1151. txfd = &lp->tfd_base[lp->tfd_start];
  1152. txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
  1153. txfd->bd.BDCtl = cpu_to_le32(skb->len);
  1154. txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
  1155. txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
  1156. if (lp->tfd_start == lp->tfd_end) {
  1157. struct tc35815_regs __iomem *tr =
  1158. (struct tc35815_regs __iomem *)dev->base_addr;
  1159. /* Start DMA Transmitter. */
  1160. txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
  1161. txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
  1162. if (netif_msg_tx_queued(lp)) {
  1163. printk("%s: starting TxFD.\n", dev->name);
  1164. dump_txfd(txfd);
  1165. }
  1166. tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
  1167. } else {
  1168. txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
  1169. if (netif_msg_tx_queued(lp)) {
  1170. printk("%s: queueing TxFD.\n", dev->name);
  1171. dump_txfd(txfd);
  1172. }
  1173. }
  1174. lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
  1175. /* If we just used up the very last entry in the
  1176. * TX ring on this device, tell the queueing
  1177. * layer to send no more.
  1178. */
  1179. if (tc35815_tx_full(dev)) {
  1180. if (netif_msg_tx_queued(lp))
  1181. printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
  1182. netif_stop_queue(dev);
  1183. }
  1184. /* When the TX completion hw interrupt arrives, this
  1185. * is when the transmit statistics are updated.
  1186. */
  1187. spin_unlock_irqrestore(&lp->lock, flags);
  1188. return NETDEV_TX_OK;
  1189. }
  1190. #define FATAL_ERROR_INT \
  1191. (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
  1192. static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
  1193. {
  1194. static int count;
  1195. printk(KERN_WARNING "%s: Fatal Error Interrupt (%#x):",
  1196. dev->name, status);
  1197. if (status & Int_IntPCI)
  1198. printk(" IntPCI");
  1199. if (status & Int_DmParErr)
  1200. printk(" DmParErr");
  1201. if (status & Int_IntNRAbt)
  1202. printk(" IntNRAbt");
  1203. printk("\n");
  1204. if (count++ > 100)
  1205. panic("%s: Too many fatal errors.", dev->name);
  1206. printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
  1207. /* Try to restart the adaptor. */
  1208. tc35815_schedule_restart(dev);
  1209. }
  1210. static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
  1211. {
  1212. struct tc35815_local *lp = netdev_priv(dev);
  1213. int ret = -1;
  1214. /* Fatal errors... */
  1215. if (status & FATAL_ERROR_INT) {
  1216. tc35815_fatal_error_interrupt(dev, status);
  1217. return 0;
  1218. }
  1219. /* recoverable errors */
  1220. if (status & Int_IntFDAEx) {
  1221. if (netif_msg_rx_err(lp))
  1222. dev_warn(&dev->dev,
  1223. "Free Descriptor Area Exhausted (%#x).\n",
  1224. status);
  1225. dev->stats.rx_dropped++;
  1226. ret = 0;
  1227. }
  1228. if (status & Int_IntBLEx) {
  1229. if (netif_msg_rx_err(lp))
  1230. dev_warn(&dev->dev,
  1231. "Buffer List Exhausted (%#x).\n",
  1232. status);
  1233. dev->stats.rx_dropped++;
  1234. ret = 0;
  1235. }
  1236. if (status & Int_IntExBD) {
  1237. if (netif_msg_rx_err(lp))
  1238. dev_warn(&dev->dev,
  1239. "Excessive Buffer Descriptors (%#x).\n",
  1240. status);
  1241. dev->stats.rx_length_errors++;
  1242. ret = 0;
  1243. }
  1244. /* normal notification */
  1245. if (status & Int_IntMacRx) {
  1246. /* Got a packet(s). */
  1247. ret = tc35815_rx(dev, limit);
  1248. lp->lstats.rx_ints++;
  1249. }
  1250. if (status & Int_IntMacTx) {
  1251. /* Transmit complete. */
  1252. lp->lstats.tx_ints++;
  1253. spin_lock_irq(&lp->lock);
  1254. tc35815_txdone(dev);
  1255. spin_unlock_irq(&lp->lock);
  1256. if (ret < 0)
  1257. ret = 0;
  1258. }
  1259. return ret;
  1260. }
  1261. /*
  1262. * The typical workload of the driver:
  1263. * Handle the network interface interrupts.
  1264. */
  1265. static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
  1266. {
  1267. struct net_device *dev = dev_id;
  1268. struct tc35815_local *lp = netdev_priv(dev);
  1269. struct tc35815_regs __iomem *tr =
  1270. (struct tc35815_regs __iomem *)dev->base_addr;
  1271. u32 dmactl = tc_readl(&tr->DMA_Ctl);
  1272. if (!(dmactl & DMA_IntMask)) {
  1273. /* disable interrupts */
  1274. tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
  1275. if (napi_schedule_prep(&lp->napi))
  1276. __napi_schedule(&lp->napi);
  1277. else {
  1278. printk(KERN_ERR "%s: interrupt taken in poll\n",
  1279. dev->name);
  1280. BUG();
  1281. }
  1282. (void)tc_readl(&tr->Int_Src); /* flush */
  1283. return IRQ_HANDLED;
  1284. }
  1285. return IRQ_NONE;
  1286. }
  1287. #ifdef CONFIG_NET_POLL_CONTROLLER
  1288. static void tc35815_poll_controller(struct net_device *dev)
  1289. {
  1290. disable_irq(dev->irq);
  1291. tc35815_interrupt(dev->irq, dev);
  1292. enable_irq(dev->irq);
  1293. }
  1294. #endif
  1295. /* We have a good packet(s), get it/them out of the buffers. */
  1296. static int
  1297. tc35815_rx(struct net_device *dev, int limit)
  1298. {
  1299. struct tc35815_local *lp = netdev_priv(dev);
  1300. unsigned int fdctl;
  1301. int i;
  1302. int received = 0;
  1303. while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
  1304. int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
  1305. int pkt_len = fdctl & FD_FDLength_MASK;
  1306. int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
  1307. #ifdef DEBUG
  1308. struct RxFD *next_rfd;
  1309. #endif
  1310. #if (RX_CTL_CMD & Rx_StripCRC) == 0
  1311. pkt_len -= ETH_FCS_LEN;
  1312. #endif
  1313. if (netif_msg_rx_status(lp))
  1314. dump_rxfd(lp->rfd_cur);
  1315. if (status & Rx_Good) {
  1316. struct sk_buff *skb;
  1317. unsigned char *data;
  1318. int cur_bd;
  1319. if (--limit < 0)
  1320. break;
  1321. BUG_ON(bd_count > 1);
  1322. cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
  1323. & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
  1324. #ifdef DEBUG
  1325. if (cur_bd >= RX_BUF_NUM) {
  1326. printk("%s: invalid BDID.\n", dev->name);
  1327. panic_queues(dev);
  1328. }
  1329. BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
  1330. (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
  1331. if (!lp->rx_skbs[cur_bd].skb) {
  1332. printk("%s: NULL skb.\n", dev->name);
  1333. panic_queues(dev);
  1334. }
  1335. #else
  1336. BUG_ON(cur_bd >= RX_BUF_NUM);
  1337. #endif
  1338. skb = lp->rx_skbs[cur_bd].skb;
  1339. prefetch(skb->data);
  1340. lp->rx_skbs[cur_bd].skb = NULL;
  1341. pci_unmap_single(lp->pci_dev,
  1342. lp->rx_skbs[cur_bd].skb_dma,
  1343. RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  1344. if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN != 0)
  1345. memmove(skb->data, skb->data - NET_IP_ALIGN,
  1346. pkt_len);
  1347. data = skb_put(skb, pkt_len);
  1348. if (netif_msg_pktdata(lp))
  1349. print_eth(data);
  1350. skb->protocol = eth_type_trans(skb, dev);
  1351. netif_receive_skb(skb);
  1352. received++;
  1353. dev->stats.rx_packets++;
  1354. dev->stats.rx_bytes += pkt_len;
  1355. } else {
  1356. dev->stats.rx_errors++;
  1357. if (netif_msg_rx_err(lp))
  1358. dev_info(&dev->dev, "Rx error (status %x)\n",
  1359. status & Rx_Stat_Mask);
  1360. /* WORKAROUND: LongErr and CRCErr means Overflow. */
  1361. if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
  1362. status &= ~(Rx_LongErr|Rx_CRCErr);
  1363. status |= Rx_Over;
  1364. }
  1365. if (status & Rx_LongErr)
  1366. dev->stats.rx_length_errors++;
  1367. if (status & Rx_Over)
  1368. dev->stats.rx_fifo_errors++;
  1369. if (status & Rx_CRCErr)
  1370. dev->stats.rx_crc_errors++;
  1371. if (status & Rx_Align)
  1372. dev->stats.rx_frame_errors++;
  1373. }
  1374. if (bd_count > 0) {
  1375. /* put Free Buffer back to controller */
  1376. int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
  1377. unsigned char id =
  1378. (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
  1379. #ifdef DEBUG
  1380. if (id >= RX_BUF_NUM) {
  1381. printk("%s: invalid BDID.\n", dev->name);
  1382. panic_queues(dev);
  1383. }
  1384. #else
  1385. BUG_ON(id >= RX_BUF_NUM);
  1386. #endif
  1387. /* free old buffers */
  1388. lp->fbl_count--;
  1389. while (lp->fbl_count < RX_BUF_NUM)
  1390. {
  1391. unsigned char curid =
  1392. (id + 1 + lp->fbl_count) % RX_BUF_NUM;
  1393. struct BDesc *bd = &lp->fbl_ptr->bd[curid];
  1394. #ifdef DEBUG
  1395. bdctl = le32_to_cpu(bd->BDCtl);
  1396. if (bdctl & BD_CownsBD) {
  1397. printk("%s: Freeing invalid BD.\n",
  1398. dev->name);
  1399. panic_queues(dev);
  1400. }
  1401. #endif
  1402. /* pass BD to controller */
  1403. if (!lp->rx_skbs[curid].skb) {
  1404. lp->rx_skbs[curid].skb =
  1405. alloc_rxbuf_skb(dev,
  1406. lp->pci_dev,
  1407. &lp->rx_skbs[curid].skb_dma);
  1408. if (!lp->rx_skbs[curid].skb)
  1409. break; /* try on next reception */
  1410. bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
  1411. }
  1412. /* Note: BDLength was modified by chip. */
  1413. bd->BDCtl = cpu_to_le32(BD_CownsBD |
  1414. (curid << BD_RxBDID_SHIFT) |
  1415. RX_BUF_SIZE);
  1416. lp->fbl_count++;
  1417. }
  1418. }
  1419. /* put RxFD back to controller */
  1420. #ifdef DEBUG
  1421. next_rfd = fd_bus_to_virt(lp,
  1422. le32_to_cpu(lp->rfd_cur->fd.FDNext));
  1423. if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
  1424. printk("%s: RxFD FDNext invalid.\n", dev->name);
  1425. panic_queues(dev);
  1426. }
  1427. #endif
  1428. for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
  1429. /* pass FD to controller */
  1430. #ifdef DEBUG
  1431. lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
  1432. #else
  1433. lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
  1434. #endif
  1435. lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
  1436. lp->rfd_cur++;
  1437. }
  1438. if (lp->rfd_cur > lp->rfd_limit)
  1439. lp->rfd_cur = lp->rfd_base;
  1440. #ifdef DEBUG
  1441. if (lp->rfd_cur != next_rfd)
  1442. printk("rfd_cur = %p, next_rfd %p\n",
  1443. lp->rfd_cur, next_rfd);
  1444. #endif
  1445. }
  1446. return received;
  1447. }
  1448. static int tc35815_poll(struct napi_struct *napi, int budget)
  1449. {
  1450. struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
  1451. struct net_device *dev = lp->dev;
  1452. struct tc35815_regs __iomem *tr =
  1453. (struct tc35815_regs __iomem *)dev->base_addr;
  1454. int received = 0, handled;
  1455. u32 status;
  1456. if (budget <= 0)
  1457. return received;
  1458. spin_lock(&lp->rx_lock);
  1459. status = tc_readl(&tr->Int_Src);
  1460. do {
  1461. /* BLEx, FDAEx will be cleared later */
  1462. tc_writel(status & ~(Int_BLEx | Int_FDAEx),
  1463. &tr->Int_Src); /* write to clear */
  1464. handled = tc35815_do_interrupt(dev, status, budget - received);
  1465. if (status & (Int_BLEx | Int_FDAEx))
  1466. tc_writel(status & (Int_BLEx | Int_FDAEx),
  1467. &tr->Int_Src);
  1468. if (handled >= 0) {
  1469. received += handled;
  1470. if (received >= budget)
  1471. break;
  1472. }
  1473. status = tc_readl(&tr->Int_Src);
  1474. } while (status);
  1475. spin_unlock(&lp->rx_lock);
  1476. if (received < budget) {
  1477. napi_complete_done(napi, received);
  1478. /* enable interrupts */
  1479. tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
  1480. }
  1481. return received;
  1482. }
  1483. #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_