/drivers/net/ethernet/atheros/atl1e/atl1e_hw.c

http://github.com/mirrors/linux · C · 637 lines · 402 code · 92 blank · 143 comment · 68 complexity · 3d4c3a1f8f5595ccd6400ef5552b508d MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright(c) 2007 Atheros Corporation. All rights reserved.
  4. *
  5. * Derived from Intel e1000 driver
  6. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  7. */
  8. #include <linux/pci.h>
  9. #include <linux/delay.h>
  10. #include <linux/mii.h>
  11. #include <linux/crc32.h>
  12. #include "atl1e.h"
  13. /*
  14. * check_eeprom_exist
  15. * return 0 if eeprom exist
  16. */
  17. int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
  18. {
  19. u32 value;
  20. value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
  21. if (value & SPI_FLASH_CTRL_EN_VPD) {
  22. value &= ~SPI_FLASH_CTRL_EN_VPD;
  23. AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
  24. }
  25. value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
  26. return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
  27. }
  28. void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
  29. {
  30. u32 value;
  31. /*
  32. * 00-0B-6A-F6-00-DC
  33. * 0: 6AF600DC 1: 000B
  34. * low dword
  35. */
  36. value = (((u32)hw->mac_addr[2]) << 24) |
  37. (((u32)hw->mac_addr[3]) << 16) |
  38. (((u32)hw->mac_addr[4]) << 8) |
  39. (((u32)hw->mac_addr[5])) ;
  40. AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
  41. /* hight dword */
  42. value = (((u32)hw->mac_addr[0]) << 8) |
  43. (((u32)hw->mac_addr[1])) ;
  44. AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
  45. }
  46. /*
  47. * atl1e_get_permanent_address
  48. * return 0 if get valid mac address,
  49. */
  50. static int atl1e_get_permanent_address(struct atl1e_hw *hw)
  51. {
  52. u32 addr[2];
  53. u32 i;
  54. u32 twsi_ctrl_data;
  55. u8 eth_addr[ETH_ALEN];
  56. if (is_valid_ether_addr(hw->perm_mac_addr))
  57. return 0;
  58. /* init */
  59. addr[0] = addr[1] = 0;
  60. if (!atl1e_check_eeprom_exist(hw)) {
  61. /* eeprom exist */
  62. twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
  63. twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
  64. AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
  65. for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
  66. msleep(10);
  67. twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
  68. if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
  69. break;
  70. }
  71. if (i >= AT_TWSI_EEPROM_TIMEOUT)
  72. return AT_ERR_TIMEOUT;
  73. }
  74. /* maybe MAC-address is from BIOS */
  75. addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
  76. addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
  77. *(u32 *) &eth_addr[2] = swab32(addr[0]);
  78. *(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
  79. if (is_valid_ether_addr(eth_addr)) {
  80. memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
  81. return 0;
  82. }
  83. return AT_ERR_EEPROM;
  84. }
  85. bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value)
  86. {
  87. return true;
  88. }
  89. bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value)
  90. {
  91. int i;
  92. u32 control;
  93. if (offset & 3)
  94. return false; /* address do not align */
  95. AT_WRITE_REG(hw, REG_VPD_DATA, 0);
  96. control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
  97. AT_WRITE_REG(hw, REG_VPD_CAP, control);
  98. for (i = 0; i < 10; i++) {
  99. msleep(2);
  100. control = AT_READ_REG(hw, REG_VPD_CAP);
  101. if (control & VPD_CAP_VPD_FLAG)
  102. break;
  103. }
  104. if (control & VPD_CAP_VPD_FLAG) {
  105. *p_value = AT_READ_REG(hw, REG_VPD_DATA);
  106. return true;
  107. }
  108. return false; /* timeout */
  109. }
  110. void atl1e_force_ps(struct atl1e_hw *hw)
  111. {
  112. AT_WRITE_REGW(hw, REG_GPHY_CTRL,
  113. GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
  114. }
  115. /*
  116. * Reads the adapter's MAC address from the EEPROM
  117. *
  118. * hw - Struct containing variables accessed by shared code
  119. */
  120. int atl1e_read_mac_addr(struct atl1e_hw *hw)
  121. {
  122. int err = 0;
  123. err = atl1e_get_permanent_address(hw);
  124. if (err)
  125. return AT_ERR_EEPROM;
  126. memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
  127. return 0;
  128. }
  129. /*
  130. * atl1e_hash_mc_addr
  131. * purpose
  132. * set hash value for a multicast address
  133. */
  134. u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr)
  135. {
  136. u32 crc32;
  137. u32 value = 0;
  138. int i;
  139. crc32 = ether_crc_le(6, mc_addr);
  140. for (i = 0; i < 32; i++)
  141. value |= (((crc32 >> i) & 1) << (31 - i));
  142. return value;
  143. }
  144. /*
  145. * Sets the bit in the multicast table corresponding to the hash value.
  146. * hw - Struct containing variables accessed by shared code
  147. * hash_value - Multicast address hash value
  148. */
  149. void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value)
  150. {
  151. u32 hash_bit, hash_reg;
  152. u32 mta;
  153. /*
  154. * The HASH Table is a register array of 2 32-bit registers.
  155. * It is treated like an array of 64 bits. We want to set
  156. * bit BitArray[hash_value]. So we figure out what register
  157. * the bit is in, read it, OR in the new bit, then write
  158. * back the new value. The register is determined by the
  159. * upper 7 bits of the hash value and the bit within that
  160. * register are determined by the lower 5 bits of the value.
  161. */
  162. hash_reg = (hash_value >> 31) & 0x1;
  163. hash_bit = (hash_value >> 26) & 0x1F;
  164. mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
  165. mta |= (1 << hash_bit);
  166. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
  167. }
  168. /*
  169. * Reads the value from a PHY register
  170. * hw - Struct containing variables accessed by shared code
  171. * reg_addr - address of the PHY register to read
  172. */
  173. int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
  174. {
  175. u32 val;
  176. int i;
  177. val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
  178. MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
  179. MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
  180. AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
  181. wmb();
  182. for (i = 0; i < MDIO_WAIT_TIMES; i++) {
  183. udelay(2);
  184. val = AT_READ_REG(hw, REG_MDIO_CTRL);
  185. if (!(val & (MDIO_START | MDIO_BUSY)))
  186. break;
  187. wmb();
  188. }
  189. if (!(val & (MDIO_START | MDIO_BUSY))) {
  190. *phy_data = (u16)val;
  191. return 0;
  192. }
  193. return AT_ERR_PHY;
  194. }
  195. /*
  196. * Writes a value to a PHY register
  197. * hw - Struct containing variables accessed by shared code
  198. * reg_addr - address of the PHY register to write
  199. * data - data to write to the PHY
  200. */
  201. int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
  202. {
  203. int i;
  204. u32 val;
  205. val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
  206. (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
  207. MDIO_SUP_PREAMBLE |
  208. MDIO_START |
  209. MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
  210. AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
  211. wmb();
  212. for (i = 0; i < MDIO_WAIT_TIMES; i++) {
  213. udelay(2);
  214. val = AT_READ_REG(hw, REG_MDIO_CTRL);
  215. if (!(val & (MDIO_START | MDIO_BUSY)))
  216. break;
  217. wmb();
  218. }
  219. if (!(val & (MDIO_START | MDIO_BUSY)))
  220. return 0;
  221. return AT_ERR_PHY;
  222. }
  223. /*
  224. * atl1e_init_pcie - init PCIE module
  225. */
  226. static void atl1e_init_pcie(struct atl1e_hw *hw)
  227. {
  228. u32 value;
  229. /* comment 2lines below to save more power when sususpend
  230. value = LTSSM_TEST_MODE_DEF;
  231. AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
  232. */
  233. /* pcie flow control mode change */
  234. value = AT_READ_REG(hw, 0x1008);
  235. value |= 0x8000;
  236. AT_WRITE_REG(hw, 0x1008, value);
  237. }
  238. /*
  239. * Configures PHY autoneg and flow control advertisement settings
  240. *
  241. * hw - Struct containing variables accessed by shared code
  242. */
  243. static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
  244. {
  245. s32 ret_val;
  246. u16 mii_autoneg_adv_reg;
  247. u16 mii_1000t_ctrl_reg;
  248. if (0 != hw->mii_autoneg_adv_reg)
  249. return 0;
  250. /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
  251. mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
  252. mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
  253. /*
  254. * Need to parse autoneg_advertised and set up
  255. * the appropriate PHY registers. First we will parse for
  256. * autoneg_advertised software override. Since we can advertise
  257. * a plethora of combinations, we need to check each bit
  258. * individually.
  259. */
  260. /*
  261. * First we clear all the 10/100 mb speed bits in the Auto-Neg
  262. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  263. * the 1000Base-T control Register (Address 9).
  264. */
  265. mii_autoneg_adv_reg &= ~ADVERTISE_ALL;
  266. mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
  267. /*
  268. * Need to parse MediaType and setup the
  269. * appropriate PHY registers.
  270. */
  271. switch (hw->media_type) {
  272. case MEDIA_TYPE_AUTO_SENSOR:
  273. mii_autoneg_adv_reg |= ADVERTISE_ALL;
  274. hw->autoneg_advertised = ADVERTISE_ALL;
  275. if (hw->nic_type == athr_l1e) {
  276. mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
  277. hw->autoneg_advertised |= ADVERTISE_1000_FULL;
  278. }
  279. break;
  280. case MEDIA_TYPE_100M_FULL:
  281. mii_autoneg_adv_reg |= ADVERTISE_100FULL;
  282. hw->autoneg_advertised = ADVERTISE_100_FULL;
  283. break;
  284. case MEDIA_TYPE_100M_HALF:
  285. mii_autoneg_adv_reg |= ADVERTISE_100_HALF;
  286. hw->autoneg_advertised = ADVERTISE_100_HALF;
  287. break;
  288. case MEDIA_TYPE_10M_FULL:
  289. mii_autoneg_adv_reg |= ADVERTISE_10_FULL;
  290. hw->autoneg_advertised = ADVERTISE_10_FULL;
  291. break;
  292. default:
  293. mii_autoneg_adv_reg |= ADVERTISE_10_HALF;
  294. hw->autoneg_advertised = ADVERTISE_10_HALF;
  295. break;
  296. }
  297. /* flow control fixed to enable all */
  298. mii_autoneg_adv_reg |= (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
  299. hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
  300. hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
  301. ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
  302. if (ret_val)
  303. return ret_val;
  304. if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
  305. ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000,
  306. mii_1000t_ctrl_reg);
  307. if (ret_val)
  308. return ret_val;
  309. }
  310. return 0;
  311. }
  312. /*
  313. * Resets the PHY and make all config validate
  314. *
  315. * hw - Struct containing variables accessed by shared code
  316. *
  317. * Sets bit 15 and 12 of the MII control regiser (for F001 bug)
  318. */
  319. int atl1e_phy_commit(struct atl1e_hw *hw)
  320. {
  321. struct atl1e_adapter *adapter = hw->adapter;
  322. int ret_val;
  323. u16 phy_data;
  324. phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
  325. ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
  326. if (ret_val) {
  327. u32 val;
  328. int i;
  329. /**************************************
  330. * pcie serdes link may be down !
  331. **************************************/
  332. for (i = 0; i < 25; i++) {
  333. msleep(1);
  334. val = AT_READ_REG(hw, REG_MDIO_CTRL);
  335. if (!(val & (MDIO_START | MDIO_BUSY)))
  336. break;
  337. }
  338. if (0 != (val & (MDIO_START | MDIO_BUSY))) {
  339. netdev_err(adapter->netdev,
  340. "pcie linkdown at least for 25ms\n");
  341. return ret_val;
  342. }
  343. netdev_err(adapter->netdev, "pcie linkup after %d ms\n", i);
  344. }
  345. return 0;
  346. }
  347. int atl1e_phy_init(struct atl1e_hw *hw)
  348. {
  349. struct atl1e_adapter *adapter = hw->adapter;
  350. s32 ret_val;
  351. u16 phy_val;
  352. if (hw->phy_configured) {
  353. if (hw->re_autoneg) {
  354. hw->re_autoneg = false;
  355. return atl1e_restart_autoneg(hw);
  356. }
  357. return 0;
  358. }
  359. /* RESET GPHY Core */
  360. AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
  361. msleep(2);
  362. AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
  363. GPHY_CTRL_EXT_RESET);
  364. msleep(2);
  365. /* patches */
  366. /* p1. eable hibernation mode */
  367. ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
  368. if (ret_val)
  369. return ret_val;
  370. ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
  371. if (ret_val)
  372. return ret_val;
  373. /* p2. set Class A/B for all modes */
  374. ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
  375. if (ret_val)
  376. return ret_val;
  377. phy_val = 0x02ef;
  378. /* remove Class AB */
  379. /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
  380. ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
  381. if (ret_val)
  382. return ret_val;
  383. /* p3. 10B ??? */
  384. ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
  385. if (ret_val)
  386. return ret_val;
  387. ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
  388. if (ret_val)
  389. return ret_val;
  390. /* p4. 1000T power */
  391. ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
  392. if (ret_val)
  393. return ret_val;
  394. ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
  395. if (ret_val)
  396. return ret_val;
  397. ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
  398. if (ret_val)
  399. return ret_val;
  400. ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
  401. if (ret_val)
  402. return ret_val;
  403. msleep(1);
  404. /*Enable PHY LinkChange Interrupt */
  405. ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
  406. if (ret_val) {
  407. netdev_err(adapter->netdev,
  408. "Error enable PHY linkChange Interrupt\n");
  409. return ret_val;
  410. }
  411. /* setup AutoNeg parameters */
  412. ret_val = atl1e_phy_setup_autoneg_adv(hw);
  413. if (ret_val) {
  414. netdev_err(adapter->netdev,
  415. "Error Setting up Auto-Negotiation\n");
  416. return ret_val;
  417. }
  418. /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
  419. netdev_dbg(adapter->netdev, "Restarting Auto-Negotiation\n");
  420. ret_val = atl1e_phy_commit(hw);
  421. if (ret_val) {
  422. netdev_err(adapter->netdev, "Error resetting the phy\n");
  423. return ret_val;
  424. }
  425. hw->phy_configured = true;
  426. return 0;
  427. }
  428. /*
  429. * Reset the transmit and receive units; mask and clear all interrupts.
  430. * hw - Struct containing variables accessed by shared code
  431. * return : 0 or idle status (if error)
  432. */
  433. int atl1e_reset_hw(struct atl1e_hw *hw)
  434. {
  435. struct atl1e_adapter *adapter = hw->adapter;
  436. struct pci_dev *pdev = adapter->pdev;
  437. u32 idle_status_data = 0;
  438. u16 pci_cfg_cmd_word = 0;
  439. int timeout = 0;
  440. /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
  441. pci_read_config_word(pdev, PCI_REG_COMMAND, &pci_cfg_cmd_word);
  442. if ((pci_cfg_cmd_word & (CMD_IO_SPACE |
  443. CMD_MEMORY_SPACE | CMD_BUS_MASTER))
  444. != (CMD_IO_SPACE | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) {
  445. pci_cfg_cmd_word |= (CMD_IO_SPACE |
  446. CMD_MEMORY_SPACE | CMD_BUS_MASTER);
  447. pci_write_config_word(pdev, PCI_REG_COMMAND, pci_cfg_cmd_word);
  448. }
  449. /*
  450. * Issue Soft Reset to the MAC. This will reset the chip's
  451. * transmit, receive, DMA. It will not effect
  452. * the current PCI configuration. The global reset bit is self-
  453. * clearing, and should clear within a microsecond.
  454. */
  455. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  456. MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST);
  457. wmb();
  458. msleep(1);
  459. /* Wait at least 10ms for All module to be Idle */
  460. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  461. idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
  462. if (idle_status_data == 0)
  463. break;
  464. msleep(1);
  465. cpu_relax();
  466. }
  467. if (timeout >= AT_HW_MAX_IDLE_DELAY) {
  468. netdev_err(adapter->netdev,
  469. "MAC state machine can't be idle since disabled for 10ms second\n");
  470. return AT_ERR_TIMEOUT;
  471. }
  472. return 0;
  473. }
  474. /*
  475. * Performs basic configuration of the adapter.
  476. *
  477. * hw - Struct containing variables accessed by shared code
  478. * Assumes that the controller has previously been reset and is in a
  479. * post-reset uninitialized state. Initializes multicast table,
  480. * and Calls routines to setup link
  481. * Leaves the transmit and receive units disabled and uninitialized.
  482. */
  483. int atl1e_init_hw(struct atl1e_hw *hw)
  484. {
  485. s32 ret_val = 0;
  486. atl1e_init_pcie(hw);
  487. /* Zero out the Multicast HASH table */
  488. /* clear the old settings from the multicast hash table */
  489. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  490. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  491. ret_val = atl1e_phy_init(hw);
  492. return ret_val;
  493. }
  494. /*
  495. * Detects the current speed and duplex settings of the hardware.
  496. *
  497. * hw - Struct containing variables accessed by shared code
  498. * speed - Speed of the connection
  499. * duplex - Duplex setting of the connection
  500. */
  501. int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
  502. {
  503. int err;
  504. u16 phy_data;
  505. /* Read PHY Specific Status Register (17) */
  506. err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
  507. if (err)
  508. return err;
  509. if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
  510. return AT_ERR_PHY_RES;
  511. switch (phy_data & MII_AT001_PSSR_SPEED) {
  512. case MII_AT001_PSSR_1000MBS:
  513. *speed = SPEED_1000;
  514. break;
  515. case MII_AT001_PSSR_100MBS:
  516. *speed = SPEED_100;
  517. break;
  518. case MII_AT001_PSSR_10MBS:
  519. *speed = SPEED_10;
  520. break;
  521. default:
  522. return AT_ERR_PHY_SPEED;
  523. }
  524. if (phy_data & MII_AT001_PSSR_DPLX)
  525. *duplex = FULL_DUPLEX;
  526. else
  527. *duplex = HALF_DUPLEX;
  528. return 0;
  529. }
  530. int atl1e_restart_autoneg(struct atl1e_hw *hw)
  531. {
  532. int err = 0;
  533. err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
  534. if (err)
  535. return err;
  536. if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
  537. err = atl1e_write_phy_reg(hw, MII_CTRL1000,
  538. hw->mii_1000t_ctrl_reg);
  539. if (err)
  540. return err;
  541. }
  542. err = atl1e_write_phy_reg(hw, MII_BMCR,
  543. BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
  544. return err;
  545. }