/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

http://github.com/mirrors/linux · C Header · 1011 lines · 824 code · 112 blank · 75 comment · 0 complexity · a4d951079ea7795d91addb765dd09747 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  4. *
  5. * Derived from Intel e1000 driver
  6. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  7. */
  8. #ifndef _ATL1C_HW_H_
  9. #define _ATL1C_HW_H_
  10. #include <linux/types.h>
  11. #include <linux/mii.h>
  12. #define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK))
  13. #define FIELD_SETX(_x, _name, _v) \
  14. (((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\
  15. (((_v) & (_name##_MASK)) << (_name##_SHIFT)))
  16. #define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT))
  17. struct atl1c_adapter;
  18. struct atl1c_hw;
  19. /* function prototype */
  20. void atl1c_phy_disable(struct atl1c_hw *hw);
  21. void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr);
  22. int atl1c_phy_reset(struct atl1c_hw *hw);
  23. int atl1c_read_mac_addr(struct atl1c_hw *hw);
  24. int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
  25. u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
  26. void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
  27. int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
  28. int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
  29. bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
  30. int atl1c_phy_init(struct atl1c_hw *hw);
  31. int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
  32. int atl1c_restart_autoneg(struct atl1c_hw *hw);
  33. int atl1c_phy_to_ps_link(struct atl1c_hw *hw);
  34. int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc);
  35. bool atl1c_wait_mdio_idle(struct atl1c_hw *hw);
  36. void atl1c_stop_phy_polling(struct atl1c_hw *hw);
  37. void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
  38. int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
  39. u16 reg, u16 *phy_data);
  40. int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
  41. u16 reg, u16 phy_data);
  42. int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
  43. u16 reg_addr, u16 *phy_data);
  44. int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
  45. u16 reg_addr, u16 phy_data);
  46. int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
  47. int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data);
  48. void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
  49. /* hw-ids */
  50. #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
  51. #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
  52. #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
  53. #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
  54. #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
  55. #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
  56. #define L2CB_V10 0xc0
  57. #define L2CB_V11 0xc1
  58. #define L2CB_V20 0xc0
  59. #define L2CB_V21 0xc1
  60. /* register definition */
  61. #define REG_DEVICE_CAP 0x5C
  62. #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
  63. #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
  64. #define DEVICE_CTRL_MAXRRS_MIN 2
  65. #define REG_LINK_CTRL 0x68
  66. #define LINK_CTRL_L0S_EN 0x01
  67. #define LINK_CTRL_L1_EN 0x02
  68. #define LINK_CTRL_EXT_SYNC 0x80
  69. #define REG_PCIE_IND_ACC_ADDR 0x80
  70. #define REG_PCIE_IND_ACC_DATA 0x84
  71. #define REG_DEV_SERIALNUM_CTRL 0x200
  72. #define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
  73. #define REG_DEV_MAC_SEL_SHIFT 0
  74. #define REG_DEV_SERIAL_NUM_EN_MASK 0x1
  75. #define REG_DEV_SERIAL_NUM_EN_SHIFT 1
  76. #define REG_TWSI_CTRL 0x218
  77. #define TWSI_CTLR_FREQ_MASK 0x3UL
  78. #define TWSI_CTRL_FREQ_SHIFT 24
  79. #define TWSI_CTRL_FREQ_100K 0
  80. #define TWSI_CTRL_FREQ_200K 1
  81. #define TWSI_CTRL_FREQ_300K 2
  82. #define TWSI_CTRL_FREQ_400K 3
  83. #define TWSI_CTRL_LD_EXIST BIT(23)
  84. #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */
  85. #define TWSI_CTRL_SW_LDSTART BIT(11)
  86. #define TWSI_CTRL_LD_OFFSET_MASK 0xFF
  87. #define TWSI_CTRL_LD_OFFSET_SHIFT 0
  88. #define REG_PCIE_DEV_MISC_CTRL 0x21C
  89. #define PCIE_DEV_MISC_EXT_PIPE 0x2
  90. #define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
  91. #define PCIE_DEV_MISC_SPIROM_EXIST 0x4
  92. #define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
  93. #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
  94. #define REG_PCIE_PHYMISC 0x1000
  95. #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2)
  96. #define PCIE_PHYMISC_NFTS_MASK 0xFFUL
  97. #define PCIE_PHYMISC_NFTS_SHIFT 16
  98. #define REG_PCIE_PHYMISC2 0x1004
  99. #define PCIE_PHYMISC2_L0S_TH_MASK 0x3UL
  100. #define PCIE_PHYMISC2_L0S_TH_SHIFT 18
  101. #define L2CB1_PCIE_PHYMISC2_L0S_TH 3
  102. #define PCIE_PHYMISC2_CDR_BW_MASK 0x3UL
  103. #define PCIE_PHYMISC2_CDR_BW_SHIFT 16
  104. #define L2CB1_PCIE_PHYMISC2_CDR_BW 3
  105. #define REG_TWSI_DEBUG 0x1108
  106. #define TWSI_DEBUG_DEV_EXIST BIT(29)
  107. #define REG_DMA_DBG 0x1114
  108. #define DMA_DBG_VENDOR_MSG BIT(0)
  109. #define REG_EEPROM_CTRL 0x12C0
  110. #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
  111. #define EEPROM_CTRL_DATA_HI_SHIFT 0
  112. #define EEPROM_CTRL_ADDR_MASK 0x3FF
  113. #define EEPROM_CTRL_ADDR_SHIFT 16
  114. #define EEPROM_CTRL_ACK 0x40000000
  115. #define EEPROM_CTRL_RW 0x80000000
  116. #define REG_EEPROM_DATA_LO 0x12C4
  117. #define REG_OTP_CTRL 0x12F0
  118. #define OTP_CTRL_CLK_EN BIT(1)
  119. #define REG_PM_CTRL 0x12F8
  120. #define PM_CTRL_HOTRST BIT(31)
  121. #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on
  122. * thrghput(setting in 15A0) */
  123. #define PM_CTRL_SA_DLY_EN BIT(29)
  124. #define PM_CTRL_L0S_BUFSRX_EN BIT(28)
  125. #define PM_CTRL_LCKDET_TIMER_MASK 0xFUL
  126. #define PM_CTRL_LCKDET_TIMER_SHIFT 24
  127. #define PM_CTRL_LCKDET_TIMER_DEF 0xC
  128. #define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL
  129. #define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @
  130. * ->L0s not L1 */
  131. #define PM_CTRL_PM_REQ_TO_DEF 0xF
  132. #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */
  133. #define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */
  134. #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16
  135. #define L1D_PMCTRL_L1_ENTRY_TM_DIS 0
  136. #define L1D_PMCTRL_L1_ENTRY_TM_2US 1
  137. #define L1D_PMCTRL_L1_ENTRY_TM_4US 2
  138. #define L1D_PMCTRL_L1_ENTRY_TM_8US 3
  139. #define L1D_PMCTRL_L1_ENTRY_TM_16US 4
  140. #define L1D_PMCTRL_L1_ENTRY_TM_24US 5
  141. #define L1D_PMCTRL_L1_ENTRY_TM_32US 6
  142. #define L1D_PMCTRL_L1_ENTRY_TM_63US 7
  143. #define PM_CTRL_L1_ENTRY_TIMER_MASK 0xFUL /* l1C 4bits */
  144. #define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
  145. #define L2CB1_PM_CTRL_L1_ENTRY_TM 7
  146. #define L1C_PM_CTRL_L1_ENTRY_TM 0xF
  147. #define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */
  148. #define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */
  149. #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
  150. #define PM_CTRL_ASPM_L0S_EN BIT(12)
  151. #define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */
  152. #define L1D_PMCTRL_L0S_TIMER_MASK 7UL /* l1d2.0+, 3bits*/
  153. #define L1D_PMCTRL_L0S_TIMER_SHIFT 8
  154. #define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xFUL /* l1c, 4bits */
  155. #define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
  156. #define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7)
  157. #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */
  158. #define PM_CTRL_SERDES_PLL_L1_EN BIT(5)
  159. #define PM_CTRL_SERDES_L1_EN BIT(4)
  160. #define PM_CTRL_ASPM_L1_EN BIT(3)
  161. #define PM_CTRL_CLK_REQ_EN BIT(2)
  162. #define PM_CTRL_RBER_EN BIT(1)
  163. #define PM_CTRL_SPRSDWER_EN BIT(0)
  164. #define REG_LTSSM_ID_CTRL 0x12FC
  165. #define LTSSM_ID_EN_WRO 0x1000
  166. /* Selene Master Control Register */
  167. #define REG_MASTER_CTRL 0x1400
  168. #define MASTER_CTRL_OTP_SEL BIT(31)
  169. #define MASTER_DEV_NUM_MASK 0x7FUL
  170. #define MASTER_DEV_NUM_SHIFT 24
  171. #define MASTER_REV_NUM_MASK 0xFFUL
  172. #define MASTER_REV_NUM_SHIFT 16
  173. #define MASTER_CTRL_INT_RDCLR BIT(14)
  174. #define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from
  175. * serdes, not sw to 25M */
  176. #define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */
  177. #define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */
  178. #define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */
  179. #define MASTER_CTRL_MANUTIMER_EN BIT(8)
  180. #define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */
  181. #define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */
  182. #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */
  183. #define MASTER_CTRL_BERT_START BIT(4)
  184. #define MASTER_PCIE_TSTMOD_MASK 3UL
  185. #define MASTER_PCIE_TSTMOD_SHIFT 2
  186. #define MASTER_PCIE_RST BIT(1)
  187. #define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */
  188. #define DMA_MAC_RST_TO 50
  189. /* Timer Initial Value Register */
  190. #define REG_MANUAL_TIMER_INIT 0x1404
  191. /* IRQ ModeratorTimer Initial Value Register */
  192. #define REG_IRQ_MODRT_TIMER_INIT 0x1408
  193. #define IRQ_MODRT_TIMER_MASK 0xffff
  194. #define IRQ_MODRT_TX_TIMER_SHIFT 0
  195. #define IRQ_MODRT_RX_TIMER_SHIFT 16
  196. #define REG_GPHY_CTRL 0x140C
  197. #define GPHY_CTRL_ADDR_MASK 0x1FUL
  198. #define GPHY_CTRL_ADDR_SHIFT 19
  199. #define GPHY_CTRL_BP_VLTGSW BIT(18)
  200. #define GPHY_CTRL_100AB_EN BIT(17)
  201. #define GPHY_CTRL_10AB_EN BIT(16)
  202. #define GPHY_CTRL_PHY_PLL_BYPASS BIT(15)
  203. #define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */
  204. #define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */
  205. #define GPHY_CTRL_SEL_ANA_RST BIT(12)
  206. #define GPHY_CTRL_HIB_PULSE BIT(11)
  207. #define GPHY_CTRL_HIB_EN BIT(10)
  208. #define GPHY_CTRL_GIGA_DIS BIT(9)
  209. #define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */
  210. #define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */
  211. #define GPHY_CTRL_LPW_EXIT BIT(6)
  212. #define GPHY_CTRL_GATE_25M_EN BIT(5)
  213. #define GPHY_CTRL_REV_ANEG BIT(4)
  214. #define GPHY_CTRL_ANEG_NOW BIT(3)
  215. #define GPHY_CTRL_LED_MODE BIT(2)
  216. #define GPHY_CTRL_RTL_MODE BIT(1)
  217. #define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */
  218. #define GPHY_CTRL_EXT_RST_TO 80 /* 800us atmost */
  219. #define GPHY_CTRL_CLS (\
  220. GPHY_CTRL_LED_MODE |\
  221. GPHY_CTRL_100AB_EN |\
  222. GPHY_CTRL_PHY_PLL_ON)
  223. /* Block IDLE Status Register */
  224. #define REG_IDLE_STATUS 0x1410
  225. #define IDLE_STATUS_SFORCE_MASK 0xFUL
  226. #define IDLE_STATUS_SFORCE_SHIFT 14
  227. #define IDLE_STATUS_CALIB_DONE BIT(13)
  228. #define IDLE_STATUS_CALIB_RES_MASK 0x1FUL
  229. #define IDLE_STATUS_CALIB_RES_SHIFT 8
  230. #define IDLE_STATUS_CALIBERR_MASK 0xFUL
  231. #define IDLE_STATUS_CALIBERR_SHIFT 4
  232. #define IDLE_STATUS_TXQ_BUSY BIT(3)
  233. #define IDLE_STATUS_RXQ_BUSY BIT(2)
  234. #define IDLE_STATUS_TXMAC_BUSY BIT(1)
  235. #define IDLE_STATUS_RXMAC_BUSY BIT(0)
  236. #define IDLE_STATUS_MASK (\
  237. IDLE_STATUS_TXQ_BUSY |\
  238. IDLE_STATUS_RXQ_BUSY |\
  239. IDLE_STATUS_TXMAC_BUSY |\
  240. IDLE_STATUS_RXMAC_BUSY)
  241. /* MDIO Control Register */
  242. #define REG_MDIO_CTRL 0x1414
  243. #define MDIO_CTRL_MODE_EXT BIT(30)
  244. #define MDIO_CTRL_POST_READ BIT(29)
  245. #define MDIO_CTRL_AP_EN BIT(28)
  246. #define MDIO_CTRL_BUSY BIT(27)
  247. #define MDIO_CTRL_CLK_SEL_MASK 0x7UL
  248. #define MDIO_CTRL_CLK_SEL_SHIFT 24
  249. #define MDIO_CTRL_CLK_25_4 0 /* 25MHz divide 4 */
  250. #define MDIO_CTRL_CLK_25_6 2
  251. #define MDIO_CTRL_CLK_25_8 3
  252. #define MDIO_CTRL_CLK_25_10 4
  253. #define MDIO_CTRL_CLK_25_32 5
  254. #define MDIO_CTRL_CLK_25_64 6
  255. #define MDIO_CTRL_CLK_25_128 7
  256. #define MDIO_CTRL_START BIT(23)
  257. #define MDIO_CTRL_SPRES_PRMBL BIT(22)
  258. #define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */
  259. #define MDIO_CTRL_REG_MASK 0x1FUL
  260. #define MDIO_CTRL_REG_SHIFT 16
  261. #define MDIO_CTRL_DATA_MASK 0xFFFFUL
  262. #define MDIO_CTRL_DATA_SHIFT 0
  263. #define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */
  264. /* for extension reg access */
  265. #define REG_MDIO_EXTN 0x1448
  266. #define MDIO_EXTN_PORTAD_MASK 0x1FUL
  267. #define MDIO_EXTN_PORTAD_SHIFT 21
  268. #define MDIO_EXTN_DEVAD_MASK 0x1FUL
  269. #define MDIO_EXTN_DEVAD_SHIFT 16
  270. #define MDIO_EXTN_REG_MASK 0xFFFFUL
  271. #define MDIO_EXTN_REG_SHIFT 0
  272. /* BIST Control and Status Register0 (for the Packet Memory) */
  273. #define REG_BIST0_CTRL 0x141c
  274. #define BIST0_NOW 0x1
  275. #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
  276. * un-repairable because
  277. * it has address decoder
  278. * failure or more than 1 cell
  279. * stuck-to-x failure */
  280. #define BIST0_FUSE_FLAG 0x4
  281. /* BIST Control and Status Register1(for the retry buffer of PCI Express) */
  282. #define REG_BIST1_CTRL 0x1420
  283. #define BIST1_NOW 0x1
  284. #define BIST1_SRAM_FAIL 0x2
  285. #define BIST1_FUSE_FLAG 0x4
  286. /* SerDes Lock Detect Control and Status Register */
  287. #define REG_SERDES 0x1424
  288. #define SERDES_PHY_CLK_SLOWDOWN BIT(18)
  289. #define SERDES_MAC_CLK_SLOWDOWN BIT(17)
  290. #define SERDES_SELFB_PLL_MASK 0x3UL
  291. #define SERDES_SELFB_PLL_SHIFT 14
  292. #define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */
  293. #define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */
  294. #define SERDES_BUFS_RX_EN BIT(11)
  295. #define SERDES_PD_RX BIT(10)
  296. #define SERDES_PLL_EN BIT(9)
  297. #define SERDES_EN BIT(8)
  298. #define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */
  299. #define SERDES_SELFB_PLL_CSR_MASK 0x3UL
  300. #define SERDES_SELFB_PLL_CSR_SHIFT 4
  301. #define SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */
  302. #define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */
  303. #define SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */
  304. #define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */
  305. #define SERDES_VCO_SLOW BIT(3)
  306. #define SERDES_VCO_FAST BIT(2)
  307. #define SERDES_LOCK_DETECT_EN BIT(1)
  308. #define SERDES_LOCK_DETECT BIT(0)
  309. #define REG_LPI_DECISN_TIMER 0x143C
  310. #define L2CB_LPI_DESISN_TIMER 0x7D00
  311. #define REG_LPI_CTRL 0x1440
  312. #define LPI_CTRL_CHK_DA BIT(31)
  313. #define LPI_CTRL_ENH_TO_MASK 0x1FFFUL
  314. #define LPI_CTRL_ENH_TO_SHIFT 12
  315. #define LPI_CTRL_ENH_TH_MASK 0x1FUL
  316. #define LPI_CTRL_ENH_TH_SHIFT 6
  317. #define LPI_CTRL_ENH_EN BIT(5)
  318. #define LPI_CTRL_CHK_RX BIT(4)
  319. #define LPI_CTRL_CHK_STATE BIT(3)
  320. #define LPI_CTRL_GMII BIT(2)
  321. #define LPI_CTRL_TO_PHY BIT(1)
  322. #define LPI_CTRL_EN BIT(0)
  323. #define REG_LPI_WAIT 0x1444
  324. #define LPI_WAIT_TIMER_MASK 0xFFFFUL
  325. #define LPI_WAIT_TIMER_SHIFT 0
  326. /* MAC Control Register */
  327. #define REG_MAC_CTRL 0x1480
  328. #define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */
  329. #define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */
  330. #define MAC_CTRL_SINGLE_PAUSE_EN BIT(28)
  331. #define MAC_CTRL_DBG BIT(27)
  332. #define MAC_CTRL_BC_EN BIT(26)
  333. #define MAC_CTRL_MC_ALL_EN BIT(25)
  334. #define MAC_CTRL_RX_CHKSUM_EN BIT(24)
  335. #define MAC_CTRL_TX_HUGE BIT(23)
  336. #define MAC_CTRL_DBG_TX_BKPRESURE BIT(22)
  337. #define MAC_CTRL_SPEED_MASK 3UL
  338. #define MAC_CTRL_SPEED_SHIFT 20
  339. #define MAC_CTRL_SPEED_10_100 1
  340. #define MAC_CTRL_SPEED_1000 2
  341. #define MAC_CTRL_TX_SIMURST BIT(19)
  342. #define MAC_CTRL_SCNT BIT(17)
  343. #define MAC_CTRL_TX_PAUSE BIT(16)
  344. #define MAC_CTRL_PROMIS_EN BIT(15)
  345. #define MAC_CTRL_RMV_VLAN BIT(14)
  346. #define MAC_CTRL_PRMLEN_MASK 0xFUL
  347. #define MAC_CTRL_PRMLEN_SHIFT 10
  348. #define MAC_CTRL_HUGE_EN BIT(9)
  349. #define MAC_CTRL_LENCHK BIT(8)
  350. #define MAC_CTRL_PAD BIT(7)
  351. #define MAC_CTRL_ADD_CRC BIT(6)
  352. #define MAC_CTRL_DUPLX BIT(5)
  353. #define MAC_CTRL_LOOPBACK BIT(4)
  354. #define MAC_CTRL_RX_FLOW BIT(3)
  355. #define MAC_CTRL_TX_FLOW BIT(2)
  356. #define MAC_CTRL_RX_EN BIT(1)
  357. #define MAC_CTRL_TX_EN BIT(0)
  358. /* MAC IPG/IFG Control Register */
  359. #define REG_MAC_IPG_IFG 0x1484
  360. #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
  361. * inter-packet gap. The
  362. * default is 96-bit time */
  363. #define MAC_IPG_IFG_IPGT_MASK 0x7f
  364. #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to
  365. * enforce in between RX frames */
  366. #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
  367. #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
  368. #define MAC_IPG_IFG_IPGR1_MASK 0x7f
  369. #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
  370. #define MAC_IPG_IFG_IPGR2_MASK 0x7f
  371. /* MAC STATION ADDRESS */
  372. #define REG_MAC_STA_ADDR 0x1488
  373. /* Hash table for multicast address */
  374. #define REG_RX_HASH_TABLE 0x1490
  375. /* MAC Half-Duplex Control Register */
  376. #define REG_MAC_HALF_DUPLX_CTRL 0x1498
  377. #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
  378. #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
  379. #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
  380. #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
  381. #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
  382. #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
  383. #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
  384. * immediately start the
  385. * transmission after back pressure */
  386. #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
  387. #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
  388. #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
  389. #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
  390. #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
  391. /* Maximum Frame Length Control Register */
  392. #define REG_MTU 0x149c
  393. /* Wake-On-Lan control register */
  394. #define REG_WOL_CTRL 0x14a0
  395. #define WOL_PT7_MATCH BIT(31)
  396. #define WOL_PT6_MATCH BIT(30)
  397. #define WOL_PT5_MATCH BIT(29)
  398. #define WOL_PT4_MATCH BIT(28)
  399. #define WOL_PT3_MATCH BIT(27)
  400. #define WOL_PT2_MATCH BIT(26)
  401. #define WOL_PT1_MATCH BIT(25)
  402. #define WOL_PT0_MATCH BIT(24)
  403. #define WOL_PT7_EN BIT(23)
  404. #define WOL_PT6_EN BIT(22)
  405. #define WOL_PT5_EN BIT(21)
  406. #define WOL_PT4_EN BIT(20)
  407. #define WOL_PT3_EN BIT(19)
  408. #define WOL_PT2_EN BIT(18)
  409. #define WOL_PT1_EN BIT(17)
  410. #define WOL_PT0_EN BIT(16)
  411. #define WOL_LNKCHG_ST BIT(10)
  412. #define WOL_MAGIC_ST BIT(9)
  413. #define WOL_PATTERN_ST BIT(8)
  414. #define WOL_OOB_EN BIT(6)
  415. #define WOL_LINK_CHG_PME_EN BIT(5)
  416. #define WOL_LINK_CHG_EN BIT(4)
  417. #define WOL_MAGIC_PME_EN BIT(3)
  418. #define WOL_MAGIC_EN BIT(2)
  419. #define WOL_PATTERN_PME_EN BIT(1)
  420. #define WOL_PATTERN_EN BIT(0)
  421. /* WOL Length ( 2 DWORD ) */
  422. #define REG_WOL_PTLEN1 0x14A4
  423. #define WOL_PTLEN1_3_MASK 0xFFUL
  424. #define WOL_PTLEN1_3_SHIFT 24
  425. #define WOL_PTLEN1_2_MASK 0xFFUL
  426. #define WOL_PTLEN1_2_SHIFT 16
  427. #define WOL_PTLEN1_1_MASK 0xFFUL
  428. #define WOL_PTLEN1_1_SHIFT 8
  429. #define WOL_PTLEN1_0_MASK 0xFFUL
  430. #define WOL_PTLEN1_0_SHIFT 0
  431. #define REG_WOL_PTLEN2 0x14A8
  432. #define WOL_PTLEN2_7_MASK 0xFFUL
  433. #define WOL_PTLEN2_7_SHIFT 24
  434. #define WOL_PTLEN2_6_MASK 0xFFUL
  435. #define WOL_PTLEN2_6_SHIFT 16
  436. #define WOL_PTLEN2_5_MASK 0xFFUL
  437. #define WOL_PTLEN2_5_SHIFT 8
  438. #define WOL_PTLEN2_4_MASK 0xFFUL
  439. #define WOL_PTLEN2_4_SHIFT 0
  440. /* Internal SRAM Partition Register */
  441. #define RFDX_HEAD_ADDR_MASK 0x03FF
  442. #define RFDX_HARD_ADDR_SHIFT 0
  443. #define RFDX_TAIL_ADDR_MASK 0x03FF
  444. #define RFDX_TAIL_ADDR_SHIFT 16
  445. #define REG_SRAM_RFD0_INFO 0x1500
  446. #define REG_SRAM_RFD1_INFO 0x1504
  447. #define REG_SRAM_RFD2_INFO 0x1508
  448. #define REG_SRAM_RFD3_INFO 0x150C
  449. #define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
  450. #define RFD_NIC_LEN_MASK 0x03FF
  451. #define REG_SRAM_TRD_ADDR 0x1518
  452. #define TPD_HEAD_ADDR_MASK 0x03FF
  453. #define TPD_HEAD_ADDR_SHIFT 0
  454. #define TPD_TAIL_ADDR_MASK 0x03FF
  455. #define TPD_TAIL_ADDR_SHIFT 16
  456. #define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
  457. #define TPD_NIC_LEN_MASK 0x03FF
  458. #define REG_SRAM_RXF_ADDR 0x1520
  459. #define REG_SRAM_RXF_LEN 0x1524
  460. #define REG_SRAM_TXF_ADDR 0x1528
  461. #define REG_SRAM_TXF_LEN 0x152C
  462. #define REG_SRAM_TCPH_ADDR 0x1530
  463. #define REG_SRAM_PKTH_ADDR 0x1532
  464. /*
  465. * Load Ptr Register
  466. * Software sets this bit after the initialization of the head and tail */
  467. #define REG_LOAD_PTR 0x1534
  468. /*
  469. * addresses of all descriptors, as well as the following descriptor
  470. * control register, which triggers each function block to load the head
  471. * pointer to prepare for the operation. This bit is then self-cleared
  472. * after one cycle.
  473. */
  474. #define REG_RX_BASE_ADDR_HI 0x1540
  475. #define REG_TX_BASE_ADDR_HI 0x1544
  476. #define REG_RFD0_HEAD_ADDR_LO 0x1550
  477. #define REG_RFD_RING_SIZE 0x1560
  478. #define RFD_RING_SIZE_MASK 0x0FFF
  479. #define REG_RX_BUF_SIZE 0x1564
  480. #define RX_BUF_SIZE_MASK 0xFFFF
  481. #define REG_RRD0_HEAD_ADDR_LO 0x1568
  482. #define REG_RRD_RING_SIZE 0x1578
  483. #define RRD_RING_SIZE_MASK 0x0FFF
  484. #define REG_TPD_PRI1_ADDR_LO 0x157C
  485. #define REG_TPD_PRI0_ADDR_LO 0x1580
  486. #define REG_TPD_RING_SIZE 0x1584
  487. #define TPD_RING_SIZE_MASK 0xFFFF
  488. /* TXQ Control Register */
  489. #define REG_TXQ_CTRL 0x1590
  490. #define TXQ_TXF_BURST_NUM_MASK 0xFFFFUL
  491. #define TXQ_TXF_BURST_NUM_SHIFT 16
  492. #define L1C_TXQ_TXF_BURST_PREF 0x200
  493. #define L2CB_TXQ_TXF_BURST_PREF 0x40
  494. #define TXQ_CTRL_PEDING_CLR BIT(8)
  495. #define TXQ_CTRL_LS_8023_EN BIT(7)
  496. #define TXQ_CTRL_ENH_MODE BIT(6)
  497. #define TXQ_CTRL_EN BIT(5)
  498. #define TXQ_CTRL_IP_OPTION_EN BIT(4)
  499. #define TXQ_NUM_TPD_BURST_MASK 0xFUL
  500. #define TXQ_NUM_TPD_BURST_SHIFT 0
  501. #define TXQ_NUM_TPD_BURST_DEF 5
  502. #define TXQ_CFGV (\
  503. FIELDX(TXQ_NUM_TPD_BURST, TXQ_NUM_TPD_BURST_DEF) |\
  504. TXQ_CTRL_ENH_MODE |\
  505. TXQ_CTRL_LS_8023_EN |\
  506. TXQ_CTRL_IP_OPTION_EN)
  507. #define L1C_TXQ_CFGV (\
  508. TXQ_CFGV |\
  509. FIELDX(TXQ_TXF_BURST_NUM, L1C_TXQ_TXF_BURST_PREF))
  510. #define L2CB_TXQ_CFGV (\
  511. TXQ_CFGV |\
  512. FIELDX(TXQ_TXF_BURST_NUM, L2CB_TXQ_TXF_BURST_PREF))
  513. /* Jumbo packet Threshold for task offload */
  514. #define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
  515. #define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
  516. #define MAX_TSO_FRAME_SIZE (7*1024)
  517. #define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
  518. #define TXF_WATER_MARK_MASK 0x0FFF
  519. #define TXF_LOW_WATER_MARK_SHIFT 0
  520. #define TXF_HIGH_WATER_MARK_SHIFT 16
  521. #define TXQ_CTRL_BURST_MODE_EN 0x80000000
  522. #define REG_THRUPUT_MON_CTRL 0x159C
  523. #define THRUPUT_MON_RATE_MASK 0x3
  524. #define THRUPUT_MON_RATE_SHIFT 0
  525. #define THRUPUT_MON_EN 0x80
  526. /* RXQ Control Register */
  527. #define REG_RXQ_CTRL 0x15A0
  528. #define ASPM_THRUPUT_LIMIT_MASK 0x3
  529. #define ASPM_THRUPUT_LIMIT_SHIFT 0
  530. #define ASPM_THRUPUT_LIMIT_NO 0x00
  531. #define ASPM_THRUPUT_LIMIT_1M 0x01
  532. #define ASPM_THRUPUT_LIMIT_10M 0x02
  533. #define ASPM_THRUPUT_LIMIT_100M 0x03
  534. #define IPV6_CHKSUM_CTRL_EN BIT(7)
  535. #define RXQ_RFD_BURST_NUM_MASK 0x003F
  536. #define RXQ_RFD_BURST_NUM_SHIFT 20
  537. #define RXQ_NUM_RFD_PREF_DEF 8
  538. #define RSS_MODE_MASK 3UL
  539. #define RSS_MODE_SHIFT 26
  540. #define RSS_MODE_DIS 0
  541. #define RSS_MODE_SQSI 1
  542. #define RSS_MODE_MQSI 2
  543. #define RSS_MODE_MQMI 3
  544. #define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */
  545. #define RRS_HASH_CTRL_EN BIT(29)
  546. #define RX_CUT_THRU_EN BIT(30)
  547. #define RXQ_CTRL_EN BIT(31)
  548. #define REG_RFD_FREE_THRESH 0x15A4
  549. #define RFD_FREE_THRESH_MASK 0x003F
  550. #define RFD_FREE_HI_THRESH_SHIFT 0
  551. #define RFD_FREE_LO_THRESH_SHIFT 6
  552. /* RXF flow control register */
  553. #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
  554. #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
  555. #define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
  556. #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
  557. #define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
  558. #define REG_RXD_DMA_CTRL 0x15AC
  559. #define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
  560. #define RXD_DMA_THRESH_SHIFT 0
  561. #define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
  562. #define RXD_DMA_DOWN_TIMER_SHIFT 16
  563. /* DMA Engine Control Register */
  564. #define REG_DMA_CTRL 0x15C0
  565. #define DMA_CTRL_SMB_NOW BIT(31)
  566. #define DMA_CTRL_WPEND_CLR BIT(30)
  567. #define DMA_CTRL_RPEND_CLR BIT(29)
  568. #define DMA_CTRL_WDLY_CNT_MASK 0xFUL
  569. #define DMA_CTRL_WDLY_CNT_SHIFT 16
  570. #define DMA_CTRL_WDLY_CNT_DEF 4
  571. #define DMA_CTRL_RDLY_CNT_MASK 0x1FUL
  572. #define DMA_CTRL_RDLY_CNT_SHIFT 11
  573. #define DMA_CTRL_RDLY_CNT_DEF 15
  574. #define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */
  575. #define DMA_CTRL_WREQ_BLEN_MASK 7UL
  576. #define DMA_CTRL_WREQ_BLEN_SHIFT 7
  577. #define DMA_CTRL_RREQ_BLEN_MASK 7UL
  578. #define DMA_CTRL_RREQ_BLEN_SHIFT 4
  579. #define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */
  580. #define DMA_CTRL_RORDER_MODE_MASK 7UL
  581. #define DMA_CTRL_RORDER_MODE_SHIFT 0
  582. #define DMA_CTRL_RORDER_MODE_OUT 4
  583. #define DMA_CTRL_RORDER_MODE_ENHANCE 2
  584. #define DMA_CTRL_RORDER_MODE_IN 1
  585. /* INT-triggle/SMB Control Register */
  586. #define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
  587. #define SMB_STAT_TIMER_MASK 0xFFFFFF
  588. #define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */
  589. /* Mail box */
  590. #define MB_RFDX_PROD_IDX_MASK 0xFFFF
  591. #define REG_MB_RFD0_PROD_IDX 0x15E0
  592. #define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */
  593. #define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */
  594. #define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */
  595. #define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */
  596. #define REG_MB_RFD01_CONS_IDX 0x15F8
  597. #define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
  598. #define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
  599. /* Interrupt Status Register */
  600. #define REG_ISR 0x1600
  601. #define ISR_SMB 0x00000001
  602. #define ISR_TIMER 0x00000002
  603. /*
  604. * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
  605. * in Table 51 Selene Master Control Register (Offset 0x1400).
  606. */
  607. #define ISR_MANUAL 0x00000004
  608. #define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
  609. #define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
  610. #define ISR_RFD1_UR 0x00000020
  611. #define ISR_RFD2_UR 0x00000040
  612. #define ISR_RFD3_UR 0x00000080
  613. #define ISR_TXF_UR 0x00000100
  614. #define ISR_DMAR_TO_RST 0x00000200
  615. #define ISR_DMAW_TO_RST 0x00000400
  616. #define ISR_TX_CREDIT 0x00000800
  617. #define ISR_GPHY 0x00001000
  618. /* GPHY low power state interrupt */
  619. #define ISR_GPHY_LPW 0x00002000
  620. #define ISR_TXQ_TO_RST 0x00004000
  621. #define ISR_TX_PKT 0x00008000
  622. #define ISR_RX_PKT_0 0x00010000
  623. #define ISR_RX_PKT_1 0x00020000
  624. #define ISR_RX_PKT_2 0x00040000
  625. #define ISR_RX_PKT_3 0x00080000
  626. #define ISR_MAC_RX 0x00100000
  627. #define ISR_MAC_TX 0x00200000
  628. #define ISR_UR_DETECTED 0x00400000
  629. #define ISR_FERR_DETECTED 0x00800000
  630. #define ISR_NFERR_DETECTED 0x01000000
  631. #define ISR_CERR_DETECTED 0x02000000
  632. #define ISR_PHY_LINKDOWN 0x04000000
  633. #define ISR_DIS_INT 0x80000000
  634. /* Interrupt Mask Register */
  635. #define REG_IMR 0x1604
  636. #define IMR_NORMAL_MASK (\
  637. ISR_MANUAL |\
  638. ISR_HW_RXF_OV |\
  639. ISR_RFD0_UR |\
  640. ISR_TXF_UR |\
  641. ISR_DMAR_TO_RST |\
  642. ISR_TXQ_TO_RST |\
  643. ISR_DMAW_TO_RST |\
  644. ISR_GPHY |\
  645. ISR_TX_PKT |\
  646. ISR_RX_PKT_0 |\
  647. ISR_GPHY_LPW |\
  648. ISR_PHY_LINKDOWN)
  649. #define ISR_RX_PKT (\
  650. ISR_RX_PKT_0 |\
  651. ISR_RX_PKT_1 |\
  652. ISR_RX_PKT_2 |\
  653. ISR_RX_PKT_3)
  654. #define ISR_OVER (\
  655. ISR_RFD0_UR |\
  656. ISR_RFD1_UR |\
  657. ISR_RFD2_UR |\
  658. ISR_RFD3_UR |\
  659. ISR_HW_RXF_OV |\
  660. ISR_TXF_UR)
  661. #define ISR_ERROR (\
  662. ISR_DMAR_TO_RST |\
  663. ISR_TXQ_TO_RST |\
  664. ISR_DMAW_TO_RST |\
  665. ISR_PHY_LINKDOWN)
  666. #define REG_INT_RETRIG_TIMER 0x1608
  667. #define INT_RETRIG_TIMER_MASK 0xFFFF
  668. #define REG_MAC_RX_STATUS_BIN 0x1700
  669. #define REG_MAC_RX_STATUS_END 0x175c
  670. #define REG_MAC_TX_STATUS_BIN 0x1760
  671. #define REG_MAC_TX_STATUS_END 0x17c0
  672. #define REG_CLK_GATING_CTRL 0x1814
  673. #define CLK_GATING_DMAW_EN 0x0001
  674. #define CLK_GATING_DMAR_EN 0x0002
  675. #define CLK_GATING_TXQ_EN 0x0004
  676. #define CLK_GATING_RXQ_EN 0x0008
  677. #define CLK_GATING_TXMAC_EN 0x0010
  678. #define CLK_GATING_RXMAC_EN 0x0020
  679. #define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\
  680. CLK_GATING_DMAR_EN |\
  681. CLK_GATING_TXQ_EN |\
  682. CLK_GATING_RXQ_EN |\
  683. CLK_GATING_TXMAC_EN|\
  684. CLK_GATING_RXMAC_EN)
  685. /* DEBUG ADDR */
  686. #define REG_DEBUG_DATA0 0x1900
  687. #define REG_DEBUG_DATA1 0x1904
  688. #define L1D_MPW_PHYID1 0xD01C /* V7 */
  689. #define L1D_MPW_PHYID2 0xD01D /* V1-V6 */
  690. #define L1D_MPW_PHYID3 0xD01E /* V8 */
  691. /* Autoneg Advertisement Register */
  692. #define ADVERTISE_DEFAULT_CAP \
  693. (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)
  694. /* 1000BASE-T Control Register */
  695. #define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
  696. #define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
  697. #define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
  698. #define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
  699. #define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
  700. #define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
  701. #define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
  702. #define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
  703. #define GIGA_CR_1000T_SPEED_MASK 0x0300
  704. #define GIGA_CR_1000T_DEFAULT_CAP 0x0300
  705. /* PHY Specific Status Register */
  706. #define MII_GIGA_PSSR 0x11
  707. #define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
  708. #define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
  709. #define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
  710. #define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
  711. #define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
  712. #define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
  713. /* PHY Interrupt Enable Register */
  714. #define MII_IER 0x12
  715. #define IER_LINK_UP 0x0400
  716. #define IER_LINK_DOWN 0x0800
  717. /* PHY Interrupt Status Register */
  718. #define MII_ISR 0x13
  719. #define ISR_LINK_UP 0x0400
  720. #define ISR_LINK_DOWN 0x0800
  721. /* Cable-Detect-Test Control Register */
  722. #define MII_CDTC 0x16
  723. #define CDTC_EN_OFF 0 /* sc */
  724. #define CDTC_EN_BITS 1
  725. #define CDTC_PAIR_OFF 8
  726. #define CDTC_PAIR_BIT 2
  727. /* Cable-Detect-Test Status Register */
  728. #define MII_CDTS 0x1C
  729. #define CDTS_STATUS_OFF 8
  730. #define CDTS_STATUS_BITS 2
  731. #define CDTS_STATUS_NORMAL 0
  732. #define CDTS_STATUS_SHORT 1
  733. #define CDTS_STATUS_OPEN 2
  734. #define CDTS_STATUS_INVALID 3
  735. #define MII_DBG_ADDR 0x1D
  736. #define MII_DBG_DATA 0x1E
  737. /***************************** debug port *************************************/
  738. #define MIIDBG_ANACTRL 0x00
  739. #define ANACTRL_CLK125M_DELAY_EN 0x8000
  740. #define ANACTRL_VCO_FAST 0x4000
  741. #define ANACTRL_VCO_SLOW 0x2000
  742. #define ANACTRL_AFE_MODE_EN 0x1000
  743. #define ANACTRL_LCKDET_PHY 0x800
  744. #define ANACTRL_LCKDET_EN 0x400
  745. #define ANACTRL_OEN_125M 0x200
  746. #define ANACTRL_HBIAS_EN 0x100
  747. #define ANACTRL_HB_EN 0x80
  748. #define ANACTRL_SEL_HSP 0x40
  749. #define ANACTRL_CLASSA_EN 0x20
  750. #define ANACTRL_MANUSWON_SWR_MASK 3U
  751. #define ANACTRL_MANUSWON_SWR_SHIFT 2
  752. #define ANACTRL_MANUSWON_SWR_2V 0
  753. #define ANACTRL_MANUSWON_SWR_1P9V 1
  754. #define ANACTRL_MANUSWON_SWR_1P8V 2
  755. #define ANACTRL_MANUSWON_SWR_1P7V 3
  756. #define ANACTRL_MANUSWON_BW3_4M 0x2
  757. #define ANACTRL_RESTART_CAL 0x1
  758. #define ANACTRL_DEF 0x02EF
  759. #define MIIDBG_SYSMODCTRL 0x04
  760. #define SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000
  761. #define SYSMODCTRL_IECHOADJ_BIASGEN 0x4000
  762. #define SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000
  763. #define SYSMODCTRL_IECHOADJ_PS_MASK 3U
  764. #define SYSMODCTRL_IECHOADJ_PS_SHIFT 10
  765. #define SYSMODCTRL_IECHOADJ_PS_40 3
  766. #define SYSMODCTRL_IECHOADJ_PS_20 2
  767. #define SYSMODCTRL_IECHOADJ_PS_0 1
  768. #define SYSMODCTRL_IECHOADJ_10BT_100MV 0x40 /* 1:100mv, 0:200mv */
  769. #define SYSMODCTRL_IECHOADJ_HLFAP_MASK 3U
  770. #define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4
  771. #define SYSMODCTRL_IECHOADJ_VDFULBW 0x8
  772. #define SYSMODCTRL_IECHOADJ_VDBIASHLF 0x4
  773. #define SYSMODCTRL_IECHOADJ_VDAMPHLF 0x2
  774. #define SYSMODCTRL_IECHOADJ_VDLANSW 0x1
  775. #define SYSMODCTRL_IECHOADJ_DEF 0x88BB /* ???? */
  776. /* for l1d & l2cb */
  777. #define SYSMODCTRL_IECHOADJ_CUR_ADD 0x8000
  778. #define SYSMODCTRL_IECHOADJ_CUR_MASK 7U
  779. #define SYSMODCTRL_IECHOADJ_CUR_SHIFT 12
  780. #define SYSMODCTRL_IECHOADJ_VOL_MASK 0xFU
  781. #define SYSMODCTRL_IECHOADJ_VOL_SHIFT 8
  782. #define SYSMODCTRL_IECHOADJ_VOL_17ALL 3
  783. #define SYSMODCTRL_IECHOADJ_VOL_100M15 1
  784. #define SYSMODCTRL_IECHOADJ_VOL_10M17 0
  785. #define SYSMODCTRL_IECHOADJ_BIAS1_MASK 0xFU
  786. #define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT 4
  787. #define SYSMODCTRL_IECHOADJ_BIAS2_MASK 0xFU
  788. #define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT 0
  789. #define L1D_SYSMODCTRL_IECHOADJ_DEF 0x4FBB
  790. #define MIIDBG_SRDSYSMOD 0x05
  791. #define SRDSYSMOD_LCKDET_EN 0x2000
  792. #define SRDSYSMOD_PLL_EN 0x800
  793. #define SRDSYSMOD_SEL_HSP 0x400
  794. #define SRDSYSMOD_HLFTXDR 0x200
  795. #define SRDSYSMOD_TXCLK_DELAY_EN 0x100
  796. #define SRDSYSMOD_TXELECIDLE 0x80
  797. #define SRDSYSMOD_DEEMP_EN 0x40
  798. #define SRDSYSMOD_MS_PAD 0x4
  799. #define SRDSYSMOD_CDR_ADC_VLTG 0x2
  800. #define SRDSYSMOD_CDR_DAC_1MA 0x1
  801. #define SRDSYSMOD_DEF 0x2C46
  802. #define MIIDBG_CFGLPSPD 0x0A
  803. #define CFGLPSPD_RSTCNT_MASK 3U
  804. #define CFGLPSPD_RSTCNT_SHIFT 14
  805. #define CFGLPSPD_RSTCNT_CLK125SW 0x2000
  806. #define MIIDBG_HIBNEG 0x0B
  807. #define HIBNEG_PSHIB_EN 0x8000
  808. #define HIBNEG_WAKE_BOTH 0x4000
  809. #define HIBNEG_ONOFF_ANACHG_SUDEN 0x2000
  810. #define HIBNEG_HIB_PULSE 0x1000
  811. #define HIBNEG_GATE_25M_EN 0x800
  812. #define HIBNEG_RST_80U 0x400
  813. #define HIBNEG_RST_TIMER_MASK 3U
  814. #define HIBNEG_RST_TIMER_SHIFT 8
  815. #define HIBNEG_GTX_CLK_DELAY_MASK 3U
  816. #define HIBNEG_GTX_CLK_DELAY_SHIFT 5
  817. #define HIBNEG_BYPSS_BRKTIMER 0x10
  818. #define HIBNEG_DEF 0xBC40
  819. #define MIIDBG_TST10BTCFG 0x12
  820. #define TST10BTCFG_INTV_TIMER_MASK 3U
  821. #define TST10BTCFG_INTV_TIMER_SHIFT 14
  822. #define TST10BTCFG_TRIGER_TIMER_MASK 3U
  823. #define TST10BTCFG_TRIGER_TIMER_SHIFT 12
  824. #define TST10BTCFG_DIV_MAN_MLT3_EN 0x800
  825. #define TST10BTCFG_OFF_DAC_IDLE 0x400
  826. #define TST10BTCFG_LPBK_DEEP 0x4 /* 1:deep,0:shallow */
  827. #define TST10BTCFG_DEF 0x4C04
  828. #define MIIDBG_AZ_ANADECT 0x15
  829. #define AZ_ANADECT_10BTRX_TH 0x8000
  830. #define AZ_ANADECT_BOTH_01CHNL 0x4000
  831. #define AZ_ANADECT_INTV_MASK 0x3FU
  832. #define AZ_ANADECT_INTV_SHIFT 8
  833. #define AZ_ANADECT_THRESH_MASK 0xFU
  834. #define AZ_ANADECT_THRESH_SHIFT 4
  835. #define AZ_ANADECT_CHNL_MASK 0xFU
  836. #define AZ_ANADECT_CHNL_SHIFT 0
  837. #define AZ_ANADECT_DEF 0x3220
  838. #define AZ_ANADECT_LONG 0xb210
  839. #define MIIDBG_MSE16DB 0x18 /* l1d */
  840. #define L1D_MSE16DB_UP 0x05EA
  841. #define L1D_MSE16DB_DOWN 0x02EA
  842. #define MIIDBG_LEGCYPS 0x29
  843. #define LEGCYPS_EN 0x8000
  844. #define LEGCYPS_DAC_AMP1000_MASK 7U
  845. #define LEGCYPS_DAC_AMP1000_SHIFT 12
  846. #define LEGCYPS_DAC_AMP100_MASK 7U
  847. #define LEGCYPS_DAC_AMP100_SHIFT 9
  848. #define LEGCYPS_DAC_AMP10_MASK 7U
  849. #define LEGCYPS_DAC_AMP10_SHIFT 6
  850. #define LEGCYPS_UNPLUG_TIMER_MASK 7U
  851. #define LEGCYPS_UNPLUG_TIMER_SHIFT 3
  852. #define LEGCYPS_UNPLUG_DECT_EN 0x4
  853. #define LEGCYPS_ECNC_PS_EN 0x1
  854. #define L1D_LEGCYPS_DEF 0x129D
  855. #define L1C_LEGCYPS_DEF 0x36DD
  856. #define MIIDBG_TST100BTCFG 0x36
  857. #define TST100BTCFG_NORMAL_BW_EN 0x8000
  858. #define TST100BTCFG_BADLNK_BYPASS 0x4000
  859. #define TST100BTCFG_SHORTCABL_TH_MASK 0x3FU
  860. #define TST100BTCFG_SHORTCABL_TH_SHIFT 8
  861. #define TST100BTCFG_LITCH_EN 0x80
  862. #define TST100BTCFG_VLT_SW 0x40
  863. #define TST100BTCFG_LONGCABL_TH_MASK 0x3FU
  864. #define TST100BTCFG_LONGCABL_TH_SHIFT 0
  865. #define TST100BTCFG_DEF 0xE12C
  866. #define MIIDBG_VOLT_CTRL 0x3B /* only for l2cb 1 & 2 */
  867. #define VOLT_CTRL_CABLE1TH_MASK 0x1FFU
  868. #define VOLT_CTRL_CABLE1TH_SHIFT 7
  869. #define VOLT_CTRL_AMPCTRL_MASK 3U
  870. #define VOLT_CTRL_AMPCTRL_SHIFT 5
  871. #define VOLT_CTRL_SW_BYPASS 0x10
  872. #define VOLT_CTRL_SWLOWEST 0x8
  873. #define VOLT_CTRL_DACAMP10_MASK 7U
  874. #define VOLT_CTRL_DACAMP10_SHIFT 0
  875. #define MIIDBG_CABLE1TH_DET 0x3E
  876. #define CABLE1TH_DET_EN 0x8000
  877. /******* dev 3 *********/
  878. #define MIIEXT_PCS 3
  879. #define MIIEXT_CLDCTRL3 0x8003
  880. #define CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
  881. #define CLDCTRL3_AZ_DISAMP 0x1000
  882. #define L2CB_CLDCTRL3 0x4D19
  883. #define L1D_CLDCTRL3 0xDD19
  884. #define MIIEXT_CLDCTRL6 0x8006
  885. #define CLDCTRL6_CAB_LEN_MASK 0x1FFU
  886. #define CLDCTRL6_CAB_LEN_SHIFT 0
  887. #define CLDCTRL6_CAB_LEN_SHORT 0x50
  888. /********* dev 7 **********/
  889. #define MIIEXT_ANEG 7
  890. #define MIIEXT_LOCAL_EEEADV 0x3C
  891. #define LOCAL_EEEADV_1000BT 0x4
  892. #define LOCAL_EEEADV_100BT 0x2
  893. #define MIIEXT_REMOTE_EEEADV 0x3D
  894. #define REMOTE_EEEADV_1000BT 0x4
  895. #define REMOTE_EEEADV_100BT 0x2
  896. #define MIIEXT_EEE_ANEG 0x8000
  897. #define EEE_ANEG_1000M 0x4
  898. #define EEE_ANEG_100M 0x2
  899. #endif /*_ATL1C_HW_H_*/