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/drivers/net/ethernet/atheros/atl1c/atl1c_main.c

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C | 2785 lines | 2053 code | 368 blank | 364 comment | 303 complexity | d075e108d721cacb22ccb1cc972e9fc6 MD5 | raw file

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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
   4 *
   5 * Derived from Intel e1000 driver
   6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
   7 */
   8
   9#include "atl1c.h"
  10
  11char atl1c_driver_name[] = "atl1c";
  12
  13/*
  14 * atl1c_pci_tbl - PCI Device ID Table
  15 *
  16 * Wildcard entries (PCI_ANY_ID) should come last
  17 * Last entry must be all 0s
  18 *
  19 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  20 *   Class, Class Mask, private data (not used) }
  21 */
  22static const struct pci_device_id atl1c_pci_tbl[] = {
  23	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  24	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  25	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  26	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  27	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  28	{PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  29	/* required last entry */
  30	{ 0 }
  31};
  32MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  33
  34MODULE_AUTHOR("Jie Yang");
  35MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  36MODULE_DESCRIPTION("Qualcomm Atheros 100/1000M Ethernet Network Driver");
  37MODULE_LICENSE("GPL");
  38
  39static int atl1c_stop_mac(struct atl1c_hw *hw);
  40static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  41static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  42static void atl1c_start_mac(struct atl1c_adapter *adapter);
  43static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  44		   int *work_done, int work_to_do);
  45static int atl1c_up(struct atl1c_adapter *adapter);
  46static void atl1c_down(struct atl1c_adapter *adapter);
  47static int atl1c_reset_mac(struct atl1c_hw *hw);
  48static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
  49static int atl1c_configure(struct atl1c_adapter *adapter);
  50static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
  51
  52
  53static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  54	NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  55static void atl1c_pcie_patch(struct atl1c_hw *hw)
  56{
  57	u32 mst_data, data;
  58
  59	/* pclk sel could switch to 25M */
  60	AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  61	mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  62	AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  63
  64	/* WoL/PCIE related settings */
  65	if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  66		AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  67		data |= PCIE_PHYMISC_FORCE_RCV_DET;
  68		AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  69	} else { /* new dev set bit5 of MASTER */
  70		if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  71			AT_WRITE_REG(hw, REG_MASTER_CTRL,
  72				mst_data | MASTER_CTRL_WAKEN_25M);
  73	}
  74	/* aspm/PCIE setting only for l2cb 1.0 */
  75	if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  76		AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  77		data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  78			L2CB1_PCIE_PHYMISC2_CDR_BW);
  79		data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  80			L2CB1_PCIE_PHYMISC2_L0S_TH);
  81		AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  82		/* extend L1 sync timer */
  83		AT_READ_REG(hw, REG_LINK_CTRL, &data);
  84		data |= LINK_CTRL_EXT_SYNC;
  85		AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  86	}
  87	/* l2cb 1.x & l1d 1.x */
  88	if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  89		AT_READ_REG(hw, REG_PM_CTRL, &data);
  90		data |= PM_CTRL_L0S_BUFSRX_EN;
  91		AT_WRITE_REG(hw, REG_PM_CTRL, data);
  92		/* clear vendor msg */
  93		AT_READ_REG(hw, REG_DMA_DBG, &data);
  94		AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  95	}
  96}
  97
  98/* FIXME: no need any more ? */
  99/*
 100 * atl1c_init_pcie - init PCIE module
 101 */
 102static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
 103{
 104	u32 data;
 105	u32 pci_cmd;
 106	struct pci_dev *pdev = hw->adapter->pdev;
 107	int pos;
 108
 109	AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
 110	pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
 111	pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 112		PCI_COMMAND_IO);
 113	AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
 114
 115	/*
 116	 * Clear any PowerSaveing Settings
 117	 */
 118	pci_enable_wake(pdev, PCI_D3hot, 0);
 119	pci_enable_wake(pdev, PCI_D3cold, 0);
 120	/* wol sts read-clear */
 121	AT_READ_REG(hw, REG_WOL_CTRL, &data);
 122	AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
 123
 124	/*
 125	 * Mask some pcie error bits
 126	 */
 127	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 128	if (pos) {
 129		pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
 130		data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
 131		pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
 132	}
 133	/* clear error status */
 134	pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
 135			PCI_EXP_DEVSTA_NFED |
 136			PCI_EXP_DEVSTA_FED |
 137			PCI_EXP_DEVSTA_CED |
 138			PCI_EXP_DEVSTA_URD);
 139
 140	AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
 141	data &= ~LTSSM_ID_EN_WRO;
 142	AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
 143
 144	atl1c_pcie_patch(hw);
 145	if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
 146		atl1c_disable_l0s_l1(hw);
 147
 148	msleep(5);
 149}
 150
 151/**
 152 * atl1c_irq_enable - Enable default interrupt generation settings
 153 * @adapter: board private structure
 154 */
 155static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
 156{
 157	if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
 158		AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
 159		AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
 160		AT_WRITE_FLUSH(&adapter->hw);
 161	}
 162}
 163
 164/**
 165 * atl1c_irq_disable - Mask off interrupt generation on the NIC
 166 * @adapter: board private structure
 167 */
 168static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
 169{
 170	atomic_inc(&adapter->irq_sem);
 171	AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
 172	AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
 173	AT_WRITE_FLUSH(&adapter->hw);
 174	synchronize_irq(adapter->pdev->irq);
 175}
 176
 177/**
 178 * atl1c_irq_reset - reset interrupt confiure on the NIC
 179 * @adapter: board private structure
 180 */
 181static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
 182{
 183	atomic_set(&adapter->irq_sem, 1);
 184	atl1c_irq_enable(adapter);
 185}
 186
 187/*
 188 * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
 189 * of the idle status register until the device is actually idle
 190 */
 191static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
 192{
 193	int timeout;
 194	u32 data;
 195
 196	for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
 197		AT_READ_REG(hw, REG_IDLE_STATUS, &data);
 198		if ((data & modu_ctrl) == 0)
 199			return 0;
 200		msleep(1);
 201	}
 202	return data;
 203}
 204
 205/**
 206 * atl1c_phy_config - Timer Call-back
 207 * @data: pointer to netdev cast into an unsigned long
 208 */
 209static void atl1c_phy_config(struct timer_list *t)
 210{
 211	struct atl1c_adapter *adapter = from_timer(adapter, t,
 212						   phy_config_timer);
 213	struct atl1c_hw *hw = &adapter->hw;
 214	unsigned long flags;
 215
 216	spin_lock_irqsave(&adapter->mdio_lock, flags);
 217	atl1c_restart_autoneg(hw);
 218	spin_unlock_irqrestore(&adapter->mdio_lock, flags);
 219}
 220
 221void atl1c_reinit_locked(struct atl1c_adapter *adapter)
 222{
 223	WARN_ON(in_interrupt());
 224	atl1c_down(adapter);
 225	atl1c_up(adapter);
 226	clear_bit(__AT_RESETTING, &adapter->flags);
 227}
 228
 229static void atl1c_check_link_status(struct atl1c_adapter *adapter)
 230{
 231	struct atl1c_hw *hw = &adapter->hw;
 232	struct net_device *netdev = adapter->netdev;
 233	struct pci_dev    *pdev   = adapter->pdev;
 234	int err;
 235	unsigned long flags;
 236	u16 speed, duplex, phy_data;
 237
 238	spin_lock_irqsave(&adapter->mdio_lock, flags);
 239	/* MII_BMSR must read twise */
 240	atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
 241	atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
 242	spin_unlock_irqrestore(&adapter->mdio_lock, flags);
 243
 244	if ((phy_data & BMSR_LSTATUS) == 0) {
 245		/* link down */
 246		netif_carrier_off(netdev);
 247		hw->hibernate = true;
 248		if (atl1c_reset_mac(hw) != 0)
 249			if (netif_msg_hw(adapter))
 250				dev_warn(&pdev->dev, "reset mac failed\n");
 251		atl1c_set_aspm(hw, SPEED_0);
 252		atl1c_post_phy_linkchg(hw, SPEED_0);
 253		atl1c_reset_dma_ring(adapter);
 254		atl1c_configure(adapter);
 255	} else {
 256		/* Link Up */
 257		hw->hibernate = false;
 258		spin_lock_irqsave(&adapter->mdio_lock, flags);
 259		err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
 260		spin_unlock_irqrestore(&adapter->mdio_lock, flags);
 261		if (unlikely(err))
 262			return;
 263		/* link result is our setting */
 264		if (adapter->link_speed != speed ||
 265		    adapter->link_duplex != duplex) {
 266			adapter->link_speed  = speed;
 267			adapter->link_duplex = duplex;
 268			atl1c_set_aspm(hw, speed);
 269			atl1c_post_phy_linkchg(hw, speed);
 270			atl1c_start_mac(adapter);
 271			if (netif_msg_link(adapter))
 272				dev_info(&pdev->dev,
 273					"%s: %s NIC Link is Up<%d Mbps %s>\n",
 274					atl1c_driver_name, netdev->name,
 275					adapter->link_speed,
 276					adapter->link_duplex == FULL_DUPLEX ?
 277					"Full Duplex" : "Half Duplex");
 278		}
 279		if (!netif_carrier_ok(netdev))
 280			netif_carrier_on(netdev);
 281	}
 282}
 283
 284static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
 285{
 286	struct net_device *netdev = adapter->netdev;
 287	struct pci_dev    *pdev   = adapter->pdev;
 288	u16 phy_data;
 289	u16 link_up;
 290
 291	spin_lock(&adapter->mdio_lock);
 292	atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
 293	atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
 294	spin_unlock(&adapter->mdio_lock);
 295	link_up = phy_data & BMSR_LSTATUS;
 296	/* notify upper layer link down ASAP */
 297	if (!link_up) {
 298		if (netif_carrier_ok(netdev)) {
 299			/* old link state: Up */
 300			netif_carrier_off(netdev);
 301			if (netif_msg_link(adapter))
 302				dev_info(&pdev->dev,
 303					"%s: %s NIC Link is Down\n",
 304					atl1c_driver_name, netdev->name);
 305			adapter->link_speed = SPEED_0;
 306		}
 307	}
 308
 309	set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
 310	schedule_work(&adapter->common_task);
 311}
 312
 313static void atl1c_common_task(struct work_struct *work)
 314{
 315	struct atl1c_adapter *adapter;
 316	struct net_device *netdev;
 317
 318	adapter = container_of(work, struct atl1c_adapter, common_task);
 319	netdev = adapter->netdev;
 320
 321	if (test_bit(__AT_DOWN, &adapter->flags))
 322		return;
 323
 324	if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
 325		netif_device_detach(netdev);
 326		atl1c_down(adapter);
 327		atl1c_up(adapter);
 328		netif_device_attach(netdev);
 329	}
 330
 331	if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
 332		&adapter->work_event)) {
 333		atl1c_irq_disable(adapter);
 334		atl1c_check_link_status(adapter);
 335		atl1c_irq_enable(adapter);
 336	}
 337}
 338
 339
 340static void atl1c_del_timer(struct atl1c_adapter *adapter)
 341{
 342	del_timer_sync(&adapter->phy_config_timer);
 343}
 344
 345
 346/**
 347 * atl1c_tx_timeout - Respond to a Tx Hang
 348 * @netdev: network interface device structure
 349 */
 350static void atl1c_tx_timeout(struct net_device *netdev, unsigned int txqueue)
 351{
 352	struct atl1c_adapter *adapter = netdev_priv(netdev);
 353
 354	/* Do the reset outside of interrupt context */
 355	set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
 356	schedule_work(&adapter->common_task);
 357}
 358
 359/**
 360 * atl1c_set_multi - Multicast and Promiscuous mode set
 361 * @netdev: network interface device structure
 362 *
 363 * The set_multi entry point is called whenever the multicast address
 364 * list or the network interface flags are updated.  This routine is
 365 * responsible for configuring the hardware for proper multicast,
 366 * promiscuous mode, and all-multi behavior.
 367 */
 368static void atl1c_set_multi(struct net_device *netdev)
 369{
 370	struct atl1c_adapter *adapter = netdev_priv(netdev);
 371	struct atl1c_hw *hw = &adapter->hw;
 372	struct netdev_hw_addr *ha;
 373	u32 mac_ctrl_data;
 374	u32 hash_value;
 375
 376	/* Check for Promiscuous and All Multicast modes */
 377	AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
 378
 379	if (netdev->flags & IFF_PROMISC) {
 380		mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
 381	} else if (netdev->flags & IFF_ALLMULTI) {
 382		mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
 383		mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
 384	} else {
 385		mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
 386	}
 387
 388	AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
 389
 390	/* clear the old settings from the multicast hash table */
 391	AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
 392	AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
 393
 394	/* comoute mc addresses' hash value ,and put it into hash table */
 395	netdev_for_each_mc_addr(ha, netdev) {
 396		hash_value = atl1c_hash_mc_addr(hw, ha->addr);
 397		atl1c_hash_set(hw, hash_value);
 398	}
 399}
 400
 401static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
 402{
 403	if (features & NETIF_F_HW_VLAN_CTAG_RX) {
 404		/* enable VLAN tag insert/strip */
 405		*mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
 406	} else {
 407		/* disable VLAN tag insert/strip */
 408		*mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
 409	}
 410}
 411
 412static void atl1c_vlan_mode(struct net_device *netdev,
 413	netdev_features_t features)
 414{
 415	struct atl1c_adapter *adapter = netdev_priv(netdev);
 416	struct pci_dev *pdev = adapter->pdev;
 417	u32 mac_ctrl_data = 0;
 418
 419	if (netif_msg_pktdata(adapter))
 420		dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
 421
 422	atl1c_irq_disable(adapter);
 423	AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
 424	__atl1c_vlan_mode(features, &mac_ctrl_data);
 425	AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
 426	atl1c_irq_enable(adapter);
 427}
 428
 429static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
 430{
 431	struct pci_dev *pdev = adapter->pdev;
 432
 433	if (netif_msg_pktdata(adapter))
 434		dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
 435	atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
 436}
 437
 438/**
 439 * atl1c_set_mac - Change the Ethernet Address of the NIC
 440 * @netdev: network interface device structure
 441 * @p: pointer to an address structure
 442 *
 443 * Returns 0 on success, negative on failure
 444 */
 445static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
 446{
 447	struct atl1c_adapter *adapter = netdev_priv(netdev);
 448	struct sockaddr *addr = p;
 449
 450	if (!is_valid_ether_addr(addr->sa_data))
 451		return -EADDRNOTAVAIL;
 452
 453	if (netif_running(netdev))
 454		return -EBUSY;
 455
 456	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
 457	memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
 458
 459	atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
 460
 461	return 0;
 462}
 463
 464static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
 465				struct net_device *dev)
 466{
 467	unsigned int head_size;
 468	int mtu = dev->mtu;
 469
 470	adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
 471		roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
 472
 473	head_size = SKB_DATA_ALIGN(adapter->rx_buffer_len + NET_SKB_PAD) +
 474		    SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 475	adapter->rx_frag_size = roundup_pow_of_two(head_size);
 476}
 477
 478static netdev_features_t atl1c_fix_features(struct net_device *netdev,
 479	netdev_features_t features)
 480{
 481	/*
 482	 * Since there is no support for separate rx/tx vlan accel
 483	 * enable/disable make sure tx flag is always in same state as rx.
 484	 */
 485	if (features & NETIF_F_HW_VLAN_CTAG_RX)
 486		features |= NETIF_F_HW_VLAN_CTAG_TX;
 487	else
 488		features &= ~NETIF_F_HW_VLAN_CTAG_TX;
 489
 490	if (netdev->mtu > MAX_TSO_FRAME_SIZE)
 491		features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
 492
 493	return features;
 494}
 495
 496static int atl1c_set_features(struct net_device *netdev,
 497	netdev_features_t features)
 498{
 499	netdev_features_t changed = netdev->features ^ features;
 500
 501	if (changed & NETIF_F_HW_VLAN_CTAG_RX)
 502		atl1c_vlan_mode(netdev, features);
 503
 504	return 0;
 505}
 506
 507static void atl1c_set_max_mtu(struct net_device *netdev)
 508{
 509	struct atl1c_adapter *adapter = netdev_priv(netdev);
 510	struct atl1c_hw *hw = &adapter->hw;
 511
 512	switch (hw->nic_type) {
 513	/* These (GbE) devices support jumbo packets, max_mtu 6122 */
 514	case athr_l1c:
 515	case athr_l1d:
 516	case athr_l1d_2:
 517		netdev->max_mtu = MAX_JUMBO_FRAME_SIZE -
 518				  (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
 519		break;
 520	/* The 10/100 devices don't support jumbo packets, max_mtu 1500 */
 521	default:
 522		netdev->max_mtu = ETH_DATA_LEN;
 523		break;
 524	}
 525}
 526
 527/**
 528 * atl1c_change_mtu - Change the Maximum Transfer Unit
 529 * @netdev: network interface device structure
 530 * @new_mtu: new value for maximum frame size
 531 *
 532 * Returns 0 on success, negative on failure
 533 */
 534static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
 535{
 536	struct atl1c_adapter *adapter = netdev_priv(netdev);
 537
 538	/* set MTU */
 539	if (netif_running(netdev)) {
 540		while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
 541			msleep(1);
 542		netdev->mtu = new_mtu;
 543		adapter->hw.max_frame_size = new_mtu;
 544		atl1c_set_rxbufsize(adapter, netdev);
 545		atl1c_down(adapter);
 546		netdev_update_features(netdev);
 547		atl1c_up(adapter);
 548		clear_bit(__AT_RESETTING, &adapter->flags);
 549	}
 550	return 0;
 551}
 552
 553/*
 554 *  caller should hold mdio_lock
 555 */
 556static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
 557{
 558	struct atl1c_adapter *adapter = netdev_priv(netdev);
 559	u16 result;
 560
 561	atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
 562	return result;
 563}
 564
 565static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
 566			     int reg_num, int val)
 567{
 568	struct atl1c_adapter *adapter = netdev_priv(netdev);
 569
 570	atl1c_write_phy_reg(&adapter->hw, reg_num, val);
 571}
 572
 573static int atl1c_mii_ioctl(struct net_device *netdev,
 574			   struct ifreq *ifr, int cmd)
 575{
 576	struct atl1c_adapter *adapter = netdev_priv(netdev);
 577	struct pci_dev *pdev = adapter->pdev;
 578	struct mii_ioctl_data *data = if_mii(ifr);
 579	unsigned long flags;
 580	int retval = 0;
 581
 582	if (!netif_running(netdev))
 583		return -EINVAL;
 584
 585	spin_lock_irqsave(&adapter->mdio_lock, flags);
 586	switch (cmd) {
 587	case SIOCGMIIPHY:
 588		data->phy_id = 0;
 589		break;
 590
 591	case SIOCGMIIREG:
 592		if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
 593				    &data->val_out)) {
 594			retval = -EIO;
 595			goto out;
 596		}
 597		break;
 598
 599	case SIOCSMIIREG:
 600		if (data->reg_num & ~(0x1F)) {
 601			retval = -EFAULT;
 602			goto out;
 603		}
 604
 605		dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
 606				data->reg_num, data->val_in);
 607		if (atl1c_write_phy_reg(&adapter->hw,
 608				     data->reg_num, data->val_in)) {
 609			retval = -EIO;
 610			goto out;
 611		}
 612		break;
 613
 614	default:
 615		retval = -EOPNOTSUPP;
 616		break;
 617	}
 618out:
 619	spin_unlock_irqrestore(&adapter->mdio_lock, flags);
 620	return retval;
 621}
 622
 623static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 624{
 625	switch (cmd) {
 626	case SIOCGMIIPHY:
 627	case SIOCGMIIREG:
 628	case SIOCSMIIREG:
 629		return atl1c_mii_ioctl(netdev, ifr, cmd);
 630	default:
 631		return -EOPNOTSUPP;
 632	}
 633}
 634
 635/**
 636 * atl1c_alloc_queues - Allocate memory for all rings
 637 * @adapter: board private structure to initialize
 638 *
 639 */
 640static int atl1c_alloc_queues(struct atl1c_adapter *adapter)
 641{
 642	return 0;
 643}
 644
 645static void atl1c_set_mac_type(struct atl1c_hw *hw)
 646{
 647	switch (hw->device_id) {
 648	case PCI_DEVICE_ID_ATTANSIC_L2C:
 649		hw->nic_type = athr_l2c;
 650		break;
 651	case PCI_DEVICE_ID_ATTANSIC_L1C:
 652		hw->nic_type = athr_l1c;
 653		break;
 654	case PCI_DEVICE_ID_ATHEROS_L2C_B:
 655		hw->nic_type = athr_l2c_b;
 656		break;
 657	case PCI_DEVICE_ID_ATHEROS_L2C_B2:
 658		hw->nic_type = athr_l2c_b2;
 659		break;
 660	case PCI_DEVICE_ID_ATHEROS_L1D:
 661		hw->nic_type = athr_l1d;
 662		break;
 663	case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
 664		hw->nic_type = athr_l1d_2;
 665		break;
 666	default:
 667		break;
 668	}
 669}
 670
 671static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
 672{
 673	u32 link_ctrl_data;
 674
 675	atl1c_set_mac_type(hw);
 676	AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
 677
 678	hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE  |
 679			 ATL1C_TXQ_MODE_ENHANCE;
 680	hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
 681			  ATL1C_ASPM_L1_SUPPORT;
 682	hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
 683
 684	if (hw->nic_type == athr_l1c ||
 685	    hw->nic_type == athr_l1d ||
 686	    hw->nic_type == athr_l1d_2)
 687		hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
 688	return 0;
 689}
 690
 691struct atl1c_platform_patch {
 692	u16 pci_did;
 693	u8  pci_revid;
 694	u16 subsystem_vid;
 695	u16 subsystem_did;
 696	u32 patch_flag;
 697#define ATL1C_LINK_PATCH	0x1
 698};
 699static const struct atl1c_platform_patch plats[] = {
 700{0x2060, 0xC1, 0x1019, 0x8152, 0x1},
 701{0x2060, 0xC1, 0x1019, 0x2060, 0x1},
 702{0x2060, 0xC1, 0x1019, 0xE000, 0x1},
 703{0x2062, 0xC0, 0x1019, 0x8152, 0x1},
 704{0x2062, 0xC0, 0x1019, 0x2062, 0x1},
 705{0x2062, 0xC0, 0x1458, 0xE000, 0x1},
 706{0x2062, 0xC1, 0x1019, 0x8152, 0x1},
 707{0x2062, 0xC1, 0x1019, 0x2062, 0x1},
 708{0x2062, 0xC1, 0x1458, 0xE000, 0x1},
 709{0x2062, 0xC1, 0x1565, 0x2802, 0x1},
 710{0x2062, 0xC1, 0x1565, 0x2801, 0x1},
 711{0x1073, 0xC0, 0x1019, 0x8151, 0x1},
 712{0x1073, 0xC0, 0x1019, 0x1073, 0x1},
 713{0x1073, 0xC0, 0x1458, 0xE000, 0x1},
 714{0x1083, 0xC0, 0x1458, 0xE000, 0x1},
 715{0x1083, 0xC0, 0x1019, 0x8151, 0x1},
 716{0x1083, 0xC0, 0x1019, 0x1083, 0x1},
 717{0x1083, 0xC0, 0x1462, 0x7680, 0x1},
 718{0x1083, 0xC0, 0x1565, 0x2803, 0x1},
 719{0},
 720};
 721
 722static void atl1c_patch_assign(struct atl1c_hw *hw)
 723{
 724	struct pci_dev	*pdev = hw->adapter->pdev;
 725	u32 misc_ctrl;
 726	int i = 0;
 727
 728	hw->msi_lnkpatch = false;
 729
 730	while (plats[i].pci_did != 0) {
 731		if (plats[i].pci_did == hw->device_id &&
 732		    plats[i].pci_revid == hw->revision_id &&
 733		    plats[i].subsystem_vid == hw->subsystem_vendor_id &&
 734		    plats[i].subsystem_did == hw->subsystem_id) {
 735			if (plats[i].patch_flag & ATL1C_LINK_PATCH)
 736				hw->msi_lnkpatch = true;
 737		}
 738		i++;
 739	}
 740
 741	if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
 742	    hw->revision_id == L2CB_V21) {
 743		/* config access mode */
 744		pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
 745				       REG_PCIE_DEV_MISC_CTRL);
 746		pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
 747		misc_ctrl &= ~0x100;
 748		pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
 749				       REG_PCIE_DEV_MISC_CTRL);
 750		pci_write_config_dword(pdev, REG_PCIE_IND_ACC_DATA, misc_ctrl);
 751	}
 752}
 753/**
 754 * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
 755 * @adapter: board private structure to initialize
 756 *
 757 * atl1c_sw_init initializes the Adapter private data structure.
 758 * Fields are initialized based on PCI device information and
 759 * OS network device settings (MTU size).
 760 */
 761static int atl1c_sw_init(struct atl1c_adapter *adapter)
 762{
 763	struct atl1c_hw *hw   = &adapter->hw;
 764	struct pci_dev	*pdev = adapter->pdev;
 765	u32 revision;
 766
 767
 768	adapter->wol = 0;
 769	device_set_wakeup_enable(&pdev->dev, false);
 770	adapter->link_speed = SPEED_0;
 771	adapter->link_duplex = FULL_DUPLEX;
 772	adapter->tpd_ring[0].count = 1024;
 773	adapter->rfd_ring.count = 512;
 774
 775	hw->vendor_id = pdev->vendor;
 776	hw->device_id = pdev->device;
 777	hw->subsystem_vendor_id = pdev->subsystem_vendor;
 778	hw->subsystem_id = pdev->subsystem_device;
 779	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &revision);
 780	hw->revision_id = revision & 0xFF;
 781	/* before link up, we assume hibernate is true */
 782	hw->hibernate = true;
 783	hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
 784	if (atl1c_setup_mac_funcs(hw) != 0) {
 785		dev_err(&pdev->dev, "set mac function pointers failed\n");
 786		return -1;
 787	}
 788	atl1c_patch_assign(hw);
 789
 790	hw->intr_mask = IMR_NORMAL_MASK;
 791	hw->phy_configured = false;
 792	hw->preamble_len = 7;
 793	hw->max_frame_size = adapter->netdev->mtu;
 794	hw->autoneg_advertised = ADVERTISED_Autoneg;
 795	hw->indirect_tab = 0xE4E4E4E4;
 796	hw->base_cpu = 0;
 797
 798	hw->ict = 50000;		/* 100ms */
 799	hw->smb_timer = 200000;	  	/* 400ms */
 800	hw->rx_imt = 200;
 801	hw->tx_imt = 1000;
 802
 803	hw->tpd_burst = 5;
 804	hw->rfd_burst = 8;
 805	hw->dma_order = atl1c_dma_ord_out;
 806	hw->dmar_block = atl1c_dma_req_1024;
 807
 808	if (atl1c_alloc_queues(adapter)) {
 809		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
 810		return -ENOMEM;
 811	}
 812	/* TODO */
 813	atl1c_set_rxbufsize(adapter, adapter->netdev);
 814	atomic_set(&adapter->irq_sem, 1);
 815	spin_lock_init(&adapter->mdio_lock);
 816	set_bit(__AT_DOWN, &adapter->flags);
 817
 818	return 0;
 819}
 820
 821static inline void atl1c_clean_buffer(struct pci_dev *pdev,
 822				struct atl1c_buffer *buffer_info)
 823{
 824	u16 pci_driection;
 825	if (buffer_info->flags & ATL1C_BUFFER_FREE)
 826		return;
 827	if (buffer_info->dma) {
 828		if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
 829			pci_driection = PCI_DMA_FROMDEVICE;
 830		else
 831			pci_driection = PCI_DMA_TODEVICE;
 832
 833		if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
 834			pci_unmap_single(pdev, buffer_info->dma,
 835					buffer_info->length, pci_driection);
 836		else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
 837			pci_unmap_page(pdev, buffer_info->dma,
 838					buffer_info->length, pci_driection);
 839	}
 840	if (buffer_info->skb)
 841		dev_consume_skb_any(buffer_info->skb);
 842	buffer_info->dma = 0;
 843	buffer_info->skb = NULL;
 844	ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
 845}
 846/**
 847 * atl1c_clean_tx_ring - Free Tx-skb
 848 * @adapter: board private structure
 849 */
 850static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
 851				enum atl1c_trans_queue type)
 852{
 853	struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
 854	struct atl1c_buffer *buffer_info;
 855	struct pci_dev *pdev = adapter->pdev;
 856	u16 index, ring_count;
 857
 858	ring_count = tpd_ring->count;
 859	for (index = 0; index < ring_count; index++) {
 860		buffer_info = &tpd_ring->buffer_info[index];
 861		atl1c_clean_buffer(pdev, buffer_info);
 862	}
 863
 864	netdev_reset_queue(adapter->netdev);
 865
 866	/* Zero out Tx-buffers */
 867	memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
 868		ring_count);
 869	atomic_set(&tpd_ring->next_to_clean, 0);
 870	tpd_ring->next_to_use = 0;
 871}
 872
 873/**
 874 * atl1c_clean_rx_ring - Free rx-reservation skbs
 875 * @adapter: board private structure
 876 */
 877static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
 878{
 879	struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
 880	struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
 881	struct atl1c_buffer *buffer_info;
 882	struct pci_dev *pdev = adapter->pdev;
 883	int j;
 884
 885	for (j = 0; j < rfd_ring->count; j++) {
 886		buffer_info = &rfd_ring->buffer_info[j];
 887		atl1c_clean_buffer(pdev, buffer_info);
 888	}
 889	/* zero out the descriptor ring */
 890	memset(rfd_ring->desc, 0, rfd_ring->size);
 891	rfd_ring->next_to_clean = 0;
 892	rfd_ring->next_to_use = 0;
 893	rrd_ring->next_to_use = 0;
 894	rrd_ring->next_to_clean = 0;
 895}
 896
 897/*
 898 * Read / Write Ptr Initialize:
 899 */
 900static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
 901{
 902	struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
 903	struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
 904	struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
 905	struct atl1c_buffer *buffer_info;
 906	int i, j;
 907
 908	for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
 909		tpd_ring[i].next_to_use = 0;
 910		atomic_set(&tpd_ring[i].next_to_clean, 0);
 911		buffer_info = tpd_ring[i].buffer_info;
 912		for (j = 0; j < tpd_ring->count; j++)
 913			ATL1C_SET_BUFFER_STATE(&buffer_info[i],
 914					ATL1C_BUFFER_FREE);
 915	}
 916	rfd_ring->next_to_use = 0;
 917	rfd_ring->next_to_clean = 0;
 918	rrd_ring->next_to_use = 0;
 919	rrd_ring->next_to_clean = 0;
 920	for (j = 0; j < rfd_ring->count; j++) {
 921		buffer_info = &rfd_ring->buffer_info[j];
 922		ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
 923	}
 924}
 925
 926/**
 927 * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
 928 * @adapter: board private structure
 929 *
 930 * Free all transmit software resources
 931 */
 932static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
 933{
 934	struct pci_dev *pdev = adapter->pdev;
 935
 936	pci_free_consistent(pdev, adapter->ring_header.size,
 937					adapter->ring_header.desc,
 938					adapter->ring_header.dma);
 939	adapter->ring_header.desc = NULL;
 940
 941	/* Note: just free tdp_ring.buffer_info,
 942	*  it contain rfd_ring.buffer_info, do not double free */
 943	if (adapter->tpd_ring[0].buffer_info) {
 944		kfree(adapter->tpd_ring[0].buffer_info);
 945		adapter->tpd_ring[0].buffer_info = NULL;
 946	}
 947	if (adapter->rx_page) {
 948		put_page(adapter->rx_page);
 949		adapter->rx_page = NULL;
 950	}
 951}
 952
 953/**
 954 * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
 955 * @adapter: board private structure
 956 *
 957 * Return 0 on success, negative on failure
 958 */
 959static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
 960{
 961	struct pci_dev *pdev = adapter->pdev;
 962	struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
 963	struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
 964	struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
 965	struct atl1c_ring_header *ring_header = &adapter->ring_header;
 966	int size;
 967	int i;
 968	int count = 0;
 969	int rx_desc_count = 0;
 970	u32 offset = 0;
 971
 972	rrd_ring->count = rfd_ring->count;
 973	for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
 974		tpd_ring[i].count = tpd_ring[0].count;
 975
 976	/* 2 tpd queue, one high priority queue,
 977	 * another normal priority queue */
 978	size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
 979		rfd_ring->count);
 980	tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
 981	if (unlikely(!tpd_ring->buffer_info))
 982		goto err_nomem;
 983
 984	for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
 985		tpd_ring[i].buffer_info =
 986			(tpd_ring->buffer_info + count);
 987		count += tpd_ring[i].count;
 988	}
 989
 990	rfd_ring->buffer_info =
 991		(tpd_ring->buffer_info + count);
 992	count += rfd_ring->count;
 993	rx_desc_count += rfd_ring->count;
 994
 995	/*
 996	 * real ring DMA buffer
 997	 * each ring/block may need up to 8 bytes for alignment, hence the
 998	 * additional bytes tacked onto the end.
 999	 */
1000	ring_header->size = size =
1001		sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
1002		sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
1003		sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
1004		8 * 4;
1005
1006	ring_header->desc = dma_alloc_coherent(&pdev->dev, ring_header->size,
1007					       &ring_header->dma, GFP_KERNEL);
1008	if (unlikely(!ring_header->desc)) {
1009		dev_err(&pdev->dev, "could not get memory for DMA buffer\n");
1010		goto err_nomem;
1011	}
1012	/* init TPD ring */
1013
1014	tpd_ring[0].dma = roundup(ring_header->dma, 8);
1015	offset = tpd_ring[0].dma - ring_header->dma;
1016	for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
1017		tpd_ring[i].dma = ring_header->dma + offset;
1018		tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
1019		tpd_ring[i].size =
1020			sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
1021		offset += roundup(tpd_ring[i].size, 8);
1022	}
1023	/* init RFD ring */
1024	rfd_ring->dma = ring_header->dma + offset;
1025	rfd_ring->desc = (u8 *) ring_header->desc + offset;
1026	rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
1027	offset += roundup(rfd_ring->size, 8);
1028
1029	/* init RRD ring */
1030	rrd_ring->dma = ring_header->dma + offset;
1031	rrd_ring->desc = (u8 *) ring_header->desc + offset;
1032	rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
1033		rrd_ring->count;
1034	offset += roundup(rrd_ring->size, 8);
1035
1036	return 0;
1037
1038err_nomem:
1039	kfree(tpd_ring->buffer_info);
1040	return -ENOMEM;
1041}
1042
1043static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
1044{
1045	struct atl1c_hw *hw = &adapter->hw;
1046	struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
1047	struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
1048	struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1049				adapter->tpd_ring;
1050
1051	/* TPD */
1052	AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
1053			(u32)((tpd_ring[atl1c_trans_normal].dma &
1054				AT_DMA_HI_ADDR_MASK) >> 32));
1055	/* just enable normal priority TX queue */
1056	AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
1057			(u32)(tpd_ring[atl1c_trans_normal].dma &
1058				AT_DMA_LO_ADDR_MASK));
1059	AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
1060			(u32)(tpd_ring[atl1c_trans_high].dma &
1061				AT_DMA_LO_ADDR_MASK));
1062	AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
1063			(u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
1064
1065
1066	/* RFD */
1067	AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
1068			(u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
1069	AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
1070			(u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
1071
1072	AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
1073			rfd_ring->count & RFD_RING_SIZE_MASK);
1074	AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
1075			adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
1076
1077	/* RRD */
1078	AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
1079			(u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
1080	AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
1081			(rrd_ring->count & RRD_RING_SIZE_MASK));
1082
1083	if (hw->nic_type == athr_l2c_b) {
1084		AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
1085		AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
1086		AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
1087		AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
1088		AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
1089		AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
1090		AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0);	/* TX watermark, to enter l1 state.*/
1091		AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0);		/* RXD threshold.*/
1092	}
1093	/* Load all of base address above */
1094	AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
1095}
1096
1097static void atl1c_configure_tx(struct atl1c_adapter *adapter)
1098{
1099	struct atl1c_hw *hw = &adapter->hw;
1100	int max_pay_load;
1101	u16 tx_offload_thresh;
1102	u32 txq_ctrl_data;
1103
1104	tx_offload_thresh = MAX_TSO_FRAME_SIZE;
1105	AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
1106		(tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
1107	max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
1108	hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
1109	/*
1110	 * if BIOS had changed the dam-read-max-length to an invalid value,
1111	 * restore it to default value
1112	 */
1113	if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
1114		pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
1115		hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
1116	}
1117	txq_ctrl_data =
1118		hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
1119		L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
1120
1121	AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
1122}
1123
1124static void atl1c_configure_rx(struct atl1c_adapter *adapter)
1125{
1126	struct atl1c_hw *hw = &adapter->hw;
1127	u32 rxq_ctrl_data;
1128
1129	rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
1130			RXQ_RFD_BURST_NUM_SHIFT;
1131
1132	if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
1133		rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
1134
1135	/* aspm for gigabit */
1136	if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
1137		rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
1138			ASPM_THRUPUT_LIMIT_100M);
1139
1140	AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1141}
1142
1143static void atl1c_configure_dma(struct atl1c_adapter *adapter)
1144{
1145	struct atl1c_hw *hw = &adapter->hw;
1146	u32 dma_ctrl_data;
1147
1148	dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
1149		DMA_CTRL_RREQ_PRI_DATA |
1150		FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
1151		FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
1152		FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
1153
1154	AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1155}
1156
1157/*
1158 * Stop the mac, transmit and receive units
1159 * hw - Struct containing variables accessed by shared code
1160 * return : 0  or  idle status (if error)
1161 */
1162static int atl1c_stop_mac(struct atl1c_hw *hw)
1163{
1164	u32 data;
1165
1166	AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1167	data &= ~RXQ_CTRL_EN;
1168	AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1169
1170	AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1171	data &= ~TXQ_CTRL_EN;
1172	AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
1173
1174	atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
1175
1176	AT_READ_REG(hw, REG_MAC_CTRL, &data);
1177	data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
1178	AT_WRITE_REG(hw, REG_MAC_CTRL, data);
1179
1180	return (int)atl1c_wait_until_idle(hw,
1181		IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
1182}
1183
1184static void atl1c_start_mac(struct atl1c_adapter *adapter)
1185{
1186	struct atl1c_hw *hw = &adapter->hw;
1187	u32 mac, txq, rxq;
1188
1189	hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
1190	hw->mac_speed = adapter->link_speed == SPEED_1000 ?
1191		atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
1192
1193	AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
1194	AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
1195	AT_READ_REG(hw, REG_MAC_CTRL, &mac);
1196
1197	txq |= TXQ_CTRL_EN;
1198	rxq |= RXQ_CTRL_EN;
1199	mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
1200	       MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
1201	       MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
1202	       MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
1203	       MAC_CTRL_HASH_ALG_CRC32;
1204	if (hw->mac_duplex)
1205		mac |= MAC_CTRL_DUPLX;
1206	else
1207		mac &= ~MAC_CTRL_DUPLX;
1208	mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
1209	mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
1210
1211	AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
1212	AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
1213	AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
1214}
1215
1216/*
1217 * Reset the transmit and receive units; mask and clear all interrupts.
1218 * hw - Struct containing variables accessed by shared code
1219 * return : 0  or  idle status (if error)
1220 */
1221static int atl1c_reset_mac(struct atl1c_hw *hw)
1222{
1223	struct atl1c_adapter *adapter = hw->adapter;
1224	struct pci_dev *pdev = adapter->pdev;
1225	u32 ctrl_data = 0;
1226
1227	atl1c_stop_mac(hw);
1228	/*
1229	 * Issue Soft Reset to the MAC.  This will reset the chip's
1230	 * transmit, receive, DMA.  It will not effect
1231	 * the current PCI configuration.  The global reset bit is self-
1232	 * clearing, and should clear within a microsecond.
1233	 */
1234	AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
1235	ctrl_data |= MASTER_CTRL_OOB_DIS;
1236	AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
1237
1238	AT_WRITE_FLUSH(hw);
1239	msleep(10);
1240	/* Wait at least 10ms for All module to be Idle */
1241
1242	if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
1243		dev_err(&pdev->dev,
1244			"MAC state machine can't be idle since"
1245			" disabled for 10ms second\n");
1246		return -1;
1247	}
1248	AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
1249
1250	/* driver control speed/duplex */
1251	AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
1252	AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
1253
1254	/* clk switch setting */
1255	AT_READ_REG(hw, REG_SERDES, &ctrl_data);
1256	switch (hw->nic_type) {
1257	case athr_l2c_b:
1258		ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
1259				SERDES_MAC_CLK_SLOWDOWN);
1260		AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
1261		break;
1262	case athr_l2c_b2:
1263	case athr_l1d_2:
1264		ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
1265		AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
1266		break;
1267	default:
1268		break;
1269	}
1270
1271	return 0;
1272}
1273
1274static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
1275{
1276	u16 ctrl_flags = hw->ctrl_flags;
1277
1278	hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
1279	atl1c_set_aspm(hw, SPEED_0);
1280	hw->ctrl_flags = ctrl_flags;
1281}
1282
1283/*
1284 * Set ASPM state.
1285 * Enable/disable L0s/L1 depend on link state.
1286 */
1287static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
1288{
1289	u32 pm_ctrl_data;
1290	u32 link_l1_timer;
1291
1292	AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1293	pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
1294			  PM_CTRL_ASPM_L0S_EN |
1295			  PM_CTRL_MAC_ASPM_CHK);
1296	/* L1 timer */
1297	if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
1298		pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
1299		link_l1_timer =
1300			link_speed == SPEED_1000 || link_speed == SPEED_100 ?
1301			L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
1302		pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
1303			L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
1304	} else {
1305		link_l1_timer = hw->nic_type == athr_l2c_b ?
1306			L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
1307		if (link_speed != SPEED_1000 && link_speed != SPEED_100)
1308			link_l1_timer = 1;
1309		pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
1310			PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
1311	}
1312
1313	/* L0S/L1 enable */
1314	if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
1315		pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
1316	if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1317		pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
1318
1319	/* l2cb & l1d & l2cb2 & l1d2 */
1320	if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1321	    hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
1322		pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
1323			PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
1324		pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
1325				PM_CTRL_SERDES_PD_EX_L1 |
1326				PM_CTRL_CLK_SWH_L1;
1327		pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
1328				  PM_CTRL_SERDES_PLL_L1_EN |
1329				  PM_CTRL_SERDES_BUFS_RX_L1_EN |
1330				  PM_CTRL_SA_DLY_EN |
1331				  PM_CTRL_HOTRST);
1332		/* disable l0s if link down or l2cb */
1333		if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
1334			pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1335	} else { /* l1c */
1336		pm_ctrl_data =
1337			FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
1338		if (link_speed != SPEED_0) {
1339			pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
1340					PM_CTRL_SERDES_PLL_L1_EN |
1341					PM_CTRL_SERDES_BUFS_RX_L1_EN;
1342			pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
1343					  PM_CTRL_CLK_SWH_L1 |
1344					  PM_CTRL_ASPM_L0S_EN |
1345					  PM_CTRL_ASPM_L1_EN);
1346		} else { /* link down */
1347			pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1348			pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
1349					  PM_CTRL_SERDES_PLL_L1_EN |
1350					  PM_CTRL_SERDES_BUFS_RX_L1_EN |
1351					  PM_CTRL_ASPM_L0S_EN);
1352		}
1353	}
1354	AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1355
1356	return;
1357}
1358
1359/**
1360 * atl1c_configure - Configure Transmit&Receive Unit after Reset
1361 * @adapter: board private structure
1362 *
1363 * Configure the Tx /Rx unit of the MAC after a reset.
1364 */
1365static int atl1c_configure_mac(struct atl1c_adapter *adapter)
1366{
1367	struct atl1c_hw *hw = &adapter->hw;
1368	u32 master_ctrl_data = 0;
1369	u32 intr_modrt_data;
1370	u32 data;
1371
1372	AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
1373	master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
1374			      MASTER_CTRL_RX_ITIMER_EN |
1375			      MASTER_CTRL_INT_RDCLR);
1376	/* clear interrupt status */
1377	AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
1378	/*  Clear any WOL status */
1379	AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1380	/* set Interrupt Clear Timer
1381	 * HW will enable self to assert interrupt event to system after
1382	 * waiting x-time for software to notify it accept interrupt.
1383	 */
1384
1385	data = CLK_GATING_EN_ALL;
1386	if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
1387		if (hw->nic_type == athr_l2c_b)
1388			data &= ~CLK_GATING_RXMAC_EN;
1389	} else
1390		data = 0;
1391	AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
1392
1393	AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
1394		hw->ict & INT_RETRIG_TIMER_MASK);
1395
1396	atl1c_configure_des_ring(adapter);
1397
1398	if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
1399		intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
1400					IRQ_MODRT_TX_TIMER_SHIFT;
1401		intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
1402					IRQ_MODRT_RX_TIMER_SHIFT;
1403		AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
1404		master_ctrl_data |=
1405			MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
1406	}
1407
1408	if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
1409		master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
1410
1411	master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
1412	AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
1413
1414	AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
1415		hw->smb_timer & SMB_STAT_TIMER_MASK);
1416
1417	/* set MTU */
1418	AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1419			VLAN_HLEN + ETH_FCS_LEN);
1420
1421	atl1c_configure_tx(adapter);
1422	atl1c_configure_rx(adapter);
1423	atl1c_configure_dma(adapter);
1424
1425	return 0;
1426}
1427
1428static int atl1c_configure(struct atl1c_adapter *adapter)
1429{
1430	struct net_device *netdev = adapter->netdev;
1431	int num;
1432
1433	atl1c_init_ring_ptrs(adapter);
1434	atl1c_set_multi(netdev);
1435	atl1c_restore_vlan(adapter);
1436
1437	num = atl1c_alloc_rx_buffer(adapter);
1438	if (unlikely(num == 0))
1439		return -ENOMEM;
1440
1441	if (atl1c_configure_mac(adapter))
1442		return -EIO;
1443
1444	return 0;
1445}
1446
1447static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
1448{
1449	u16 hw_reg_addr = 0;
1450	unsigned long *stats_item = NULL;
1451	u32 data;
1452
1453	/* update rx status */
1454	hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1455	stats_item  = &adapter->hw_stats.rx_ok;
1456	while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1457		AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1458		*stats_item += data;
1459		stats_item++;
1460		hw_reg_addr += 4;
1461	}
1462/* update tx status */
1463	hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1464	stats_item  = &adapter->hw_stats.tx_ok;
1465	while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1466		AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1467		*stats_item += data;
1468		stats_item++;
1469		hw_reg_addr += 4;
1470	}
1471}
1472
1473/**
1474 * atl1c_get_stats - Get System Network Statistics
1475 * @netdev: network interface device structure
1476 *
1477 * Returns the address of the device statistics structure.
1478 * The statistics are actually updated from the timer callback.
1479 */
1480static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
1481{
1482	struct atl1c_adapter *adapter = netdev_priv(netdev);
1483	struct atl1c_hw_stats  *hw_stats = &adapter->hw_stats;
1484	struct net_device_stats *net_stats = &netdev->stats;
1485
1486	atl1c_update_hw_stats(adapter);
1487	net_stats->rx_bytes   = hw_stats->rx_byte_cnt;
1488	net_stats->tx_bytes   = hw_stats->tx_byte_cnt;
1489	net_stats->multicast  = hw_stats->rx_mcast;
1490	net_stats->collisions = hw_stats->tx_1_col +
1491				hw_stats->tx_2_col +
1492				hw_stats->tx_late_col +
1493				hw_stats->tx_abort_col;
1494
1495	net_stats->rx_errors  = hw_stats->rx_frag +
1496				hw_stats->rx_fcs_err +
1497				hw_stats->rx_len_err +
1498				hw_stats->rx_sz_ov +
1499				hw_stats->rx_rrd_ov +
1500				hw_stats->rx_align_err +
1501				hw_stats->rx_rxf_ov;
1502
1503	net_stats->rx_fifo_errors   = hw_stats->rx_rxf_ov;
1504	net_stats->rx_length_errors = hw_stats->rx_len_err;
1505	net_stats->rx_crc_errors    = hw_stats->rx_fcs_err;
1506	net_stats->rx_frame_errors  = hw_stats->rx_align_err;
1507	net_stats->rx_dropped       = hw_stats->rx_rrd_ov;
1508
1509	net_stats->tx_errors = hw_stats->tx_late_col +
1510			       hw_stats->tx_abort_col +
1511			       hw_stats->tx_underrun +
1512			       hw_stats->tx_trunc;
1513
1514	net_stats->tx_fifo_errors    = hw_stats->tx_underrun;
1515	net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1516	net_stats->tx_window_errors  = hw_stats->tx_late_col;
1517
1518	net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
1519	net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
1520
1521	return net_stats;
1522}
1523
1524static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
1525{
1526	u16 phy_data;
1527
1528	spin_lock(&adapter->mdio_lock);
1529	atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
1530	spin_unlock(&adapter->mdio_lock);
1531}
1532
1533static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
1534				enum atl1c_trans_queue type)
1535{
1536	struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1537	struct atl1c_buffer *buffer_info;
1538	struct pci_dev *pdev = adapter->pdev;
1539	u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1540	u16 hw_next_to_clean;
1541	u16 reg;
1542	unsigned int total_bytes = 0, total_packets = 0;
1543
1544	reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
1545
1546	AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
1547
1548	while (next_to_clean != hw_next_to_clean) {
1549		buffer_info = &tpd_ring->buffer_info[next_to_clean];
1550		if (buffer_info->skb) {
1551			total_bytes += buffer_info->skb->len;
1552			total_packets++;
1553		}
1554		atl1c_clean_buffer(pdev, buffer_info);
1555		if (++next_to_clean == tpd_ring->count)
1556			next_to_clean = 0;
1557		atomic_set(&tpd_ring->next_to_clean, next_to_clean);
1558	}
1559
1560	netdev_completed_queue(adapter->netdev, total_packets, total_bytes);
1561
1562	if (netif_queue_stopped(adapter->netdev) &&
1563			netif_carrier_ok(adapter->netdev)) {
1564		netif_wake_queue(adapter->netdev);
1565	}
1566
1567	return true;
1568}
1569
1570/**
1571 * atl1c_intr - Interrupt Handler
1572 * @irq: interrupt number
1573 * @data: pointer to a network interface device structure
1574 */
1575static irqreturn_t atl1c_intr(int irq, void *data)
1576{
1577	struct net_device *netdev  = data;
1578	struct atl1c_adapter *adapter = netdev_priv(netdev);
1579	struct pci_dev *pdev = adapter->pdev;
1580	struct atl1c_hw *hw = &adapter->hw;
1581	int max_ints = AT_MAX_INT_WORK;
1582	int handled = IRQ_NONE;
1583	u32 status;
1584	u32 reg_data;
1585
1586	do {
1587		AT_READ_REG(hw, REG_ISR, &reg_data);
1588		status = reg_data & hw->intr_mask;
1589
1590		if (status == 0 || (status & ISR_DIS_INT) != 0) {
1591			if (max_ints != AT_MAX_INT_WORK)
1592				handled = IRQ_HANDLED;
1593			break;
1594		}
1595		/* link event */
1596		if (status & ISR_GPHY)
1597			atl1c_clear_phy_int(adapter);
1598		/* Ack ISR */
1599		AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1600		if (status & ISR_RX_PKT) {
1601			if (likely(napi_schedule_prep(&adapter->napi))) {
1602				hw->intr_mask &= ~ISR_RX_PKT;
1603				AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
1604				__napi_schedule(&adapter->napi);
1605			}
1606		}
1607		if (status & ISR_TX_PKT)
1608			atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
1609
1610		handled = IRQ_HANDLED;
1611		/* check if PCIE PHY Link down */
1612		if (status & ISR_ERROR) {
1613			if (netif_msg_hw(adapter))
1614				dev_err(&pdev->dev,
1615					"atl1c hardware error (status = 0x%x)\n",
1616					status & ISR_ERROR);
1617			/* reset MAC */
1618			set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
1619			schedule_work(&adapter->common_task);
1620			return IRQ_HANDLED;
1621		}
1622
1623		if (status & ISR_OVER)
1624			if (netif_msg_intr(adapter))
1625				dev_warn(&pdev->dev,
1626					"TX/RX overflow (status = 0x%x)\n",
1627					status & ISR_OVER);
1628
1629		/* link event */
1630		if (status & (ISR_GPHY | ISR_MANUAL)) {
1631			netdev->stats.tx_carrier_errors++;
1632			atl1c_link_chg_event(adapter);
1633			break;
1634		}
1635
1636	} while (--max_ints > 0);
1637	/* re-enable Interrupt*/
1638	AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1639	return handled;
1640}
1641
1642static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
1643		  struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
1644{
1645	/*
1646	 * The pid field in RRS in not correct sometimes, so we
1647	 * cannot figure out if the packet is fragmented or not,
1648	 * so we tell the KERNEL CHECKSUM_NONE
1649	 */
1650	skb_checksum_none_assert(skb);
1651}
1652
1653static struct sk_buff *atl1c_alloc_skb(struct atl1c_adapter *adapter)
1654{
1655	struct sk_buff *skb;
1656	struct page *page;
1657
1658	if (adapter->rx_frag_size > PAGE_SIZE)
1659		return netdev_alloc_skb(adapter->netdev,
1660					adapter->rx_buffer_len);
1661
1662	page = adapter->rx_page;
1663	if (!page) {
1664		adapter->rx_page = page = alloc_page(GFP_ATOMIC);
1665		if (unlikely(!page))
1666			return NULL;
1667		adapter->rx_page_offset = 0;
1668	}
1669
1670	skb = build_skb(page_address(page) + adapter->rx_page_offset,
1671			adapter->rx_frag_size);
1672	if (likely(skb)) {
1673		skb_reserve(skb, NET_SKB_PAD);
1674		adapter->rx_page_offset += adapter->rx_frag_size;
1675		if (adapter->rx_page_offset >= PAGE_SIZE)
1676			adapter->rx_page = NULL;
1677		else
1678			get_page(page);
1679	}
1680	return skb;
1681}
1682
1683static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
1684{
1685	struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
1686	struct pci_dev *pdev = adapter->pdev;
1687	struct atl1c_buffer *buffer_info, *next_info;
1688	struct sk_buff *skb;
1689	void *vir_addr = NULL;
1690	u16 num_alloc = 0;
1691	u16 rfd_next_to_use, next_next;
1692	struct atl1c_rx_free_desc *rfd_desc;
1693	dma_addr_t mapping;
1694
1695	next_next = rfd_next_to_use = rfd_ring->next_to_use;
1696	if (++next_next == rfd_ring->count)
1697		next_next = 0;
1698	buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1699	next_info = &rfd_ring->buffer_info[next_next];
1700
1701	while (next_info->flags & ATL1C_BUFFER_FREE) {
1702		rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
1703
1704		skb = atl1c_alloc_skb(adapter);
1705		if (unlikely(!skb)) {
1706			if (netif_msg_rx_err(adapter))
1707				dev_warn(&pdev->dev, "alloc rx buffer failed\n");
1708			break;
1709		}
1710
1711		/*
1712		 * Make buffer alignment 2 beyond a 16 byte boundary
1713		 * this will result in a 16 byte aligned IP header after
1714		 * the 14 byte MAC header is removed
1715		 */
1716		vir_addr = skb->data;
1717		ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
1718		buffer_info->skb = skb;
1719		buffer_info->length = adapter->rx_buffer_len;
1720		mapping = pci_map_single(pdev, vir_addr,
1721						buffer_info->length,
1722						PCI_DMA_FROMDEVICE);
1723		if (unlikely(pci_dma_mapping_error(pdev, mapping))) {
1724			dev_kfree_skb(skb);
1725			buffer_info->skb = NULL;
1726			buffer_info->length = 0;
1727			ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
1728			netif_warn(adapter, rx_err, adapter->netdev, "RX pci_map_single failed");
1729			break;
1730		}
1731		buffer_info->dma = mapping;
1732		ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
1733			ATL1C_PCIMAP_FROMDEVICE);
1734		rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1735		rfd_next_to_use = next_next;
1736		if (++next_next == rfd_ring->count)
1737			next_next = 0;
1738		buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1739		next_info = &rfd_ring->buffer_info[next_next];
1740		num_alloc++;
1741	}
1742
1743	if (num_alloc) {
1744		/* TODO: update mailbox here */
1745		wmb();
1746		rfd_ring->next_to_use = rfd_next_to_use;
1747		AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
1748			rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
1749	}
1750
1751	return num_alloc;
1752}
1753
1754static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_rin…

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