/drivers/net/ethernet/broadcom/bnx2.c
C | 8845 lines | 6903 code | 1592 blank | 350 comment | 1327 complexity | 08a381652f80ecee18c3449f12095e97 MD5 | raw file
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1/* bnx2.c: QLogic bnx2 network driver. 2 * 3 * Copyright (c) 2004-2014 Broadcom Corporation 4 * Copyright (c) 2014-2015 QLogic Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * Written by: Michael Chan (mchan@broadcom.com) 11 */ 12 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15#include <linux/module.h> 16#include <linux/moduleparam.h> 17 18#include <linux/stringify.h> 19#include <linux/kernel.h> 20#include <linux/timer.h> 21#include <linux/errno.h> 22#include <linux/ioport.h> 23#include <linux/slab.h> 24#include <linux/vmalloc.h> 25#include <linux/interrupt.h> 26#include <linux/pci.h> 27#include <linux/netdevice.h> 28#include <linux/etherdevice.h> 29#include <linux/skbuff.h> 30#include <linux/dma-mapping.h> 31#include <linux/bitops.h> 32#include <asm/io.h> 33#include <asm/irq.h> 34#include <linux/delay.h> 35#include <asm/byteorder.h> 36#include <asm/page.h> 37#include <linux/time.h> 38#include <linux/ethtool.h> 39#include <linux/mii.h> 40#include <linux/if.h> 41#include <linux/if_vlan.h> 42#include <net/ip.h> 43#include <net/tcp.h> 44#include <net/checksum.h> 45#include <linux/workqueue.h> 46#include <linux/crc32.h> 47#include <linux/prefetch.h> 48#include <linux/cache.h> 49#include <linux/firmware.h> 50#include <linux/log2.h> 51#include <linux/aer.h> 52#include <linux/crash_dump.h> 53 54#if IS_ENABLED(CONFIG_CNIC) 55#define BCM_CNIC 1 56#include "cnic_if.h" 57#endif 58#include "bnx2.h" 59#include "bnx2_fw.h" 60 61#define DRV_MODULE_NAME "bnx2" 62#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw" 63#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw" 64#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw" 65#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw" 66#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw" 67 68#define RUN_AT(x) (jiffies + (x)) 69 70/* Time in jiffies before concluding the transmitter is hung. */ 71#define TX_TIMEOUT (5*HZ) 72 73MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); 74MODULE_DESCRIPTION("QLogic BCM5706/5708/5709/5716 Driver"); 75MODULE_LICENSE("GPL"); 76MODULE_FIRMWARE(FW_MIPS_FILE_06); 77MODULE_FIRMWARE(FW_RV2P_FILE_06); 78MODULE_FIRMWARE(FW_MIPS_FILE_09); 79MODULE_FIRMWARE(FW_RV2P_FILE_09); 80MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax); 81 82static int disable_msi = 0; 83 84module_param(disable_msi, int, 0444); 85MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 86 87typedef enum { 88 BCM5706 = 0, 89 NC370T, 90 NC370I, 91 BCM5706S, 92 NC370F, 93 BCM5708, 94 BCM5708S, 95 BCM5709, 96 BCM5709S, 97 BCM5716, 98 BCM5716S, 99} board_t; 100 101/* indexed by board_t, above */ 102static struct { 103 char *name; 104} board_info[] = { 105 { "Broadcom NetXtreme II BCM5706 1000Base-T" }, 106 { "HP NC370T Multifunction Gigabit Server Adapter" }, 107 { "HP NC370i Multifunction Gigabit Server Adapter" }, 108 { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 109 { "HP NC370F Multifunction Gigabit Server Adapter" }, 110 { "Broadcom NetXtreme II BCM5708 1000Base-T" }, 111 { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 112 { "Broadcom NetXtreme II BCM5709 1000Base-T" }, 113 { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 114 { "Broadcom NetXtreme II BCM5716 1000Base-T" }, 115 { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, 116 }; 117 118static const struct pci_device_id bnx2_pci_tbl[] = { 119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 120 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, 121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 122 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, 123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, 125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, 126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 }, 127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 128 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, 129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, 131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, 132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, 133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, 134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, 135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, 136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, 137 { PCI_VENDOR_ID_BROADCOM, 0x163b, 138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, 139 { PCI_VENDOR_ID_BROADCOM, 0x163c, 140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, 141 { 0, } 142}; 143 144static const struct flash_spec flash_table[] = 145{ 146#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) 147#define NONBUFFERED_FLAGS (BNX2_NV_WREN) 148 /* Slow EEPROM */ 149 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 150 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 151 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 152 "EEPROM - slow"}, 153 /* Expansion entry 0001 */ 154 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 155 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 156 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 157 "Entry 0001"}, 158 /* Saifun SA25F010 (non-buffered flash) */ 159 /* strap, cfg1, & write1 need updates */ 160 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 162 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 163 "Non-buffered flash (128kB)"}, 164 /* Saifun SA25F020 (non-buffered flash) */ 165 /* strap, cfg1, & write1 need updates */ 166 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 167 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 168 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 169 "Non-buffered flash (256kB)"}, 170 /* Expansion entry 0100 */ 171 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 173 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 174 "Entry 0100"}, 175 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 176 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 177 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 178 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 179 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 180 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 181 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 184 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 185 /* Saifun SA25F005 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 190 "Non-buffered flash (64kB)"}, 191 /* Fast EEPROM */ 192 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 193 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 194 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 195 "EEPROM - fast"}, 196 /* Expansion entry 1001 */ 197 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 200 "Entry 1001"}, 201 /* Expansion entry 1010 */ 202 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 205 "Entry 1010"}, 206 /* ATMEL AT45DB011B (buffered flash) */ 207 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 209 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 210 "Buffered flash (128kB)"}, 211 /* Expansion entry 1100 */ 212 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 213 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 214 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 215 "Entry 1100"}, 216 /* Expansion entry 1101 */ 217 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 220 "Entry 1101"}, 221 /* Ateml Expansion entry 1110 */ 222 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 223 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 224 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 225 "Entry 1110 (Atmel)"}, 226 /* ATMEL AT45DB021B (buffered flash) */ 227 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 229 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 230 "Buffered flash (256kB)"}, 231}; 232 233static const struct flash_spec flash_5709 = { 234 .flags = BNX2_NV_BUFFERED, 235 .page_bits = BCM5709_FLASH_PAGE_BITS, 236 .page_size = BCM5709_FLASH_PAGE_SIZE, 237 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 238 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, 239 .name = "5709 Buffered flash (256kB)", 240}; 241 242MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); 243 244static void bnx2_init_napi(struct bnx2 *bp); 245static void bnx2_del_napi(struct bnx2 *bp); 246 247static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) 248{ 249 u32 diff; 250 251 /* The ring uses 256 indices for 255 entries, one of them 252 * needs to be skipped. 253 */ 254 diff = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons); 255 if (unlikely(diff >= BNX2_TX_DESC_CNT)) { 256 diff &= 0xffff; 257 if (diff == BNX2_TX_DESC_CNT) 258 diff = BNX2_MAX_TX_DESC_CNT; 259 } 260 return bp->tx_ring_size - diff; 261} 262 263static u32 264bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) 265{ 266 unsigned long flags; 267 u32 val; 268 269 spin_lock_irqsave(&bp->indirect_lock, flags); 270 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 271 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); 272 spin_unlock_irqrestore(&bp->indirect_lock, flags); 273 return val; 274} 275 276static void 277bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) 278{ 279 unsigned long flags; 280 281 spin_lock_irqsave(&bp->indirect_lock, flags); 282 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 283 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val); 284 spin_unlock_irqrestore(&bp->indirect_lock, flags); 285} 286 287static void 288bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) 289{ 290 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); 291} 292 293static u32 294bnx2_shmem_rd(struct bnx2 *bp, u32 offset) 295{ 296 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); 297} 298 299static void 300bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) 301{ 302 unsigned long flags; 303 304 offset += cid_addr; 305 spin_lock_irqsave(&bp->indirect_lock, flags); 306 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 307 int i; 308 309 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); 310 BNX2_WR(bp, BNX2_CTX_CTX_CTRL, 311 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); 312 for (i = 0; i < 5; i++) { 313 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); 314 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) 315 break; 316 udelay(5); 317 } 318 } else { 319 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset); 320 BNX2_WR(bp, BNX2_CTX_DATA, val); 321 } 322 spin_unlock_irqrestore(&bp->indirect_lock, flags); 323} 324 325#ifdef BCM_CNIC 326static int 327bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) 328{ 329 struct bnx2 *bp = netdev_priv(dev); 330 struct drv_ctl_io *io = &info->data.io; 331 332 switch (info->cmd) { 333 case DRV_CTL_IO_WR_CMD: 334 bnx2_reg_wr_ind(bp, io->offset, io->data); 335 break; 336 case DRV_CTL_IO_RD_CMD: 337 io->data = bnx2_reg_rd_ind(bp, io->offset); 338 break; 339 case DRV_CTL_CTX_WR_CMD: 340 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); 341 break; 342 default: 343 return -EINVAL; 344 } 345 return 0; 346} 347 348static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) 349{ 350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 351 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 352 int sb_id; 353 354 if (bp->flags & BNX2_FLAG_USING_MSIX) { 355 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 356 bnapi->cnic_present = 0; 357 sb_id = bp->irq_nvecs; 358 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 359 } else { 360 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 361 bnapi->cnic_tag = bnapi->last_status_idx; 362 bnapi->cnic_present = 1; 363 sb_id = 0; 364 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 365 } 366 367 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; 368 cp->irq_arr[0].status_blk = (void *) 369 ((unsigned long) bnapi->status_blk.msi + 370 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); 371 cp->irq_arr[0].status_blk_num = sb_id; 372 cp->num_irq = 1; 373} 374 375static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, 376 void *data) 377{ 378 struct bnx2 *bp = netdev_priv(dev); 379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 380 381 if (!ops) 382 return -EINVAL; 383 384 if (cp->drv_state & CNIC_DRV_STATE_REGD) 385 return -EBUSY; 386 387 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN)) 388 return -ENODEV; 389 390 bp->cnic_data = data; 391 rcu_assign_pointer(bp->cnic_ops, ops); 392 393 cp->num_irq = 0; 394 cp->drv_state = CNIC_DRV_STATE_REGD; 395 396 bnx2_setup_cnic_irq_info(bp); 397 398 return 0; 399} 400 401static int bnx2_unregister_cnic(struct net_device *dev) 402{ 403 struct bnx2 *bp = netdev_priv(dev); 404 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 405 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 406 407 mutex_lock(&bp->cnic_lock); 408 cp->drv_state = 0; 409 bnapi->cnic_present = 0; 410 RCU_INIT_POINTER(bp->cnic_ops, NULL); 411 mutex_unlock(&bp->cnic_lock); 412 synchronize_rcu(); 413 return 0; 414} 415 416static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) 417{ 418 struct bnx2 *bp = netdev_priv(dev); 419 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 420 421 if (!cp->max_iscsi_conn) 422 return NULL; 423 424 cp->drv_owner = THIS_MODULE; 425 cp->chip_id = bp->chip_id; 426 cp->pdev = bp->pdev; 427 cp->io_base = bp->regview; 428 cp->drv_ctl = bnx2_drv_ctl; 429 cp->drv_register_cnic = bnx2_register_cnic; 430 cp->drv_unregister_cnic = bnx2_unregister_cnic; 431 432 return cp; 433} 434 435static void 436bnx2_cnic_stop(struct bnx2 *bp) 437{ 438 struct cnic_ops *c_ops; 439 struct cnic_ctl_info info; 440 441 mutex_lock(&bp->cnic_lock); 442 c_ops = rcu_dereference_protected(bp->cnic_ops, 443 lockdep_is_held(&bp->cnic_lock)); 444 if (c_ops) { 445 info.cmd = CNIC_CTL_STOP_CMD; 446 c_ops->cnic_ctl(bp->cnic_data, &info); 447 } 448 mutex_unlock(&bp->cnic_lock); 449} 450 451static void 452bnx2_cnic_start(struct bnx2 *bp) 453{ 454 struct cnic_ops *c_ops; 455 struct cnic_ctl_info info; 456 457 mutex_lock(&bp->cnic_lock); 458 c_ops = rcu_dereference_protected(bp->cnic_ops, 459 lockdep_is_held(&bp->cnic_lock)); 460 if (c_ops) { 461 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { 462 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 463 464 bnapi->cnic_tag = bnapi->last_status_idx; 465 } 466 info.cmd = CNIC_CTL_START_CMD; 467 c_ops->cnic_ctl(bp->cnic_data, &info); 468 } 469 mutex_unlock(&bp->cnic_lock); 470} 471 472#else 473 474static void 475bnx2_cnic_stop(struct bnx2 *bp) 476{ 477} 478 479static void 480bnx2_cnic_start(struct bnx2 *bp) 481{ 482} 483 484#endif 485 486static int 487bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) 488{ 489 u32 val1; 490 int i, ret; 491 492 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 493 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 494 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 495 496 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 497 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 498 499 udelay(40); 500 } 501 502 val1 = (bp->phy_addr << 21) | (reg << 16) | 503 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | 504 BNX2_EMAC_MDIO_COMM_START_BUSY; 505 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 506 507 for (i = 0; i < 50; i++) { 508 udelay(10); 509 510 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 511 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 512 udelay(5); 513 514 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 515 val1 &= BNX2_EMAC_MDIO_COMM_DATA; 516 517 break; 518 } 519 } 520 521 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { 522 *val = 0x0; 523 ret = -EBUSY; 524 } 525 else { 526 *val = val1; 527 ret = 0; 528 } 529 530 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 531 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 532 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 533 534 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 535 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 536 537 udelay(40); 538 } 539 540 return ret; 541} 542 543static int 544bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) 545{ 546 u32 val1; 547 int i, ret; 548 549 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 550 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 551 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 552 553 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 554 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 555 556 udelay(40); 557 } 558 559 val1 = (bp->phy_addr << 21) | (reg << 16) | val | 560 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | 561 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; 562 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 563 564 for (i = 0; i < 50; i++) { 565 udelay(10); 566 567 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 568 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 569 udelay(5); 570 break; 571 } 572 } 573 574 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) 575 ret = -EBUSY; 576 else 577 ret = 0; 578 579 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 580 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 581 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 582 583 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 584 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 585 586 udelay(40); 587 } 588 589 return ret; 590} 591 592static void 593bnx2_disable_int(struct bnx2 *bp) 594{ 595 int i; 596 struct bnx2_napi *bnapi; 597 598 for (i = 0; i < bp->irq_nvecs; i++) { 599 bnapi = &bp->bnx2_napi[i]; 600 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 601 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 602 } 603 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); 604} 605 606static void 607bnx2_enable_int(struct bnx2 *bp) 608{ 609 int i; 610 struct bnx2_napi *bnapi; 611 612 for (i = 0; i < bp->irq_nvecs; i++) { 613 bnapi = &bp->bnx2_napi[i]; 614 615 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 617 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 618 bnapi->last_status_idx); 619 620 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 621 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 622 bnapi->last_status_idx); 623 } 624 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 625} 626 627static void 628bnx2_disable_int_sync(struct bnx2 *bp) 629{ 630 int i; 631 632 atomic_inc(&bp->intr_sem); 633 if (!netif_running(bp->dev)) 634 return; 635 636 bnx2_disable_int(bp); 637 for (i = 0; i < bp->irq_nvecs; i++) 638 synchronize_irq(bp->irq_tbl[i].vector); 639} 640 641static void 642bnx2_napi_disable(struct bnx2 *bp) 643{ 644 int i; 645 646 for (i = 0; i < bp->irq_nvecs; i++) 647 napi_disable(&bp->bnx2_napi[i].napi); 648} 649 650static void 651bnx2_napi_enable(struct bnx2 *bp) 652{ 653 int i; 654 655 for (i = 0; i < bp->irq_nvecs; i++) 656 napi_enable(&bp->bnx2_napi[i].napi); 657} 658 659static void 660bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic) 661{ 662 if (stop_cnic) 663 bnx2_cnic_stop(bp); 664 if (netif_running(bp->dev)) { 665 bnx2_napi_disable(bp); 666 netif_tx_disable(bp->dev); 667 } 668 bnx2_disable_int_sync(bp); 669 netif_carrier_off(bp->dev); /* prevent tx timeout */ 670} 671 672static void 673bnx2_netif_start(struct bnx2 *bp, bool start_cnic) 674{ 675 if (atomic_dec_and_test(&bp->intr_sem)) { 676 if (netif_running(bp->dev)) { 677 netif_tx_wake_all_queues(bp->dev); 678 spin_lock_bh(&bp->phy_lock); 679 if (bp->link_up) 680 netif_carrier_on(bp->dev); 681 spin_unlock_bh(&bp->phy_lock); 682 bnx2_napi_enable(bp); 683 bnx2_enable_int(bp); 684 if (start_cnic) 685 bnx2_cnic_start(bp); 686 } 687 } 688} 689 690static void 691bnx2_free_tx_mem(struct bnx2 *bp) 692{ 693 int i; 694 695 for (i = 0; i < bp->num_tx_rings; i++) { 696 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 697 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 698 699 if (txr->tx_desc_ring) { 700 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 701 txr->tx_desc_ring, 702 txr->tx_desc_mapping); 703 txr->tx_desc_ring = NULL; 704 } 705 kfree(txr->tx_buf_ring); 706 txr->tx_buf_ring = NULL; 707 } 708} 709 710static void 711bnx2_free_rx_mem(struct bnx2 *bp) 712{ 713 int i; 714 715 for (i = 0; i < bp->num_rx_rings; i++) { 716 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 717 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 718 int j; 719 720 for (j = 0; j < bp->rx_max_ring; j++) { 721 if (rxr->rx_desc_ring[j]) 722 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 723 rxr->rx_desc_ring[j], 724 rxr->rx_desc_mapping[j]); 725 rxr->rx_desc_ring[j] = NULL; 726 } 727 vfree(rxr->rx_buf_ring); 728 rxr->rx_buf_ring = NULL; 729 730 for (j = 0; j < bp->rx_max_pg_ring; j++) { 731 if (rxr->rx_pg_desc_ring[j]) 732 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 733 rxr->rx_pg_desc_ring[j], 734 rxr->rx_pg_desc_mapping[j]); 735 rxr->rx_pg_desc_ring[j] = NULL; 736 } 737 vfree(rxr->rx_pg_ring); 738 rxr->rx_pg_ring = NULL; 739 } 740} 741 742static int 743bnx2_alloc_tx_mem(struct bnx2 *bp) 744{ 745 int i; 746 747 for (i = 0; i < bp->num_tx_rings; i++) { 748 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 749 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 750 751 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); 752 if (!txr->tx_buf_ring) 753 return -ENOMEM; 754 755 txr->tx_desc_ring = 756 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 757 &txr->tx_desc_mapping, GFP_KERNEL); 758 if (!txr->tx_desc_ring) 759 return -ENOMEM; 760 } 761 return 0; 762} 763 764static int 765bnx2_alloc_rx_mem(struct bnx2 *bp) 766{ 767 int i; 768 769 for (i = 0; i < bp->num_rx_rings; i++) { 770 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 771 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 772 int j; 773 774 rxr->rx_buf_ring = 775 vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring)); 776 if (!rxr->rx_buf_ring) 777 return -ENOMEM; 778 779 for (j = 0; j < bp->rx_max_ring; j++) { 780 rxr->rx_desc_ring[j] = 781 dma_alloc_coherent(&bp->pdev->dev, 782 RXBD_RING_SIZE, 783 &rxr->rx_desc_mapping[j], 784 GFP_KERNEL); 785 if (!rxr->rx_desc_ring[j]) 786 return -ENOMEM; 787 788 } 789 790 if (bp->rx_pg_ring_size) { 791 rxr->rx_pg_ring = 792 vzalloc(array_size(SW_RXPG_RING_SIZE, 793 bp->rx_max_pg_ring)); 794 if (!rxr->rx_pg_ring) 795 return -ENOMEM; 796 797 } 798 799 for (j = 0; j < bp->rx_max_pg_ring; j++) { 800 rxr->rx_pg_desc_ring[j] = 801 dma_alloc_coherent(&bp->pdev->dev, 802 RXBD_RING_SIZE, 803 &rxr->rx_pg_desc_mapping[j], 804 GFP_KERNEL); 805 if (!rxr->rx_pg_desc_ring[j]) 806 return -ENOMEM; 807 808 } 809 } 810 return 0; 811} 812 813static void 814bnx2_free_stats_blk(struct net_device *dev) 815{ 816 struct bnx2 *bp = netdev_priv(dev); 817 818 if (bp->status_blk) { 819 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, 820 bp->status_blk, 821 bp->status_blk_mapping); 822 bp->status_blk = NULL; 823 bp->stats_blk = NULL; 824 } 825} 826 827static int 828bnx2_alloc_stats_blk(struct net_device *dev) 829{ 830 int status_blk_size; 831 void *status_blk; 832 struct bnx2 *bp = netdev_priv(dev); 833 834 /* Combine status and statistics blocks into one allocation. */ 835 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); 836 if (bp->flags & BNX2_FLAG_MSIX_CAP) 837 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * 838 BNX2_SBLK_MSIX_ALIGN_SIZE); 839 bp->status_stats_size = status_blk_size + 840 sizeof(struct statistics_block); 841 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, 842 &bp->status_blk_mapping, GFP_KERNEL); 843 if (!status_blk) 844 return -ENOMEM; 845 846 bp->status_blk = status_blk; 847 bp->stats_blk = status_blk + status_blk_size; 848 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; 849 850 return 0; 851} 852 853static void 854bnx2_free_mem(struct bnx2 *bp) 855{ 856 int i; 857 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 858 859 bnx2_free_tx_mem(bp); 860 bnx2_free_rx_mem(bp); 861 862 for (i = 0; i < bp->ctx_pages; i++) { 863 if (bp->ctx_blk[i]) { 864 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, 865 bp->ctx_blk[i], 866 bp->ctx_blk_mapping[i]); 867 bp->ctx_blk[i] = NULL; 868 } 869 } 870 871 if (bnapi->status_blk.msi) 872 bnapi->status_blk.msi = NULL; 873} 874 875static int 876bnx2_alloc_mem(struct bnx2 *bp) 877{ 878 int i, err; 879 struct bnx2_napi *bnapi; 880 881 bnapi = &bp->bnx2_napi[0]; 882 bnapi->status_blk.msi = bp->status_blk; 883 bnapi->hw_tx_cons_ptr = 884 &bnapi->status_blk.msi->status_tx_quick_consumer_index0; 885 bnapi->hw_rx_cons_ptr = 886 &bnapi->status_blk.msi->status_rx_quick_consumer_index0; 887 if (bp->flags & BNX2_FLAG_MSIX_CAP) { 888 for (i = 1; i < bp->irq_nvecs; i++) { 889 struct status_block_msix *sblk; 890 891 bnapi = &bp->bnx2_napi[i]; 892 893 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i); 894 bnapi->status_blk.msix = sblk; 895 bnapi->hw_tx_cons_ptr = 896 &sblk->status_tx_quick_consumer_index; 897 bnapi->hw_rx_cons_ptr = 898 &sblk->status_rx_quick_consumer_index; 899 bnapi->int_num = i << 24; 900 } 901 } 902 903 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 904 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; 905 if (bp->ctx_pages == 0) 906 bp->ctx_pages = 1; 907 for (i = 0; i < bp->ctx_pages; i++) { 908 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, 909 BNX2_PAGE_SIZE, 910 &bp->ctx_blk_mapping[i], 911 GFP_KERNEL); 912 if (!bp->ctx_blk[i]) 913 goto alloc_mem_err; 914 } 915 } 916 917 err = bnx2_alloc_rx_mem(bp); 918 if (err) 919 goto alloc_mem_err; 920 921 err = bnx2_alloc_tx_mem(bp); 922 if (err) 923 goto alloc_mem_err; 924 925 return 0; 926 927alloc_mem_err: 928 bnx2_free_mem(bp); 929 return -ENOMEM; 930} 931 932static void 933bnx2_report_fw_link(struct bnx2 *bp) 934{ 935 u32 fw_link_status = 0; 936 937 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 938 return; 939 940 if (bp->link_up) { 941 u32 bmsr; 942 943 switch (bp->line_speed) { 944 case SPEED_10: 945 if (bp->duplex == DUPLEX_HALF) 946 fw_link_status = BNX2_LINK_STATUS_10HALF; 947 else 948 fw_link_status = BNX2_LINK_STATUS_10FULL; 949 break; 950 case SPEED_100: 951 if (bp->duplex == DUPLEX_HALF) 952 fw_link_status = BNX2_LINK_STATUS_100HALF; 953 else 954 fw_link_status = BNX2_LINK_STATUS_100FULL; 955 break; 956 case SPEED_1000: 957 if (bp->duplex == DUPLEX_HALF) 958 fw_link_status = BNX2_LINK_STATUS_1000HALF; 959 else 960 fw_link_status = BNX2_LINK_STATUS_1000FULL; 961 break; 962 case SPEED_2500: 963 if (bp->duplex == DUPLEX_HALF) 964 fw_link_status = BNX2_LINK_STATUS_2500HALF; 965 else 966 fw_link_status = BNX2_LINK_STATUS_2500FULL; 967 break; 968 } 969 970 fw_link_status |= BNX2_LINK_STATUS_LINK_UP; 971 972 if (bp->autoneg) { 973 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; 974 975 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 976 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 977 978 if (!(bmsr & BMSR_ANEGCOMPLETE) || 979 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) 980 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; 981 else 982 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; 983 } 984 } 985 else 986 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; 987 988 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); 989} 990 991static char * 992bnx2_xceiver_str(struct bnx2 *bp) 993{ 994 return (bp->phy_port == PORT_FIBRE) ? "SerDes" : 995 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : 996 "Copper"); 997} 998 999static void 1000bnx2_report_link(struct bnx2 *bp) 1001{ 1002 if (bp->link_up) { 1003 netif_carrier_on(bp->dev); 1004 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", 1005 bnx2_xceiver_str(bp), 1006 bp->line_speed, 1007 bp->duplex == DUPLEX_FULL ? "full" : "half"); 1008 1009 if (bp->flow_ctrl) { 1010 if (bp->flow_ctrl & FLOW_CTRL_RX) { 1011 pr_cont(", receive "); 1012 if (bp->flow_ctrl & FLOW_CTRL_TX) 1013 pr_cont("& transmit "); 1014 } 1015 else { 1016 pr_cont(", transmit "); 1017 } 1018 pr_cont("flow control ON"); 1019 } 1020 pr_cont("\n"); 1021 } else { 1022 netif_carrier_off(bp->dev); 1023 netdev_err(bp->dev, "NIC %s Link is Down\n", 1024 bnx2_xceiver_str(bp)); 1025 } 1026 1027 bnx2_report_fw_link(bp); 1028} 1029 1030static void 1031bnx2_resolve_flow_ctrl(struct bnx2 *bp) 1032{ 1033 u32 local_adv, remote_adv; 1034 1035 bp->flow_ctrl = 0; 1036 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 1037 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { 1038 1039 if (bp->duplex == DUPLEX_FULL) { 1040 bp->flow_ctrl = bp->req_flow_ctrl; 1041 } 1042 return; 1043 } 1044 1045 if (bp->duplex != DUPLEX_FULL) { 1046 return; 1047 } 1048 1049 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1050 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { 1051 u32 val; 1052 1053 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1054 if (val & BCM5708S_1000X_STAT1_TX_PAUSE) 1055 bp->flow_ctrl |= FLOW_CTRL_TX; 1056 if (val & BCM5708S_1000X_STAT1_RX_PAUSE) 1057 bp->flow_ctrl |= FLOW_CTRL_RX; 1058 return; 1059 } 1060 1061 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1062 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1063 1064 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1065 u32 new_local_adv = 0; 1066 u32 new_remote_adv = 0; 1067 1068 if (local_adv & ADVERTISE_1000XPAUSE) 1069 new_local_adv |= ADVERTISE_PAUSE_CAP; 1070 if (local_adv & ADVERTISE_1000XPSE_ASYM) 1071 new_local_adv |= ADVERTISE_PAUSE_ASYM; 1072 if (remote_adv & ADVERTISE_1000XPAUSE) 1073 new_remote_adv |= ADVERTISE_PAUSE_CAP; 1074 if (remote_adv & ADVERTISE_1000XPSE_ASYM) 1075 new_remote_adv |= ADVERTISE_PAUSE_ASYM; 1076 1077 local_adv = new_local_adv; 1078 remote_adv = new_remote_adv; 1079 } 1080 1081 /* See Table 28B-3 of 802.3ab-1999 spec. */ 1082 if (local_adv & ADVERTISE_PAUSE_CAP) { 1083 if(local_adv & ADVERTISE_PAUSE_ASYM) { 1084 if (remote_adv & ADVERTISE_PAUSE_CAP) { 1085 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1086 } 1087 else if (remote_adv & ADVERTISE_PAUSE_ASYM) { 1088 bp->flow_ctrl = FLOW_CTRL_RX; 1089 } 1090 } 1091 else { 1092 if (remote_adv & ADVERTISE_PAUSE_CAP) { 1093 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1094 } 1095 } 1096 } 1097 else if (local_adv & ADVERTISE_PAUSE_ASYM) { 1098 if ((remote_adv & ADVERTISE_PAUSE_CAP) && 1099 (remote_adv & ADVERTISE_PAUSE_ASYM)) { 1100 1101 bp->flow_ctrl = FLOW_CTRL_TX; 1102 } 1103 } 1104} 1105 1106static int 1107bnx2_5709s_linkup(struct bnx2 *bp) 1108{ 1109 u32 val, speed; 1110 1111 bp->link_up = 1; 1112 1113 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); 1114 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); 1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1116 1117 if ((bp->autoneg & AUTONEG_SPEED) == 0) { 1118 bp->line_speed = bp->req_line_speed; 1119 bp->duplex = bp->req_duplex; 1120 return 0; 1121 } 1122 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; 1123 switch (speed) { 1124 case MII_BNX2_GP_TOP_AN_SPEED_10: 1125 bp->line_speed = SPEED_10; 1126 break; 1127 case MII_BNX2_GP_TOP_AN_SPEED_100: 1128 bp->line_speed = SPEED_100; 1129 break; 1130 case MII_BNX2_GP_TOP_AN_SPEED_1G: 1131 case MII_BNX2_GP_TOP_AN_SPEED_1GKV: 1132 bp->line_speed = SPEED_1000; 1133 break; 1134 case MII_BNX2_GP_TOP_AN_SPEED_2_5G: 1135 bp->line_speed = SPEED_2500; 1136 break; 1137 } 1138 if (val & MII_BNX2_GP_TOP_AN_FD) 1139 bp->duplex = DUPLEX_FULL; 1140 else 1141 bp->duplex = DUPLEX_HALF; 1142 return 0; 1143} 1144 1145static int 1146bnx2_5708s_linkup(struct bnx2 *bp) 1147{ 1148 u32 val; 1149 1150 bp->link_up = 1; 1151 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1152 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { 1153 case BCM5708S_1000X_STAT1_SPEED_10: 1154 bp->line_speed = SPEED_10; 1155 break; 1156 case BCM5708S_1000X_STAT1_SPEED_100: 1157 bp->line_speed = SPEED_100; 1158 break; 1159 case BCM5708S_1000X_STAT1_SPEED_1G: 1160 bp->line_speed = SPEED_1000; 1161 break; 1162 case BCM5708S_1000X_STAT1_SPEED_2G5: 1163 bp->line_speed = SPEED_2500; 1164 break; 1165 } 1166 if (val & BCM5708S_1000X_STAT1_FD) 1167 bp->duplex = DUPLEX_FULL; 1168 else 1169 bp->duplex = DUPLEX_HALF; 1170 1171 return 0; 1172} 1173 1174static int 1175bnx2_5706s_linkup(struct bnx2 *bp) 1176{ 1177 u32 bmcr, local_adv, remote_adv, common; 1178 1179 bp->link_up = 1; 1180 bp->line_speed = SPEED_1000; 1181 1182 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1183 if (bmcr & BMCR_FULLDPLX) { 1184 bp->duplex = DUPLEX_FULL; 1185 } 1186 else { 1187 bp->duplex = DUPLEX_HALF; 1188 } 1189 1190 if (!(bmcr & BMCR_ANENABLE)) { 1191 return 0; 1192 } 1193 1194 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1195 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1196 1197 common = local_adv & remote_adv; 1198 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { 1199 1200 if (common & ADVERTISE_1000XFULL) { 1201 bp->duplex = DUPLEX_FULL; 1202 } 1203 else { 1204 bp->duplex = DUPLEX_HALF; 1205 } 1206 } 1207 1208 return 0; 1209} 1210 1211static int 1212bnx2_copper_linkup(struct bnx2 *bp) 1213{ 1214 u32 bmcr; 1215 1216 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX; 1217 1218 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1219 if (bmcr & BMCR_ANENABLE) { 1220 u32 local_adv, remote_adv, common; 1221 1222 bnx2_read_phy(bp, MII_CTRL1000, &local_adv); 1223 bnx2_read_phy(bp, MII_STAT1000, &remote_adv); 1224 1225 common = local_adv & (remote_adv >> 2); 1226 if (common & ADVERTISE_1000FULL) { 1227 bp->line_speed = SPEED_1000; 1228 bp->duplex = DUPLEX_FULL; 1229 } 1230 else if (common & ADVERTISE_1000HALF) { 1231 bp->line_speed = SPEED_1000; 1232 bp->duplex = DUPLEX_HALF; 1233 } 1234 else { 1235 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1236 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1237 1238 common = local_adv & remote_adv; 1239 if (common & ADVERTISE_100FULL) { 1240 bp->line_speed = SPEED_100; 1241 bp->duplex = DUPLEX_FULL; 1242 } 1243 else if (common & ADVERTISE_100HALF) { 1244 bp->line_speed = SPEED_100; 1245 bp->duplex = DUPLEX_HALF; 1246 } 1247 else if (common & ADVERTISE_10FULL) { 1248 bp->line_speed = SPEED_10; 1249 bp->duplex = DUPLEX_FULL; 1250 } 1251 else if (common & ADVERTISE_10HALF) { 1252 bp->line_speed = SPEED_10; 1253 bp->duplex = DUPLEX_HALF; 1254 } 1255 else { 1256 bp->line_speed = 0; 1257 bp->link_up = 0; 1258 } 1259 } 1260 } 1261 else { 1262 if (bmcr & BMCR_SPEED100) { 1263 bp->line_speed = SPEED_100; 1264 } 1265 else { 1266 bp->line_speed = SPEED_10; 1267 } 1268 if (bmcr & BMCR_FULLDPLX) { 1269 bp->duplex = DUPLEX_FULL; 1270 } 1271 else { 1272 bp->duplex = DUPLEX_HALF; 1273 } 1274 } 1275 1276 if (bp->link_up) { 1277 u32 ext_status; 1278 1279 bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status); 1280 if (ext_status & EXT_STATUS_MDIX) 1281 bp->phy_flags |= BNX2_PHY_FLAG_MDIX; 1282 } 1283 1284 return 0; 1285} 1286 1287static void 1288bnx2_init_rx_context(struct bnx2 *bp, u32 cid) 1289{ 1290 u32 val, rx_cid_addr = GET_CID_ADDR(cid); 1291 1292 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 1293 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; 1294 val |= 0x02 << 8; 1295 1296 if (bp->flow_ctrl & FLOW_CTRL_TX) 1297 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE; 1298 1299 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); 1300} 1301 1302static void 1303bnx2_init_all_rx_contexts(struct bnx2 *bp) 1304{ 1305 int i; 1306 u32 cid; 1307 1308 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { 1309 if (i == 1) 1310 cid = RX_RSS_CID; 1311 bnx2_init_rx_context(bp, cid); 1312 } 1313} 1314 1315static void 1316bnx2_set_mac_link(struct bnx2 *bp) 1317{ 1318 u32 val; 1319 1320 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); 1321 if (bp->link_up && (bp->line_speed == SPEED_1000) && 1322 (bp->duplex == DUPLEX_HALF)) { 1323 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); 1324 } 1325 1326 /* Configure the EMAC mode register. */ 1327 val = BNX2_RD(bp, BNX2_EMAC_MODE); 1328 1329 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 1330 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 1331 BNX2_EMAC_MODE_25G_MODE); 1332 1333 if (bp->link_up) { 1334 switch (bp->line_speed) { 1335 case SPEED_10: 1336 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) { 1337 val |= BNX2_EMAC_MODE_PORT_MII_10M; 1338 break; 1339 } 1340 /* fall through */ 1341 case SPEED_100: 1342 val |= BNX2_EMAC_MODE_PORT_MII; 1343 break; 1344 case SPEED_2500: 1345 val |= BNX2_EMAC_MODE_25G_MODE; 1346 /* fall through */ 1347 case SPEED_1000: 1348 val |= BNX2_EMAC_MODE_PORT_GMII; 1349 break; 1350 } 1351 } 1352 else { 1353 val |= BNX2_EMAC_MODE_PORT_GMII; 1354 } 1355 1356 /* Set the MAC to operate in the appropriate duplex mode. */ 1357 if (bp->duplex == DUPLEX_HALF) 1358 val |= BNX2_EMAC_MODE_HALF_DUPLEX; 1359 BNX2_WR(bp, BNX2_EMAC_MODE, val); 1360 1361 /* Enable/disable rx PAUSE. */ 1362 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; 1363 1364 if (bp->flow_ctrl & FLOW_CTRL_RX) 1365 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; 1366 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); 1367 1368 /* Enable/disable tx PAUSE. */ 1369 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); 1370 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; 1371 1372 if (bp->flow_ctrl & FLOW_CTRL_TX) 1373 val |= BNX2_EMAC_TX_MODE_FLOW_EN; 1374 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val); 1375 1376 /* Acknowledge the interrupt. */ 1377 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); 1378 1379 bnx2_init_all_rx_contexts(bp); 1380} 1381 1382static void 1383bnx2_enable_bmsr1(struct bnx2 *bp) 1384{ 1385 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1386 (BNX2_CHIP(bp) == BNX2_CHIP_5709)) 1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1388 MII_BNX2_BLK_ADDR_GP_STATUS); 1389} 1390 1391static void 1392bnx2_disable_bmsr1(struct bnx2 *bp) 1393{ 1394 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1395 (BNX2_CHIP(bp) == BNX2_CHIP_5709)) 1396 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1397 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1398} 1399 1400static int 1401bnx2_test_and_enable_2g5(struct bnx2 *bp) 1402{ 1403 u32 up1; 1404 int ret = 1; 1405 1406 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1407 return 0; 1408 1409 if (bp->autoneg & AUTONEG_SPEED) 1410 bp->advertising |= ADVERTISED_2500baseX_Full; 1411 1412 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1413 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1414 1415 bnx2_read_phy(bp, bp->mii_up1, &up1); 1416 if (!(up1 & BCM5708S_UP1_2G5)) { 1417 up1 |= BCM5708S_UP1_2G5; 1418 bnx2_write_phy(bp, bp->mii_up1, up1); 1419 ret = 0; 1420 } 1421 1422 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1423 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1424 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1425 1426 return ret; 1427} 1428 1429static int 1430bnx2_test_and_disable_2g5(struct bnx2 *bp) 1431{ 1432 u32 up1; 1433 int ret = 0; 1434 1435 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1436 return 0; 1437 1438 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1439 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1440 1441 bnx2_read_phy(bp, bp->mii_up1, &up1); 1442 if (up1 & BCM5708S_UP1_2G5) { 1443 up1 &= ~BCM5708S_UP1_2G5; 1444 bnx2_write_phy(bp, bp->mii_up1, up1); 1445 ret = 1; 1446 } 1447 1448 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1449 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1450 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1451 1452 return ret; 1453} 1454 1455static void 1456bnx2_enable_forced_2g5(struct bnx2 *bp) 1457{ 1458 u32 uninitialized_var(bmcr); 1459 int err; 1460 1461 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1462 return; 1463 1464 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1465 u32 val; 1466 1467 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1468 MII_BNX2_BLK_ADDR_SERDES_DIG); 1469 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1470 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; 1471 val |= MII_BNX2_SD_MISC1_FORCE | 1472 MII_BNX2_SD_MISC1_FORCE_2_5G; 1473 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1474 } 1475 1476 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1477 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1478 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1479 1480 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1481 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1482 if (!err) 1483 bmcr |= BCM5708S_BMCR_FORCE_2500; 1484 } else { 1485 return; 1486 } 1487 1488 if (err) 1489 return; 1490 1491 if (bp->autoneg & AUTONEG_SPEED) { 1492 bmcr &= ~BMCR_ANENABLE; 1493 if (bp->req_duplex == DUPLEX_FULL) 1494 bmcr |= BMCR_FULLDPLX; 1495 } 1496 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1497} 1498 1499static void 1500bnx2_disable_forced_2g5(struct bnx2 *bp) 1501{ 1502 u32 uninitialized_var(bmcr); 1503 int err; 1504 1505 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1506 return; 1507 1508 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1509 u32 val; 1510 1511 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1512 MII_BNX2_BLK_ADDR_SERDES_DIG); 1513 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1514 val &= ~MII_BNX2_SD_MISC1_FORCE; 1515 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1516 } 1517 1518 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1519 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1520 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1521 1522 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1523 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1524 if (!err) 1525 bmcr &= ~BCM5708S_BMCR_FORCE_2500; 1526 } else { 1527 return; 1528 } 1529 1530 if (err) 1531 return; 1532 1533 if (bp->autoneg & AUTONEG_SPEED) 1534 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; 1535 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1536} 1537 1538static void 1539bnx2_5706s_force_link_dn(struct bnx2 *bp, int start) 1540{ 1541 u32 val; 1542 1543 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); 1544 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); 1545 if (start) 1546 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); 1547 else 1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); 1549} 1550 1551static int 1552bnx2_set_link(struct bnx2 *bp) 1553{ 1554 u32 bmsr; 1555 u8 link_up; 1556 1557 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { 1558 bp->link_up = 1; 1559 return 0; 1560 } 1561 1562 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1563 return 0; 1564 1565 link_up = bp->link_up; 1566 1567 bnx2_enable_bmsr1(bp); 1568 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1569 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1570 bnx2_disable_bmsr1(bp); 1571 1572 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1573 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) { 1574 u32 val, an_dbg; 1575 1576 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { 1577 bnx2_5706s_force_link_dn(bp, 0); 1578 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; 1579 } 1580 val = BNX2_RD(bp, BNX2_EMAC_STATUS); 1581 1582 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 1583 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1584 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1585 1586 if ((val & BNX2_EMAC_STATUS_LINK) && 1587 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) 1588 bmsr |= BMSR_LSTATUS; 1589 else 1590 bmsr &= ~BMSR_LSTATUS; 1591 } 1592 1593 if (bmsr & BMSR_LSTATUS) { 1594 bp->link_up = 1; 1595 1596 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1597 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 1598 bnx2_5706s_linkup(bp); 1599 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) 1600 bnx2_5708s_linkup(bp); 1601 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1602 bnx2_5709s_linkup(bp); 1603 } 1604 else { 1605 bnx2_copper_linkup(bp); 1606 } 1607 bnx2_resolve_flow_ctrl(bp); 1608 } 1609 else { 1610 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1611 (bp->autoneg & AUTONEG_SPEED)) 1612 bnx2_disable_forced_2g5(bp); 1613 1614 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { 1615 u32 bmcr; 1616 1617 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1618 bmcr |= BMCR_ANENABLE; 1619 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1620 1621 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 1622 } 1623 bp->link_up = 0; 1624 } 1625 1626 if (bp->link_up != link_up) { 1627 bnx2_report_link(bp); 1628 } 1629 1630 bnx2_set_mac_link(bp); 1631 1632 return 0; 1633} 1634 1635static int 1636bnx2_reset_phy(struct bnx2 *bp) 1637{ 1638 int i; 1639 u32 reg; 1640 1641 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); 1642 1643#define PHY_RESET_MAX_WAIT 100 1644 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { 1645 udelay(10); 1646 1647 bnx2_read_phy(bp, bp->mii_bmcr, ®); 1648 if (!(reg & BMCR_RESET)) { 1649 udelay(20); 1650 break; 1651 } 1652 } 1653 if (i == PHY_RESET_MAX_WAIT) { 1654 return -EBUSY; 1655 } 1656 return 0; 1657} 1658 1659static u32 1660bnx2_phy_get_pause_adv(struct bnx2 *bp) 1661{ 1662 u32 adv = 0; 1663 1664 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == 1665 (FLOW_CTRL_RX | FLOW_CTRL_TX)) { 1666 1667 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1668 adv = ADVERTISE_1000XPAUSE; 1669 } 1670 else { 1671 adv = ADVERTISE_PAUSE_CAP; 1672 } 1673 } 1674 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { 1675 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1676 adv = ADVERTISE_1000XPSE_ASYM; 1677 } 1678 else { 1679 adv = ADVERTISE_PAUSE_ASYM; 1680 } 1681 } 1682 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { 1683 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1684 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; 1685 } 1686 else { 1687 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1688 } 1689 } 1690 return adv; 1691} 1692 1693static int bnx2_fw_sync(struct bnx2 *, u32, int, int); 1694 1695static int 1696bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) 1697__releases(&bp->phy_lock) 1698__acquires(&bp->phy_lock) 1699{ 1700 u32 speed_arg = 0, pause_adv; 1701 1702 pause_adv = bnx2_phy_get_pause_adv(bp); 1703 1704 if (bp->autoneg & AUTONEG_SPEED) { 1705 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; 1706 if (bp->advertising & ADVERTISED_10baseT_Half) 1707 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1708 if (bp->advertising & ADVERTISED_10baseT_Full) 1709 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1710 if (bp->advertising & ADVERTISED_100baseT_Half) 1711 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1712 if (bp->advertising & ADVERTISED_100baseT_Full) 1713 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1714 if (bp->advertising & ADVERTISED_1000baseT_Full) 1715 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1716 if (bp->advertising & ADVERTISED_2500baseX_Full) 1717 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1718 } else { 1719 if (bp->req_line_speed == SPEED_2500) 1720 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1721 else if (bp->req_line_speed == SPEED_1000) 1722 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1723 else if (bp->req_line_speed == SPEED_100) { 1724 if (bp->req_duplex == DUPLEX_FULL) 1725 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1726 else 1727 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1728 } else if (bp->req_line_speed == SPEED_10) { 1729 if (bp->req_duplex == DUPLEX_FULL) 1730 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1731 else 1732 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1733 } 1734 } 1735 1736 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) 1737 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; 1738 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) 1739 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; 1740 1741 if (port == PORT_TP) 1742 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | 1743 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; 1744 1745 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); 1746 1747 spin_unlock_bh(&bp->phy_lock); 1748 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); 1749 spin_lock_bh(&bp->phy_lock); 1750 1751 return 0; 1752} 1753 1754static int 1755bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) 1756__releases(&bp->phy_lock) 1757__acquires(&bp->phy_lock) 1758{ 1759 u32 adv, bmcr; 1760 u32 new_adv = 0; 1761 1762 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1763 return bnx2_setup_remote_phy(bp, port); 1764 1765 if (!(bp->autoneg & AUTONEG_SPEED)) { 1766 u32 new_bmcr; 1767 int force_link_down = 0; 1768 1769 if (bp->req_line_speed == SPEED_2500) { 1770 if (!bnx2_test_and_enable_2g5(bp)) 1771 force_link_down = 1; 1772 } else if (bp->req_line_speed == SPEED_1000) { 1773 if (bnx2_test_and_disable_2g5(bp)) 1774 force_link_down = 1; 1775 } 1776 bnx2_read_phy(bp, bp->mii_adv, &adv); 1777 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); 1778 1779 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1780 new_bmcr = bmcr & ~BMCR_ANENABLE; 1781 new_bmcr |= BMCR_SPEED1000; 1782 1783 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1784 if (bp->req_line_speed == SPEED_2500) 1785 bnx2_enable_forced_2g5(bp); 1786 else if (bp->req_line_speed == SPEED_1000) { 1787 bnx2_disable_forced_2g5(bp); 1788 new_bmcr &= ~0x2000; 1789 } 1790 1791 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1792 if (bp->req_line_speed == SPEED_2500) 1793 new_bmcr |= BCM5708S_BMCR_FORCE_2500; 1794 else 1795 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; 1796 } 1797 1798 if (bp->req_duplex == DUPLEX_FULL) { 1799 adv |= ADVERTISE_1000XFULL; 1800 new_bmcr |= BMCR_FULLDPLX; 1801 } 1802 else { 1803 adv |= ADVERTISE_1000XHALF; 1804 new_bmcr &= ~BMCR_FULLDPLX; 1805 } 1806 if ((new_bmcr != bmcr) || (force_link_down)) { 1807 /* Force a link down visible on the other side */ 1808 if (bp->link_up) { 1809 bnx2_write_phy(bp, bp->mii_adv, adv & 1810 ~(ADVERTISE_1000XFULL | 1811 ADVERTISE_1000XHALF)); 1812 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | 1813 BMCR_ANRESTART | BMCR_ANENABLE); 1814 1815 bp->link_up = 0; 1816 netif_carrier_off(bp->dev); 1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1818 bnx2_report_link(bp); 1819 } 1820 bnx2_write_phy(bp, bp->mii_adv, adv); 1821 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1822 } else { 1823 bnx2_resolve_flow_ctrl(bp); 1824 bnx2_set_mac_link(bp); 1825 } 1826 return 0; 1827 } 1828 1829 bnx2_test_and_enable_2g5(bp); 1830 1831 if (bp->advertising & ADVERTISED_1000baseT_Full) 1832 new_adv |= ADVERTISE_1000XFULL; 1833 1834 new_adv |= bnx2_phy_get_pause_adv(bp); 1835 1836 bnx2_read_phy(bp, bp->mii_adv, &adv); 1837 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1838 1839 bp->serdes_an_pending = 0; 1840 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { 1841 /* Force a link down visible on the other side */ 1842 if (bp->link_up) { 1843 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 1844 spin_unlock_bh(&bp->phy_lock); 1845 msleep(20); 1846 spin_lock_bh(&bp->phy_lock); 1847 } 1848 1849 bnx2_write_phy(bp, bp->mii_adv, new_adv); 1850 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | 1851 BMCR_ANENABLE); 1852 /* Speed up link-up time when the link partner 1853 * does not autonegotiate which is very common 1854 * in blade servers. Some blade servers use 1855 * IPMI for kerboard input and it's important 1856 * to minimize link disruptions. Autoneg. involves 1857 * exchanging base pages plus 3 next pages and 1858 * normally completes in about 120 msec. 1859 */ 1860 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; 1861 bp->serdes_an_pending = 1; 1862 mod_timer(&bp->timer, jiffies + bp->current_interval); 1863 } else { 1864 bnx2_resolve_flow_ctrl(bp); 1865 bnx2_set_mac_link(bp); 1866 } 1867 1868 return 0; 1869} 1870 1871#define ETHTOOL_ALL_FIBRE_SPEED \ 1872 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ 1873 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ 1874 (ADVERTISED_1000baseT_Full) 1875 1876#define ETHTOOL_ALL_COPPER_SPEED \ 1877 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ 1878 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ 1879 ADVERTISED_1000baseT_Full) 1880 1881#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 1882 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) 1883 1884#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) 1885 1886static void 1887bnx2_set_default_remote_link(struct bnx2 *bp) 1888{ 1889 u32 link; 1890 1891 if (bp->phy_port == PORT_TP) 1892 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); 1893 else 1894 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); 1895 1896 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { 1897 bp->req_line_speed = 0; 1898 bp->autoneg |= AUTONEG_SPEED; 1899 bp->advertising = ADVERTISED_Autoneg; 1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1901 bp->advertising |= ADVERTISED_10baseT_Half; 1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) 1903 bp->advertising |= ADVERTISED_10baseT_Full; 1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1905 bp->advertising |= ADVERTISED_100baseT_Half; 1906 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) 1907 bp->advertising |= ADVERTISED_100baseT_Full; 1908 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1909 bp->advertising |= ADVERTISED_1000baseT_Full; 1910 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1911 bp->advertising |= ADVERTISED_2500baseX_Full; 1912 } else { 1913 bp->autoneg = 0; 1914 bp->advertising = 0; 1915 bp->req_duplex = DUPLEX_FULL; 1916 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { 1917 bp->req_line_speed = SPEED_10; 1918 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1919 bp->req_duplex = DUPLEX_HALF; 1920 } 1921 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { 1922 bp->req_line_speed = SPEED_100; 1923 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1924 bp->req_duplex = DUPLEX_HALF; 1925 } 1926 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1927 bp->req_line_speed = SPEED_1000; 1928 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1929 bp->req_line_speed = SPEED_2500; 1930 } 1931} 1932 1933static void 1934bnx2_set_default_link(struct bnx2 *bp) 1935{ 1936 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 1937 bnx2_set_default_remote_link(bp); 1938 return; 1939 } 1940 1941 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; 1942 bp->req_line_speed = 0; 1943 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1944 u32 reg; 1945 1946 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; 1947 1948 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); 1949 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; 1950 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { 1951 bp->autoneg = 0; 1952 bp->req_line_speed = bp->line_speed = SPEED_1000; 1953 bp->req_duplex = DUPLEX_FULL; 1954 } 1955 } else 1956 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; 1957} 1958 1959static void 1960bnx2_send_heart_beat(struct bnx2 *bp) 1961{ 1962 u32 msg; 1963 u32 addr; 1964 1965 spin_lock(&bp->indirect_lock); 1966 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); 1967 addr = bp->shmem_base + BNX2_DRV_PULSE_MB; 1968 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); 1969 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); 1970 spin_unlock(&bp->indirect_lock); 1971} 1972 1973static void 1974bnx2_remote_phy_event(struct bnx2 *bp) 1975{ 1976 u32 msg; 1977 u8 link_up = bp->link_up; 1978 u8 old_port; 1979 1980 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 1981 1982 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) 1983 bnx2_send_heart_beat(bp); 1984 1985 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; 1986 1987 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) 1988 bp->link_up = 0; 1989 else { 1990 u32 speed; 1991 1992 bp->link_up = 1; 1993 speed = msg & BNX2_LINK_STATUS_SPEED_MASK; 1994 bp->duplex = DUPLEX_FULL; 1995 switch (speed) { 1996 case BNX2_LINK_STATUS_10HALF: 1997 bp->duplex = DUPLEX_HALF; 1998 /* fall through */ 1999 case BNX2_LINK_STATUS_10FULL: 2000 bp->line_speed = SPEED_10; 2001 break; 2002 case BNX2_LINK_STATUS_100HALF: 2003 bp->duplex = DUPLEX_HALF; 2004 /* fall through */ 2005 case BNX2_LINK_STATUS_100BASE_T4: 2006 ca…
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