/drivers/net/ethernet/broadcom/tg3.h
C Header | 3449 lines | 2947 code | 256 blank | 246 comment | 47 complexity | f204653c23c1fa04b519a2c819e16e2a MD5 | raw file
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1/* SPDX-License-Identifier: GPL-2.0 */ 2/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ 3 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 4 * 5 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 6 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 7 * Copyright (C) 2004 Sun Microsystems Inc. 8 * Copyright (C) 2007-2016 Broadcom Corporation. 9 * Copyright (C) 2016-2017 Broadcom Limited. 10 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom" 11 * refers to Broadcom Inc. and/or its subsidiaries. 12 */ 13 14#ifndef _T3_H 15#define _T3_H 16 17#define TG3_64BIT_REG_HIGH 0x00UL 18#define TG3_64BIT_REG_LOW 0x04UL 19 20/* Descriptor block info. */ 21#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 22#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 23#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 24#define BDINFO_FLAGS_DISABLED 0x00000002 25#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 26#define BDINFO_FLAGS_MAXLEN_SHIFT 16 27#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 28#define TG3_BDINFO_SIZE 0x10UL 29 30#define TG3_RX_STD_MAX_SIZE_5700 512 31#define TG3_RX_STD_MAX_SIZE_5717 2048 32#define TG3_RX_JMB_MAX_SIZE_5700 256 33#define TG3_RX_JMB_MAX_SIZE_5717 1024 34#define TG3_RX_RET_MAX_SIZE_5700 1024 35#define TG3_RX_RET_MAX_SIZE_5705 512 36#define TG3_RX_RET_MAX_SIZE_5717 4096 37 38#define TG3_RSS_INDIR_TBL_SIZE 128 39 40/* First 256 bytes are a mirror of PCI config space. */ 41#define TG3PCI_VENDOR 0x00000000 42#define TG3PCI_VENDOR_BROADCOM 0x14e4 43#define TG3PCI_DEVICE 0x00000002 44#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 45#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 46#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 47#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 48#define TG3PCI_DEVICE_TIGON3_5761S 0x1688 49#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 50#define TG3PCI_DEVICE_TIGON3_57780 0x1692 51#define TG3PCI_DEVICE_TIGON3_5787M 0x1693 52#define TG3PCI_DEVICE_TIGON3_57760 0x1690 53#define TG3PCI_DEVICE_TIGON3_57790 0x1694 54#define TG3PCI_DEVICE_TIGON3_57788 0x1691 55#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ 56#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ 57#define TG3PCI_DEVICE_TIGON3_5717 0x1655 58#define TG3PCI_DEVICE_TIGON3_5717_C 0x1665 59#define TG3PCI_DEVICE_TIGON3_5718 0x1656 60#define TG3PCI_DEVICE_TIGON3_57781 0x16b1 61#define TG3PCI_DEVICE_TIGON3_57785 0x16b5 62#define TG3PCI_DEVICE_TIGON3_57761 0x16b0 63#define TG3PCI_DEVICE_TIGON3_57765 0x16b4 64#define TG3PCI_DEVICE_TIGON3_57791 0x16b2 65#define TG3PCI_DEVICE_TIGON3_57795 0x16b6 66#define TG3PCI_DEVICE_TIGON3_5719 0x1657 67#define TG3PCI_DEVICE_TIGON3_5720 0x165f 68#define TG3PCI_DEVICE_TIGON3_57762 0x1682 69#define TG3PCI_DEVICE_TIGON3_57766 0x1686 70#define TG3PCI_DEVICE_TIGON3_57786 0x16b3 71#define TG3PCI_DEVICE_TIGON3_57782 0x16b7 72#define TG3PCI_DEVICE_TIGON3_5762 0x1687 73#define TG3PCI_DEVICE_TIGON3_5725 0x1643 74#define TG3PCI_DEVICE_TIGON3_5727 0x16f3 75#define TG3PCI_DEVICE_TIGON3_57764 0x1642 76#define TG3PCI_DEVICE_TIGON3_57767 0x1683 77#define TG3PCI_DEVICE_TIGON3_57787 0x1641 78/* 0x04 --> 0x2c unused */ 79#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM 80#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 81#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 82#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 83#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 84#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 85#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 86#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 87#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 88#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 89#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 90#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 91#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM 92#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 93#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 94#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 95#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 96#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 97#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL 98#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 99#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 100#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 101#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a 102#define TG3PCI_SUBDEVICE_ID_DELL_5762 0x07f0 103#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ 104#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c 105#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a 106#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d 107#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 108#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 109#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM 110#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 111#define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601 112#define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612 113#define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056 114 115/* 0x30 --> 0x64 unused */ 116#define TG3PCI_MSI_DATA 0x00000064 117/* 0x66 --> 0x68 unused */ 118#define TG3PCI_MISC_HOST_CTRL 0x00000068 119#define MISC_HOST_CTRL_CLEAR_INT 0x00000001 120#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 121#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 122#define MISC_HOST_CTRL_WORD_SWAP 0x00000008 123#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 124#define MISC_HOST_CTRL_CLKREG_RW 0x00000020 125#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 126#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 127#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 128#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 129#define MISC_HOST_CTRL_CHIPREV 0xffff0000 130#define MISC_HOST_CTRL_CHIPREV_SHIFT 16 131 132#define CHIPREV_ID_5700_A0 0x7000 133#define CHIPREV_ID_5700_A1 0x7001 134#define CHIPREV_ID_5700_B0 0x7100 135#define CHIPREV_ID_5700_B1 0x7101 136#define CHIPREV_ID_5700_B3 0x7102 137#define CHIPREV_ID_5700_ALTIMA 0x7104 138#define CHIPREV_ID_5700_C0 0x7200 139#define CHIPREV_ID_5701_A0 0x0000 140#define CHIPREV_ID_5701_B0 0x0100 141#define CHIPREV_ID_5701_B2 0x0102 142#define CHIPREV_ID_5701_B5 0x0105 143#define CHIPREV_ID_5703_A0 0x1000 144#define CHIPREV_ID_5703_A1 0x1001 145#define CHIPREV_ID_5703_A2 0x1002 146#define CHIPREV_ID_5703_A3 0x1003 147#define CHIPREV_ID_5704_A0 0x2000 148#define CHIPREV_ID_5704_A1 0x2001 149#define CHIPREV_ID_5704_A2 0x2002 150#define CHIPREV_ID_5704_A3 0x2003 151#define CHIPREV_ID_5705_A0 0x3000 152#define CHIPREV_ID_5705_A1 0x3001 153#define CHIPREV_ID_5705_A2 0x3002 154#define CHIPREV_ID_5705_A3 0x3003 155#define CHIPREV_ID_5750_A0 0x4000 156#define CHIPREV_ID_5750_A1 0x4001 157#define CHIPREV_ID_5750_A3 0x4003 158#define CHIPREV_ID_5750_C2 0x4202 159#define CHIPREV_ID_5752_A0_HW 0x5000 160#define CHIPREV_ID_5752_A0 0x6000 161#define CHIPREV_ID_5752_A1 0x6001 162#define CHIPREV_ID_5714_A2 0x9002 163#define CHIPREV_ID_5906_A1 0xc001 164#define CHIPREV_ID_57780_A0 0x57780000 165#define CHIPREV_ID_57780_A1 0x57780001 166#define CHIPREV_ID_5717_A0 0x05717000 167#define CHIPREV_ID_5717_C0 0x05717200 168#define CHIPREV_ID_57765_A0 0x57785000 169#define CHIPREV_ID_5719_A0 0x05719000 170#define CHIPREV_ID_5720_A0 0x05720000 171#define CHIPREV_ID_5762_A0 0x05762000 172 173#define ASIC_REV_5700 0x07 174#define ASIC_REV_5701 0x00 175#define ASIC_REV_5703 0x01 176#define ASIC_REV_5704 0x02 177#define ASIC_REV_5705 0x03 178#define ASIC_REV_5750 0x04 179#define ASIC_REV_5752 0x06 180#define ASIC_REV_5780 0x08 181#define ASIC_REV_5714 0x09 182#define ASIC_REV_5755 0x0a 183#define ASIC_REV_5787 0x0b 184#define ASIC_REV_5906 0x0c 185#define ASIC_REV_USE_PROD_ID_REG 0x0f 186#define ASIC_REV_5784 0x5784 187#define ASIC_REV_5761 0x5761 188#define ASIC_REV_5785 0x5785 189#define ASIC_REV_57780 0x57780 190#define ASIC_REV_5717 0x5717 191#define ASIC_REV_57765 0x57785 192#define ASIC_REV_5719 0x5719 193#define ASIC_REV_5720 0x5720 194#define ASIC_REV_57766 0x57766 195#define ASIC_REV_5762 0x5762 196#define CHIPREV_5700_AX 0x70 197#define CHIPREV_5700_BX 0x71 198#define CHIPREV_5700_CX 0x72 199#define CHIPREV_5701_AX 0x00 200#define CHIPREV_5703_AX 0x10 201#define CHIPREV_5704_AX 0x20 202#define CHIPREV_5704_BX 0x21 203#define CHIPREV_5750_AX 0x40 204#define CHIPREV_5750_BX 0x41 205#define CHIPREV_5784_AX 0x57840 206#define CHIPREV_5761_AX 0x57610 207#define CHIPREV_57765_AX 0x577650 208#define METAL_REV_A0 0x00 209#define METAL_REV_A1 0x01 210#define METAL_REV_B0 0x00 211#define METAL_REV_B1 0x01 212#define METAL_REV_B2 0x02 213#define TG3PCI_DMA_RW_CTRL 0x0000006c 214#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 215#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 216#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 217#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 218#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 219#define DMA_RWCTRL_READ_BNDRY_16 0x00000100 220#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 221#define DMA_RWCTRL_READ_BNDRY_32 0x00000200 222#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 223#define DMA_RWCTRL_READ_BNDRY_64 0x00000300 224#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 225#define DMA_RWCTRL_READ_BNDRY_128 0x00000400 226#define DMA_RWCTRL_READ_BNDRY_256 0x00000500 227#define DMA_RWCTRL_READ_BNDRY_512 0x00000600 228#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 229#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 230#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 231#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 232#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 233#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 234#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 235#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 236#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 237#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 238#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 239#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 240#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 241#define DMA_RWCTRL_ONE_DMA 0x00004000 242#define DMA_RWCTRL_READ_WATER 0x00070000 243#define DMA_RWCTRL_READ_WATER_SHIFT 16 244#define DMA_RWCTRL_WRITE_WATER 0x00380000 245#define DMA_RWCTRL_WRITE_WATER_SHIFT 19 246#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 247#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 248#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 249#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 250#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 251#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 252#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 253#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 254#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 255#define TG3PCI_PCISTATE 0x00000070 256#define PCISTATE_FORCE_RESET 0x00000001 257#define PCISTATE_INT_NOT_ACTIVE 0x00000002 258#define PCISTATE_CONV_PCI_MODE 0x00000004 259#define PCISTATE_BUS_SPEED_HIGH 0x00000008 260#define PCISTATE_BUS_32BIT 0x00000010 261#define PCISTATE_ROM_ENABLE 0x00000020 262#define PCISTATE_ROM_RETRY_ENABLE 0x00000040 263#define PCISTATE_FLAT_VIEW 0x00000100 264#define PCISTATE_RETRY_SAME_DMA 0x00002000 265#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 266#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 267#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 268#define TG3PCI_CLOCK_CTRL 0x00000074 269#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 270#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 271#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 272#define CLOCK_CTRL_ALTCLK 0x00001000 273#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 274#define CLOCK_CTRL_44MHZ_CORE 0x00040000 275#define CLOCK_CTRL_625_CORE 0x00100000 276#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 277#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 278#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 279#define TG3PCI_REG_BASE_ADDR 0x00000078 280#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 281#define TG3PCI_REG_DATA 0x00000080 282#define TG3PCI_MEM_WIN_DATA 0x00000084 283#define TG3PCI_MISC_LOCAL_CTRL 0x00000090 284/* 0x94 --> 0x98 unused */ 285#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 286#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 287/* 0xa8 --> 0xb8 unused */ 288#define TG3PCI_DEV_STATUS_CTRL 0x000000b4 289#define MAX_READ_REQ_SIZE_2048 0x00004000 290#define MAX_READ_REQ_MASK 0x00007000 291#define TG3PCI_DUAL_MAC_CTRL 0x000000b8 292#define DUAL_MAC_CTRL_CH_MASK 0x00000003 293#define DUAL_MAC_CTRL_ID 0x00000004 294#define TG3PCI_PRODID_ASICREV 0x000000bc 295#define PROD_ID_ASIC_REV_MASK 0x0fffffff 296/* 0xc0 --> 0xf4 unused */ 297 298#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 299#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc 300/* 0xf8 --> 0x200 unused */ 301 302#define TG3_CORR_ERR_STAT 0x00000110 303#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff 304/* 0x114 --> 0x200 unused */ 305 306/* Mailbox registers */ 307#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 308#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 309#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 310#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 311#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 312#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 313#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 314#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 315#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 316#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 317#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 318#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 319#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 320#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 321#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ 322 TG3_64BIT_REG_LOW) 323#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 324#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ 325 TG3_64BIT_REG_LOW) 326#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 327#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 328#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 329#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 330#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 331#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 332#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 333#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 334#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 335#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 336#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 337#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 338#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 339#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 340#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 341#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 342#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 343#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 344#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 345#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 346#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 347#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 348#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 349#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 350#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 351#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 352#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 353#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 354#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 355#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 356#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 357#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 358#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 359#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 360#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 361#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 362#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 363#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 364#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 365#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 366#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 367#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 368#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 369#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 370#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 371#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 372#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 373#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 374#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 375 376/* MAC control registers */ 377#define MAC_MODE 0x00000400 378#define MAC_MODE_RESET 0x00000001 379#define MAC_MODE_HALF_DUPLEX 0x00000002 380#define MAC_MODE_PORT_MODE_MASK 0x0000000c 381#define MAC_MODE_PORT_MODE_TBI 0x0000000c 382#define MAC_MODE_PORT_MODE_GMII 0x00000008 383#define MAC_MODE_PORT_MODE_MII 0x00000004 384#define MAC_MODE_PORT_MODE_NONE 0x00000000 385#define MAC_MODE_PORT_INT_LPBACK 0x00000010 386#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 387#define MAC_MODE_TX_BURSTING 0x00000100 388#define MAC_MODE_MAX_DEFER 0x00000200 389#define MAC_MODE_LINK_POLARITY 0x00000400 390#define MAC_MODE_RXSTAT_ENABLE 0x00000800 391#define MAC_MODE_RXSTAT_CLEAR 0x00001000 392#define MAC_MODE_RXSTAT_FLUSH 0x00002000 393#define MAC_MODE_TXSTAT_ENABLE 0x00004000 394#define MAC_MODE_TXSTAT_CLEAR 0x00008000 395#define MAC_MODE_TXSTAT_FLUSH 0x00010000 396#define MAC_MODE_SEND_CONFIGS 0x00020000 397#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 398#define MAC_MODE_ACPI_ENABLE 0x00080000 399#define MAC_MODE_MIP_ENABLE 0x00100000 400#define MAC_MODE_TDE_ENABLE 0x00200000 401#define MAC_MODE_RDE_ENABLE 0x00400000 402#define MAC_MODE_FHDE_ENABLE 0x00800000 403#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 404#define MAC_MODE_APE_RX_EN 0x08000000 405#define MAC_MODE_APE_TX_EN 0x10000000 406#define MAC_STATUS 0x00000404 407#define MAC_STATUS_PCS_SYNCED 0x00000001 408#define MAC_STATUS_SIGNAL_DET 0x00000002 409#define MAC_STATUS_RCVD_CFG 0x00000004 410#define MAC_STATUS_CFG_CHANGED 0x00000008 411#define MAC_STATUS_SYNC_CHANGED 0x00000010 412#define MAC_STATUS_PORT_DEC_ERR 0x00000400 413#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 414#define MAC_STATUS_MI_COMPLETION 0x00400000 415#define MAC_STATUS_MI_INTERRUPT 0x00800000 416#define MAC_STATUS_AP_ERROR 0x01000000 417#define MAC_STATUS_ODI_ERROR 0x02000000 418#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 419#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 420#define MAC_EVENT 0x00000408 421#define MAC_EVENT_PORT_DECODE_ERR 0x00000400 422#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 423#define MAC_EVENT_MI_COMPLETION 0x00400000 424#define MAC_EVENT_MI_INTERRUPT 0x00800000 425#define MAC_EVENT_AP_ERROR 0x01000000 426#define MAC_EVENT_ODI_ERROR 0x02000000 427#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 428#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 429#define MAC_LED_CTRL 0x0000040c 430#define LED_CTRL_LNKLED_OVERRIDE 0x00000001 431#define LED_CTRL_1000MBPS_ON 0x00000002 432#define LED_CTRL_100MBPS_ON 0x00000004 433#define LED_CTRL_10MBPS_ON 0x00000008 434#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 435#define LED_CTRL_TRAFFIC_BLINK 0x00000020 436#define LED_CTRL_TRAFFIC_LED 0x00000040 437#define LED_CTRL_1000MBPS_STATUS 0x00000080 438#define LED_CTRL_100MBPS_STATUS 0x00000100 439#define LED_CTRL_10MBPS_STATUS 0x00000200 440#define LED_CTRL_TRAFFIC_STATUS 0x00000400 441#define LED_CTRL_MODE_MAC 0x00000000 442#define LED_CTRL_MODE_PHY_1 0x00000800 443#define LED_CTRL_MODE_PHY_2 0x00001000 444#define LED_CTRL_MODE_SHASTA_MAC 0x00002000 445#define LED_CTRL_MODE_SHARED 0x00004000 446#define LED_CTRL_MODE_COMBO 0x00008000 447#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 448#define LED_CTRL_BLINK_RATE_SHIFT 19 449#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 450#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 451#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 452#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 453#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 454#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 455#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 456#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 457#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 458#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 459#define MAC_ACPI_MBUF_PTR 0x00000430 460#define MAC_ACPI_LEN_OFFSET 0x00000434 461#define ACPI_LENOFF_LEN_MASK 0x0000ffff 462#define ACPI_LENOFF_LEN_SHIFT 0 463#define ACPI_LENOFF_OFF_MASK 0x0fff0000 464#define ACPI_LENOFF_OFF_SHIFT 16 465#define MAC_TX_BACKOFF_SEED 0x00000438 466#define TX_BACKOFF_SEED_MASK 0x000003ff 467#define MAC_RX_MTU_SIZE 0x0000043c 468#define RX_MTU_SIZE_MASK 0x0000ffff 469#define MAC_PCS_TEST 0x00000440 470#define PCS_TEST_PATTERN_MASK 0x000fffff 471#define PCS_TEST_PATTERN_SHIFT 0 472#define PCS_TEST_ENABLE 0x00100000 473#define MAC_TX_AUTO_NEG 0x00000444 474#define TX_AUTO_NEG_MASK 0x0000ffff 475#define TX_AUTO_NEG_SHIFT 0 476#define MAC_RX_AUTO_NEG 0x00000448 477#define RX_AUTO_NEG_MASK 0x0000ffff 478#define RX_AUTO_NEG_SHIFT 0 479#define MAC_MI_COM 0x0000044c 480#define MI_COM_CMD_MASK 0x0c000000 481#define MI_COM_CMD_WRITE 0x04000000 482#define MI_COM_CMD_READ 0x08000000 483#define MI_COM_READ_FAILED 0x10000000 484#define MI_COM_START 0x20000000 485#define MI_COM_BUSY 0x20000000 486#define MI_COM_PHY_ADDR_MASK 0x03e00000 487#define MI_COM_PHY_ADDR_SHIFT 21 488#define MI_COM_REG_ADDR_MASK 0x001f0000 489#define MI_COM_REG_ADDR_SHIFT 16 490#define MI_COM_DATA_MASK 0x0000ffff 491#define MAC_MI_STAT 0x00000450 492#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 493#define MAC_MI_STAT_10MBPS_MODE 0x00000002 494#define MAC_MI_MODE 0x00000454 495#define MAC_MI_MODE_CLK_10MHZ 0x00000001 496#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 497#define MAC_MI_MODE_AUTO_POLL 0x00000010 498#define MAC_MI_MODE_500KHZ_CONST 0x00008000 499#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 500#define MAC_AUTO_POLL_STATUS 0x00000458 501#define MAC_AUTO_POLL_ERROR 0x00000001 502#define MAC_TX_MODE 0x0000045c 503#define TX_MODE_RESET 0x00000001 504#define TX_MODE_ENABLE 0x00000002 505#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 506#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 507#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 508#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 509#define TX_MODE_JMB_FRM_LEN 0x00400000 510#define TX_MODE_CNT_DN_MODE 0x00800000 511#define MAC_TX_STATUS 0x00000460 512#define TX_STATUS_XOFFED 0x00000001 513#define TX_STATUS_SENT_XOFF 0x00000002 514#define TX_STATUS_SENT_XON 0x00000004 515#define TX_STATUS_LINK_UP 0x00000008 516#define TX_STATUS_ODI_UNDERRUN 0x00000010 517#define TX_STATUS_ODI_OVERRUN 0x00000020 518#define MAC_TX_LENGTHS 0x00000464 519#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 520#define TX_LENGTHS_SLOT_TIME_SHIFT 0 521#define TX_LENGTHS_IPG_MASK 0x00000f00 522#define TX_LENGTHS_IPG_SHIFT 8 523#define TX_LENGTHS_IPG_CRS_MASK 0x00003000 524#define TX_LENGTHS_IPG_CRS_SHIFT 12 525#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000 526#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000 527#define MAC_RX_MODE 0x00000468 528#define RX_MODE_RESET 0x00000001 529#define RX_MODE_ENABLE 0x00000002 530#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 531#define RX_MODE_KEEP_MAC_CTRL 0x00000008 532#define RX_MODE_KEEP_PAUSE 0x00000010 533#define RX_MODE_ACCEPT_OVERSIZED 0x00000020 534#define RX_MODE_ACCEPT_RUNTS 0x00000040 535#define RX_MODE_LEN_CHECK 0x00000080 536#define RX_MODE_PROMISC 0x00000100 537#define RX_MODE_NO_CRC_CHECK 0x00000200 538#define RX_MODE_KEEP_VLAN_TAG 0x00000400 539#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 540#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 541#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 542#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 543#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 544#define RX_MODE_RSS_ENABLE 0x00800000 545#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 546#define RX_MODE_IPV4_FRAG_FIX 0x02000000 547#define MAC_RX_STATUS 0x0000046c 548#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 549#define RX_STATUS_XOFF_RCVD 0x00000002 550#define RX_STATUS_XON_RCVD 0x00000004 551#define MAC_HASH_REG_0 0x00000470 552#define MAC_HASH_REG_1 0x00000474 553#define MAC_HASH_REG_2 0x00000478 554#define MAC_HASH_REG_3 0x0000047c 555#define MAC_RCV_RULE_0 0x00000480 556#define MAC_RCV_VALUE_0 0x00000484 557#define MAC_RCV_RULE_1 0x00000488 558#define MAC_RCV_VALUE_1 0x0000048c 559#define MAC_RCV_RULE_2 0x00000490 560#define MAC_RCV_VALUE_2 0x00000494 561#define MAC_RCV_RULE_3 0x00000498 562#define MAC_RCV_VALUE_3 0x0000049c 563#define MAC_RCV_RULE_4 0x000004a0 564#define MAC_RCV_VALUE_4 0x000004a4 565#define MAC_RCV_RULE_5 0x000004a8 566#define MAC_RCV_VALUE_5 0x000004ac 567#define MAC_RCV_RULE_6 0x000004b0 568#define MAC_RCV_VALUE_6 0x000004b4 569#define MAC_RCV_RULE_7 0x000004b8 570#define MAC_RCV_VALUE_7 0x000004bc 571#define MAC_RCV_RULE_8 0x000004c0 572#define MAC_RCV_VALUE_8 0x000004c4 573#define MAC_RCV_RULE_9 0x000004c8 574#define MAC_RCV_VALUE_9 0x000004cc 575#define MAC_RCV_RULE_10 0x000004d0 576#define MAC_RCV_VALUE_10 0x000004d4 577#define MAC_RCV_RULE_11 0x000004d8 578#define MAC_RCV_VALUE_11 0x000004dc 579#define MAC_RCV_RULE_12 0x000004e0 580#define MAC_RCV_VALUE_12 0x000004e4 581#define MAC_RCV_RULE_13 0x000004e8 582#define MAC_RCV_VALUE_13 0x000004ec 583#define MAC_RCV_RULE_14 0x000004f0 584#define MAC_RCV_VALUE_14 0x000004f4 585#define MAC_RCV_RULE_15 0x000004f8 586#define MAC_RCV_VALUE_15 0x000004fc 587#define RCV_RULE_DISABLE_MASK 0x7fffffff 588#define MAC_RCV_RULE_CFG 0x00000500 589#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 590#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 591/* 0x508 --> 0x520 unused */ 592#define MAC_HASHREGU_0 0x00000520 593#define MAC_HASHREGU_1 0x00000524 594#define MAC_HASHREGU_2 0x00000528 595#define MAC_HASHREGU_3 0x0000052c 596#define MAC_EXTADDR_0_HIGH 0x00000530 597#define MAC_EXTADDR_0_LOW 0x00000534 598#define MAC_EXTADDR_1_HIGH 0x00000538 599#define MAC_EXTADDR_1_LOW 0x0000053c 600#define MAC_EXTADDR_2_HIGH 0x00000540 601#define MAC_EXTADDR_2_LOW 0x00000544 602#define MAC_EXTADDR_3_HIGH 0x00000548 603#define MAC_EXTADDR_3_LOW 0x0000054c 604#define MAC_EXTADDR_4_HIGH 0x00000550 605#define MAC_EXTADDR_4_LOW 0x00000554 606#define MAC_EXTADDR_5_HIGH 0x00000558 607#define MAC_EXTADDR_5_LOW 0x0000055c 608#define MAC_EXTADDR_6_HIGH 0x00000560 609#define MAC_EXTADDR_6_LOW 0x00000564 610#define MAC_EXTADDR_7_HIGH 0x00000568 611#define MAC_EXTADDR_7_LOW 0x0000056c 612#define MAC_EXTADDR_8_HIGH 0x00000570 613#define MAC_EXTADDR_8_LOW 0x00000574 614#define MAC_EXTADDR_9_HIGH 0x00000578 615#define MAC_EXTADDR_9_LOW 0x0000057c 616#define MAC_EXTADDR_10_HIGH 0x00000580 617#define MAC_EXTADDR_10_LOW 0x00000584 618#define MAC_EXTADDR_11_HIGH 0x00000588 619#define MAC_EXTADDR_11_LOW 0x0000058c 620#define MAC_SERDES_CFG 0x00000590 621#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 622#define MAC_SERDES_STAT 0x00000594 623/* 0x598 --> 0x5a0 unused */ 624#define MAC_PHYCFG1 0x000005a0 625#define MAC_PHYCFG1_RGMII_INT 0x00000001 626#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 627#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 628#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 629#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 630#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 631#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 632#define MAC_PHYCFG1_TXC_DRV 0x20000000 633#define MAC_PHYCFG2 0x000005a4 634#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 635#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 636#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 637#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 638#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 639#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 640#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 641#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 642#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 643#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 644#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 645#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 646#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 647#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 648#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 649#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 650#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 651#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 652#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 653#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 654#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 655#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 656#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 657#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 658#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 659#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 660#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 661#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 662#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 663#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 664#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 665#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 666#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 667#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 668#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 669#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 670#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 671#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 672#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 673#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 674#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 675#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 676#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 677#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 678#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 679#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 680#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 681#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 682#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 683#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 684#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 685#define MAC_PHYCFG2_50610_LED_MODES \ 686 (MAC_PHYCFG2_EMODE_MASK_50610 | \ 687 MAC_PHYCFG2_EMODE_COMP_50610 | \ 688 MAC_PHYCFG2_FMODE_MASK_50610 | \ 689 MAC_PHYCFG2_FMODE_COMP_50610 | \ 690 MAC_PHYCFG2_GMODE_MASK_50610 | \ 691 MAC_PHYCFG2_GMODE_COMP_50610 | \ 692 MAC_PHYCFG2_ACT_MASK_50610 | \ 693 MAC_PHYCFG2_ACT_COMP_50610 | \ 694 MAC_PHYCFG2_QUAL_MASK_50610 | \ 695 MAC_PHYCFG2_QUAL_COMP_50610) 696#define MAC_PHYCFG2_AC131_LED_MODES \ 697 (MAC_PHYCFG2_EMODE_MASK_AC131 | \ 698 MAC_PHYCFG2_EMODE_COMP_AC131 | \ 699 MAC_PHYCFG2_FMODE_MASK_AC131 | \ 700 MAC_PHYCFG2_FMODE_COMP_AC131 | \ 701 MAC_PHYCFG2_GMODE_MASK_AC131 | \ 702 MAC_PHYCFG2_GMODE_COMP_AC131 | \ 703 MAC_PHYCFG2_ACT_MASK_AC131 | \ 704 MAC_PHYCFG2_ACT_COMP_AC131 | \ 705 MAC_PHYCFG2_QUAL_MASK_AC131 | \ 706 MAC_PHYCFG2_QUAL_COMP_AC131) 707#define MAC_PHYCFG2_RTL8211C_LED_MODES \ 708 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ 709 MAC_PHYCFG2_EMODE_COMP_RT8211 | \ 710 MAC_PHYCFG2_FMODE_MASK_RT8211 | \ 711 MAC_PHYCFG2_FMODE_COMP_RT8211 | \ 712 MAC_PHYCFG2_GMODE_MASK_RT8211 | \ 713 MAC_PHYCFG2_GMODE_COMP_RT8211 | \ 714 MAC_PHYCFG2_ACT_MASK_RT8211 | \ 715 MAC_PHYCFG2_ACT_COMP_RT8211 | \ 716 MAC_PHYCFG2_QUAL_MASK_RT8211 | \ 717 MAC_PHYCFG2_QUAL_COMP_RT8211) 718#define MAC_PHYCFG2_RTL8201E_LED_MODES \ 719 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ 720 MAC_PHYCFG2_EMODE_COMP_RT8201 | \ 721 MAC_PHYCFG2_FMODE_MASK_RT8201 | \ 722 MAC_PHYCFG2_FMODE_COMP_RT8201 | \ 723 MAC_PHYCFG2_GMODE_MASK_RT8201 | \ 724 MAC_PHYCFG2_GMODE_COMP_RT8201 | \ 725 MAC_PHYCFG2_ACT_MASK_RT8201 | \ 726 MAC_PHYCFG2_ACT_COMP_RT8201 | \ 727 MAC_PHYCFG2_QUAL_MASK_RT8201 | \ 728 MAC_PHYCFG2_QUAL_COMP_RT8201) 729#define MAC_EXT_RGMII_MODE 0x000005a8 730#define MAC_RGMII_MODE_TX_ENABLE 0x00000001 731#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 732#define MAC_RGMII_MODE_TX_RESET 0x00000004 733#define MAC_RGMII_MODE_RX_INT_B 0x00000100 734#define MAC_RGMII_MODE_RX_QUALITY 0x00000200 735#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 736#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 737/* 0x5ac --> 0x5b0 unused */ 738#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 739#define SERDES_RX_SIG_DETECT 0x00000400 740#define SG_DIG_CTRL 0x000005b0 741#define SG_DIG_USING_HW_AUTONEG 0x80000000 742#define SG_DIG_SOFT_RESET 0x40000000 743#define SG_DIG_DISABLE_LINKRDY 0x20000000 744#define SG_DIG_CRC16_CLEAR_N 0x01000000 745#define SG_DIG_EN10B 0x00800000 746#define SG_DIG_CLEAR_STATUS 0x00400000 747#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 748#define SG_DIG_LOCAL_LINK_STATUS 0x00100000 749#define SG_DIG_SPEED_STATUS_MASK 0x000c0000 750#define SG_DIG_SPEED_STATUS_SHIFT 18 751#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 752#define SG_DIG_RESTART_AUTONEG 0x00010000 753#define SG_DIG_FIBER_MODE 0x00008000 754#define SG_DIG_REMOTE_FAULT_MASK 0x00006000 755#define SG_DIG_PAUSE_MASK 0x00001800 756#define SG_DIG_PAUSE_CAP 0x00000800 757#define SG_DIG_ASYM_PAUSE 0x00001000 758#define SG_DIG_GBIC_ENABLE 0x00000400 759#define SG_DIG_CHECK_END_ENABLE 0x00000200 760#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 761#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 762#define SG_DIG_GMII_INPUT_SELECT 0x00000040 763#define SG_DIG_MRADV_CRC16_SELECT 0x00000020 764#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 765#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 766#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 767#define SG_DIG_REMOTE_LOOPBACK 0x00000002 768#define SG_DIG_LOOPBACK 0x00000001 769#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ 770 SG_DIG_LOCAL_DUPLEX_STATUS | \ 771 SG_DIG_LOCAL_LINK_STATUS | \ 772 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ 773 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) 774#define SG_DIG_STATUS 0x000005b4 775#define SG_DIG_CRC16_BUS_MASK 0xffff0000 776#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 777#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 778#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 779#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 780#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 781#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 782#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 783#define SG_DIG_IS_SERDES 0x00000100 784#define SG_DIG_COMMA_DETECTOR 0x00000008 785#define SG_DIG_MAC_ACK_STATUS 0x00000004 786#define SG_DIG_AUTONEG_COMPLETE 0x00000002 787#define SG_DIG_AUTONEG_ERROR 0x00000001 788#define TG3_TX_TSTAMP_LSB 0x000005c0 789#define TG3_TX_TSTAMP_MSB 0x000005c4 790#define TG3_TSTAMP_MASK 0x7fffffffffffffffLL 791/* 0x5c8 --> 0x600 unused */ 792#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 793#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 794/* 0x624 --> 0x670 unused */ 795 796#define MAC_RSS_INDIR_TBL_0 0x00000630 797 798#define MAC_RSS_HASH_KEY_0 0x00000670 799#define MAC_RSS_HASH_KEY_1 0x00000674 800#define MAC_RSS_HASH_KEY_2 0x00000678 801#define MAC_RSS_HASH_KEY_3 0x0000067c 802#define MAC_RSS_HASH_KEY_4 0x00000680 803#define MAC_RSS_HASH_KEY_5 0x00000684 804#define MAC_RSS_HASH_KEY_6 0x00000688 805#define MAC_RSS_HASH_KEY_7 0x0000068c 806#define MAC_RSS_HASH_KEY_8 0x00000690 807#define MAC_RSS_HASH_KEY_9 0x00000694 808/* 0x698 --> 0x6b0 unused */ 809 810#define TG3_RX_TSTAMP_LSB 0x000006b0 811#define TG3_RX_TSTAMP_MSB 0x000006b4 812/* 0x6b8 --> 0x6c8 unused */ 813 814#define TG3_RX_PTP_CTL 0x000006c8 815#define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001 816#define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002 817#define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004 818#define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008 819#define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 820 TG3_RX_PTP_CTL_DELAY_REQ) 821#define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 822 TG3_RX_PTP_CTL_DELAY_REQ | \ 823 TG3_RX_PTP_CTL_PDLAY_REQ | \ 824 TG3_RX_PTP_CTL_PDLAY_RES) 825#define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100 826#define TG3_RX_PTP_CTL_DELAY_RES 0x00000200 827#define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400 828#define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800 829#define TG3_RX_PTP_CTL_SIGNALING 0x00001000 830#define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000 831#define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000 832#define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000 833#define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \ 834 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN) 835#define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000 836#define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000 837/* 0x6cc --> 0x800 unused */ 838 839#define MAC_TX_STATS_OCTETS 0x00000800 840#define MAC_TX_STATS_RESV1 0x00000804 841#define MAC_TX_STATS_COLLISIONS 0x00000808 842#define MAC_TX_STATS_XON_SENT 0x0000080c 843#define MAC_TX_STATS_XOFF_SENT 0x00000810 844#define MAC_TX_STATS_RESV2 0x00000814 845#define MAC_TX_STATS_MAC_ERRORS 0x00000818 846#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 847#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 848#define MAC_TX_STATS_DEFERRED 0x00000824 849#define MAC_TX_STATS_RESV3 0x00000828 850#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 851#define MAC_TX_STATS_LATE_COL 0x00000830 852#define MAC_TX_STATS_RESV4_1 0x00000834 853#define MAC_TX_STATS_RESV4_2 0x00000838 854#define MAC_TX_STATS_RESV4_3 0x0000083c 855#define MAC_TX_STATS_RESV4_4 0x00000840 856#define MAC_TX_STATS_RESV4_5 0x00000844 857#define MAC_TX_STATS_RESV4_6 0x00000848 858#define MAC_TX_STATS_RESV4_7 0x0000084c 859#define MAC_TX_STATS_RESV4_8 0x00000850 860#define MAC_TX_STATS_RESV4_9 0x00000854 861#define MAC_TX_STATS_RESV4_10 0x00000858 862#define MAC_TX_STATS_RESV4_11 0x0000085c 863#define MAC_TX_STATS_RESV4_12 0x00000860 864#define MAC_TX_STATS_RESV4_13 0x00000864 865#define MAC_TX_STATS_RESV4_14 0x00000868 866#define MAC_TX_STATS_UCAST 0x0000086c 867#define MAC_TX_STATS_MCAST 0x00000870 868#define MAC_TX_STATS_BCAST 0x00000874 869#define MAC_TX_STATS_RESV5_1 0x00000878 870#define MAC_TX_STATS_RESV5_2 0x0000087c 871#define MAC_RX_STATS_OCTETS 0x00000880 872#define MAC_RX_STATS_RESV1 0x00000884 873#define MAC_RX_STATS_FRAGMENTS 0x00000888 874#define MAC_RX_STATS_UCAST 0x0000088c 875#define MAC_RX_STATS_MCAST 0x00000890 876#define MAC_RX_STATS_BCAST 0x00000894 877#define MAC_RX_STATS_FCS_ERRORS 0x00000898 878#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 879#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 880#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 881#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 882#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 883#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 884#define MAC_RX_STATS_JABBERS 0x000008b4 885#define MAC_RX_STATS_UNDERSIZE 0x000008b8 886/* 0x8bc --> 0xc00 unused */ 887 888/* Send data initiator control registers */ 889#define SNDDATAI_MODE 0x00000c00 890#define SNDDATAI_MODE_RESET 0x00000001 891#define SNDDATAI_MODE_ENABLE 0x00000002 892#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 893#define SNDDATAI_STATUS 0x00000c04 894#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 895#define SNDDATAI_STATSCTRL 0x00000c08 896#define SNDDATAI_SCTRL_ENABLE 0x00000001 897#define SNDDATAI_SCTRL_FASTUPD 0x00000002 898#define SNDDATAI_SCTRL_CLEAR 0x00000004 899#define SNDDATAI_SCTRL_FLUSH 0x00000008 900#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 901#define SNDDATAI_STATSENAB 0x00000c0c 902#define SNDDATAI_STATSINCMASK 0x00000c10 903#define ISO_PKT_TX 0x00000c20 904/* 0xc24 --> 0xc80 unused */ 905#define SNDDATAI_COS_CNT_0 0x00000c80 906#define SNDDATAI_COS_CNT_1 0x00000c84 907#define SNDDATAI_COS_CNT_2 0x00000c88 908#define SNDDATAI_COS_CNT_3 0x00000c8c 909#define SNDDATAI_COS_CNT_4 0x00000c90 910#define SNDDATAI_COS_CNT_5 0x00000c94 911#define SNDDATAI_COS_CNT_6 0x00000c98 912#define SNDDATAI_COS_CNT_7 0x00000c9c 913#define SNDDATAI_COS_CNT_8 0x00000ca0 914#define SNDDATAI_COS_CNT_9 0x00000ca4 915#define SNDDATAI_COS_CNT_10 0x00000ca8 916#define SNDDATAI_COS_CNT_11 0x00000cac 917#define SNDDATAI_COS_CNT_12 0x00000cb0 918#define SNDDATAI_COS_CNT_13 0x00000cb4 919#define SNDDATAI_COS_CNT_14 0x00000cb8 920#define SNDDATAI_COS_CNT_15 0x00000cbc 921#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 922#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 923#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 924#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 925#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 926#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 927#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 928#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 929/* 0xce0 --> 0x1000 unused */ 930 931/* Send data completion control registers */ 932#define SNDDATAC_MODE 0x00001000 933#define SNDDATAC_MODE_RESET 0x00000001 934#define SNDDATAC_MODE_ENABLE 0x00000002 935#define SNDDATAC_MODE_CDELAY 0x00000010 936/* 0x1004 --> 0x1400 unused */ 937 938/* Send BD ring selector */ 939#define SNDBDS_MODE 0x00001400 940#define SNDBDS_MODE_RESET 0x00000001 941#define SNDBDS_MODE_ENABLE 0x00000002 942#define SNDBDS_MODE_ATTN_ENABLE 0x00000004 943#define SNDBDS_STATUS 0x00001404 944#define SNDBDS_STATUS_ERROR_ATTN 0x00000004 945#define SNDBDS_HWDIAG 0x00001408 946/* 0x140c --> 0x1440 */ 947#define SNDBDS_SEL_CON_IDX_0 0x00001440 948#define SNDBDS_SEL_CON_IDX_1 0x00001444 949#define SNDBDS_SEL_CON_IDX_2 0x00001448 950#define SNDBDS_SEL_CON_IDX_3 0x0000144c 951#define SNDBDS_SEL_CON_IDX_4 0x00001450 952#define SNDBDS_SEL_CON_IDX_5 0x00001454 953#define SNDBDS_SEL_CON_IDX_6 0x00001458 954#define SNDBDS_SEL_CON_IDX_7 0x0000145c 955#define SNDBDS_SEL_CON_IDX_8 0x00001460 956#define SNDBDS_SEL_CON_IDX_9 0x00001464 957#define SNDBDS_SEL_CON_IDX_10 0x00001468 958#define SNDBDS_SEL_CON_IDX_11 0x0000146c 959#define SNDBDS_SEL_CON_IDX_12 0x00001470 960#define SNDBDS_SEL_CON_IDX_13 0x00001474 961#define SNDBDS_SEL_CON_IDX_14 0x00001478 962#define SNDBDS_SEL_CON_IDX_15 0x0000147c 963/* 0x1480 --> 0x1800 unused */ 964 965/* Send BD initiator control registers */ 966#define SNDBDI_MODE 0x00001800 967#define SNDBDI_MODE_RESET 0x00000001 968#define SNDBDI_MODE_ENABLE 0x00000002 969#define SNDBDI_MODE_ATTN_ENABLE 0x00000004 970#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 971#define SNDBDI_STATUS 0x00001804 972#define SNDBDI_STATUS_ERROR_ATTN 0x00000004 973#define SNDBDI_IN_PROD_IDX_0 0x00001808 974#define SNDBDI_IN_PROD_IDX_1 0x0000180c 975#define SNDBDI_IN_PROD_IDX_2 0x00001810 976#define SNDBDI_IN_PROD_IDX_3 0x00001814 977#define SNDBDI_IN_PROD_IDX_4 0x00001818 978#define SNDBDI_IN_PROD_IDX_5 0x0000181c 979#define SNDBDI_IN_PROD_IDX_6 0x00001820 980#define SNDBDI_IN_PROD_IDX_7 0x00001824 981#define SNDBDI_IN_PROD_IDX_8 0x00001828 982#define SNDBDI_IN_PROD_IDX_9 0x0000182c 983#define SNDBDI_IN_PROD_IDX_10 0x00001830 984#define SNDBDI_IN_PROD_IDX_11 0x00001834 985#define SNDBDI_IN_PROD_IDX_12 0x00001838 986#define SNDBDI_IN_PROD_IDX_13 0x0000183c 987#define SNDBDI_IN_PROD_IDX_14 0x00001840 988#define SNDBDI_IN_PROD_IDX_15 0x00001844 989/* 0x1848 --> 0x1c00 unused */ 990 991/* Send BD completion control registers */ 992#define SNDBDC_MODE 0x00001c00 993#define SNDBDC_MODE_RESET 0x00000001 994#define SNDBDC_MODE_ENABLE 0x00000002 995#define SNDBDC_MODE_ATTN_ENABLE 0x00000004 996/* 0x1c04 --> 0x2000 unused */ 997 998/* Receive list placement control registers */ 999#define RCVLPC_MODE 0x00002000 1000#define RCVLPC_MODE_RESET 0x00000001 1001#define RCVLPC_MODE_ENABLE 0x00000002 1002#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 1003#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 1004#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 1005#define RCVLPC_STATUS 0x00002004 1006#define RCVLPC_STATUS_CLASS0 0x00000004 1007#define RCVLPC_STATUS_MAPOOR 0x00000008 1008#define RCVLPC_STATUS_STAT_OFLOW 0x00000010 1009#define RCVLPC_LOCK 0x00002008 1010#define RCVLPC_LOCK_REQ_MASK 0x0000ffff 1011#define RCVLPC_LOCK_REQ_SHIFT 0 1012#define RCVLPC_LOCK_GRANT_MASK 0xffff0000 1013#define RCVLPC_LOCK_GRANT_SHIFT 16 1014#define RCVLPC_NON_EMPTY_BITS 0x0000200c 1015#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 1016#define RCVLPC_CONFIG 0x00002010 1017#define RCVLPC_STATSCTRL 0x00002014 1018#define RCVLPC_STATSCTRL_ENABLE 0x00000001 1019#define RCVLPC_STATSCTRL_FASTUPD 0x00000002 1020#define RCVLPC_STATS_ENABLE 0x00002018 1021#define RCVLPC_STATSENAB_ASF_FIX 0x00000002 1022#define RCVLPC_STATSENAB_DACK_FIX 0x00040000 1023#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 1024#define RCVLPC_STATS_INCMASK 0x0000201c 1025/* 0x2020 --> 0x2100 unused */ 1026#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 1027#define SELLST_TAIL 0x00000004 1028#define SELLST_CONT 0x00000008 1029#define SELLST_UNUSED 0x0000000c 1030#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 1031#define RCVLPC_DROP_FILTER_CNT 0x00002240 1032#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 1033#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 1034#define RCVLPC_NO_RCV_BD_CNT 0x0000224c 1035#define RCVLPC_IN_DISCARDS_CNT 0x00002250 1036#define RCVLPC_IN_ERRORS_CNT 0x00002254 1037#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 1038/* 0x225c --> 0x2400 unused */ 1039 1040/* Receive Data and Receive BD Initiator Control */ 1041#define RCVDBDI_MODE 0x00002400 1042#define RCVDBDI_MODE_RESET 0x00000001 1043#define RCVDBDI_MODE_ENABLE 0x00000002 1044#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 1045#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 1046#define RCVDBDI_MODE_INV_RING_SZ 0x00000010 1047#define RCVDBDI_MODE_LRG_RING_SZ 0x00010000 1048#define RCVDBDI_STATUS 0x00002404 1049#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 1050#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 1051#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 1052#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 1053/* 0x240c --> 0x2440 unused */ 1054#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 1055#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 1056#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 1057#define RCVDBDI_JUMBO_CON_IDX 0x00002470 1058#define RCVDBDI_STD_CON_IDX 0x00002474 1059#define RCVDBDI_MINI_CON_IDX 0x00002478 1060/* 0x247c --> 0x2480 unused */ 1061#define RCVDBDI_BD_PROD_IDX_0 0x00002480 1062#define RCVDBDI_BD_PROD_IDX_1 0x00002484 1063#define RCVDBDI_BD_PROD_IDX_2 0x00002488 1064#define RCVDBDI_BD_PROD_IDX_3 0x0000248c 1065#define RCVDBDI_BD_PROD_IDX_4 0x00002490 1066#define RCVDBDI_BD_PROD_IDX_5 0x00002494 1067#define RCVDBDI_BD_PROD_IDX_6 0x00002498 1068#define RCVDBDI_BD_PROD_IDX_7 0x0000249c 1069#define RCVDBDI_BD_PROD_IDX_8 0x000024a0 1070#define RCVDBDI_BD_PROD_IDX_9 0x000024a4 1071#define RCVDBDI_BD_PROD_IDX_10 0x000024a8 1072#define RCVDBDI_BD_PROD_IDX_11 0x000024ac 1073#define RCVDBDI_BD_PROD_IDX_12 0x000024b0 1074#define RCVDBDI_BD_PROD_IDX_13 0x000024b4 1075#define RCVDBDI_BD_PROD_IDX_14 0x000024b8 1076#define RCVDBDI_BD_PROD_IDX_15 0x000024bc 1077#define RCVDBDI_HWDIAG 0x000024c0 1078/* 0x24c4 --> 0x2800 unused */ 1079 1080/* Receive Data Completion Control */ 1081#define RCVDCC_MODE 0x00002800 1082#define RCVDCC_MODE_RESET 0x00000001 1083#define RCVDCC_MODE_ENABLE 0x00000002 1084#define RCVDCC_MODE_ATTN_ENABLE 0x00000004 1085/* 0x2804 --> 0x2c00 unused */ 1086 1087/* Receive BD Initiator Control Registers */ 1088#define RCVBDI_MODE 0x00002c00 1089#define RCVBDI_MODE_RESET 0x00000001 1090#define RCVBDI_MODE_ENABLE 0x00000002 1091#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 1092#define RCVBDI_STATUS 0x00002c04 1093#define RCVBDI_STATUS_RCB_ATTN 0x00000004 1094#define RCVBDI_JUMBO_PROD_IDX 0x00002c08 1095#define RCVBDI_STD_PROD_IDX 0x00002c0c 1096#define RCVBDI_MINI_PROD_IDX 0x00002c10 1097#define RCVBDI_MINI_THRESH 0x00002c14 1098#define RCVBDI_STD_THRESH 0x00002c18 1099#define RCVBDI_JUMBO_THRESH 0x00002c1c 1100/* 0x2c20 --> 0x2d00 unused */ 1101 1102#define STD_REPLENISH_LWM 0x00002d00 1103#define JMB_REPLENISH_LWM 0x00002d04 1104/* 0x2d08 --> 0x3000 unused */ 1105 1106/* Receive BD Completion Control Registers */ 1107#define RCVCC_MODE 0x00003000 1108#define RCVCC_MODE_RESET 0x00000001 1109#define RCVCC_MODE_ENABLE 0x00000002 1110#define RCVCC_MODE_ATTN_ENABLE 0x00000004 1111#define RCVCC_STATUS 0x00003004 1112#define RCVCC_STATUS_ERROR_ATTN 0x00000004 1113#define RCVCC_JUMP_PROD_IDX 0x00003008 1114#define RCVCC_STD_PROD_IDX 0x0000300c 1115#define RCVCC_MINI_PROD_IDX 0x00003010 1116/* 0x3014 --> 0x3400 unused */ 1117 1118/* Receive list selector control registers */ 1119#define RCVLSC_MODE 0x00003400 1120#define RCVLSC_MODE_RESET 0x00000001 1121#define RCVLSC_MODE_ENABLE 0x00000002 1122#define RCVLSC_MODE_ATTN_ENABLE 0x00000004 1123#define RCVLSC_STATUS 0x00003404 1124#define RCVLSC_STATUS_ERROR_ATTN 0x00000004 1125/* 0x3408 --> 0x3600 unused */ 1126 1127#define TG3_CPMU_DRV_STATUS 0x0000344c 1128 1129/* CPMU registers */ 1130#define TG3_CPMU_CTRL 0x00003600 1131#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1132#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1133#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1134#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1135#define TG3_CPMU_LSPD_10MB_CLK 0x00003604 1136#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 1137#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1138/* 0x3608 --> 0x360c unused */ 1139 1140#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c 1141#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1142#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1143#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 1144#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 1145#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 1146#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1147/* 0x3614 --> 0x361c unused */ 1148 1149#define TG3_CPMU_HST_ACC 0x0000361c 1150#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 1151#define CPMU_HST_ACC_MACCLK_6_25 0x00130000 1152/* 0x3620 --> 0x3630 unused */ 1153 1154#define TG3_CPMU_CLCK_ORIDE 0x00003624 1155#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1156 1157#define TG3_CPMU_CLCK_ORIDE_ENABLE 0x00003628 1158#define TG3_CPMU_MAC_ORIDE_ENABLE (1 << 13) 1159 1160#define TG3_CPMU_STATUS 0x0000362c 1161#define TG3_CPMU_STATUS_FMSK_5717 0x20000000 1162#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000 1163#define TG3_CPMU_STATUS_FSHFT_5719 30 1164#define TG3_CPMU_STATUS_LINK_MASK 0x180000 1165 1166#define TG3_CPMU_CLCK_STAT 0x00003630 1167#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1168#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1169#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1170#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1171/* 0x3634 --> 0x365c unused */ 1172 1173#define TG3_CPMU_MUTEX_REQ 0x0000365c 1174#define CPMU_MUTEX_REQ_DRIVER 0x00001000 1175#define TG3_CPMU_MUTEX_GNT 0x00003660 1176#define CPMU_MUTEX_GNT_DRIVER 0x00001000 1177#define TG3_CPMU_PHY_STRAP 0x00003664 1178#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1179#define TG3_CPMU_PADRNG_CTL 0x00003668 1180#define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000 1181/* 0x3664 --> 0x36b0 unused */ 1182 1183#define TG3_CPMU_EEE_MODE 0x000036b0 1184#define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 1185#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 1186#define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 1187#define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 1188#define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 1189#define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 1190#define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 1191#define TG3_CPMU_EEE_DBTMR1 0x000036b4 1192#define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 1193#define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff 1194#define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff 1195#define TG3_CPMU_EEE_DBTMR2 0x000036b8 1196#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000 1197#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff 1198#define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc 1199#define TG3_CPMU_EEE_LNKI…
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