/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
C Header | 7702 lines | 3878 code | 127 blank | 3697 comment | 3 complexity | c7e25dd77d3bdda700158c038a9ca6ee MD5 | raw file
Large files files are truncated, but you can click here to view the full file
1/* bnx2x_reg.h: Qlogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * The registers description starts with the register Access type followed 12 * by size in bits. For example [RW 32]. The access types are: 13 * R - Read only 14 * RC - Clear on read 15 * RW - Read/Write 16 * ST - Statistics register (clear on read) 17 * W - Write only 18 * WB - Wide bus register - the size is over 32 bits and it should be 19 * read/write in consecutive 32 bits accesses 20 * WR - Write Clear (write 1 to clear the bit) 21 * 22 */ 23#ifndef BNX2X_REG_H 24#define BNX2X_REG_H 25 26#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 27#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2) 28#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5) 29#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) 30#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4) 31#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1) 32/* [RW 1] Initiate the ATC array - reset all the valid bits */ 33#define ATC_REG_ATC_INIT_ARRAY 0x1100b8 34/* [R 1] ATC initialization done */ 35#define ATC_REG_ATC_INIT_DONE 0x1100bc 36/* [RC 6] Interrupt register #0 read clear */ 37#define ATC_REG_ATC_INT_STS_CLR 0x1101c0 38/* [RW 5] Parity mask register #0 read/write */ 39#define ATC_REG_ATC_PRTY_MASK 0x1101d8 40/* [R 5] Parity register #0 read */ 41#define ATC_REG_ATC_PRTY_STS 0x1101cc 42/* [RC 5] Parity register #0 read clear */ 43#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 44/* [RW 19] Interrupt mask register #0 read/write */ 45#define BRB1_REG_BRB1_INT_MASK 0x60128 46/* [R 19] Interrupt register #0 read */ 47#define BRB1_REG_BRB1_INT_STS 0x6011c 48/* [RW 4] Parity mask register #0 read/write */ 49#define BRB1_REG_BRB1_PRTY_MASK 0x60138 50/* [R 4] Parity register #0 read */ 51#define BRB1_REG_BRB1_PRTY_STS 0x6012c 52/* [RC 4] Parity register #0 read clear */ 53#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130 54/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At 55 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address 56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - 57 * following reset the first rbc access to this reg must be write; there can 58 * be no more rbc writes after the first one; there can be any number of rbc 59 * read following the first write; rbc access not following these rules will 60 * result in hang condition. */ 61#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 62/* [RW 10] The number of free blocks below which the full signal to class 0 63 * is asserted */ 64#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 65#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230 66/* [RW 11] The number of free blocks above which the full signal to class 0 67 * is de-asserted */ 68#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 69#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234 70/* [RW 11] The number of free blocks below which the full signal to class 1 71 * is asserted */ 72#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 73#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238 74/* [RW 11] The number of free blocks above which the full signal to class 1 75 * is de-asserted */ 76#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 77#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c 78/* [RW 11] The number of free blocks below which the full signal to the LB 79 * port is asserted */ 80#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 81/* [RW 10] The number of free blocks above which the full signal to the LB 82 * port is de-asserted */ 83#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4 84/* [RW 10] The number of free blocks above which the High_llfc signal to 85 interface #n is de-asserted. */ 86#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c 87/* [RW 10] The number of free blocks below which the High_llfc signal to 88 interface #n is asserted. */ 89#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 90/* [RW 11] The number of blocks guarantied for the LB port */ 91#define BRB1_REG_LB_GUARANTIED 0x601ec 92/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port 93 * before signaling XON. */ 94#define BRB1_REG_LB_GUARANTIED_HYST 0x60264 95/* [RW 24] LL RAM data. */ 96#define BRB1_REG_LL_RAM 0x61000 97/* [RW 10] The number of free blocks above which the Low_llfc signal to 98 interface #n is de-asserted. */ 99#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 100/* [RW 10] The number of free blocks below which the Low_llfc signal to 101 interface #n is asserted. */ 102#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 103/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The 104 * register is applicable only when per_class_guaranty_mode is set. */ 105#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244 106/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 107 * 1 before signaling XON. The register is applicable only when 108 * per_class_guaranty_mode is set. */ 109#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254 110/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The 111 * register is applicable only when per_class_guaranty_mode is set. */ 112#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248 113/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0 114 * before signaling XON. The register is applicable only when 115 * per_class_guaranty_mode is set. */ 116#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258 117/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register 118 * is applicable only when per_class_guaranty_mode is set. */ 119#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c 120/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 121 * 1 before signaling XON. The register is applicable only when 122 * per_class_guaranty_mode is set. */ 123#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c 124/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The 125 * register is applicable only when per_class_guaranty_mode is set. */ 126#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250 127/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC 128 * 1 before signaling XON. The register is applicable only when 129 * per_class_guaranty_mode is set. */ 130#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260 131/* [RW 11] The number of blocks guarantied for the MAC port. The register is 132 * applicable only when per_class_guaranty_mode is reset. */ 133#define BRB1_REG_MAC_GUARANTIED_0 0x601e8 134#define BRB1_REG_MAC_GUARANTIED_1 0x60240 135/* [R 24] The number of full blocks. */ 136#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 137/* [ST 32] The number of cycles that the write_full signal towards MAC #0 138 was asserted. */ 139#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 140#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 141#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 142/* [ST 32] The number of cycles that the pause signal towards MAC #0 was 143 asserted. */ 144#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 145#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 146/* [RW 10] The number of free blocks below which the pause signal to class 0 147 * is asserted */ 148#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 149#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220 150/* [RW 11] The number of free blocks above which the pause signal to class 0 151 * is de-asserted */ 152#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 153#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224 154/* [RW 11] The number of free blocks below which the pause signal to class 1 155 * is asserted */ 156#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 157#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228 158/* [RW 11] The number of free blocks above which the pause signal to class 1 159 * is de-asserted */ 160#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 161#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c 162/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 163#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 164#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 165/* [RW 10] Write client 0: Assert pause threshold. */ 166#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 167/* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC 168 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC 169 * mode). 1=per-class guaranty mode (new mode). */ 170#define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268 171/* [R 24] The number of full blocks occpied by port. */ 172#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 173/* [RW 1] Reset the design by software. */ 174#define BRB1_REG_SOFT_RESET 0x600dc 175/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 176#define CCM_REG_CAM_OCCUP 0xd0188 177/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 178 acknowledge output is deasserted; all other signals are treated as usual; 179 if 1 - normal activity. */ 180#define CCM_REG_CCM_CFC_IFEN 0xd003c 181/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 182 disregarded; valid is deasserted; all other signals are treated as usual; 183 if 1 - normal activity. */ 184#define CCM_REG_CCM_CQM_IFEN 0xd000c 185/* [RW 1] If set the Q index; received from the QM is inserted to event ID. 186 Otherwise 0 is inserted. */ 187#define CCM_REG_CCM_CQM_USE_Q 0xd00c0 188/* [RW 11] Interrupt mask register #0 read/write */ 189#define CCM_REG_CCM_INT_MASK 0xd01e4 190/* [R 11] Interrupt register #0 read */ 191#define CCM_REG_CCM_INT_STS 0xd01d8 192/* [RW 27] Parity mask register #0 read/write */ 193#define CCM_REG_CCM_PRTY_MASK 0xd01f4 194/* [R 27] Parity register #0 read */ 195#define CCM_REG_CCM_PRTY_STS 0xd01e8 196/* [RC 27] Parity register #0 read clear */ 197#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec 198/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 199 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 200 Is used to determine the number of the AG context REG-pairs written back; 201 when the input message Reg1WbFlg isn't set. */ 202#define CCM_REG_CCM_REG0_SZ 0xd00c4 203/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 204 disregarded; valid is deasserted; all other signals are treated as usual; 205 if 1 - normal activity. */ 206#define CCM_REG_CCM_STORM0_IFEN 0xd0004 207/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 208 disregarded; valid is deasserted; all other signals are treated as usual; 209 if 1 - normal activity. */ 210#define CCM_REG_CCM_STORM1_IFEN 0xd0008 211/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 212 disregarded; valid output is deasserted; all other signals are treated as 213 usual; if 1 - normal activity. */ 214#define CCM_REG_CDU_AG_RD_IFEN 0xd0030 215/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 216 are disregarded; all other signals are treated as usual; if 1 - normal 217 activity. */ 218#define CCM_REG_CDU_AG_WR_IFEN 0xd002c 219/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 220 disregarded; valid output is deasserted; all other signals are treated as 221 usual; if 1 - normal activity. */ 222#define CCM_REG_CDU_SM_RD_IFEN 0xd0038 223/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 224 input is disregarded; all other signals are treated as usual; if 1 - 225 normal activity. */ 226#define CCM_REG_CDU_SM_WR_IFEN 0xd0034 227/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 228 the initial credit value; read returns the current value of the credit 229 counter. Must be initialized to 1 at start-up. */ 230#define CCM_REG_CFC_INIT_CRD 0xd0204 231/* [RW 2] Auxiliary counter flag Q number 1. */ 232#define CCM_REG_CNT_AUX1_Q 0xd00c8 233/* [RW 2] Auxiliary counter flag Q number 2. */ 234#define CCM_REG_CNT_AUX2_Q 0xd00cc 235/* [RW 28] The CM header value for QM request (primary). */ 236#define CCM_REG_CQM_CCM_HDR_P 0xd008c 237/* [RW 28] The CM header value for QM request (secondary). */ 238#define CCM_REG_CQM_CCM_HDR_S 0xd0090 239/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 240 acknowledge output is deasserted; all other signals are treated as usual; 241 if 1 - normal activity. */ 242#define CCM_REG_CQM_CCM_IFEN 0xd0014 243/* [RW 6] QM output initial credit. Max credit available - 32. Write writes 244 the initial credit value; read returns the current value of the credit 245 counter. Must be initialized to 32 at start-up. */ 246#define CCM_REG_CQM_INIT_CRD 0xd020c 247/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 248 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 249 prioritised); 2 stands for weight 2; tc. */ 250#define CCM_REG_CQM_P_WEIGHT 0xd00b8 251/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 252 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 253 prioritised); 2 stands for weight 2; tc. */ 254#define CCM_REG_CQM_S_WEIGHT 0xd00bc 255/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 256 acknowledge output is deasserted; all other signals are treated as usual; 257 if 1 - normal activity. */ 258#define CCM_REG_CSDM_IFEN 0xd0018 259/* [RC 1] Set when the message length mismatch (relative to last indication) 260 at the SDM interface is detected. */ 261#define CCM_REG_CSDM_LENGTH_MIS 0xd0170 262/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 263 weight 8 (the most prioritised); 1 stands for weight 1(least 264 prioritised); 2 stands for weight 2; tc. */ 265#define CCM_REG_CSDM_WEIGHT 0xd00b4 266/* [RW 28] The CM header for QM formatting in case of an error in the QM 267 inputs. */ 268#define CCM_REG_ERR_CCM_HDR 0xd0094 269/* [RW 8] The Event ID in case the input message ErrorFlg is set. */ 270#define CCM_REG_ERR_EVNT_ID 0xd0098 271/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 272 writes the initial credit value; read returns the current value of the 273 credit counter. Must be initialized to 64 at start-up. */ 274#define CCM_REG_FIC0_INIT_CRD 0xd0210 275/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 276 writes the initial credit value; read returns the current value of the 277 credit counter. Must be initialized to 64 at start-up. */ 278#define CCM_REG_FIC1_INIT_CRD 0xd0214 279/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 280 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; 281 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and 282 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and 283 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ 284#define CCM_REG_GR_ARB_TYPE 0xd015c 285/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 286 highest priority is 3. It is supposed; that the Store channel priority is 287 the compliment to 4 of the rest priorities - Aggregation channel; Load 288 (FIC0) channel and Load (FIC1). */ 289#define CCM_REG_GR_LD0_PR 0xd0164 290/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 291 highest priority is 3. It is supposed; that the Store channel priority is 292 the compliment to 4 of the rest priorities - Aggregation channel; Load 293 (FIC0) channel and Load (FIC1). */ 294#define CCM_REG_GR_LD1_PR 0xd0168 295/* [RW 2] General flags index. */ 296#define CCM_REG_INV_DONE_Q 0xd0108 297/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM 298 context and sent to STORM; for a specific connection type. The double 299 REG-pairs are used in order to align to STORM context row size of 128 300 bits. The offset of these data in the STORM context is always 0. Index 301 _(0..15) stands for the connection type (one of 16). */ 302#define CCM_REG_N_SM_CTX_LD_0 0xd004c 303#define CCM_REG_N_SM_CTX_LD_1 0xd0050 304#define CCM_REG_N_SM_CTX_LD_2 0xd0054 305#define CCM_REG_N_SM_CTX_LD_3 0xd0058 306#define CCM_REG_N_SM_CTX_LD_4 0xd005c 307/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 308 acknowledge output is deasserted; all other signals are treated as usual; 309 if 1 - normal activity. */ 310#define CCM_REG_PBF_IFEN 0xd0028 311/* [RC 1] Set when the message length mismatch (relative to last indication) 312 at the pbf interface is detected. */ 313#define CCM_REG_PBF_LENGTH_MIS 0xd0180 314/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 315 weight 8 (the most prioritised); 1 stands for weight 1(least 316 prioritised); 2 stands for weight 2; tc. */ 317#define CCM_REG_PBF_WEIGHT 0xd00ac 318#define CCM_REG_PHYS_QNUM1_0 0xd0134 319#define CCM_REG_PHYS_QNUM1_1 0xd0138 320#define CCM_REG_PHYS_QNUM2_0 0xd013c 321#define CCM_REG_PHYS_QNUM2_1 0xd0140 322#define CCM_REG_PHYS_QNUM3_0 0xd0144 323#define CCM_REG_PHYS_QNUM3_1 0xd0148 324#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 325#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 326#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 327#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 328#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 329#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 330#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c 331#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 332/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 333 disregarded; acknowledge output is deasserted; all other signals are 334 treated as usual; if 1 - normal activity. */ 335#define CCM_REG_STORM_CCM_IFEN 0xd0010 336/* [RC 1] Set when the message length mismatch (relative to last indication) 337 at the STORM interface is detected. */ 338#define CCM_REG_STORM_LENGTH_MIS 0xd016c 339/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) 340 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for 341 weight 1(least prioritised); 2 stands for weight 2 (more prioritised); 342 tc. */ 343#define CCM_REG_STORM_WEIGHT 0xd009c 344/* [RW 1] Input tsem Interface enable. If 0 - the valid input is 345 disregarded; acknowledge output is deasserted; all other signals are 346 treated as usual; if 1 - normal activity. */ 347#define CCM_REG_TSEM_IFEN 0xd001c 348/* [RC 1] Set when the message length mismatch (relative to last indication) 349 at the tsem interface is detected. */ 350#define CCM_REG_TSEM_LENGTH_MIS 0xd0174 351/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 352 weight 8 (the most prioritised); 1 stands for weight 1(least 353 prioritised); 2 stands for weight 2; tc. */ 354#define CCM_REG_TSEM_WEIGHT 0xd00a0 355/* [RW 1] Input usem Interface enable. If 0 - the valid input is 356 disregarded; acknowledge output is deasserted; all other signals are 357 treated as usual; if 1 - normal activity. */ 358#define CCM_REG_USEM_IFEN 0xd0024 359/* [RC 1] Set when message length mismatch (relative to last indication) at 360 the usem interface is detected. */ 361#define CCM_REG_USEM_LENGTH_MIS 0xd017c 362/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 363 weight 8 (the most prioritised); 1 stands for weight 1(least 364 prioritised); 2 stands for weight 2; tc. */ 365#define CCM_REG_USEM_WEIGHT 0xd00a8 366/* [RW 1] Input xsem Interface enable. If 0 - the valid input is 367 disregarded; acknowledge output is deasserted; all other signals are 368 treated as usual; if 1 - normal activity. */ 369#define CCM_REG_XSEM_IFEN 0xd0020 370/* [RC 1] Set when the message length mismatch (relative to last indication) 371 at the xsem interface is detected. */ 372#define CCM_REG_XSEM_LENGTH_MIS 0xd0178 373/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 374 weight 8 (the most prioritised); 1 stands for weight 1(least 375 prioritised); 2 stands for weight 2; tc. */ 376#define CCM_REG_XSEM_WEIGHT 0xd00a4 377/* [RW 19] Indirect access to the descriptor table of the XX protection 378 mechanism. The fields are: [5:0] - message length; [12:6] - message 379 pointer; 18:13] - next pointer. */ 380#define CCM_REG_XX_DESCR_TABLE 0xd0300 381#define CCM_REG_XX_DESCR_TABLE_SIZE 24 382/* [R 7] Used to read the value of XX protection Free counter. */ 383#define CCM_REG_XX_FREE 0xd0184 384/* [RW 6] Initial value for the credit counter; responsible for fulfilling 385 of the Input Stage XX protection buffer by the XX protection pending 386 messages. Max credit available - 127. Write writes the initial credit 387 value; read returns the current value of the credit counter. Must be 388 initialized to maximum XX protected message size - 2 at start-up. */ 389#define CCM_REG_XX_INIT_CRD 0xd0220 390/* [RW 7] The maximum number of pending messages; which may be stored in XX 391 protection. At read the ~ccm_registers_xx_free.xx_free counter is read. 392 At write comprises the start value of the ~ccm_registers_xx_free.xx_free 393 counter. */ 394#define CCM_REG_XX_MSG_NUM 0xd0224 395/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 396#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 397/* [RW 18] Indirect access to the XX table of the XX protection mechanism. 398 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - 399 header pointer. */ 400#define CCM_REG_XX_TABLE 0xd0280 401#define CDU_REG_CDU_CHK_MASK0 0x101000 402#define CDU_REG_CDU_CHK_MASK1 0x101004 403#define CDU_REG_CDU_CONTROL0 0x101008 404#define CDU_REG_CDU_DEBUG 0x101010 405#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 406/* [RW 7] Interrupt mask register #0 read/write */ 407#define CDU_REG_CDU_INT_MASK 0x10103c 408/* [R 7] Interrupt register #0 read */ 409#define CDU_REG_CDU_INT_STS 0x101030 410/* [RW 5] Parity mask register #0 read/write */ 411#define CDU_REG_CDU_PRTY_MASK 0x10104c 412/* [R 5] Parity register #0 read */ 413#define CDU_REG_CDU_PRTY_STS 0x101040 414/* [RC 5] Parity register #0 read clear */ 415#define CDU_REG_CDU_PRTY_STS_CLR 0x101044 416/* [RC 32] logging of error data in case of a CDU load error: 417 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 418 ype_error; ctual_active; ctual_compressed_context}; */ 419#define CDU_REG_ERROR_DATA 0x101014 420/* [WB 216] L1TT ram access. each entry has the following format : 421 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; 422 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ 423#define CDU_REG_L1TT 0x101800 424/* [WB 24] MATT ram access. each entry has the following 425 format:{RegionLength[11:0]; egionOffset[11:0]} */ 426#define CDU_REG_MATT 0x101100 427/* [RW 1] when this bit is set the CDU operates in e1hmf mode */ 428#define CDU_REG_MF_MODE 0x101050 429/* [R 1] indication the initializing the activity counter by the hardware 430 was done. */ 431#define CFC_REG_AC_INIT_DONE 0x104078 432/* [RW 13] activity counter ram access */ 433#define CFC_REG_ACTIVITY_COUNTER 0x104400 434#define CFC_REG_ACTIVITY_COUNTER_SIZE 256 435/* [R 1] indication the initializing the cams by the hardware was done. */ 436#define CFC_REG_CAM_INIT_DONE 0x10407c 437/* [RW 2] Interrupt mask register #0 read/write */ 438#define CFC_REG_CFC_INT_MASK 0x104108 439/* [R 2] Interrupt register #0 read */ 440#define CFC_REG_CFC_INT_STS 0x1040fc 441/* [RC 2] Interrupt register #0 read clear */ 442#define CFC_REG_CFC_INT_STS_CLR 0x104100 443/* [RW 4] Parity mask register #0 read/write */ 444#define CFC_REG_CFC_PRTY_MASK 0x104118 445/* [R 4] Parity register #0 read */ 446#define CFC_REG_CFC_PRTY_STS 0x10410c 447/* [RC 4] Parity register #0 read clear */ 448#define CFC_REG_CFC_PRTY_STS_CLR 0x104110 449/* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 450#define CFC_REG_CID_CAM 0x104800 451#define CFC_REG_CONTROL0 0x104028 452#define CFC_REG_DEBUG0 0x104050 453/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error 454 vector) whether the cfc should be disabled upon it */ 455#define CFC_REG_DISABLE_ON_ERROR 0x104044 456/* [RC 14] CFC error vector. when the CFC detects an internal error it will 457 set one of these bits. the bit description can be found in CFC 458 specifications */ 459#define CFC_REG_ERROR_VECTOR 0x10403c 460/* [WB 93] LCID info ram access */ 461#define CFC_REG_INFO_RAM 0x105000 462#define CFC_REG_INFO_RAM_SIZE 1024 463#define CFC_REG_INIT_REG 0x10404c 464#define CFC_REG_INTERFACES 0x104058 465/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this 466 field allows changing the priorities of the weighted-round-robin arbiter 467 which selects which CFC load client should be served next */ 468#define CFC_REG_LCREQ_WEIGHTS 0x104084 469/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ 470#define CFC_REG_LINK_LIST 0x104c00 471#define CFC_REG_LINK_LIST_SIZE 256 472/* [R 1] indication the initializing the link list by the hardware was done. */ 473#define CFC_REG_LL_INIT_DONE 0x104074 474/* [R 9] Number of allocated LCIDs which are at empty state */ 475#define CFC_REG_NUM_LCIDS_ALLOC 0x104020 476/* [R 9] Number of Arriving LCIDs in Link List Block */ 477#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 478#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120 479/* [R 9] Number of Leaving LCIDs in Link List Block */ 480#define CFC_REG_NUM_LCIDS_LEAVING 0x104018 481#define CFC_REG_WEAK_ENABLE_PF 0x104124 482/* [RW 8] The event id for aggregated interrupt 0 */ 483#define CSDM_REG_AGG_INT_EVENT_0 0xc2038 484#define CSDM_REG_AGG_INT_EVENT_10 0xc2060 485#define CSDM_REG_AGG_INT_EVENT_11 0xc2064 486#define CSDM_REG_AGG_INT_EVENT_12 0xc2068 487#define CSDM_REG_AGG_INT_EVENT_13 0xc206c 488#define CSDM_REG_AGG_INT_EVENT_14 0xc2070 489#define CSDM_REG_AGG_INT_EVENT_15 0xc2074 490#define CSDM_REG_AGG_INT_EVENT_16 0xc2078 491#define CSDM_REG_AGG_INT_EVENT_2 0xc2040 492#define CSDM_REG_AGG_INT_EVENT_3 0xc2044 493#define CSDM_REG_AGG_INT_EVENT_4 0xc2048 494#define CSDM_REG_AGG_INT_EVENT_5 0xc204c 495#define CSDM_REG_AGG_INT_EVENT_6 0xc2050 496#define CSDM_REG_AGG_INT_EVENT_7 0xc2054 497#define CSDM_REG_AGG_INT_EVENT_8 0xc2058 498#define CSDM_REG_AGG_INT_EVENT_9 0xc205c 499/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 500 or auto-mask-mode (1) */ 501#define CSDM_REG_AGG_INT_MODE_10 0xc21e0 502#define CSDM_REG_AGG_INT_MODE_11 0xc21e4 503#define CSDM_REG_AGG_INT_MODE_12 0xc21e8 504#define CSDM_REG_AGG_INT_MODE_13 0xc21ec 505#define CSDM_REG_AGG_INT_MODE_14 0xc21f0 506#define CSDM_REG_AGG_INT_MODE_15 0xc21f4 507#define CSDM_REG_AGG_INT_MODE_16 0xc21f8 508#define CSDM_REG_AGG_INT_MODE_6 0xc21d0 509#define CSDM_REG_AGG_INT_MODE_7 0xc21d4 510#define CSDM_REG_AGG_INT_MODE_8 0xc21d8 511#define CSDM_REG_AGG_INT_MODE_9 0xc21dc 512/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 513#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 514/* [RW 16] The maximum value of the completion counter #0 */ 515#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c 516/* [RW 16] The maximum value of the completion counter #1 */ 517#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 518/* [RW 16] The maximum value of the completion counter #2 */ 519#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 520/* [RW 16] The maximum value of the completion counter #3 */ 521#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 522/* [RW 13] The start address in the internal RAM for the completion 523 counters. */ 524#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c 525/* [RW 32] Interrupt mask register #0 read/write */ 526#define CSDM_REG_CSDM_INT_MASK_0 0xc229c 527#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 528/* [R 32] Interrupt register #0 read */ 529#define CSDM_REG_CSDM_INT_STS_0 0xc2290 530#define CSDM_REG_CSDM_INT_STS_1 0xc22a0 531/* [RW 11] Parity mask register #0 read/write */ 532#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 533/* [R 11] Parity register #0 read */ 534#define CSDM_REG_CSDM_PRTY_STS 0xc22b0 535/* [RC 11] Parity register #0 read clear */ 536#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4 537#define CSDM_REG_ENABLE_IN1 0xc2238 538#define CSDM_REG_ENABLE_IN2 0xc223c 539#define CSDM_REG_ENABLE_OUT1 0xc2240 540#define CSDM_REG_ENABLE_OUT2 0xc2244 541/* [RW 4] The initial number of messages that can be sent to the pxp control 542 interface without receiving any ACK. */ 543#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc 544/* [ST 32] The number of ACK after placement messages received */ 545#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c 546/* [ST 32] The number of packet end messages received from the parser */ 547#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 548/* [ST 32] The number of requests received from the pxp async if */ 549#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 550/* [ST 32] The number of commands received in queue 0 */ 551#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 552/* [ST 32] The number of commands received in queue 10 */ 553#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c 554/* [ST 32] The number of commands received in queue 11 */ 555#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 556/* [ST 32] The number of commands received in queue 1 */ 557#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c 558/* [ST 32] The number of commands received in queue 3 */ 559#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 560/* [ST 32] The number of commands received in queue 4 */ 561#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 562/* [ST 32] The number of commands received in queue 5 */ 563#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 564/* [ST 32] The number of commands received in queue 6 */ 565#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c 566/* [ST 32] The number of commands received in queue 7 */ 567#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 568/* [ST 32] The number of commands received in queue 8 */ 569#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 570/* [ST 32] The number of commands received in queue 9 */ 571#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 572/* [RW 13] The start address in the internal RAM for queue counters */ 573#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 574/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 575#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 576/* [R 1] parser fifo empty in sdm_sync block */ 577#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 578/* [R 1] parser serial fifo empty in sdm_sync block */ 579#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 580/* [RW 32] Tick for timer counter. Applicable only when 581 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ 582#define CSDM_REG_TIMER_TICK 0xc2000 583/* [RW 5] The number of time_slots in the arbitration cycle */ 584#define CSEM_REG_ARB_CYCLE_SIZE 0x200034 585/* [RW 3] The source that is associated with arbitration element 0. Source 586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 587 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 588#define CSEM_REG_ARB_ELEMENT0 0x200020 589/* [RW 3] The source that is associated with arbitration element 1. Source 590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 591 sleeping thread with priority 1; 4- sleeping thread with priority 2. 592 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ 593#define CSEM_REG_ARB_ELEMENT1 0x200024 594/* [RW 3] The source that is associated with arbitration element 2. Source 595 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 596 sleeping thread with priority 1; 4- sleeping thread with priority 2. 597 Could not be equal to register ~csem_registers_arb_element0.arb_element0 598 and ~csem_registers_arb_element1.arb_element1 */ 599#define CSEM_REG_ARB_ELEMENT2 0x200028 600/* [RW 3] The source that is associated with arbitration element 3. Source 601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 602 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 603 not be equal to register ~csem_registers_arb_element0.arb_element0 and 604 ~csem_registers_arb_element1.arb_element1 and 605 ~csem_registers_arb_element2.arb_element2 */ 606#define CSEM_REG_ARB_ELEMENT3 0x20002c 607/* [RW 3] The source that is associated with arbitration element 4. Source 608 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 609 sleeping thread with priority 1; 4- sleeping thread with priority 2. 610 Could not be equal to register ~csem_registers_arb_element0.arb_element0 611 and ~csem_registers_arb_element1.arb_element1 and 612 ~csem_registers_arb_element2.arb_element2 and 613 ~csem_registers_arb_element3.arb_element3 */ 614#define CSEM_REG_ARB_ELEMENT4 0x200030 615/* [RW 32] Interrupt mask register #0 read/write */ 616#define CSEM_REG_CSEM_INT_MASK_0 0x200110 617#define CSEM_REG_CSEM_INT_MASK_1 0x200120 618/* [R 32] Interrupt register #0 read */ 619#define CSEM_REG_CSEM_INT_STS_0 0x200104 620#define CSEM_REG_CSEM_INT_STS_1 0x200114 621/* [RW 32] Parity mask register #0 read/write */ 622#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 623#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 624/* [R 32] Parity register #0 read */ 625#define CSEM_REG_CSEM_PRTY_STS_0 0x200124 626#define CSEM_REG_CSEM_PRTY_STS_1 0x200134 627/* [RC 32] Parity register #0 read clear */ 628#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128 629#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138 630#define CSEM_REG_ENABLE_IN 0x2000a4 631#define CSEM_REG_ENABLE_OUT 0x2000a8 632/* [RW 32] This address space contains all registers and memories that are 633 placed in SEM_FAST block. The SEM_FAST registers are described in 634 appendix B. In order to access the sem_fast registers the base address 635 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 636#define CSEM_REG_FAST_MEMORY 0x220000 637/* [RW 1] Disables input messages from FIC0 May be updated during run_time 638 by the microcode */ 639#define CSEM_REG_FIC0_DISABLE 0x200224 640/* [RW 1] Disables input messages from FIC1 May be updated during run_time 641 by the microcode */ 642#define CSEM_REG_FIC1_DISABLE 0x200234 643/* [RW 15] Interrupt table Read and write access to it is not possible in 644 the middle of the work */ 645#define CSEM_REG_INT_TABLE 0x200400 646/* [ST 24] Statistics register. The number of messages that entered through 647 FIC0 */ 648#define CSEM_REG_MSG_NUM_FIC0 0x200000 649/* [ST 24] Statistics register. The number of messages that entered through 650 FIC1 */ 651#define CSEM_REG_MSG_NUM_FIC1 0x200004 652/* [ST 24] Statistics register. The number of messages that were sent to 653 FOC0 */ 654#define CSEM_REG_MSG_NUM_FOC0 0x200008 655/* [ST 24] Statistics register. The number of messages that were sent to 656 FOC1 */ 657#define CSEM_REG_MSG_NUM_FOC1 0x20000c 658/* [ST 24] Statistics register. The number of messages that were sent to 659 FOC2 */ 660#define CSEM_REG_MSG_NUM_FOC2 0x200010 661/* [ST 24] Statistics register. The number of messages that were sent to 662 FOC3 */ 663#define CSEM_REG_MSG_NUM_FOC3 0x200014 664/* [RW 1] Disables input messages from the passive buffer May be updated 665 during run_time by the microcode */ 666#define CSEM_REG_PAS_DISABLE 0x20024c 667/* [WB 128] Debug only. Passive buffer memory */ 668#define CSEM_REG_PASSIVE_BUFFER 0x202000 669/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 670#define CSEM_REG_PRAM 0x240000 671/* [R 16] Valid sleeping threads indication have bit per thread */ 672#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 673/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 674#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 675/* [RW 16] List of free threads . There is a bit per thread. */ 676#define CSEM_REG_THREADS_LIST 0x2002e4 677/* [RW 3] The arbitration scheme of time_slot 0 */ 678#define CSEM_REG_TS_0_AS 0x200038 679/* [RW 3] The arbitration scheme of time_slot 10 */ 680#define CSEM_REG_TS_10_AS 0x200060 681/* [RW 3] The arbitration scheme of time_slot 11 */ 682#define CSEM_REG_TS_11_AS 0x200064 683/* [RW 3] The arbitration scheme of time_slot 12 */ 684#define CSEM_REG_TS_12_AS 0x200068 685/* [RW 3] The arbitration scheme of time_slot 13 */ 686#define CSEM_REG_TS_13_AS 0x20006c 687/* [RW 3] The arbitration scheme of time_slot 14 */ 688#define CSEM_REG_TS_14_AS 0x200070 689/* [RW 3] The arbitration scheme of time_slot 15 */ 690#define CSEM_REG_TS_15_AS 0x200074 691/* [RW 3] The arbitration scheme of time_slot 16 */ 692#define CSEM_REG_TS_16_AS 0x200078 693/* [RW 3] The arbitration scheme of time_slot 17 */ 694#define CSEM_REG_TS_17_AS 0x20007c 695/* [RW 3] The arbitration scheme of time_slot 18 */ 696#define CSEM_REG_TS_18_AS 0x200080 697/* [RW 3] The arbitration scheme of time_slot 1 */ 698#define CSEM_REG_TS_1_AS 0x20003c 699/* [RW 3] The arbitration scheme of time_slot 2 */ 700#define CSEM_REG_TS_2_AS 0x200040 701/* [RW 3] The arbitration scheme of time_slot 3 */ 702#define CSEM_REG_TS_3_AS 0x200044 703/* [RW 3] The arbitration scheme of time_slot 4 */ 704#define CSEM_REG_TS_4_AS 0x200048 705/* [RW 3] The arbitration scheme of time_slot 5 */ 706#define CSEM_REG_TS_5_AS 0x20004c 707/* [RW 3] The arbitration scheme of time_slot 6 */ 708#define CSEM_REG_TS_6_AS 0x200050 709/* [RW 3] The arbitration scheme of time_slot 7 */ 710#define CSEM_REG_TS_7_AS 0x200054 711/* [RW 3] The arbitration scheme of time_slot 8 */ 712#define CSEM_REG_TS_8_AS 0x200058 713/* [RW 3] The arbitration scheme of time_slot 9 */ 714#define CSEM_REG_TS_9_AS 0x20005c 715/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 716 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 717#define CSEM_REG_VFPF_ERR_NUM 0x200380 718/* [RW 1] Parity mask register #0 read/write */ 719#define DBG_REG_DBG_PRTY_MASK 0xc0a8 720/* [R 1] Parity register #0 read */ 721#define DBG_REG_DBG_PRTY_STS 0xc09c 722/* [RC 1] Parity register #0 read clear */ 723#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0 724/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The 725 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 726 * 4.Completion function=0; 5.Error handling=0 */ 727#define DMAE_REG_BACKWARD_COMP_EN 0x10207c 728/* [RW 32] Commands memory. The address to command X; row Y is to calculated 729 as 14*X+Y. */ 730#define DMAE_REG_CMD_MEM 0x102400 731#define DMAE_REG_CMD_MEM_SIZE 224 732/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 733 initial value is all ones. */ 734#define DMAE_REG_CRC16C_INIT 0x10201c 735/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the 736 CRC-16 T10 initial value is all ones. */ 737#define DMAE_REG_CRC16T10_INIT 0x102020 738/* [RW 2] Interrupt mask register #0 read/write */ 739#define DMAE_REG_DMAE_INT_MASK 0x102054 740/* [RW 4] Parity mask register #0 read/write */ 741#define DMAE_REG_DMAE_PRTY_MASK 0x102064 742/* [R 4] Parity register #0 read */ 743#define DMAE_REG_DMAE_PRTY_STS 0x102058 744/* [RC 4] Parity register #0 read clear */ 745#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c 746/* [RW 1] Command 0 go. */ 747#define DMAE_REG_GO_C0 0x102080 748/* [RW 1] Command 1 go. */ 749#define DMAE_REG_GO_C1 0x102084 750/* [RW 1] Command 10 go. */ 751#define DMAE_REG_GO_C10 0x102088 752/* [RW 1] Command 11 go. */ 753#define DMAE_REG_GO_C11 0x10208c 754/* [RW 1] Command 12 go. */ 755#define DMAE_REG_GO_C12 0x102090 756/* [RW 1] Command 13 go. */ 757#define DMAE_REG_GO_C13 0x102094 758/* [RW 1] Command 14 go. */ 759#define DMAE_REG_GO_C14 0x102098 760/* [RW 1] Command 15 go. */ 761#define DMAE_REG_GO_C15 0x10209c 762/* [RW 1] Command 2 go. */ 763#define DMAE_REG_GO_C2 0x1020a0 764/* [RW 1] Command 3 go. */ 765#define DMAE_REG_GO_C3 0x1020a4 766/* [RW 1] Command 4 go. */ 767#define DMAE_REG_GO_C4 0x1020a8 768/* [RW 1] Command 5 go. */ 769#define DMAE_REG_GO_C5 0x1020ac 770/* [RW 1] Command 6 go. */ 771#define DMAE_REG_GO_C6 0x1020b0 772/* [RW 1] Command 7 go. */ 773#define DMAE_REG_GO_C7 0x1020b4 774/* [RW 1] Command 8 go. */ 775#define DMAE_REG_GO_C8 0x1020b8 776/* [RW 1] Command 9 go. */ 777#define DMAE_REG_GO_C9 0x1020bc 778/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge 779 input is disregarded; valid is deasserted; all other signals are treated 780 as usual; if 1 - normal activity. */ 781#define DMAE_REG_GRC_IFEN 0x102008 782/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the 783 acknowledge input is disregarded; valid is deasserted; full is asserted; 784 all other signals are treated as usual; if 1 - normal activity. */ 785#define DMAE_REG_PCI_IFEN 0x102004 786/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the 787 initial value to the credit counter; related to the address. Read returns 788 the current value of the counter. */ 789#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 790/* [RW 8] Aggregation command. */ 791#define DORQ_REG_AGG_CMD0 0x170060 792/* [RW 8] Aggregation command. */ 793#define DORQ_REG_AGG_CMD1 0x170064 794/* [RW 8] Aggregation command. */ 795#define DORQ_REG_AGG_CMD2 0x170068 796/* [RW 8] Aggregation command. */ 797#define DORQ_REG_AGG_CMD3 0x17006c 798/* [RW 28] UCM Header. */ 799#define DORQ_REG_CMHEAD_RX 0x170050 800/* [RW 32] Doorbell address for RBC doorbells (function 0). */ 801#define DORQ_REG_DB_ADDR0 0x17008c 802/* [RW 5] Interrupt mask register #0 read/write */ 803#define DORQ_REG_DORQ_INT_MASK 0x170180 804/* [R 5] Interrupt register #0 read */ 805#define DORQ_REG_DORQ_INT_STS 0x170174 806/* [RC 5] Interrupt register #0 read clear */ 807#define DORQ_REG_DORQ_INT_STS_CLR 0x170178 808/* [RW 2] Parity mask register #0 read/write */ 809#define DORQ_REG_DORQ_PRTY_MASK 0x170190 810/* [R 2] Parity register #0 read */ 811#define DORQ_REG_DORQ_PRTY_STS 0x170184 812/* [RC 2] Parity register #0 read clear */ 813#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188 814/* [RW 8] The address to write the DPM CID to STORM. */ 815#define DORQ_REG_DPM_CID_ADDR 0x170044 816/* [RW 5] The DPM mode CID extraction offset. */ 817#define DORQ_REG_DPM_CID_OFST 0x170030 818/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ 819#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c 820/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ 821#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 822/* [R 13] Current value of the DQ FIFO fill level according to following 823 pointer. The range is 0 - 256 FIFO rows; where each row stands for the 824 doorbell. */ 825#define DORQ_REG_DQ_FILL_LVLF 0x1700a4 826/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 827 equal to full threshold; reset on full clear. */ 828#define DORQ_REG_DQ_FULL_ST 0x1700c0 829/* [RW 28] The value sent to CM header in the case of CFC load error. */ 830#define DORQ_REG_ERR_CMHEAD 0x170058 831#define DORQ_REG_IF_EN 0x170004 832#define DORQ_REG_MAX_RVFID_SIZE 0x1701ec 833#define DORQ_REG_MODE_ACT 0x170008 834/* [RW 5] The normal mode CID extraction offset. */ 835#define DORQ_REG_NORM_CID_OFST 0x17002c 836/* [RW 28] TCM Header when only TCP context is loaded. */ 837#define DORQ_REG_NORM_CMHEAD_TX 0x17004c 838/* [RW 3] The number of simultaneous outstanding requests to Context Fetch 839 Interface. */ 840#define DORQ_REG_OUTST_REQ 0x17003c 841#define DORQ_REG_PF_USAGE_CNT 0x1701d0 842#define DORQ_REG_REGN 0x170038 843/* [R 4] Current value of response A counter credit. Initial credit is 844 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 845 register. */ 846#define DORQ_REG_RSPA_CRD_CNT 0x1700ac 847/* [R 4] Current value of response B counter credit. Initial credit is 848 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 849 register. */ 850#define DORQ_REG_RSPB_CRD_CNT 0x1700b0 851/* [RW 4] The initial credit at the Doorbell Response Interface. The write 852 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The 853 read reads this written value. */ 854#define DORQ_REG_RSP_INIT_CRD 0x170048 855#define DORQ_REG_RSPB_CRD_CNT 0x1700b0 856#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0 857#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4 858#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4 859#define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4 860#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8 861/* [RW 10] VF type validation mask value */ 862#define DORQ_REG_VF_TYPE_MASK_0 0x170218 863/* [RW 17] VF type validation Min MCID value */ 864#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8 865/* [RW 17] VF type validation Max MCID value */ 866#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298 867/* [RW 10] VF type validation comp value */ 868#define DORQ_REG_VF_TYPE_VALUE_0 0x170258 869#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340 870 871/* [RW 4] Initial activity counter value on the load request; when the 872 shortcut is done. */ 873#define DORQ_REG_SHRT_ACT_CNT 0x170070 874/* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 875#define DORQ_REG_SHRT_CMHEAD 0x170054 876#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 877#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0) 878#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 879#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 880#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 881#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 882#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0) 883#define DORQ_REG_VF_USAGE_CNT 0x170320 884#define HC_REG_AGG_INT_0 0x108050 885#define HC_REG_AGG_INT_1 0x108054 886#define HC_REG_ATTN_BIT 0x108120 887#define HC_REG_ATTN_IDX 0x108100 888#define HC_REG_ATTN_MSG0_ADDR_L 0x108018 889#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 890#define HC_REG_ATTN_NUM_P0 0x108038 891#define HC_REG_ATTN_NUM_P1 0x10803c 892#define HC_REG_COMMAND_REG 0x108180 893#define HC_REG_CONFIG_0 0x108000 894#define HC_REG_CONFIG_1 0x108004 895#define HC_REG_FUNC_NUM_P0 0x1080ac 896#define HC_REG_FUNC_NUM_P1 0x1080b0 897/* [RW 3] Parity mask register #0 read/write */ 898#define HC_REG_HC_PRTY_MASK 0x1080a0 899/* [R 3] Parity register #0 read */ 900#define HC_REG_HC_PRTY_STS 0x108094 901/* [RC 3] Parity register #0 read clear */ 902#define HC_REG_HC_PRTY_STS_CLR 0x108098 903#define HC_REG_INT_MASK 0x108108 904#define HC_REG_LEADING_EDGE_0 0x108040 905#define HC_REG_LEADING_EDGE_1 0x108048 906#define HC_REG_MAIN_MEMORY 0x108800 907#define HC_REG_MAIN_MEMORY_SIZE 152 908#define HC_REG_P0_PROD_CONS 0x108200 909#define HC_REG_P1_PROD_CONS 0x108400 910#define HC_REG_PBA_COMMAND 0x108140 911#define HC_REG_PCI_CONFIG_0 0x108010 912#define HC_REG_PCI_CONFIG_1 0x108014 913#define HC_REG_STATISTIC_COUNTERS 0x109000 914#define HC_REG_TRAILING_EDGE_0 0x108044 915#define HC_REG_TRAILING_EDGE_1 0x10804c 916#define HC_REG_UC_RAM_ADDR_0 0x108028 917#define HC_REG_UC_RAM_ADDR_1 0x108030 918#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 919#define HC_REG_VQID_0 0x108008 920#define HC_REG_VQID_1 0x10800c 921#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 922#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0) 923#define IGU_REG_ATTENTION_ACK_BITS 0x130108 924/* [R 4] Debug: attn_fsm */ 925#define IGU_REG_ATTN_FSM 0x130054 926#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c 927#define IGU_REG_ATTN_MSG_ADDR_L 0x130120 928/* [R 4] Debug: [3] - attention write done message is pending (0-no pending; 929 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but 930 * write done didn't receive. */ 931#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030 932#define IGU_REG_BLOCK_CONFIGURATION 0x130000 933#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124 934#define IGU_REG_COMMAND_REG_CTRL 0x13012c 935/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit 936 * is clear. The bits in this registers are set and clear via the producer 937 * command. Data valid only in addresses 0-4. all the rest are zero. */ 938#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200 939/* [R 5] Debug: ctrl_fsm */ 940#define IGU_REG_CTRL_FSM 0x130064 941/* [R 1] data available for error memory. If this bit is clear do not red 942 * from error_handling_memory. */ 943#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130 944/* [RW 11] Parity mask register #0 read/write */ 945#define IGU_REG_IGU_PRTY_MASK 0x1300a8 946/* [R 11] Parity register #0 read */ 947#define IGU_REG_IGU_PRTY_STS 0x13009c 948/* [RC 11] Parity register #0 read clear */ 949#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0 950/* [R 4] Debug: int_handle_fsm */ 951#define IGU_REG_INT_HANDLE_FSM 0x130050 952#define IGU_REG_LEADING_EDGE_LATCH 0x130134 953/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. 954 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF 955 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */ 956#define IGU_REG_MAPPING_MEMORY 0x131000 957#define IGU_REG_MAPPING_MEMORY_SIZE 136 958#define IGU_REG_PBA_STATUS_LSB 0x130138 959#define IGU_REG_PBA_STATUS_MSB 0x13013c 960#define IGU_REG_PCI_PF_MSI_EN 0x130140 961#define IGU_REG_PCI_PF_MSIX_EN 0x130144 962#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148 963/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no 964 * pending; 1 = pending. Pendings means interrupt was asserted; and write 965 * done was not received. Data valid only in addresses 0-4. all the rest are 966 * zero. */ 967#define IGU_REG_PENDING_BITS_STATUS 0x130300 968#define IGU_REG_PF_CONFIGURATION 0x130154 969/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping 970 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default 971 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 972 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode 973 * - In backward compatible mode; for non default SB; each even line in the 974 * memory holds the U producer and each odd line hold the C producer. The 975 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The 976 * last 20 producers are for the DSB for each PF. each PF has five segments 977 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 978 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */ 979#define IGU_REG_PROD_CONS_MEMORY 0x132000 980/* [R 3] Debug: pxp_arb_fsm */ 981#define IGU_REG_PXP_ARB_FSM 0x130068 982/* [RW 6] Write one for each bit will reset the appropriate memory. When the 983 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping 984 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 985 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */ 986#define IGU_REG_RESET_MEMORIES 0x130158 987/* [R 4] Debug: sb_ctrl_fsm */ 988#define IGU_REG_SB_CTRL_FSM 0x13004c 989#define IGU_REG_SB_INT_BEFORE_M…
Large files files are truncated, but you can click here to view the full file