/drivers/net/ethernet/rdc/r6040.c

http://github.com/mirrors/linux · C · 1200 lines · 893 code · 196 blank · 111 comment · 86 complexity · 099a6a41b502f7c1c873ca0b2c25dd38 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * RDC R6040 Fast Ethernet MAC support
  4. *
  5. * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
  6. * Copyright (C) 2007
  7. * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
  8. * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/string.h>
  14. #include <linux/timer.h>
  15. #include <linux/errno.h>
  16. #include <linux/ioport.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/pci.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/skbuff.h>
  22. #include <linux/delay.h>
  23. #include <linux/mii.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/crc32.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/bitops.h>
  28. #include <linux/io.h>
  29. #include <linux/irq.h>
  30. #include <linux/uaccess.h>
  31. #include <linux/phy.h>
  32. #include <asm/processor.h>
  33. #define DRV_NAME "r6040"
  34. #define DRV_VERSION "0.29"
  35. #define DRV_RELDATE "04Jul2016"
  36. /* Time in jiffies before concluding the transmitter is hung. */
  37. #define TX_TIMEOUT (6000 * HZ / 1000)
  38. /* RDC MAC I/O Size */
  39. #define R6040_IO_SIZE 256
  40. /* MAX RDC MAC */
  41. #define MAX_MAC 2
  42. /* MAC registers */
  43. #define MCR0 0x00 /* Control register 0 */
  44. #define MCR0_RCVEN 0x0002 /* Receive enable */
  45. #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
  46. #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
  47. #define MCR0_XMTEN 0x1000 /* Transmission enable */
  48. #define MCR0_FD 0x8000 /* Full/Half duplex */
  49. #define MCR1 0x04 /* Control register 1 */
  50. #define MAC_RST 0x0001 /* Reset the MAC */
  51. #define MBCR 0x08 /* Bus control */
  52. #define MT_ICR 0x0C /* TX interrupt control */
  53. #define MR_ICR 0x10 /* RX interrupt control */
  54. #define MTPR 0x14 /* TX poll command register */
  55. #define TM2TX 0x0001 /* Trigger MAC to transmit */
  56. #define MR_BSR 0x18 /* RX buffer size */
  57. #define MR_DCR 0x1A /* RX descriptor control */
  58. #define MLSR 0x1C /* Last status */
  59. #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
  60. #define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
  61. #define TX_LATEC 0x4000 /* Transmit late collision */
  62. #define MMDIO 0x20 /* MDIO control register */
  63. #define MDIO_WRITE 0x4000 /* MDIO write */
  64. #define MDIO_READ 0x2000 /* MDIO read */
  65. #define MMRD 0x24 /* MDIO read data register */
  66. #define MMWD 0x28 /* MDIO write data register */
  67. #define MTD_SA0 0x2C /* TX descriptor start address 0 */
  68. #define MTD_SA1 0x30 /* TX descriptor start address 1 */
  69. #define MRD_SA0 0x34 /* RX descriptor start address 0 */
  70. #define MRD_SA1 0x38 /* RX descriptor start address 1 */
  71. #define MISR 0x3C /* Status register */
  72. #define MIER 0x40 /* INT enable register */
  73. #define MSK_INT 0x0000 /* Mask off interrupts */
  74. #define RX_FINISH 0x0001 /* RX finished */
  75. #define RX_NO_DESC 0x0002 /* No RX descriptor available */
  76. #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
  77. #define RX_EARLY 0x0008 /* RX early */
  78. #define TX_FINISH 0x0010 /* TX finished */
  79. #define TX_EARLY 0x0080 /* TX early */
  80. #define EVENT_OVRFL 0x0100 /* Event counter overflow */
  81. #define LINK_CHANGED 0x0200 /* PHY link changed */
  82. #define ME_CISR 0x44 /* Event counter INT status */
  83. #define ME_CIER 0x48 /* Event counter INT enable */
  84. #define MR_CNT 0x50 /* Successfully received packet counter */
  85. #define ME_CNT0 0x52 /* Event counter 0 */
  86. #define ME_CNT1 0x54 /* Event counter 1 */
  87. #define ME_CNT2 0x56 /* Event counter 2 */
  88. #define ME_CNT3 0x58 /* Event counter 3 */
  89. #define MT_CNT 0x5A /* Successfully transmit packet counter */
  90. #define ME_CNT4 0x5C /* Event counter 4 */
  91. #define MP_CNT 0x5E /* Pause frame counter register */
  92. #define MAR0 0x60 /* Hash table 0 */
  93. #define MAR1 0x62 /* Hash table 1 */
  94. #define MAR2 0x64 /* Hash table 2 */
  95. #define MAR3 0x66 /* Hash table 3 */
  96. #define MID_0L 0x68 /* Multicast address MID0 Low */
  97. #define MID_0M 0x6A /* Multicast address MID0 Medium */
  98. #define MID_0H 0x6C /* Multicast address MID0 High */
  99. #define MID_1L 0x70 /* MID1 Low */
  100. #define MID_1M 0x72 /* MID1 Medium */
  101. #define MID_1H 0x74 /* MID1 High */
  102. #define MID_2L 0x78 /* MID2 Low */
  103. #define MID_2M 0x7A /* MID2 Medium */
  104. #define MID_2H 0x7C /* MID2 High */
  105. #define MID_3L 0x80 /* MID3 Low */
  106. #define MID_3M 0x82 /* MID3 Medium */
  107. #define MID_3H 0x84 /* MID3 High */
  108. #define PHY_CC 0x88 /* PHY status change configuration register */
  109. #define SCEN 0x8000 /* PHY status change enable */
  110. #define PHYAD_SHIFT 8 /* PHY address shift */
  111. #define TMRDIV_SHIFT 0 /* Timer divider shift */
  112. #define PHY_ST 0x8A /* PHY status register */
  113. #define MAC_SM 0xAC /* MAC status machine */
  114. #define MAC_SM_RST 0x0002 /* MAC status machine reset */
  115. #define MAC_ID 0xBE /* Identifier register */
  116. #define TX_DCNT 0x80 /* TX descriptor count */
  117. #define RX_DCNT 0x80 /* RX descriptor count */
  118. #define MAX_BUF_SIZE 0x600
  119. #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
  120. #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
  121. #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
  122. #define MCAST_MAX 3 /* Max number multicast addresses to filter */
  123. #define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
  124. /* Descriptor status */
  125. #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
  126. #define DSC_RX_OK 0x4000 /* RX was successful */
  127. #define DSC_RX_ERR 0x0800 /* RX PHY error */
  128. #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
  129. #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
  130. #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
  131. #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
  132. #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
  133. #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
  134. #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
  135. #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
  136. #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
  137. #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
  138. MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
  139. "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
  140. "Florian Fainelli <f.fainelli@gmail.com>");
  141. MODULE_LICENSE("GPL");
  142. MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
  143. MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
  144. /* RX and TX interrupts that we handle */
  145. #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
  146. #define TX_INTS (TX_FINISH)
  147. #define INT_MASK (RX_INTS | TX_INTS)
  148. struct r6040_descriptor {
  149. u16 status, len; /* 0-3 */
  150. __le32 buf; /* 4-7 */
  151. __le32 ndesc; /* 8-B */
  152. u32 rev1; /* C-F */
  153. char *vbufp; /* 10-13 */
  154. struct r6040_descriptor *vndescp; /* 14-17 */
  155. struct sk_buff *skb_ptr; /* 18-1B */
  156. u32 rev2; /* 1C-1F */
  157. } __aligned(32);
  158. struct r6040_private {
  159. spinlock_t lock; /* driver lock */
  160. struct pci_dev *pdev;
  161. struct r6040_descriptor *rx_insert_ptr;
  162. struct r6040_descriptor *rx_remove_ptr;
  163. struct r6040_descriptor *tx_insert_ptr;
  164. struct r6040_descriptor *tx_remove_ptr;
  165. struct r6040_descriptor *rx_ring;
  166. struct r6040_descriptor *tx_ring;
  167. dma_addr_t rx_ring_dma;
  168. dma_addr_t tx_ring_dma;
  169. u16 tx_free_desc;
  170. u16 mcr0;
  171. struct net_device *dev;
  172. struct mii_bus *mii_bus;
  173. struct napi_struct napi;
  174. void __iomem *base;
  175. int old_link;
  176. int old_duplex;
  177. };
  178. static char version[] = DRV_NAME
  179. ": RDC R6040 NAPI net driver,"
  180. "version "DRV_VERSION " (" DRV_RELDATE ")";
  181. /* Read a word data from PHY Chip */
  182. static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
  183. {
  184. int limit = MAC_DEF_TIMEOUT;
  185. u16 cmd;
  186. iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
  187. /* Wait for the read bit to be cleared */
  188. while (limit--) {
  189. cmd = ioread16(ioaddr + MMDIO);
  190. if (!(cmd & MDIO_READ))
  191. break;
  192. udelay(1);
  193. }
  194. if (limit < 0)
  195. return -ETIMEDOUT;
  196. return ioread16(ioaddr + MMRD);
  197. }
  198. /* Write a word data from PHY Chip */
  199. static int r6040_phy_write(void __iomem *ioaddr,
  200. int phy_addr, int reg, u16 val)
  201. {
  202. int limit = MAC_DEF_TIMEOUT;
  203. u16 cmd;
  204. iowrite16(val, ioaddr + MMWD);
  205. /* Write the command to the MDIO bus */
  206. iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
  207. /* Wait for the write bit to be cleared */
  208. while (limit--) {
  209. cmd = ioread16(ioaddr + MMDIO);
  210. if (!(cmd & MDIO_WRITE))
  211. break;
  212. udelay(1);
  213. }
  214. return (limit < 0) ? -ETIMEDOUT : 0;
  215. }
  216. static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
  217. {
  218. struct net_device *dev = bus->priv;
  219. struct r6040_private *lp = netdev_priv(dev);
  220. void __iomem *ioaddr = lp->base;
  221. return r6040_phy_read(ioaddr, phy_addr, reg);
  222. }
  223. static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
  224. int reg, u16 value)
  225. {
  226. struct net_device *dev = bus->priv;
  227. struct r6040_private *lp = netdev_priv(dev);
  228. void __iomem *ioaddr = lp->base;
  229. return r6040_phy_write(ioaddr, phy_addr, reg, value);
  230. }
  231. static void r6040_free_txbufs(struct net_device *dev)
  232. {
  233. struct r6040_private *lp = netdev_priv(dev);
  234. int i;
  235. for (i = 0; i < TX_DCNT; i++) {
  236. if (lp->tx_insert_ptr->skb_ptr) {
  237. pci_unmap_single(lp->pdev,
  238. le32_to_cpu(lp->tx_insert_ptr->buf),
  239. MAX_BUF_SIZE, PCI_DMA_TODEVICE);
  240. dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
  241. lp->tx_insert_ptr->skb_ptr = NULL;
  242. }
  243. lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
  244. }
  245. }
  246. static void r6040_free_rxbufs(struct net_device *dev)
  247. {
  248. struct r6040_private *lp = netdev_priv(dev);
  249. int i;
  250. for (i = 0; i < RX_DCNT; i++) {
  251. if (lp->rx_insert_ptr->skb_ptr) {
  252. pci_unmap_single(lp->pdev,
  253. le32_to_cpu(lp->rx_insert_ptr->buf),
  254. MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  255. dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
  256. lp->rx_insert_ptr->skb_ptr = NULL;
  257. }
  258. lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
  259. }
  260. }
  261. static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
  262. dma_addr_t desc_dma, int size)
  263. {
  264. struct r6040_descriptor *desc = desc_ring;
  265. dma_addr_t mapping = desc_dma;
  266. while (size-- > 0) {
  267. mapping += sizeof(*desc);
  268. desc->ndesc = cpu_to_le32(mapping);
  269. desc->vndescp = desc + 1;
  270. desc++;
  271. }
  272. desc--;
  273. desc->ndesc = cpu_to_le32(desc_dma);
  274. desc->vndescp = desc_ring;
  275. }
  276. static void r6040_init_txbufs(struct net_device *dev)
  277. {
  278. struct r6040_private *lp = netdev_priv(dev);
  279. lp->tx_free_desc = TX_DCNT;
  280. lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
  281. r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
  282. }
  283. static int r6040_alloc_rxbufs(struct net_device *dev)
  284. {
  285. struct r6040_private *lp = netdev_priv(dev);
  286. struct r6040_descriptor *desc;
  287. struct sk_buff *skb;
  288. int rc;
  289. lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
  290. r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
  291. /* Allocate skbs for the rx descriptors */
  292. desc = lp->rx_ring;
  293. do {
  294. skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
  295. if (!skb) {
  296. rc = -ENOMEM;
  297. goto err_exit;
  298. }
  299. desc->skb_ptr = skb;
  300. desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
  301. desc->skb_ptr->data,
  302. MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
  303. desc->status = DSC_OWNER_MAC;
  304. desc = desc->vndescp;
  305. } while (desc != lp->rx_ring);
  306. return 0;
  307. err_exit:
  308. /* Deallocate all previously allocated skbs */
  309. r6040_free_rxbufs(dev);
  310. return rc;
  311. }
  312. static void r6040_reset_mac(struct r6040_private *lp)
  313. {
  314. void __iomem *ioaddr = lp->base;
  315. int limit = MAC_DEF_TIMEOUT;
  316. u16 cmd;
  317. iowrite16(MAC_RST, ioaddr + MCR1);
  318. while (limit--) {
  319. cmd = ioread16(ioaddr + MCR1);
  320. if (cmd & MAC_RST)
  321. break;
  322. }
  323. /* Reset internal state machine */
  324. iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
  325. iowrite16(0, ioaddr + MAC_SM);
  326. mdelay(5);
  327. }
  328. static void r6040_init_mac_regs(struct net_device *dev)
  329. {
  330. struct r6040_private *lp = netdev_priv(dev);
  331. void __iomem *ioaddr = lp->base;
  332. /* Mask Off Interrupt */
  333. iowrite16(MSK_INT, ioaddr + MIER);
  334. /* Reset RDC MAC */
  335. r6040_reset_mac(lp);
  336. /* MAC Bus Control Register */
  337. iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
  338. /* Buffer Size Register */
  339. iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
  340. /* Write TX ring start address */
  341. iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
  342. iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
  343. /* Write RX ring start address */
  344. iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
  345. iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
  346. /* Set interrupt waiting time and packet numbers */
  347. iowrite16(0, ioaddr + MT_ICR);
  348. iowrite16(0, ioaddr + MR_ICR);
  349. /* Enable interrupts */
  350. iowrite16(INT_MASK, ioaddr + MIER);
  351. /* Enable TX and RX */
  352. iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
  353. /* Let TX poll the descriptors
  354. * we may got called by r6040_tx_timeout which has left
  355. * some unsent tx buffers */
  356. iowrite16(TM2TX, ioaddr + MTPR);
  357. }
  358. static void r6040_tx_timeout(struct net_device *dev, unsigned int txqueue)
  359. {
  360. struct r6040_private *priv = netdev_priv(dev);
  361. void __iomem *ioaddr = priv->base;
  362. netdev_warn(dev, "transmit timed out, int enable %4.4x "
  363. "status %4.4x\n",
  364. ioread16(ioaddr + MIER),
  365. ioread16(ioaddr + MISR));
  366. dev->stats.tx_errors++;
  367. /* Reset MAC and re-init all registers */
  368. r6040_init_mac_regs(dev);
  369. }
  370. static struct net_device_stats *r6040_get_stats(struct net_device *dev)
  371. {
  372. struct r6040_private *priv = netdev_priv(dev);
  373. void __iomem *ioaddr = priv->base;
  374. unsigned long flags;
  375. spin_lock_irqsave(&priv->lock, flags);
  376. dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
  377. dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
  378. spin_unlock_irqrestore(&priv->lock, flags);
  379. return &dev->stats;
  380. }
  381. /* Stop RDC MAC and Free the allocated resource */
  382. static void r6040_down(struct net_device *dev)
  383. {
  384. struct r6040_private *lp = netdev_priv(dev);
  385. void __iomem *ioaddr = lp->base;
  386. u16 *adrp;
  387. /* Stop MAC */
  388. iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
  389. /* Reset RDC MAC */
  390. r6040_reset_mac(lp);
  391. /* Restore MAC Address to MIDx */
  392. adrp = (u16 *) dev->dev_addr;
  393. iowrite16(adrp[0], ioaddr + MID_0L);
  394. iowrite16(adrp[1], ioaddr + MID_0M);
  395. iowrite16(adrp[2], ioaddr + MID_0H);
  396. }
  397. static int r6040_close(struct net_device *dev)
  398. {
  399. struct r6040_private *lp = netdev_priv(dev);
  400. struct pci_dev *pdev = lp->pdev;
  401. phy_stop(dev->phydev);
  402. napi_disable(&lp->napi);
  403. netif_stop_queue(dev);
  404. spin_lock_irq(&lp->lock);
  405. r6040_down(dev);
  406. /* Free RX buffer */
  407. r6040_free_rxbufs(dev);
  408. /* Free TX buffer */
  409. r6040_free_txbufs(dev);
  410. spin_unlock_irq(&lp->lock);
  411. free_irq(dev->irq, dev);
  412. /* Free Descriptor memory */
  413. if (lp->rx_ring) {
  414. pci_free_consistent(pdev,
  415. RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
  416. lp->rx_ring = NULL;
  417. }
  418. if (lp->tx_ring) {
  419. pci_free_consistent(pdev,
  420. TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
  421. lp->tx_ring = NULL;
  422. }
  423. return 0;
  424. }
  425. static int r6040_rx(struct net_device *dev, int limit)
  426. {
  427. struct r6040_private *priv = netdev_priv(dev);
  428. struct r6040_descriptor *descptr = priv->rx_remove_ptr;
  429. struct sk_buff *skb_ptr, *new_skb;
  430. int count = 0;
  431. u16 err;
  432. /* Limit not reached and the descriptor belongs to the CPU */
  433. while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
  434. /* Read the descriptor status */
  435. err = descptr->status;
  436. /* Global error status set */
  437. if (err & DSC_RX_ERR) {
  438. /* RX dribble */
  439. if (err & DSC_RX_ERR_DRI)
  440. dev->stats.rx_frame_errors++;
  441. /* Buffer length exceeded */
  442. if (err & DSC_RX_ERR_BUF)
  443. dev->stats.rx_length_errors++;
  444. /* Packet too long */
  445. if (err & DSC_RX_ERR_LONG)
  446. dev->stats.rx_length_errors++;
  447. /* Packet < 64 bytes */
  448. if (err & DSC_RX_ERR_RUNT)
  449. dev->stats.rx_length_errors++;
  450. /* CRC error */
  451. if (err & DSC_RX_ERR_CRC) {
  452. spin_lock(&priv->lock);
  453. dev->stats.rx_crc_errors++;
  454. spin_unlock(&priv->lock);
  455. }
  456. goto next_descr;
  457. }
  458. /* Packet successfully received */
  459. new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
  460. if (!new_skb) {
  461. dev->stats.rx_dropped++;
  462. goto next_descr;
  463. }
  464. skb_ptr = descptr->skb_ptr;
  465. skb_ptr->dev = priv->dev;
  466. /* Do not count the CRC */
  467. skb_put(skb_ptr, descptr->len - 4);
  468. pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
  469. MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  470. skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
  471. /* Send to upper layer */
  472. netif_receive_skb(skb_ptr);
  473. dev->stats.rx_packets++;
  474. dev->stats.rx_bytes += descptr->len - 4;
  475. /* put new skb into descriptor */
  476. descptr->skb_ptr = new_skb;
  477. descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
  478. descptr->skb_ptr->data,
  479. MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
  480. next_descr:
  481. /* put the descriptor back to the MAC */
  482. descptr->status = DSC_OWNER_MAC;
  483. descptr = descptr->vndescp;
  484. count++;
  485. }
  486. priv->rx_remove_ptr = descptr;
  487. return count;
  488. }
  489. static void r6040_tx(struct net_device *dev)
  490. {
  491. struct r6040_private *priv = netdev_priv(dev);
  492. struct r6040_descriptor *descptr;
  493. void __iomem *ioaddr = priv->base;
  494. struct sk_buff *skb_ptr;
  495. u16 err;
  496. spin_lock(&priv->lock);
  497. descptr = priv->tx_remove_ptr;
  498. while (priv->tx_free_desc < TX_DCNT) {
  499. /* Check for errors */
  500. err = ioread16(ioaddr + MLSR);
  501. if (err & TX_FIFO_UNDR)
  502. dev->stats.tx_fifo_errors++;
  503. if (err & (TX_EXCEEDC | TX_LATEC))
  504. dev->stats.tx_carrier_errors++;
  505. if (descptr->status & DSC_OWNER_MAC)
  506. break; /* Not complete */
  507. skb_ptr = descptr->skb_ptr;
  508. /* Statistic Counter */
  509. dev->stats.tx_packets++;
  510. dev->stats.tx_bytes += skb_ptr->len;
  511. pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
  512. skb_ptr->len, PCI_DMA_TODEVICE);
  513. /* Free buffer */
  514. dev_kfree_skb(skb_ptr);
  515. descptr->skb_ptr = NULL;
  516. /* To next descriptor */
  517. descptr = descptr->vndescp;
  518. priv->tx_free_desc++;
  519. }
  520. priv->tx_remove_ptr = descptr;
  521. if (priv->tx_free_desc)
  522. netif_wake_queue(dev);
  523. spin_unlock(&priv->lock);
  524. }
  525. static int r6040_poll(struct napi_struct *napi, int budget)
  526. {
  527. struct r6040_private *priv =
  528. container_of(napi, struct r6040_private, napi);
  529. struct net_device *dev = priv->dev;
  530. void __iomem *ioaddr = priv->base;
  531. int work_done;
  532. r6040_tx(dev);
  533. work_done = r6040_rx(dev, budget);
  534. if (work_done < budget) {
  535. napi_complete_done(napi, work_done);
  536. /* Enable RX/TX interrupt */
  537. iowrite16(ioread16(ioaddr + MIER) | RX_INTS | TX_INTS,
  538. ioaddr + MIER);
  539. }
  540. return work_done;
  541. }
  542. /* The RDC interrupt handler. */
  543. static irqreturn_t r6040_interrupt(int irq, void *dev_id)
  544. {
  545. struct net_device *dev = dev_id;
  546. struct r6040_private *lp = netdev_priv(dev);
  547. void __iomem *ioaddr = lp->base;
  548. u16 misr, status;
  549. /* Save MIER */
  550. misr = ioread16(ioaddr + MIER);
  551. /* Mask off RDC MAC interrupt */
  552. iowrite16(MSK_INT, ioaddr + MIER);
  553. /* Read MISR status and clear */
  554. status = ioread16(ioaddr + MISR);
  555. if (status == 0x0000 || status == 0xffff) {
  556. /* Restore RDC MAC interrupt */
  557. iowrite16(misr, ioaddr + MIER);
  558. return IRQ_NONE;
  559. }
  560. /* RX interrupt request */
  561. if (status & (RX_INTS | TX_INTS)) {
  562. if (status & RX_NO_DESC) {
  563. /* RX descriptor unavailable */
  564. dev->stats.rx_dropped++;
  565. dev->stats.rx_missed_errors++;
  566. }
  567. if (status & RX_FIFO_FULL)
  568. dev->stats.rx_fifo_errors++;
  569. if (likely(napi_schedule_prep(&lp->napi))) {
  570. /* Mask off RX interrupt */
  571. misr &= ~(RX_INTS | TX_INTS);
  572. __napi_schedule_irqoff(&lp->napi);
  573. }
  574. }
  575. /* Restore RDC MAC interrupt */
  576. iowrite16(misr, ioaddr + MIER);
  577. return IRQ_HANDLED;
  578. }
  579. #ifdef CONFIG_NET_POLL_CONTROLLER
  580. static void r6040_poll_controller(struct net_device *dev)
  581. {
  582. disable_irq(dev->irq);
  583. r6040_interrupt(dev->irq, dev);
  584. enable_irq(dev->irq);
  585. }
  586. #endif
  587. /* Init RDC MAC */
  588. static int r6040_up(struct net_device *dev)
  589. {
  590. struct r6040_private *lp = netdev_priv(dev);
  591. void __iomem *ioaddr = lp->base;
  592. int ret;
  593. /* Initialise and alloc RX/TX buffers */
  594. r6040_init_txbufs(dev);
  595. ret = r6040_alloc_rxbufs(dev);
  596. if (ret)
  597. return ret;
  598. /* improve performance (by RDC guys) */
  599. r6040_phy_write(ioaddr, 30, 17,
  600. (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
  601. r6040_phy_write(ioaddr, 30, 17,
  602. ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
  603. r6040_phy_write(ioaddr, 0, 19, 0x0000);
  604. r6040_phy_write(ioaddr, 0, 30, 0x01F0);
  605. /* Initialize all MAC registers */
  606. r6040_init_mac_regs(dev);
  607. phy_start(dev->phydev);
  608. return 0;
  609. }
  610. /* Read/set MAC address routines */
  611. static void r6040_mac_address(struct net_device *dev)
  612. {
  613. struct r6040_private *lp = netdev_priv(dev);
  614. void __iomem *ioaddr = lp->base;
  615. u16 *adrp;
  616. /* Reset MAC */
  617. r6040_reset_mac(lp);
  618. /* Restore MAC Address */
  619. adrp = (u16 *) dev->dev_addr;
  620. iowrite16(adrp[0], ioaddr + MID_0L);
  621. iowrite16(adrp[1], ioaddr + MID_0M);
  622. iowrite16(adrp[2], ioaddr + MID_0H);
  623. }
  624. static int r6040_open(struct net_device *dev)
  625. {
  626. struct r6040_private *lp = netdev_priv(dev);
  627. int ret;
  628. /* Request IRQ and Register interrupt handler */
  629. ret = request_irq(dev->irq, r6040_interrupt,
  630. IRQF_SHARED, dev->name, dev);
  631. if (ret)
  632. goto out;
  633. /* Set MAC address */
  634. r6040_mac_address(dev);
  635. /* Allocate Descriptor memory */
  636. lp->rx_ring =
  637. pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
  638. if (!lp->rx_ring) {
  639. ret = -ENOMEM;
  640. goto err_free_irq;
  641. }
  642. lp->tx_ring =
  643. pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
  644. if (!lp->tx_ring) {
  645. ret = -ENOMEM;
  646. goto err_free_rx_ring;
  647. }
  648. ret = r6040_up(dev);
  649. if (ret)
  650. goto err_free_tx_ring;
  651. napi_enable(&lp->napi);
  652. netif_start_queue(dev);
  653. return 0;
  654. err_free_tx_ring:
  655. pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
  656. lp->tx_ring_dma);
  657. err_free_rx_ring:
  658. pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
  659. lp->rx_ring_dma);
  660. err_free_irq:
  661. free_irq(dev->irq, dev);
  662. out:
  663. return ret;
  664. }
  665. static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
  666. struct net_device *dev)
  667. {
  668. struct r6040_private *lp = netdev_priv(dev);
  669. struct r6040_descriptor *descptr;
  670. void __iomem *ioaddr = lp->base;
  671. unsigned long flags;
  672. if (skb_put_padto(skb, ETH_ZLEN) < 0)
  673. return NETDEV_TX_OK;
  674. /* Critical Section */
  675. spin_lock_irqsave(&lp->lock, flags);
  676. /* TX resource check */
  677. if (!lp->tx_free_desc) {
  678. spin_unlock_irqrestore(&lp->lock, flags);
  679. netif_stop_queue(dev);
  680. netdev_err(dev, ": no tx descriptor\n");
  681. return NETDEV_TX_BUSY;
  682. }
  683. /* Set TX descriptor & Transmit it */
  684. lp->tx_free_desc--;
  685. descptr = lp->tx_insert_ptr;
  686. descptr->len = skb->len;
  687. descptr->skb_ptr = skb;
  688. descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
  689. skb->data, skb->len, PCI_DMA_TODEVICE));
  690. descptr->status = DSC_OWNER_MAC;
  691. skb_tx_timestamp(skb);
  692. /* Trigger the MAC to check the TX descriptor */
  693. if (!netdev_xmit_more() || netif_queue_stopped(dev))
  694. iowrite16(TM2TX, ioaddr + MTPR);
  695. lp->tx_insert_ptr = descptr->vndescp;
  696. /* If no tx resource, stop */
  697. if (!lp->tx_free_desc)
  698. netif_stop_queue(dev);
  699. spin_unlock_irqrestore(&lp->lock, flags);
  700. return NETDEV_TX_OK;
  701. }
  702. static void r6040_multicast_list(struct net_device *dev)
  703. {
  704. struct r6040_private *lp = netdev_priv(dev);
  705. void __iomem *ioaddr = lp->base;
  706. unsigned long flags;
  707. struct netdev_hw_addr *ha;
  708. int i;
  709. u16 *adrp;
  710. u16 hash_table[4] = { 0 };
  711. spin_lock_irqsave(&lp->lock, flags);
  712. /* Keep our MAC Address */
  713. adrp = (u16 *)dev->dev_addr;
  714. iowrite16(adrp[0], ioaddr + MID_0L);
  715. iowrite16(adrp[1], ioaddr + MID_0M);
  716. iowrite16(adrp[2], ioaddr + MID_0H);
  717. /* Clear AMCP & PROM bits */
  718. lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
  719. /* Promiscuous mode */
  720. if (dev->flags & IFF_PROMISC)
  721. lp->mcr0 |= MCR0_PROMISC;
  722. /* Enable multicast hash table function to
  723. * receive all multicast packets. */
  724. else if (dev->flags & IFF_ALLMULTI) {
  725. lp->mcr0 |= MCR0_HASH_EN;
  726. for (i = 0; i < MCAST_MAX ; i++) {
  727. iowrite16(0, ioaddr + MID_1L + 8 * i);
  728. iowrite16(0, ioaddr + MID_1M + 8 * i);
  729. iowrite16(0, ioaddr + MID_1H + 8 * i);
  730. }
  731. for (i = 0; i < 4; i++)
  732. hash_table[i] = 0xffff;
  733. }
  734. /* Use internal multicast address registers if the number of
  735. * multicast addresses is not greater than MCAST_MAX. */
  736. else if (netdev_mc_count(dev) <= MCAST_MAX) {
  737. i = 0;
  738. netdev_for_each_mc_addr(ha, dev) {
  739. u16 *adrp = (u16 *) ha->addr;
  740. iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
  741. iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
  742. iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
  743. i++;
  744. }
  745. while (i < MCAST_MAX) {
  746. iowrite16(0, ioaddr + MID_1L + 8 * i);
  747. iowrite16(0, ioaddr + MID_1M + 8 * i);
  748. iowrite16(0, ioaddr + MID_1H + 8 * i);
  749. i++;
  750. }
  751. }
  752. /* Otherwise, Enable multicast hash table function. */
  753. else {
  754. u32 crc;
  755. lp->mcr0 |= MCR0_HASH_EN;
  756. for (i = 0; i < MCAST_MAX ; i++) {
  757. iowrite16(0, ioaddr + MID_1L + 8 * i);
  758. iowrite16(0, ioaddr + MID_1M + 8 * i);
  759. iowrite16(0, ioaddr + MID_1H + 8 * i);
  760. }
  761. /* Build multicast hash table */
  762. netdev_for_each_mc_addr(ha, dev) {
  763. u8 *addrs = ha->addr;
  764. crc = ether_crc(ETH_ALEN, addrs);
  765. crc >>= 26;
  766. hash_table[crc >> 4] |= 1 << (crc & 0xf);
  767. }
  768. }
  769. iowrite16(lp->mcr0, ioaddr + MCR0);
  770. /* Fill the MAC hash tables with their values */
  771. if (lp->mcr0 & MCR0_HASH_EN) {
  772. iowrite16(hash_table[0], ioaddr + MAR0);
  773. iowrite16(hash_table[1], ioaddr + MAR1);
  774. iowrite16(hash_table[2], ioaddr + MAR2);
  775. iowrite16(hash_table[3], ioaddr + MAR3);
  776. }
  777. spin_unlock_irqrestore(&lp->lock, flags);
  778. }
  779. static void netdev_get_drvinfo(struct net_device *dev,
  780. struct ethtool_drvinfo *info)
  781. {
  782. struct r6040_private *rp = netdev_priv(dev);
  783. strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
  784. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  785. strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
  786. }
  787. static const struct ethtool_ops netdev_ethtool_ops = {
  788. .get_drvinfo = netdev_get_drvinfo,
  789. .get_link = ethtool_op_get_link,
  790. .get_ts_info = ethtool_op_get_ts_info,
  791. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  792. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  793. };
  794. static const struct net_device_ops r6040_netdev_ops = {
  795. .ndo_open = r6040_open,
  796. .ndo_stop = r6040_close,
  797. .ndo_start_xmit = r6040_start_xmit,
  798. .ndo_get_stats = r6040_get_stats,
  799. .ndo_set_rx_mode = r6040_multicast_list,
  800. .ndo_validate_addr = eth_validate_addr,
  801. .ndo_set_mac_address = eth_mac_addr,
  802. .ndo_do_ioctl = phy_do_ioctl,
  803. .ndo_tx_timeout = r6040_tx_timeout,
  804. #ifdef CONFIG_NET_POLL_CONTROLLER
  805. .ndo_poll_controller = r6040_poll_controller,
  806. #endif
  807. };
  808. static void r6040_adjust_link(struct net_device *dev)
  809. {
  810. struct r6040_private *lp = netdev_priv(dev);
  811. struct phy_device *phydev = dev->phydev;
  812. int status_changed = 0;
  813. void __iomem *ioaddr = lp->base;
  814. BUG_ON(!phydev);
  815. if (lp->old_link != phydev->link) {
  816. status_changed = 1;
  817. lp->old_link = phydev->link;
  818. }
  819. /* reflect duplex change */
  820. if (phydev->link && (lp->old_duplex != phydev->duplex)) {
  821. lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
  822. iowrite16(lp->mcr0, ioaddr);
  823. status_changed = 1;
  824. lp->old_duplex = phydev->duplex;
  825. }
  826. if (status_changed)
  827. phy_print_status(phydev);
  828. }
  829. static int r6040_mii_probe(struct net_device *dev)
  830. {
  831. struct r6040_private *lp = netdev_priv(dev);
  832. struct phy_device *phydev = NULL;
  833. phydev = phy_find_first(lp->mii_bus);
  834. if (!phydev) {
  835. dev_err(&lp->pdev->dev, "no PHY found\n");
  836. return -ENODEV;
  837. }
  838. phydev = phy_connect(dev, phydev_name(phydev), &r6040_adjust_link,
  839. PHY_INTERFACE_MODE_MII);
  840. if (IS_ERR(phydev)) {
  841. dev_err(&lp->pdev->dev, "could not attach to PHY\n");
  842. return PTR_ERR(phydev);
  843. }
  844. phy_set_max_speed(phydev, SPEED_100);
  845. lp->old_link = 0;
  846. lp->old_duplex = -1;
  847. phy_attached_info(phydev);
  848. return 0;
  849. }
  850. static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  851. {
  852. struct net_device *dev;
  853. struct r6040_private *lp;
  854. void __iomem *ioaddr;
  855. int err, io_size = R6040_IO_SIZE;
  856. static int card_idx = -1;
  857. int bar = 0;
  858. u16 *adrp;
  859. pr_info("%s\n", version);
  860. err = pci_enable_device(pdev);
  861. if (err)
  862. goto err_out;
  863. /* this should always be supported */
  864. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  865. if (err) {
  866. dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
  867. goto err_out_disable_dev;
  868. }
  869. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  870. if (err) {
  871. dev_err(&pdev->dev, "32-bit PCI DMA addresses not supported by the card\n");
  872. goto err_out_disable_dev;
  873. }
  874. /* IO Size check */
  875. if (pci_resource_len(pdev, bar) < io_size) {
  876. dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
  877. err = -EIO;
  878. goto err_out_disable_dev;
  879. }
  880. pci_set_master(pdev);
  881. dev = alloc_etherdev(sizeof(struct r6040_private));
  882. if (!dev) {
  883. err = -ENOMEM;
  884. goto err_out_disable_dev;
  885. }
  886. SET_NETDEV_DEV(dev, &pdev->dev);
  887. lp = netdev_priv(dev);
  888. err = pci_request_regions(pdev, DRV_NAME);
  889. if (err) {
  890. dev_err(&pdev->dev, "Failed to request PCI regions\n");
  891. goto err_out_free_dev;
  892. }
  893. ioaddr = pci_iomap(pdev, bar, io_size);
  894. if (!ioaddr) {
  895. dev_err(&pdev->dev, "ioremap failed for device\n");
  896. err = -EIO;
  897. goto err_out_free_res;
  898. }
  899. /* If PHY status change register is still set to zero it means the
  900. * bootloader didn't initialize it, so we set it to:
  901. * - enable phy status change
  902. * - enable all phy addresses
  903. * - set to lowest timer divider */
  904. if (ioread16(ioaddr + PHY_CC) == 0)
  905. iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
  906. 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
  907. /* Init system & device */
  908. lp->base = ioaddr;
  909. dev->irq = pdev->irq;
  910. spin_lock_init(&lp->lock);
  911. pci_set_drvdata(pdev, dev);
  912. /* Set MAC address */
  913. card_idx++;
  914. adrp = (u16 *)dev->dev_addr;
  915. adrp[0] = ioread16(ioaddr + MID_0L);
  916. adrp[1] = ioread16(ioaddr + MID_0M);
  917. adrp[2] = ioread16(ioaddr + MID_0H);
  918. /* Some bootloader/BIOSes do not initialize
  919. * MAC address, warn about that */
  920. if (!(adrp[0] || adrp[1] || adrp[2])) {
  921. netdev_warn(dev, "MAC address not initialized, "
  922. "generating random\n");
  923. eth_hw_addr_random(dev);
  924. }
  925. /* Link new device into r6040_root_dev */
  926. lp->pdev = pdev;
  927. lp->dev = dev;
  928. /* Init RDC private data */
  929. lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
  930. /* The RDC-specific entries in the device structure. */
  931. dev->netdev_ops = &r6040_netdev_ops;
  932. dev->ethtool_ops = &netdev_ethtool_ops;
  933. dev->watchdog_timeo = TX_TIMEOUT;
  934. netif_napi_add(dev, &lp->napi, r6040_poll, 64);
  935. lp->mii_bus = mdiobus_alloc();
  936. if (!lp->mii_bus) {
  937. dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
  938. err = -ENOMEM;
  939. goto err_out_unmap;
  940. }
  941. lp->mii_bus->priv = dev;
  942. lp->mii_bus->read = r6040_mdiobus_read;
  943. lp->mii_bus->write = r6040_mdiobus_write;
  944. lp->mii_bus->name = "r6040_eth_mii";
  945. snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  946. dev_name(&pdev->dev), card_idx);
  947. err = mdiobus_register(lp->mii_bus);
  948. if (err) {
  949. dev_err(&pdev->dev, "failed to register MII bus\n");
  950. goto err_out_mdio;
  951. }
  952. err = r6040_mii_probe(dev);
  953. if (err) {
  954. dev_err(&pdev->dev, "failed to probe MII bus\n");
  955. goto err_out_mdio_unregister;
  956. }
  957. /* Register net device. After this dev->name assign */
  958. err = register_netdev(dev);
  959. if (err) {
  960. dev_err(&pdev->dev, "Failed to register net device\n");
  961. goto err_out_mdio_unregister;
  962. }
  963. return 0;
  964. err_out_mdio_unregister:
  965. mdiobus_unregister(lp->mii_bus);
  966. err_out_mdio:
  967. mdiobus_free(lp->mii_bus);
  968. err_out_unmap:
  969. netif_napi_del(&lp->napi);
  970. pci_iounmap(pdev, ioaddr);
  971. err_out_free_res:
  972. pci_release_regions(pdev);
  973. err_out_free_dev:
  974. free_netdev(dev);
  975. err_out_disable_dev:
  976. pci_disable_device(pdev);
  977. err_out:
  978. return err;
  979. }
  980. static void r6040_remove_one(struct pci_dev *pdev)
  981. {
  982. struct net_device *dev = pci_get_drvdata(pdev);
  983. struct r6040_private *lp = netdev_priv(dev);
  984. unregister_netdev(dev);
  985. mdiobus_unregister(lp->mii_bus);
  986. mdiobus_free(lp->mii_bus);
  987. netif_napi_del(&lp->napi);
  988. pci_iounmap(pdev, lp->base);
  989. pci_release_regions(pdev);
  990. free_netdev(dev);
  991. pci_disable_device(pdev);
  992. }
  993. static const struct pci_device_id r6040_pci_tbl[] = {
  994. { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
  995. { 0 }
  996. };
  997. MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
  998. static struct pci_driver r6040_driver = {
  999. .name = DRV_NAME,
  1000. .id_table = r6040_pci_tbl,
  1001. .probe = r6040_init_one,
  1002. .remove = r6040_remove_one,
  1003. };
  1004. module_pci_driver(r6040_driver);