/drivers/net/ethernet/emulex/benet/be_hw.h

http://github.com/mirrors/linux · C Header · 371 lines · 241 code · 44 blank · 86 comment · 0 complexity · 05a94e560aa78aac04806a6fc9dee403 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2005-2016 Broadcom.
  4. * All rights reserved.
  5. *
  6. * Contact Information:
  7. * linux-drivers@emulex.com
  8. *
  9. * Emulex
  10. * 3333 Susan Street
  11. * Costa Mesa, CA 92626
  12. */
  13. /********* Mailbox door bell *************/
  14. /* Used for driver communication with the FW.
  15. * The software must write this register twice to post any command. First,
  16. * it writes the register with hi=1 and the upper bits of the physical address
  17. * for the MAILBOX structure. Software must poll the ready bit until this
  18. * is acknowledged. Then, sotware writes the register with hi=0 with the lower
  19. * bits in the address. It must poll the ready bit until the command is
  20. * complete. Upon completion, the MAILBOX will contain a valid completion
  21. * queue entry.
  22. */
  23. #define MPU_MAILBOX_DB_OFFSET 0x160
  24. #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
  25. #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
  26. #define MPU_EP_CONTROL 0
  27. /********** MPU semphore: used for SH & BE *************/
  28. #define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */
  29. #define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
  30. #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
  31. #define POST_STAGE_MASK 0x0000FFFF
  32. #define POST_ERR_MASK 0x1
  33. #define POST_ERR_SHIFT 31
  34. #define POST_ERR_RECOVERY_CODE_MASK 0xFFF
  35. /* Soft Reset register masks */
  36. #define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
  37. /* MPU semphore POST stage values */
  38. #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
  39. #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
  40. #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
  41. #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
  42. #define POST_STAGE_RECOVERABLE_ERR 0xE000 /* Recoverable err detected */
  43. /* FW has detected a UE and is dumping FAT log data */
  44. #define POST_STAGE_FAT_LOG_START 0x0D00
  45. #define POST_STAGE_ARMFW_UE 0xF000 /*FW has asserted an UE*/
  46. /* Lancer SLIPORT registers */
  47. #define SLIPORT_STATUS_OFFSET 0x404
  48. #define SLIPORT_CONTROL_OFFSET 0x408
  49. #define SLIPORT_ERROR1_OFFSET 0x40C
  50. #define SLIPORT_ERROR2_OFFSET 0x410
  51. #define PHYSDEV_CONTROL_OFFSET 0x414
  52. #define SLIPORT_STATUS_ERR_MASK 0x80000000
  53. #define SLIPORT_STATUS_DIP_MASK 0x02000000
  54. #define SLIPORT_STATUS_RN_MASK 0x01000000
  55. #define SLIPORT_STATUS_RDY_MASK 0x00800000
  56. #define SLI_PORT_CONTROL_IP_MASK 0x08000000
  57. #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
  58. #define PHYSDEV_CONTROL_DD_MASK 0x00000004
  59. #define PHYSDEV_CONTROL_INP_MASK 0x40000000
  60. #define SLIPORT_ERROR_NO_RESOURCE1 0x2
  61. #define SLIPORT_ERROR_NO_RESOURCE2 0x9
  62. #define SLIPORT_ERROR_FW_RESET1 0x2
  63. #define SLIPORT_ERROR_FW_RESET2 0x0
  64. /********* Memory BAR register ************/
  65. #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
  66. /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
  67. * Disable" may still globally block interrupts in addition to individual
  68. * interrupt masks; a mechanism for the device driver to block all interrupts
  69. * atomically without having to arbitrate for the PCI Interrupt Disable bit
  70. * with the OS.
  71. */
  72. #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK BIT(29) /* bit 29 */
  73. /********* PCI Function Capability *********/
  74. #define BE_FUNCTION_CAPS_RSS 0x2
  75. #define BE_FUNCTION_CAPS_SUPER_NIC 0x40
  76. /********* Power management (WOL) **********/
  77. #define PCICFG_PM_CONTROL_OFFSET 0x44
  78. #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
  79. /********* Online Control Registers *******/
  80. #define PCICFG_ONLINE0 0xB0
  81. #define PCICFG_ONLINE1 0xB4
  82. /********* UE Status and Mask Registers ***/
  83. #define PCICFG_UE_STATUS_LOW 0xA0
  84. #define PCICFG_UE_STATUS_HIGH 0xA4
  85. #define PCICFG_UE_STATUS_LOW_MASK 0xA8
  86. #define PCICFG_UE_STATUS_HI_MASK 0xAC
  87. /******** SLI_INTF ***********************/
  88. #define SLI_INTF_REG_OFFSET 0x58
  89. #define SLI_INTF_VALID_MASK 0xE0000000
  90. #define SLI_INTF_VALID 0xC0000000
  91. #define SLI_INTF_HINT2_MASK 0x1F000000
  92. #define SLI_INTF_HINT2_SHIFT 24
  93. #define SLI_INTF_HINT1_MASK 0x00FF0000
  94. #define SLI_INTF_HINT1_SHIFT 16
  95. #define SLI_INTF_FAMILY_MASK 0x00000F00
  96. #define SLI_INTF_FAMILY_SHIFT 8
  97. #define SLI_INTF_IF_TYPE_MASK 0x0000F000
  98. #define SLI_INTF_IF_TYPE_SHIFT 12
  99. #define SLI_INTF_REV_MASK 0x000000F0
  100. #define SLI_INTF_REV_SHIFT 4
  101. #define SLI_INTF_FT_MASK 0x00000001
  102. #define SLI_INTF_TYPE_2 2
  103. #define SLI_INTF_TYPE_3 3
  104. /********* ISR0 Register offset **********/
  105. #define CEV_ISR0_OFFSET 0xC18
  106. #define CEV_ISR_SIZE 4
  107. /********* Event Q door bell *************/
  108. #define DB_EQ_OFFSET DB_CQ_OFFSET
  109. #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
  110. #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
  111. #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
  112. /* Clear the interrupt for this eq */
  113. #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
  114. /* Must be 1 */
  115. #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
  116. /* Number of event entries processed */
  117. #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
  118. /* Rearm bit */
  119. #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
  120. /* Rearm to interrupt delay encoding */
  121. #define DB_EQ_R2I_DLY_SHIFT (30) /* bits 30 - 31 */
  122. /* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different
  123. * values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is
  124. * programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay
  125. * between rearming the EQ and next interrupt on this EQ is desired.
  126. */
  127. #define R2I_DLY_ENC_0 0 /* No delay */
  128. #define R2I_DLY_ENC_1 1 /* maps to 160us EQ delay */
  129. #define R2I_DLY_ENC_2 2 /* maps to 96us EQ delay */
  130. #define R2I_DLY_ENC_3 3 /* maps to 48us EQ delay */
  131. /********* Compl Q door bell *************/
  132. #define DB_CQ_OFFSET 0x120
  133. #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
  134. #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
  135. #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
  136. placing at 11-15 */
  137. /* Number of event entries processed */
  138. #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
  139. /* Rearm bit */
  140. #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
  141. /********** TX ULP door bell *************/
  142. #define DB_TXULP1_OFFSET 0x60
  143. #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
  144. /* Number of tx entries posted */
  145. #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
  146. #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
  147. /********** RQ(erx) door bell ************/
  148. #define DB_RQ_OFFSET 0x100
  149. #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
  150. /* Number of rx frags posted */
  151. #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
  152. /********** MCC door bell ************/
  153. #define DB_MCCQ_OFFSET 0x140
  154. #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
  155. /* Number of entries posted */
  156. #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
  157. /********** SRIOV VF PCICFG OFFSET ********/
  158. #define SRIOV_VF_PCICFG_OFFSET (4096)
  159. /********** FAT TABLE ********/
  160. #define RETRIEVE_FAT 0
  161. #define QUERY_FAT 1
  162. /************* Rx Packet Type Encoding **************/
  163. #define BE_UNICAST_PACKET 0
  164. #define BE_MULTICAST_PACKET 1
  165. #define BE_BROADCAST_PACKET 2
  166. #define BE_RSVD_PACKET 3
  167. /*
  168. * BE descriptors: host memory data structures whose formats
  169. * are hardwired in BE silicon.
  170. */
  171. /* Event Queue Descriptor */
  172. #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
  173. #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
  174. #define EQ_ENTRY_RES_ID_SHIFT 16
  175. struct be_eq_entry {
  176. u32 evt;
  177. };
  178. /* TX Queue Descriptor */
  179. #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
  180. struct be_eth_wrb {
  181. __le32 frag_pa_hi; /* dword 0 */
  182. __le32 frag_pa_lo; /* dword 1 */
  183. u32 rsvd0; /* dword 2 */
  184. __le32 frag_len; /* dword 3: bits 0 - 15 */
  185. } __packed;
  186. /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
  187. * actual structure is defined as a byte : used to calculate
  188. * offset/shift/mask of each field */
  189. struct amap_eth_hdr_wrb {
  190. u8 rsvd0[32]; /* dword 0 */
  191. u8 rsvd1[32]; /* dword 1 */
  192. u8 complete; /* dword 2 */
  193. u8 event;
  194. u8 crc;
  195. u8 forward;
  196. u8 lso6;
  197. u8 mgmt;
  198. u8 ipcs;
  199. u8 udpcs;
  200. u8 tcpcs;
  201. u8 lso;
  202. u8 vlan;
  203. u8 gso[2];
  204. u8 num_wrb[5];
  205. u8 lso_mss[14];
  206. u8 len[16]; /* dword 3 */
  207. u8 vlan_tag[16];
  208. } __packed;
  209. #define TX_HDR_WRB_COMPL 1 /* word 2 */
  210. #define TX_HDR_WRB_EVT BIT(1) /* word 2 */
  211. #define TX_HDR_WRB_NUM_SHIFT 13 /* word 2: bits 13:17 */
  212. #define TX_HDR_WRB_NUM_MASK 0x1F /* word 2: bits 13:17 */
  213. struct be_eth_hdr_wrb {
  214. __le32 dw[4];
  215. };
  216. /********* Tx Compl Status Encoding *********/
  217. #define BE_TX_COMP_HDR_PARSE_ERR 0x2
  218. #define BE_TX_COMP_NDMA_ERR 0x3
  219. #define BE_TX_COMP_ACL_ERR 0x5
  220. #define LANCER_TX_COMP_LSO_ERR 0x1
  221. #define LANCER_TX_COMP_HSW_DROP_MAC_ERR 0x3
  222. #define LANCER_TX_COMP_HSW_DROP_VLAN_ERR 0x5
  223. #define LANCER_TX_COMP_QINQ_ERR 0x7
  224. #define LANCER_TX_COMP_SGE_ERR 0x9
  225. #define LANCER_TX_COMP_PARITY_ERR 0xb
  226. #define LANCER_TX_COMP_DMA_ERR 0xd
  227. /* TX Compl Queue Descriptor */
  228. /* Pseudo amap definition for eth_tx_compl in which each bit of the
  229. * actual structure is defined as a byte: used to calculate
  230. * offset/shift/mask of each field */
  231. struct amap_eth_tx_compl {
  232. u8 wrb_index[16]; /* dword 0 */
  233. u8 ct[2]; /* dword 0 */
  234. u8 port[2]; /* dword 0 */
  235. u8 rsvd0[8]; /* dword 0 */
  236. u8 status[4]; /* dword 0 */
  237. u8 user_bytes[16]; /* dword 1 */
  238. u8 nwh_bytes[8]; /* dword 1 */
  239. u8 lso; /* dword 1 */
  240. u8 cast_enc[2]; /* dword 1 */
  241. u8 rsvd1[5]; /* dword 1 */
  242. u8 rsvd2[32]; /* dword 2 */
  243. u8 pkts[16]; /* dword 3 */
  244. u8 ringid[11]; /* dword 3 */
  245. u8 hash_val[4]; /* dword 3 */
  246. u8 valid; /* dword 3 */
  247. } __packed;
  248. struct be_eth_tx_compl {
  249. u32 dw[4];
  250. };
  251. /* RX Queue Descriptor */
  252. struct be_eth_rx_d {
  253. u32 fragpa_hi;
  254. u32 fragpa_lo;
  255. };
  256. /* RX Compl Queue Descriptor */
  257. /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
  258. * each bit of the actual structure is defined as a byte: used to calculate
  259. * offset/shift/mask of each field */
  260. struct amap_eth_rx_compl_v0 {
  261. u8 vlan_tag[16]; /* dword 0 */
  262. u8 pktsize[14]; /* dword 0 */
  263. u8 port; /* dword 0 */
  264. u8 ip_opt; /* dword 0 */
  265. u8 err; /* dword 1 */
  266. u8 rsshp; /* dword 1 */
  267. u8 ipf; /* dword 1 */
  268. u8 tcpf; /* dword 1 */
  269. u8 udpf; /* dword 1 */
  270. u8 ipcksm; /* dword 1 */
  271. u8 l4_cksm; /* dword 1 */
  272. u8 ip_version; /* dword 1 */
  273. u8 macdst[6]; /* dword 1 */
  274. u8 vtp; /* dword 1 */
  275. u8 ip_frag; /* dword 1 */
  276. u8 fragndx[10]; /* dword 1 */
  277. u8 ct[2]; /* dword 1 */
  278. u8 sw; /* dword 1 */
  279. u8 numfrags[3]; /* dword 1 */
  280. u8 rss_flush; /* dword 2 */
  281. u8 cast_enc[2]; /* dword 2 */
  282. u8 qnq; /* dword 2 */
  283. u8 rss_bank; /* dword 2 */
  284. u8 rsvd1[23]; /* dword 2 */
  285. u8 lro_pkt; /* dword 2 */
  286. u8 rsvd2[2]; /* dword 2 */
  287. u8 valid; /* dword 2 */
  288. u8 rsshash[32]; /* dword 3 */
  289. } __packed;
  290. /* Pseudo amap definition for BE3 native mode eth_rx_compl in which
  291. * each bit of the actual structure is defined as a byte: used to calculate
  292. * offset/shift/mask of each field */
  293. struct amap_eth_rx_compl_v1 {
  294. u8 vlan_tag[16]; /* dword 0 */
  295. u8 pktsize[14]; /* dword 0 */
  296. u8 vtp; /* dword 0 */
  297. u8 ip_opt; /* dword 0 */
  298. u8 err; /* dword 1 */
  299. u8 rsshp; /* dword 1 */
  300. u8 ipf; /* dword 1 */
  301. u8 tcpf; /* dword 1 */
  302. u8 udpf; /* dword 1 */
  303. u8 ipcksm; /* dword 1 */
  304. u8 l4_cksm; /* dword 1 */
  305. u8 ip_version; /* dword 1 */
  306. u8 macdst[7]; /* dword 1 */
  307. u8 rsvd0; /* dword 1 */
  308. u8 fragndx[10]; /* dword 1 */
  309. u8 ct[2]; /* dword 1 */
  310. u8 sw; /* dword 1 */
  311. u8 numfrags[3]; /* dword 1 */
  312. u8 rss_flush; /* dword 2 */
  313. u8 cast_enc[2]; /* dword 2 */
  314. u8 qnq; /* dword 2 */
  315. u8 rss_bank; /* dword 2 */
  316. u8 port[2]; /* dword 2 */
  317. u8 vntagp; /* dword 2 */
  318. u8 header_len[8]; /* dword 2 */
  319. u8 header_split[2]; /* dword 2 */
  320. u8 rsvd1[12]; /* dword 2 */
  321. u8 tunneled;
  322. u8 valid; /* dword 2 */
  323. u8 rsshash[32]; /* dword 3 */
  324. } __packed;
  325. struct be_eth_rx_compl {
  326. u32 dw[4];
  327. };