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/drivers/net/ethernet/emulex/benet/be_hw.h

http://github.com/mirrors/linux
C Header | 371 lines | 241 code | 44 blank | 86 comment | 0 complexity | 05a94e560aa78aac04806a6fc9dee403 MD5 | raw file
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2005-2016 Broadcom.
  4 * All rights reserved.
  5 *
  6 * Contact Information:
  7 * linux-drivers@emulex.com
  8 *
  9 * Emulex
 10 * 3333 Susan Street
 11 * Costa Mesa, CA 92626
 12 */
 13
 14/********* Mailbox door bell *************/
 15/* Used for driver communication with the FW.
 16 * The software must write this register twice to post any command. First,
 17 * it writes the register with hi=1 and the upper bits of the physical address
 18 * for the MAILBOX structure. Software must poll the ready bit until this
 19 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
 20 * bits in the address. It must poll the ready bit until the command is
 21 * complete. Upon completion, the MAILBOX will contain a valid completion
 22 * queue entry.
 23 */
 24#define MPU_MAILBOX_DB_OFFSET	0x160
 25#define MPU_MAILBOX_DB_RDY_MASK	0x1 	/* bit 0 */
 26#define MPU_MAILBOX_DB_HI_MASK	0x2	/* bit 1 */
 27
 28#define MPU_EP_CONTROL 		0
 29
 30/********** MPU semphore: used for SH & BE  *************/
 31#define SLIPORT_SOFTRESET_OFFSET		0x5c	/* CSR BAR offset */
 32#define SLIPORT_SEMAPHORE_OFFSET_BEx		0xac  /* CSR BAR offset */
 33#define SLIPORT_SEMAPHORE_OFFSET_SH		0x94  /* PCI-CFG offset */
 34#define POST_STAGE_MASK				0x0000FFFF
 35#define POST_ERR_MASK				0x1
 36#define POST_ERR_SHIFT				31
 37#define POST_ERR_RECOVERY_CODE_MASK		0xFFF
 38
 39/* Soft Reset register masks */
 40#define SLIPORT_SOFTRESET_SR_MASK		0x00000080	/* SR bit */
 41
 42/* MPU semphore POST stage values */
 43#define POST_STAGE_AWAITING_HOST_RDY 	0x1 /* FW awaiting goahead from host */
 44#define POST_STAGE_HOST_RDY 		0x2 /* Host has given go-ahed to FW */
 45#define POST_STAGE_BE_RESET		0x3 /* Host wants to reset chip */
 46#define POST_STAGE_ARMFW_RDY		0xc000	/* FW is done with POST */
 47#define POST_STAGE_RECOVERABLE_ERR	0xE000	/* Recoverable err detected */
 48/* FW has detected a UE and is dumping FAT log data */
 49#define POST_STAGE_FAT_LOG_START       0x0D00
 50#define POST_STAGE_ARMFW_UE            0xF000  /*FW has asserted an UE*/
 51
 52/* Lancer SLIPORT registers */
 53#define SLIPORT_STATUS_OFFSET		0x404
 54#define SLIPORT_CONTROL_OFFSET		0x408
 55#define SLIPORT_ERROR1_OFFSET		0x40C
 56#define SLIPORT_ERROR2_OFFSET		0x410
 57#define PHYSDEV_CONTROL_OFFSET		0x414
 58
 59#define SLIPORT_STATUS_ERR_MASK		0x80000000
 60#define SLIPORT_STATUS_DIP_MASK		0x02000000
 61#define SLIPORT_STATUS_RN_MASK		0x01000000
 62#define SLIPORT_STATUS_RDY_MASK		0x00800000
 63#define SLI_PORT_CONTROL_IP_MASK	0x08000000
 64#define PHYSDEV_CONTROL_FW_RESET_MASK	0x00000002
 65#define PHYSDEV_CONTROL_DD_MASK		0x00000004
 66#define PHYSDEV_CONTROL_INP_MASK	0x40000000
 67
 68#define SLIPORT_ERROR_NO_RESOURCE1	0x2
 69#define SLIPORT_ERROR_NO_RESOURCE2	0x9
 70
 71#define SLIPORT_ERROR_FW_RESET1		0x2
 72#define SLIPORT_ERROR_FW_RESET2		0x0
 73
 74/********* Memory BAR register ************/
 75#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 	0xfc
 76/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 77 * Disable" may still globally block interrupts in addition to individual
 78 * interrupt masks; a mechanism for the device driver to block all interrupts
 79 * atomically without having to arbitrate for the PCI Interrupt Disable bit
 80 * with the OS.
 81 */
 82#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	BIT(29) /* bit 29 */
 83
 84/********* PCI Function Capability *********/
 85#define BE_FUNCTION_CAPS_RSS			0x2
 86#define BE_FUNCTION_CAPS_SUPER_NIC		0x40
 87
 88/********* Power management (WOL) **********/
 89#define PCICFG_PM_CONTROL_OFFSET		0x44
 90#define PCICFG_PM_CONTROL_MASK			0x108	/* bits 3 & 8 */
 91
 92/********* Online Control Registers *******/
 93#define PCICFG_ONLINE0				0xB0
 94#define PCICFG_ONLINE1				0xB4
 95
 96/********* UE Status and Mask Registers ***/
 97#define PCICFG_UE_STATUS_LOW			0xA0
 98#define PCICFG_UE_STATUS_HIGH			0xA4
 99#define PCICFG_UE_STATUS_LOW_MASK		0xA8
100#define PCICFG_UE_STATUS_HI_MASK		0xAC
101
102/******** SLI_INTF ***********************/
103#define SLI_INTF_REG_OFFSET			0x58
104#define SLI_INTF_VALID_MASK			0xE0000000
105#define SLI_INTF_VALID				0xC0000000
106#define SLI_INTF_HINT2_MASK			0x1F000000
107#define SLI_INTF_HINT2_SHIFT			24
108#define SLI_INTF_HINT1_MASK			0x00FF0000
109#define SLI_INTF_HINT1_SHIFT			16
110#define SLI_INTF_FAMILY_MASK			0x00000F00
111#define SLI_INTF_FAMILY_SHIFT			8
112#define SLI_INTF_IF_TYPE_MASK			0x0000F000
113#define SLI_INTF_IF_TYPE_SHIFT			12
114#define SLI_INTF_REV_MASK			0x000000F0
115#define SLI_INTF_REV_SHIFT			4
116#define SLI_INTF_FT_MASK			0x00000001
117
118#define SLI_INTF_TYPE_2		2
119#define SLI_INTF_TYPE_3		3
120
121/********* ISR0 Register offset **********/
122#define CEV_ISR0_OFFSET 			0xC18
123#define CEV_ISR_SIZE				4
124
125/********* Event Q door bell *************/
126#define DB_EQ_OFFSET			DB_CQ_OFFSET
127#define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
128#define DB_EQ_RING_ID_EXT_MASK		0x3e00  /* bits 9-13 */
129#define DB_EQ_RING_ID_EXT_MASK_SHIFT	(2) /* qid bits 9-13 placing at 11-15 */
130
131/* Clear the interrupt for this eq */
132#define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
133/* Must be 1 */
134#define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
135/* Number of event entries processed */
136#define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
137/* Rearm bit */
138#define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */
139/* Rearm to interrupt delay encoding */
140#define DB_EQ_R2I_DLY_SHIFT		(30)    /* bits 30 - 31 */
141
142/* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different
143 * values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is
144 * programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay
145 * between rearming the EQ and next interrupt on this EQ is desired.
146 */
147#define	R2I_DLY_ENC_0			0	/* No delay */
148#define	R2I_DLY_ENC_1			1	/* maps to 160us EQ delay */
149#define	R2I_DLY_ENC_2			2	/* maps to 96us EQ delay */
150#define	R2I_DLY_ENC_3			3	/* maps to 48us EQ delay */
151
152/********* Compl Q door bell *************/
153#define DB_CQ_OFFSET 			0x120
154#define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
155#define DB_CQ_RING_ID_EXT_MASK		0x7C00	/* bits 10-14 */
156#define DB_CQ_RING_ID_EXT_MASK_SHIFT	(1)	/* qid bits 10-14
157						 placing at 11-15 */
158
159/* Number of event entries processed */
160#define DB_CQ_NUM_POPPED_SHIFT		(16) 	/* bits 16 - 28 */
161/* Rearm bit */
162#define DB_CQ_REARM_SHIFT		(29) 	/* bit 29 */
163
164/********** TX ULP door bell *************/
165#define DB_TXULP1_OFFSET		0x60
166#define DB_TXULP_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
167/* Number of tx entries posted */
168#define DB_TXULP_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
169#define DB_TXULP_NUM_POSTED_MASK	0x3FFF	/* bits 16 - 29 */
170
171/********** RQ(erx) door bell ************/
172#define DB_RQ_OFFSET 			0x100
173#define DB_RQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
174/* Number of rx frags posted */
175#define DB_RQ_NUM_POSTED_SHIFT		(24)	/* bits 24 - 31 */
176
177/********** MCC door bell ************/
178#define DB_MCCQ_OFFSET 			0x140
179#define DB_MCCQ_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
180/* Number of entries posted */
181#define DB_MCCQ_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
182
183/********** SRIOV VF PCICFG OFFSET ********/
184#define SRIOV_VF_PCICFG_OFFSET		(4096)
185
186/********** FAT TABLE  ********/
187#define RETRIEVE_FAT	0
188#define QUERY_FAT	1
189
190/************* Rx Packet Type Encoding **************/
191#define BE_UNICAST_PACKET		0
192#define BE_MULTICAST_PACKET		1
193#define BE_BROADCAST_PACKET		2
194#define BE_RSVD_PACKET			3
195
196/*
197 * BE descriptors: host memory data structures whose formats
198 * are hardwired in BE silicon.
199 */
200/* Event Queue Descriptor */
201#define EQ_ENTRY_VALID_MASK 		0x1	/* bit 0 */
202#define EQ_ENTRY_RES_ID_MASK 		0xFFFF	/* bits 16 - 31 */
203#define EQ_ENTRY_RES_ID_SHIFT 		16
204
205struct be_eq_entry {
206	u32 evt;
207};
208
209/* TX Queue Descriptor */
210#define ETH_WRB_FRAG_LEN_MASK		0xFFFF
211struct be_eth_wrb {
212	__le32 frag_pa_hi;		/* dword 0 */
213	__le32 frag_pa_lo;		/* dword 1 */
214	u32 rsvd0;			/* dword 2 */
215	__le32 frag_len;		/* dword 3: bits 0 - 15 */
216} __packed;
217
218/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
219 * actual structure is defined as a byte : used to calculate
220 * offset/shift/mask of each field */
221struct amap_eth_hdr_wrb {
222	u8 rsvd0[32];		/* dword 0 */
223	u8 rsvd1[32];		/* dword 1 */
224	u8 complete;		/* dword 2 */
225	u8 event;
226	u8 crc;
227	u8 forward;
228	u8 lso6;
229	u8 mgmt;
230	u8 ipcs;
231	u8 udpcs;
232	u8 tcpcs;
233	u8 lso;
234	u8 vlan;
235	u8 gso[2];
236	u8 num_wrb[5];
237	u8 lso_mss[14];
238	u8 len[16];		/* dword 3 */
239	u8 vlan_tag[16];
240} __packed;
241
242#define TX_HDR_WRB_COMPL		1		/* word 2 */
243#define TX_HDR_WRB_EVT			BIT(1)		/* word 2 */
244#define TX_HDR_WRB_NUM_SHIFT		13		/* word 2: bits 13:17 */
245#define TX_HDR_WRB_NUM_MASK		0x1F		/* word 2: bits 13:17 */
246
247struct be_eth_hdr_wrb {
248	__le32 dw[4];
249};
250
251/********* Tx Compl Status Encoding *********/
252#define BE_TX_COMP_HDR_PARSE_ERR	0x2
253#define BE_TX_COMP_NDMA_ERR		0x3
254#define BE_TX_COMP_ACL_ERR		0x5
255
256#define LANCER_TX_COMP_LSO_ERR			0x1
257#define LANCER_TX_COMP_HSW_DROP_MAC_ERR		0x3
258#define LANCER_TX_COMP_HSW_DROP_VLAN_ERR	0x5
259#define LANCER_TX_COMP_QINQ_ERR			0x7
260#define LANCER_TX_COMP_SGE_ERR			0x9
261#define LANCER_TX_COMP_PARITY_ERR		0xb
262#define LANCER_TX_COMP_DMA_ERR			0xd
263
264/* TX Compl Queue Descriptor */
265
266/* Pseudo amap definition for eth_tx_compl in which each bit of the
267 * actual structure is defined as a byte: used to calculate
268 * offset/shift/mask of each field */
269struct amap_eth_tx_compl {
270	u8 wrb_index[16];	/* dword 0 */
271	u8 ct[2]; 		/* dword 0 */
272	u8 port[2];		/* dword 0 */
273	u8 rsvd0[8];		/* dword 0 */
274	u8 status[4];		/* dword 0 */
275	u8 user_bytes[16];	/* dword 1 */
276	u8 nwh_bytes[8];	/* dword 1 */
277	u8 lso;			/* dword 1 */
278	u8 cast_enc[2];		/* dword 1 */
279	u8 rsvd1[5];		/* dword 1 */
280	u8 rsvd2[32];		/* dword 2 */
281	u8 pkts[16];		/* dword 3 */
282	u8 ringid[11];		/* dword 3 */
283	u8 hash_val[4];		/* dword 3 */
284	u8 valid;		/* dword 3 */
285} __packed;
286
287struct be_eth_tx_compl {
288	u32 dw[4];
289};
290
291/* RX Queue Descriptor */
292struct be_eth_rx_d {
293	u32 fragpa_hi;
294	u32 fragpa_lo;
295};
296
297/* RX Compl Queue Descriptor */
298
299/* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
300 * each bit of the actual structure is defined as a byte: used to calculate
301 * offset/shift/mask of each field */
302struct amap_eth_rx_compl_v0 {
303	u8 vlan_tag[16];	/* dword 0 */
304	u8 pktsize[14];		/* dword 0 */
305	u8 port;		/* dword 0 */
306	u8 ip_opt;		/* dword 0 */
307	u8 err;			/* dword 1 */
308	u8 rsshp;		/* dword 1 */
309	u8 ipf;			/* dword 1 */
310	u8 tcpf;		/* dword 1 */
311	u8 udpf;		/* dword 1 */
312	u8 ipcksm;		/* dword 1 */
313	u8 l4_cksm;		/* dword 1 */
314	u8 ip_version;		/* dword 1 */
315	u8 macdst[6];		/* dword 1 */
316	u8 vtp;			/* dword 1 */
317	u8 ip_frag;		/* dword 1 */
318	u8 fragndx[10];		/* dword 1 */
319	u8 ct[2];		/* dword 1 */
320	u8 sw;			/* dword 1 */
321	u8 numfrags[3];		/* dword 1 */
322	u8 rss_flush;		/* dword 2 */
323	u8 cast_enc[2];		/* dword 2 */
324	u8 qnq;			/* dword 2 */
325	u8 rss_bank;		/* dword 2 */
326	u8 rsvd1[23];		/* dword 2 */
327	u8 lro_pkt;		/* dword 2 */
328	u8 rsvd2[2];		/* dword 2 */
329	u8 valid;		/* dword 2 */
330	u8 rsshash[32];		/* dword 3 */
331} __packed;
332
333/* Pseudo amap definition for BE3 native mode eth_rx_compl in which
334 * each bit of the actual structure is defined as a byte: used to calculate
335 * offset/shift/mask of each field */
336struct amap_eth_rx_compl_v1 {
337	u8 vlan_tag[16];	/* dword 0 */
338	u8 pktsize[14];		/* dword 0 */
339	u8 vtp;			/* dword 0 */
340	u8 ip_opt;		/* dword 0 */
341	u8 err;			/* dword 1 */
342	u8 rsshp;		/* dword 1 */
343	u8 ipf;			/* dword 1 */
344	u8 tcpf;		/* dword 1 */
345	u8 udpf;		/* dword 1 */
346	u8 ipcksm;		/* dword 1 */
347	u8 l4_cksm;		/* dword 1 */
348	u8 ip_version;		/* dword 1 */
349	u8 macdst[7];		/* dword 1 */
350	u8 rsvd0;		/* dword 1 */
351	u8 fragndx[10];		/* dword 1 */
352	u8 ct[2];		/* dword 1 */
353	u8 sw;			/* dword 1 */
354	u8 numfrags[3];		/* dword 1 */
355	u8 rss_flush;		/* dword 2 */
356	u8 cast_enc[2];		/* dword 2 */
357	u8 qnq;			/* dword 2 */
358	u8 rss_bank;		/* dword 2 */
359	u8 port[2];		/* dword 2 */
360	u8 vntagp;		/* dword 2 */
361	u8 header_len[8];	/* dword 2 */
362	u8 header_split[2];	/* dword 2 */
363	u8 rsvd1[12];		/* dword 2 */
364	u8 tunneled;
365	u8 valid;		/* dword 2 */
366	u8 rsshash[32];		/* dword 3 */
367} __packed;
368
369struct be_eth_rx_compl {
370	u32 dw[4];
371};