/drivers/net/wireless/mwl8k.c
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1/* 2 * drivers/net/wireless/mwl8k.c 3 * Driver for Marvell TOPDOG 802.11 Wireless cards 4 * 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#include <linux/init.h> 13#include <linux/interrupt.h> 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/sched.h> 17#include <linux/spinlock.h> 18#include <linux/list.h> 19#include <linux/pci.h> 20#include <linux/delay.h> 21#include <linux/completion.h> 22#include <linux/etherdevice.h> 23#include <linux/slab.h> 24#include <net/mac80211.h> 25#include <linux/moduleparam.h> 26#include <linux/firmware.h> 27#include <linux/workqueue.h> 28 29#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" 30#define MWL8K_NAME KBUILD_MODNAME 31#define MWL8K_VERSION "0.13" 32 33/* Module parameters */ 34static bool ap_mode_default; 35module_param(ap_mode_default, bool, 0); 36MODULE_PARM_DESC(ap_mode_default, 37 "Set to 1 to make ap mode the default instead of sta mode"); 38 39/* Register definitions */ 40#define MWL8K_HIU_GEN_PTR 0x00000c10 41#define MWL8K_MODE_STA 0x0000005a 42#define MWL8K_MODE_AP 0x000000a5 43#define MWL8K_HIU_INT_CODE 0x00000c14 44#define MWL8K_FWSTA_READY 0xf0f1f2f4 45#define MWL8K_FWAP_READY 0xf1f2f4a5 46#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 47#define MWL8K_HIU_SCRATCH 0x00000c40 48 49/* Host->device communications */ 50#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 51#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c 52#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 53#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 54#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 55#define MWL8K_H2A_INT_DUMMY (1 << 20) 56#define MWL8K_H2A_INT_RESET (1 << 15) 57#define MWL8K_H2A_INT_DOORBELL (1 << 1) 58#define MWL8K_H2A_INT_PPA_READY (1 << 0) 59 60/* Device->host communications */ 61#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c 62#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 63#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 64#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 65#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c 66#define MWL8K_A2H_INT_DUMMY (1 << 20) 67#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14) 68#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) 69#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) 70#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) 71#define MWL8K_A2H_INT_RADIO_ON (1 << 6) 72#define MWL8K_A2H_INT_RADIO_OFF (1 << 5) 73#define MWL8K_A2H_INT_MAC_EVENT (1 << 3) 74#define MWL8K_A2H_INT_OPC_DONE (1 << 2) 75#define MWL8K_A2H_INT_RX_READY (1 << 1) 76#define MWL8K_A2H_INT_TX_DONE (1 << 0) 77 78/* HW micro second timer register 79 * located at offset 0xA600. This 80 * will be used to timestamp tx 81 * packets. 82 */ 83 84#define MWL8K_HW_TIMER_REGISTER 0x0000a600 85 86#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ 87 MWL8K_A2H_INT_CHNL_SWITCHED | \ 88 MWL8K_A2H_INT_QUEUE_EMPTY | \ 89 MWL8K_A2H_INT_RADAR_DETECT | \ 90 MWL8K_A2H_INT_RADIO_ON | \ 91 MWL8K_A2H_INT_RADIO_OFF | \ 92 MWL8K_A2H_INT_MAC_EVENT | \ 93 MWL8K_A2H_INT_OPC_DONE | \ 94 MWL8K_A2H_INT_RX_READY | \ 95 MWL8K_A2H_INT_TX_DONE | \ 96 MWL8K_A2H_INT_BA_WATCHDOG) 97 98#define MWL8K_RX_QUEUES 1 99#define MWL8K_TX_WMM_QUEUES 4 100#define MWL8K_MAX_AMPDU_QUEUES 8 101#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES) 102#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues) 103 104/* txpriorities are mapped with hw queues. 105 * Each hw queue has a txpriority. 106 */ 107#define TOTAL_HW_TX_QUEUES 8 108 109/* Each HW queue can have one AMPDU stream. 110 * But, because one of the hw queue is reserved, 111 * maximum AMPDU queues that can be created are 112 * one short of total tx queues. 113 */ 114#define MWL8K_NUM_AMPDU_STREAMS (TOTAL_HW_TX_QUEUES - 1) 115 116struct rxd_ops { 117 int rxd_size; 118 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); 119 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); 120 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status, 121 __le16 *qos, s8 *noise); 122}; 123 124struct mwl8k_device_info { 125 char *part_name; 126 char *helper_image; 127 char *fw_image_sta; 128 char *fw_image_ap; 129 struct rxd_ops *ap_rxd_ops; 130 u32 fw_api_ap; 131}; 132 133struct mwl8k_rx_queue { 134 int rxd_count; 135 136 /* hw receives here */ 137 int head; 138 139 /* refill descs here */ 140 int tail; 141 142 void *rxd; 143 dma_addr_t rxd_dma; 144 struct { 145 struct sk_buff *skb; 146 DEFINE_DMA_UNMAP_ADDR(dma); 147 } *buf; 148}; 149 150struct mwl8k_tx_queue { 151 /* hw transmits here */ 152 int head; 153 154 /* sw appends here */ 155 int tail; 156 157 unsigned int len; 158 struct mwl8k_tx_desc *txd; 159 dma_addr_t txd_dma; 160 struct sk_buff **skb; 161}; 162 163enum { 164 AMPDU_NO_STREAM, 165 AMPDU_STREAM_NEW, 166 AMPDU_STREAM_IN_PROGRESS, 167 AMPDU_STREAM_ACTIVE, 168}; 169 170struct mwl8k_ampdu_stream { 171 struct ieee80211_sta *sta; 172 u8 tid; 173 u8 state; 174 u8 idx; 175}; 176 177struct mwl8k_priv { 178 struct ieee80211_hw *hw; 179 struct pci_dev *pdev; 180 int irq; 181 182 struct mwl8k_device_info *device_info; 183 184 void __iomem *sram; 185 void __iomem *regs; 186 187 /* firmware */ 188 const struct firmware *fw_helper; 189 const struct firmware *fw_ucode; 190 191 /* hardware/firmware parameters */ 192 bool ap_fw; 193 struct rxd_ops *rxd_ops; 194 struct ieee80211_supported_band band_24; 195 struct ieee80211_channel channels_24[14]; 196 struct ieee80211_rate rates_24[13]; 197 struct ieee80211_supported_band band_50; 198 struct ieee80211_channel channels_50[4]; 199 struct ieee80211_rate rates_50[8]; 200 u32 ap_macids_supported; 201 u32 sta_macids_supported; 202 203 /* Ampdu stream information */ 204 u8 num_ampdu_queues; 205 spinlock_t stream_lock; 206 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES]; 207 struct work_struct watchdog_ba_handle; 208 209 /* firmware access */ 210 struct mutex fw_mutex; 211 struct task_struct *fw_mutex_owner; 212 struct task_struct *hw_restart_owner; 213 int fw_mutex_depth; 214 struct completion *hostcmd_wait; 215 216 atomic_t watchdog_event_pending; 217 218 /* lock held over TX and TX reap */ 219 spinlock_t tx_lock; 220 221 /* TX quiesce completion, protected by fw_mutex and tx_lock */ 222 struct completion *tx_wait; 223 224 /* List of interfaces. */ 225 u32 macids_used; 226 struct list_head vif_list; 227 228 /* power management status cookie from firmware */ 229 u32 *cookie; 230 dma_addr_t cookie_dma; 231 232 u16 num_mcaddrs; 233 u8 hw_rev; 234 u32 fw_rev; 235 u32 caps; 236 237 /* 238 * Running count of TX packets in flight, to avoid 239 * iterating over the transmit rings each time. 240 */ 241 int pending_tx_pkts; 242 243 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; 244 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES]; 245 u32 txq_offset[MWL8K_MAX_TX_QUEUES]; 246 247 bool radio_on; 248 bool radio_short_preamble; 249 bool sniffer_enabled; 250 bool wmm_enabled; 251 252 /* XXX need to convert this to handle multiple interfaces */ 253 bool capture_beacon; 254 u8 capture_bssid[ETH_ALEN]; 255 struct sk_buff *beacon_skb; 256 257 /* 258 * This FJ worker has to be global as it is scheduled from the 259 * RX handler. At this point we don't know which interface it 260 * belongs to until the list of bssids waiting to complete join 261 * is checked. 262 */ 263 struct work_struct finalize_join_worker; 264 265 /* Tasklet to perform TX reclaim. */ 266 struct tasklet_struct poll_tx_task; 267 268 /* Tasklet to perform RX. */ 269 struct tasklet_struct poll_rx_task; 270 271 /* Most recently reported noise in dBm */ 272 s8 noise; 273 274 /* 275 * preserve the queue configurations so they can be restored if/when 276 * the firmware image is swapped. 277 */ 278 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES]; 279 280 /* To perform the task of reloading the firmware */ 281 struct work_struct fw_reload; 282 bool hw_restart_in_progress; 283 284 /* async firmware loading state */ 285 unsigned fw_state; 286 char *fw_pref; 287 char *fw_alt; 288 bool is_8764; 289 struct completion firmware_loading_complete; 290 291 /* bitmap of running BSSes */ 292 u32 running_bsses; 293}; 294 295#define MAX_WEP_KEY_LEN 13 296#define NUM_WEP_KEYS 4 297 298/* Per interface specific private data */ 299struct mwl8k_vif { 300 struct list_head list; 301 struct ieee80211_vif *vif; 302 303 /* Firmware macid for this vif. */ 304 int macid; 305 306 /* Non AMPDU sequence number assigned by driver. */ 307 u16 seqno; 308 309 /* Saved WEP keys */ 310 struct { 311 u8 enabled; 312 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN]; 313 } wep_key_conf[NUM_WEP_KEYS]; 314 315 /* BSSID */ 316 u8 bssid[ETH_ALEN]; 317 318 /* A flag to indicate is HW crypto is enabled for this bssid */ 319 bool is_hw_crypto_enabled; 320}; 321#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) 322#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8)) 323 324struct tx_traffic_info { 325 u32 start_time; 326 u32 pkts; 327}; 328 329#define MWL8K_MAX_TID 8 330struct mwl8k_sta { 331 /* Index into station database. Returned by UPDATE_STADB. */ 332 u8 peer_id; 333 u8 is_ampdu_allowed; 334 struct tx_traffic_info tx_stats[MWL8K_MAX_TID]; 335}; 336#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv)) 337 338static const struct ieee80211_channel mwl8k_channels_24[] = { 339 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412, .hw_value = 1, }, 340 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417, .hw_value = 2, }, 341 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422, .hw_value = 3, }, 342 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427, .hw_value = 4, }, 343 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432, .hw_value = 5, }, 344 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437, .hw_value = 6, }, 345 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442, .hw_value = 7, }, 346 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447, .hw_value = 8, }, 347 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452, .hw_value = 9, }, 348 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457, .hw_value = 10, }, 349 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462, .hw_value = 11, }, 350 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467, .hw_value = 12, }, 351 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472, .hw_value = 13, }, 352 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484, .hw_value = 14, }, 353}; 354 355static const struct ieee80211_rate mwl8k_rates_24[] = { 356 { .bitrate = 10, .hw_value = 2, }, 357 { .bitrate = 20, .hw_value = 4, }, 358 { .bitrate = 55, .hw_value = 11, }, 359 { .bitrate = 110, .hw_value = 22, }, 360 { .bitrate = 220, .hw_value = 44, }, 361 { .bitrate = 60, .hw_value = 12, }, 362 { .bitrate = 90, .hw_value = 18, }, 363 { .bitrate = 120, .hw_value = 24, }, 364 { .bitrate = 180, .hw_value = 36, }, 365 { .bitrate = 240, .hw_value = 48, }, 366 { .bitrate = 360, .hw_value = 72, }, 367 { .bitrate = 480, .hw_value = 96, }, 368 { .bitrate = 540, .hw_value = 108, }, 369}; 370 371static const struct ieee80211_channel mwl8k_channels_50[] = { 372 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5180, .hw_value = 36, }, 373 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5200, .hw_value = 40, }, 374 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5220, .hw_value = 44, }, 375 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5240, .hw_value = 48, }, 376}; 377 378static const struct ieee80211_rate mwl8k_rates_50[] = { 379 { .bitrate = 60, .hw_value = 12, }, 380 { .bitrate = 90, .hw_value = 18, }, 381 { .bitrate = 120, .hw_value = 24, }, 382 { .bitrate = 180, .hw_value = 36, }, 383 { .bitrate = 240, .hw_value = 48, }, 384 { .bitrate = 360, .hw_value = 72, }, 385 { .bitrate = 480, .hw_value = 96, }, 386 { .bitrate = 540, .hw_value = 108, }, 387}; 388 389/* Set or get info from Firmware */ 390#define MWL8K_CMD_GET 0x0000 391#define MWL8K_CMD_SET 0x0001 392#define MWL8K_CMD_SET_LIST 0x0002 393 394/* Firmware command codes */ 395#define MWL8K_CMD_CODE_DNLD 0x0001 396#define MWL8K_CMD_GET_HW_SPEC 0x0003 397#define MWL8K_CMD_SET_HW_SPEC 0x0004 398#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 399#define MWL8K_CMD_GET_STAT 0x0014 400#define MWL8K_CMD_RADIO_CONTROL 0x001c 401#define MWL8K_CMD_RF_TX_POWER 0x001e 402#define MWL8K_CMD_TX_POWER 0x001f 403#define MWL8K_CMD_RF_ANTENNA 0x0020 404#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */ 405#define MWL8K_CMD_SET_PRE_SCAN 0x0107 406#define MWL8K_CMD_SET_POST_SCAN 0x0108 407#define MWL8K_CMD_SET_RF_CHANNEL 0x010a 408#define MWL8K_CMD_SET_AID 0x010d 409#define MWL8K_CMD_SET_RATE 0x0110 410#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 411#define MWL8K_CMD_RTS_THRESHOLD 0x0113 412#define MWL8K_CMD_SET_SLOT 0x0114 413#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 414#define MWL8K_CMD_SET_WMM_MODE 0x0123 415#define MWL8K_CMD_MIMO_CONFIG 0x0125 416#define MWL8K_CMD_USE_FIXED_RATE 0x0126 417#define MWL8K_CMD_ENABLE_SNIFFER 0x0150 418#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */ 419#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 420#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205 421#define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */ 422#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */ 423#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */ 424#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */ 425#define MWL8K_CMD_UPDATE_STADB 0x1123 426#define MWL8K_CMD_BASTREAM 0x1125 427 428static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize) 429{ 430 u16 command = le16_to_cpu(cmd); 431 432#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ 433 snprintf(buf, bufsize, "%s", #x);\ 434 return buf;\ 435 } while (0) 436 switch (command & ~0x8000) { 437 MWL8K_CMDNAME(CODE_DNLD); 438 MWL8K_CMDNAME(GET_HW_SPEC); 439 MWL8K_CMDNAME(SET_HW_SPEC); 440 MWL8K_CMDNAME(MAC_MULTICAST_ADR); 441 MWL8K_CMDNAME(GET_STAT); 442 MWL8K_CMDNAME(RADIO_CONTROL); 443 MWL8K_CMDNAME(RF_TX_POWER); 444 MWL8K_CMDNAME(TX_POWER); 445 MWL8K_CMDNAME(RF_ANTENNA); 446 MWL8K_CMDNAME(SET_BEACON); 447 MWL8K_CMDNAME(SET_PRE_SCAN); 448 MWL8K_CMDNAME(SET_POST_SCAN); 449 MWL8K_CMDNAME(SET_RF_CHANNEL); 450 MWL8K_CMDNAME(SET_AID); 451 MWL8K_CMDNAME(SET_RATE); 452 MWL8K_CMDNAME(SET_FINALIZE_JOIN); 453 MWL8K_CMDNAME(RTS_THRESHOLD); 454 MWL8K_CMDNAME(SET_SLOT); 455 MWL8K_CMDNAME(SET_EDCA_PARAMS); 456 MWL8K_CMDNAME(SET_WMM_MODE); 457 MWL8K_CMDNAME(MIMO_CONFIG); 458 MWL8K_CMDNAME(USE_FIXED_RATE); 459 MWL8K_CMDNAME(ENABLE_SNIFFER); 460 MWL8K_CMDNAME(SET_MAC_ADDR); 461 MWL8K_CMDNAME(SET_RATEADAPT_MODE); 462 MWL8K_CMDNAME(BSS_START); 463 MWL8K_CMDNAME(SET_NEW_STN); 464 MWL8K_CMDNAME(UPDATE_ENCRYPTION); 465 MWL8K_CMDNAME(UPDATE_STADB); 466 MWL8K_CMDNAME(BASTREAM); 467 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP); 468 default: 469 snprintf(buf, bufsize, "0x%x", cmd); 470 } 471#undef MWL8K_CMDNAME 472 473 return buf; 474} 475 476/* Hardware and firmware reset */ 477static void mwl8k_hw_reset(struct mwl8k_priv *priv) 478{ 479 iowrite32(MWL8K_H2A_INT_RESET, 480 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 481 iowrite32(MWL8K_H2A_INT_RESET, 482 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 483 msleep(20); 484} 485 486/* Release fw image */ 487static void mwl8k_release_fw(const struct firmware **fw) 488{ 489 if (*fw == NULL) 490 return; 491 release_firmware(*fw); 492 *fw = NULL; 493} 494 495static void mwl8k_release_firmware(struct mwl8k_priv *priv) 496{ 497 mwl8k_release_fw(&priv->fw_ucode); 498 mwl8k_release_fw(&priv->fw_helper); 499} 500 501/* states for asynchronous f/w loading */ 502static void mwl8k_fw_state_machine(const struct firmware *fw, void *context); 503enum { 504 FW_STATE_INIT = 0, 505 FW_STATE_LOADING_PREF, 506 FW_STATE_LOADING_ALT, 507 FW_STATE_ERROR, 508}; 509 510/* Request fw image */ 511static int mwl8k_request_fw(struct mwl8k_priv *priv, 512 const char *fname, const struct firmware **fw, 513 bool nowait) 514{ 515 /* release current image */ 516 if (*fw != NULL) 517 mwl8k_release_fw(fw); 518 519 if (nowait) 520 return request_firmware_nowait(THIS_MODULE, 1, fname, 521 &priv->pdev->dev, GFP_KERNEL, 522 priv, mwl8k_fw_state_machine); 523 else 524 return request_firmware(fw, fname, &priv->pdev->dev); 525} 526 527static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image, 528 bool nowait) 529{ 530 struct mwl8k_device_info *di = priv->device_info; 531 int rc; 532 533 if (di->helper_image != NULL) { 534 if (nowait) 535 rc = mwl8k_request_fw(priv, di->helper_image, 536 &priv->fw_helper, true); 537 else 538 rc = mwl8k_request_fw(priv, di->helper_image, 539 &priv->fw_helper, false); 540 if (rc) 541 printk(KERN_ERR "%s: Error requesting helper fw %s\n", 542 pci_name(priv->pdev), di->helper_image); 543 544 if (rc || nowait) 545 return rc; 546 } 547 548 if (nowait) { 549 /* 550 * if we get here, no helper image is needed. Skip the 551 * FW_STATE_INIT state. 552 */ 553 priv->fw_state = FW_STATE_LOADING_PREF; 554 rc = mwl8k_request_fw(priv, fw_image, 555 &priv->fw_ucode, 556 true); 557 } else 558 rc = mwl8k_request_fw(priv, fw_image, 559 &priv->fw_ucode, false); 560 if (rc) { 561 printk(KERN_ERR "%s: Error requesting firmware file %s\n", 562 pci_name(priv->pdev), fw_image); 563 mwl8k_release_fw(&priv->fw_helper); 564 return rc; 565 } 566 567 return 0; 568} 569 570struct mwl8k_cmd_pkt { 571 __le16 code; 572 __le16 length; 573 __u8 seq_num; 574 __u8 macid; 575 __le16 result; 576 char payload[0]; 577} __packed; 578 579/* 580 * Firmware loading. 581 */ 582static int 583mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) 584{ 585 void __iomem *regs = priv->regs; 586 dma_addr_t dma_addr; 587 int loops; 588 589 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); 590 if (pci_dma_mapping_error(priv->pdev, dma_addr)) 591 return -ENOMEM; 592 593 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); 594 iowrite32(0, regs + MWL8K_HIU_INT_CODE); 595 iowrite32(MWL8K_H2A_INT_DOORBELL, 596 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 597 iowrite32(MWL8K_H2A_INT_DUMMY, 598 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 599 600 loops = 1000; 601 do { 602 u32 int_code; 603 if (priv->is_8764) { 604 int_code = ioread32(regs + 605 MWL8K_HIU_H2A_INTERRUPT_STATUS); 606 if (int_code == 0) 607 break; 608 } else { 609 int_code = ioread32(regs + MWL8K_HIU_INT_CODE); 610 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { 611 iowrite32(0, regs + MWL8K_HIU_INT_CODE); 612 break; 613 } 614 } 615 cond_resched(); 616 udelay(1); 617 } while (--loops); 618 619 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); 620 621 return loops ? 0 : -ETIMEDOUT; 622} 623 624static int mwl8k_load_fw_image(struct mwl8k_priv *priv, 625 const u8 *data, size_t length) 626{ 627 struct mwl8k_cmd_pkt *cmd; 628 int done; 629 int rc = 0; 630 631 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); 632 if (cmd == NULL) 633 return -ENOMEM; 634 635 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); 636 cmd->seq_num = 0; 637 cmd->macid = 0; 638 cmd->result = 0; 639 640 done = 0; 641 while (length) { 642 int block_size = length > 256 ? 256 : length; 643 644 memcpy(cmd->payload, data + done, block_size); 645 cmd->length = cpu_to_le16(block_size); 646 647 rc = mwl8k_send_fw_load_cmd(priv, cmd, 648 sizeof(*cmd) + block_size); 649 if (rc) 650 break; 651 652 done += block_size; 653 length -= block_size; 654 } 655 656 if (!rc) { 657 cmd->length = 0; 658 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); 659 } 660 661 kfree(cmd); 662 663 return rc; 664} 665 666static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, 667 const u8 *data, size_t length) 668{ 669 unsigned char *buffer; 670 int may_continue, rc = 0; 671 u32 done, prev_block_size; 672 673 buffer = kmalloc(1024, GFP_KERNEL); 674 if (buffer == NULL) 675 return -ENOMEM; 676 677 done = 0; 678 prev_block_size = 0; 679 may_continue = 1000; 680 while (may_continue > 0) { 681 u32 block_size; 682 683 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); 684 if (block_size & 1) { 685 block_size &= ~1; 686 may_continue--; 687 } else { 688 done += prev_block_size; 689 length -= prev_block_size; 690 } 691 692 if (block_size > 1024 || block_size > length) { 693 rc = -EOVERFLOW; 694 break; 695 } 696 697 if (length == 0) { 698 rc = 0; 699 break; 700 } 701 702 if (block_size == 0) { 703 rc = -EPROTO; 704 may_continue--; 705 udelay(1); 706 continue; 707 } 708 709 prev_block_size = block_size; 710 memcpy(buffer, data + done, block_size); 711 712 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); 713 if (rc) 714 break; 715 } 716 717 if (!rc && length != 0) 718 rc = -EREMOTEIO; 719 720 kfree(buffer); 721 722 return rc; 723} 724 725static int mwl8k_load_firmware(struct ieee80211_hw *hw) 726{ 727 struct mwl8k_priv *priv = hw->priv; 728 const struct firmware *fw = priv->fw_ucode; 729 int rc; 730 int loops; 731 732 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4) && !priv->is_8764) { 733 const struct firmware *helper = priv->fw_helper; 734 735 if (helper == NULL) { 736 printk(KERN_ERR "%s: helper image needed but none " 737 "given\n", pci_name(priv->pdev)); 738 return -EINVAL; 739 } 740 741 rc = mwl8k_load_fw_image(priv, helper->data, helper->size); 742 if (rc) { 743 printk(KERN_ERR "%s: unable to load firmware " 744 "helper image\n", pci_name(priv->pdev)); 745 return rc; 746 } 747 msleep(20); 748 749 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); 750 } else { 751 if (priv->is_8764) 752 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); 753 else 754 rc = mwl8k_load_fw_image(priv, fw->data, fw->size); 755 } 756 757 if (rc) { 758 printk(KERN_ERR "%s: unable to load firmware image\n", 759 pci_name(priv->pdev)); 760 return rc; 761 } 762 763 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); 764 765 loops = 500000; 766 do { 767 u32 ready_code; 768 769 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); 770 if (ready_code == MWL8K_FWAP_READY) { 771 priv->ap_fw = true; 772 break; 773 } else if (ready_code == MWL8K_FWSTA_READY) { 774 priv->ap_fw = false; 775 break; 776 } 777 778 cond_resched(); 779 udelay(1); 780 } while (--loops); 781 782 return loops ? 0 : -ETIMEDOUT; 783} 784 785 786/* DMA header used by firmware and hardware. */ 787struct mwl8k_dma_data { 788 __le16 fwlen; 789 struct ieee80211_hdr wh; 790 char data[0]; 791} __packed; 792 793/* Routines to add/remove DMA header from skb. */ 794static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos) 795{ 796 struct mwl8k_dma_data *tr; 797 int hdrlen; 798 799 tr = (struct mwl8k_dma_data *)skb->data; 800 hdrlen = ieee80211_hdrlen(tr->wh.frame_control); 801 802 if (hdrlen != sizeof(tr->wh)) { 803 if (ieee80211_is_data_qos(tr->wh.frame_control)) { 804 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2); 805 *((__le16 *)(tr->data - 2)) = qos; 806 } else { 807 memmove(tr->data - hdrlen, &tr->wh, hdrlen); 808 } 809 } 810 811 if (hdrlen != sizeof(*tr)) 812 skb_pull(skb, sizeof(*tr) - hdrlen); 813} 814 815#define REDUCED_TX_HEADROOM 8 816 817static void 818mwl8k_add_dma_header(struct mwl8k_priv *priv, struct sk_buff *skb, 819 int head_pad, int tail_pad) 820{ 821 struct ieee80211_hdr *wh; 822 int hdrlen; 823 int reqd_hdrlen; 824 struct mwl8k_dma_data *tr; 825 826 /* 827 * Add a firmware DMA header; the firmware requires that we 828 * present a 2-byte payload length followed by a 4-address 829 * header (without QoS field), followed (optionally) by any 830 * WEP/ExtIV header (but only filled in for CCMP). 831 */ 832 wh = (struct ieee80211_hdr *)skb->data; 833 834 hdrlen = ieee80211_hdrlen(wh->frame_control); 835 836 /* 837 * Check if skb_resize is required because of 838 * tx_headroom adjustment. 839 */ 840 if (priv->ap_fw && (hdrlen < (sizeof(struct ieee80211_cts) 841 + REDUCED_TX_HEADROOM))) { 842 if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) { 843 844 wiphy_err(priv->hw->wiphy, 845 "Failed to reallocate TX buffer\n"); 846 return; 847 } 848 skb->truesize += REDUCED_TX_HEADROOM; 849 } 850 851 reqd_hdrlen = sizeof(*tr) + head_pad; 852 853 if (hdrlen != reqd_hdrlen) 854 skb_push(skb, reqd_hdrlen - hdrlen); 855 856 if (ieee80211_is_data_qos(wh->frame_control)) 857 hdrlen -= IEEE80211_QOS_CTL_LEN; 858 859 tr = (struct mwl8k_dma_data *)skb->data; 860 if (wh != &tr->wh) 861 memmove(&tr->wh, wh, hdrlen); 862 if (hdrlen != sizeof(tr->wh)) 863 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); 864 865 /* 866 * Firmware length is the length of the fully formed "802.11 867 * payload". That is, everything except for the 802.11 header. 868 * This includes all crypto material including the MIC. 869 */ 870 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad); 871} 872 873static void mwl8k_encapsulate_tx_frame(struct mwl8k_priv *priv, 874 struct sk_buff *skb) 875{ 876 struct ieee80211_hdr *wh; 877 struct ieee80211_tx_info *tx_info; 878 struct ieee80211_key_conf *key_conf; 879 int data_pad; 880 int head_pad = 0; 881 882 wh = (struct ieee80211_hdr *)skb->data; 883 884 tx_info = IEEE80211_SKB_CB(skb); 885 886 key_conf = NULL; 887 if (ieee80211_is_data(wh->frame_control)) 888 key_conf = tx_info->control.hw_key; 889 890 /* 891 * Make sure the packet header is in the DMA header format (4-address 892 * without QoS), and add head & tail padding when HW crypto is enabled. 893 * 894 * We have the following trailer padding requirements: 895 * - WEP: 4 trailer bytes (ICV) 896 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV) 897 * - CCMP: 8 trailer bytes (MIC) 898 */ 899 data_pad = 0; 900 if (key_conf != NULL) { 901 head_pad = key_conf->iv_len; 902 switch (key_conf->cipher) { 903 case WLAN_CIPHER_SUITE_WEP40: 904 case WLAN_CIPHER_SUITE_WEP104: 905 data_pad = 4; 906 break; 907 case WLAN_CIPHER_SUITE_TKIP: 908 data_pad = 12; 909 break; 910 case WLAN_CIPHER_SUITE_CCMP: 911 data_pad = 8; 912 break; 913 } 914 } 915 mwl8k_add_dma_header(priv, skb, head_pad, data_pad); 916} 917 918/* 919 * Packet reception for 88w8366/88w8764 AP firmware. 920 */ 921struct mwl8k_rxd_ap { 922 __le16 pkt_len; 923 __u8 sq2; 924 __u8 rate; 925 __le32 pkt_phys_addr; 926 __le32 next_rxd_phys_addr; 927 __le16 qos_control; 928 __le16 htsig2; 929 __le32 hw_rssi_info; 930 __le32 hw_noise_floor_info; 931 __u8 noise_floor; 932 __u8 pad0[3]; 933 __u8 rssi; 934 __u8 rx_status; 935 __u8 channel; 936 __u8 rx_ctrl; 937} __packed; 938 939#define MWL8K_AP_RATE_INFO_MCS_FORMAT 0x80 940#define MWL8K_AP_RATE_INFO_40MHZ 0x40 941#define MWL8K_AP_RATE_INFO_RATEID(x) ((x) & 0x3f) 942 943#define MWL8K_AP_RX_CTRL_OWNED_BY_HOST 0x80 944 945/* 8366/8764 AP rx_status bits */ 946#define MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK 0x80 947#define MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF 948#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02 949#define MWL8K_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04 950#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08 951 952static void mwl8k_rxd_ap_init(void *_rxd, dma_addr_t next_dma_addr) 953{ 954 struct mwl8k_rxd_ap *rxd = _rxd; 955 956 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); 957 rxd->rx_ctrl = MWL8K_AP_RX_CTRL_OWNED_BY_HOST; 958} 959 960static void mwl8k_rxd_ap_refill(void *_rxd, dma_addr_t addr, int len) 961{ 962 struct mwl8k_rxd_ap *rxd = _rxd; 963 964 rxd->pkt_len = cpu_to_le16(len); 965 rxd->pkt_phys_addr = cpu_to_le32(addr); 966 wmb(); 967 rxd->rx_ctrl = 0; 968} 969 970static int 971mwl8k_rxd_ap_process(void *_rxd, struct ieee80211_rx_status *status, 972 __le16 *qos, s8 *noise) 973{ 974 struct mwl8k_rxd_ap *rxd = _rxd; 975 976 if (!(rxd->rx_ctrl & MWL8K_AP_RX_CTRL_OWNED_BY_HOST)) 977 return -1; 978 rmb(); 979 980 memset(status, 0, sizeof(*status)); 981 982 status->signal = -rxd->rssi; 983 *noise = -rxd->noise_floor; 984 985 if (rxd->rate & MWL8K_AP_RATE_INFO_MCS_FORMAT) { 986 status->flag |= RX_FLAG_HT; 987 if (rxd->rate & MWL8K_AP_RATE_INFO_40MHZ) 988 status->flag |= RX_FLAG_40MHZ; 989 status->rate_idx = MWL8K_AP_RATE_INFO_RATEID(rxd->rate); 990 } else { 991 int i; 992 993 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) { 994 if (mwl8k_rates_24[i].hw_value == rxd->rate) { 995 status->rate_idx = i; 996 break; 997 } 998 } 999 } 1000 1001 if (rxd->channel > 14) { 1002 status->band = IEEE80211_BAND_5GHZ; 1003 if (!(status->flag & RX_FLAG_HT)) 1004 status->rate_idx -= 5; 1005 } else { 1006 status->band = IEEE80211_BAND_2GHZ; 1007 } 1008 status->freq = ieee80211_channel_to_frequency(rxd->channel, 1009 status->band); 1010 1011 *qos = rxd->qos_control; 1012 1013 if ((rxd->rx_status != MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR) && 1014 (rxd->rx_status & MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK) && 1015 (rxd->rx_status & MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR)) 1016 status->flag |= RX_FLAG_MMIC_ERROR; 1017 1018 return le16_to_cpu(rxd->pkt_len); 1019} 1020 1021static struct rxd_ops rxd_ap_ops = { 1022 .rxd_size = sizeof(struct mwl8k_rxd_ap), 1023 .rxd_init = mwl8k_rxd_ap_init, 1024 .rxd_refill = mwl8k_rxd_ap_refill, 1025 .rxd_process = mwl8k_rxd_ap_process, 1026}; 1027 1028/* 1029 * Packet reception for STA firmware. 1030 */ 1031struct mwl8k_rxd_sta { 1032 __le16 pkt_len; 1033 __u8 link_quality; 1034 __u8 noise_level; 1035 __le32 pkt_phys_addr; 1036 __le32 next_rxd_phys_addr; 1037 __le16 qos_control; 1038 __le16 rate_info; 1039 __le32 pad0[4]; 1040 __u8 rssi; 1041 __u8 channel; 1042 __le16 pad1; 1043 __u8 rx_ctrl; 1044 __u8 rx_status; 1045 __u8 pad2[2]; 1046} __packed; 1047 1048#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000 1049#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) 1050#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) 1051#define MWL8K_STA_RATE_INFO_40MHZ 0x0004 1052#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002 1053#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001 1054 1055#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02 1056#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04 1057/* ICV=0 or MIC=1 */ 1058#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08 1059/* Key is uploaded only in failure case */ 1060#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30 1061 1062static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr) 1063{ 1064 struct mwl8k_rxd_sta *rxd = _rxd; 1065 1066 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); 1067 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST; 1068} 1069 1070static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len) 1071{ 1072 struct mwl8k_rxd_sta *rxd = _rxd; 1073 1074 rxd->pkt_len = cpu_to_le16(len); 1075 rxd->pkt_phys_addr = cpu_to_le32(addr); 1076 wmb(); 1077 rxd->rx_ctrl = 0; 1078} 1079 1080static int 1081mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status, 1082 __le16 *qos, s8 *noise) 1083{ 1084 struct mwl8k_rxd_sta *rxd = _rxd; 1085 u16 rate_info; 1086 1087 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST)) 1088 return -1; 1089 rmb(); 1090 1091 rate_info = le16_to_cpu(rxd->rate_info); 1092 1093 memset(status, 0, sizeof(*status)); 1094 1095 status->signal = -rxd->rssi; 1096 *noise = -rxd->noise_level; 1097 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info); 1098 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info); 1099 1100 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE) 1101 status->flag |= RX_FLAG_SHORTPRE; 1102 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ) 1103 status->flag |= RX_FLAG_40MHZ; 1104 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI) 1105 status->flag |= RX_FLAG_SHORT_GI; 1106 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT) 1107 status->flag |= RX_FLAG_HT; 1108 1109 if (rxd->channel > 14) { 1110 status->band = IEEE80211_BAND_5GHZ; 1111 if (!(status->flag & RX_FLAG_HT)) 1112 status->rate_idx -= 5; 1113 } else { 1114 status->band = IEEE80211_BAND_2GHZ; 1115 } 1116 status->freq = ieee80211_channel_to_frequency(rxd->channel, 1117 status->band); 1118 1119 *qos = rxd->qos_control; 1120 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) && 1121 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE)) 1122 status->flag |= RX_FLAG_MMIC_ERROR; 1123 1124 return le16_to_cpu(rxd->pkt_len); 1125} 1126 1127static struct rxd_ops rxd_sta_ops = { 1128 .rxd_size = sizeof(struct mwl8k_rxd_sta), 1129 .rxd_init = mwl8k_rxd_sta_init, 1130 .rxd_refill = mwl8k_rxd_sta_refill, 1131 .rxd_process = mwl8k_rxd_sta_process, 1132}; 1133 1134 1135#define MWL8K_RX_DESCS 256 1136#define MWL8K_RX_MAXSZ 3800 1137 1138static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) 1139{ 1140 struct mwl8k_priv *priv = hw->priv; 1141 struct mwl8k_rx_queue *rxq = priv->rxq + index; 1142 int size; 1143 int i; 1144 1145 rxq->rxd_count = 0; 1146 rxq->head = 0; 1147 rxq->tail = 0; 1148 1149 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; 1150 1151 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); 1152 if (rxq->rxd == NULL) { 1153 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n"); 1154 return -ENOMEM; 1155 } 1156 memset(rxq->rxd, 0, size); 1157 1158 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL); 1159 if (rxq->buf == NULL) { 1160 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); 1161 return -ENOMEM; 1162 } 1163 1164 for (i = 0; i < MWL8K_RX_DESCS; i++) { 1165 int desc_size; 1166 void *rxd; 1167 int nexti; 1168 dma_addr_t next_dma_addr; 1169 1170 desc_size = priv->rxd_ops->rxd_size; 1171 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); 1172 1173 nexti = i + 1; 1174 if (nexti == MWL8K_RX_DESCS) 1175 nexti = 0; 1176 next_dma_addr = rxq->rxd_dma + (nexti * desc_size); 1177 1178 priv->rxd_ops->rxd_init(rxd, next_dma_addr); 1179 } 1180 1181 return 0; 1182} 1183 1184static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) 1185{ 1186 struct mwl8k_priv *priv = hw->priv; 1187 struct mwl8k_rx_queue *rxq = priv->rxq + index; 1188 int refilled; 1189 1190 refilled = 0; 1191 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { 1192 struct sk_buff *skb; 1193 dma_addr_t addr; 1194 int rx; 1195 void *rxd; 1196 1197 skb = dev_alloc_skb(MWL8K_RX_MAXSZ); 1198 if (skb == NULL) 1199 break; 1200 1201 addr = pci_map_single(priv->pdev, skb->data, 1202 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); 1203 1204 rxq->rxd_count++; 1205 rx = rxq->tail++; 1206 if (rxq->tail == MWL8K_RX_DESCS) 1207 rxq->tail = 0; 1208 rxq->buf[rx].skb = skb; 1209 dma_unmap_addr_set(&rxq->buf[rx], dma, addr); 1210 1211 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); 1212 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); 1213 1214 refilled++; 1215 } 1216 1217 return refilled; 1218} 1219 1220/* Must be called only when the card's reception is completely halted */ 1221static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) 1222{ 1223 struct mwl8k_priv *priv = hw->priv; 1224 struct mwl8k_rx_queue *rxq = priv->rxq + index; 1225 int i; 1226 1227 if (rxq->rxd == NULL) 1228 return; 1229 1230 for (i = 0; i < MWL8K_RX_DESCS; i++) { 1231 if (rxq->buf[i].skb != NULL) { 1232 pci_unmap_single(priv->pdev, 1233 dma_unmap_addr(&rxq->buf[i], dma), 1234 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); 1235 dma_unmap_addr_set(&rxq->buf[i], dma, 0); 1236 1237 kfree_skb(rxq->buf[i].skb); 1238 rxq->buf[i].skb = NULL; 1239 } 1240 } 1241 1242 kfree(rxq->buf); 1243 rxq->buf = NULL; 1244 1245 pci_free_consistent(priv->pdev, 1246 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, 1247 rxq->rxd, rxq->rxd_dma); 1248 rxq->rxd = NULL; 1249} 1250 1251 1252/* 1253 * Scan a list of BSSIDs to process for finalize join. 1254 * Allows for extension to process multiple BSSIDs. 1255 */ 1256static inline int 1257mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) 1258{ 1259 return priv->capture_beacon && 1260 ieee80211_is_beacon(wh->frame_control) && 1261 ether_addr_equal(wh->addr3, priv->capture_bssid); 1262} 1263 1264static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, 1265 struct sk_buff *skb) 1266{ 1267 struct mwl8k_priv *priv = hw->priv; 1268 1269 priv->capture_beacon = false; 1270 memset(priv->capture_bssid, 0, ETH_ALEN); 1271 1272 /* 1273 * Use GFP_ATOMIC as rxq_process is called from 1274 * the primary interrupt handler, memory allocation call 1275 * must not sleep. 1276 */ 1277 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); 1278 if (priv->beacon_skb != NULL) 1279 ieee80211_queue_work(hw, &priv->finalize_join_worker); 1280} 1281 1282static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list, 1283 u8 *bssid) 1284{ 1285 struct mwl8k_vif *mwl8k_vif; 1286 1287 list_for_each_entry(mwl8k_vif, 1288 vif_list, list) { 1289 if (memcmp(bssid, mwl8k_vif->bssid, 1290 ETH_ALEN) == 0) 1291 return mwl8k_vif; 1292 } 1293 1294 return NULL; 1295} 1296 1297static int rxq_process(struct ieee80211_hw *hw, int index, int limit) 1298{ 1299 struct mwl8k_priv *priv = hw->priv; 1300 struct mwl8k_vif *mwl8k_vif = NULL; 1301 struct mwl8k_rx_queue *rxq = priv->rxq + index; 1302 int processed; 1303 1304 processed = 0; 1305 while (rxq->rxd_count && limit--) { 1306 struct sk_buff *skb; 1307 void *rxd; 1308 int pkt_len; 1309 struct ieee80211_rx_status status; 1310 struct ieee80211_hdr *wh; 1311 __le16 qos; 1312 1313 skb = rxq->buf[rxq->head].skb; 1314 if (skb == NULL) 1315 break; 1316 1317 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); 1318 1319 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos, 1320 &priv->noise); 1321 if (pkt_len < 0) 1322 break; 1323 1324 rxq->buf[rxq->head].skb = NULL; 1325 1326 pci_unmap_single(priv->pdev, 1327 dma_unmap_addr(&rxq->buf[rxq->head], dma), 1328 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); 1329 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); 1330 1331 rxq->head++; 1332 if (rxq->head == MWL8K_RX_DESCS) 1333 rxq->head = 0; 1334 1335 rxq->rxd_count--; 1336 1337 wh = &((struct mwl8k_dma_data *)skb->data)->wh; 1338 1339 /* 1340 * Check for a pending join operation. Save a 1341 * copy of the beacon and schedule a tasklet to 1342 * send a FINALIZE_JOIN command to the firmware. 1343 */ 1344 if (mwl8k_capture_bssid(priv, (void *)skb->data)) 1345 mwl8k_save_beacon(hw, skb); 1346 1347 if (ieee80211_has_protected(wh->frame_control)) { 1348 1349 /* Check if hw crypto has been enabled for 1350 * this bss. If yes, set the status flags 1351 * accordingly 1352 */ 1353 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list, 1354 wh->addr1); 1355 1356 if (mwl8k_vif != NULL && 1357 mwl8k_vif->is_hw_crypto_enabled) { 1358 /* 1359 * When MMIC ERROR is encountered 1360 * by the firmware, payload is 1361 * dropped and only 32 bytes of 1362 * mwl8k Firmware header is sent 1363 * to the host. 1364 * 1365 * We need to add four bytes of 1366 * key information. In it 1367 * MAC80211 expects keyidx set to 1368 * 0 for triggering Counter 1369 * Measure of MMIC failure. 1370 */ 1371 if (status.flag & RX_FLAG_MMIC_ERROR) { 1372 struct mwl8k_dma_data *tr; 1373 tr = (struct mwl8k_dma_data *)skb->data; 1374 memset((void *)&(tr->data), 0, 4); 1375 pkt_len += 4; 1376 } 1377 1378 if (!ieee80211_is_auth(wh->frame_control)) 1379 status.flag |= RX_FLAG_IV_STRIPPED | 1380 RX_FLAG_DECRYPTED | 1381 RX_FLAG_MMIC_STRIPPED; 1382 } 1383 } 1384 1385 skb_put(skb, pkt_len); 1386 mwl8k_remove_dma_header(skb, qos); 1387 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); 1388 ieee80211_rx_irqsafe(hw, skb); 1389 1390 processed++; 1391 } 1392 1393 return processed; 1394} 1395 1396 1397/* 1398 * Packet transmission. 1399 */ 1400 1401#define MWL8K_TXD_STATUS_OK 0x00000001 1402#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 1403#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 1404#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 1405#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 1406 1407#define MWL8K_QOS_QLEN_UNSPEC 0xff00 1408#define MWL8K_QOS_ACK_POLICY_MASK 0x0060 1409#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000 1410#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060 1411#define MWL8K_QOS_EOSP 0x0010 1412 1413struct mwl8k_tx_desc { 1414 __le32 status; 1415 __u8 data_rate; 1416 __u8 tx_priority; 1417 __le16 qos_control; 1418 __le32 pkt_phys_addr; 1419 __le16 pkt_len; 1420 __u8 dest_MAC_addr[ETH_ALEN]; 1421 __le32 next_txd_phys_addr; 1422 __le32 timestamp; 1423 __le16 rate_info; 1424 __u8 peer_id; 1425 __u8 tx_frag_cnt; 1426} __packed; 1427 1428#define MWL8K_TX_DESCS 128 1429 1430static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) 1431{ 1432 struct mwl8k_priv *priv = hw->priv; 1433 struct mwl8k_tx_queue *txq = priv->txq + index; 1434 int size; 1435 int i; 1436 1437 txq->len = 0; 1438 txq->head = 0; 1439 txq->tail = 0; 1440 1441 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); 1442 1443 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); 1444 if (txq->txd == NULL) { 1445 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n"); 1446 return -ENOMEM; 1447 } 1448 memset(txq->txd, 0, size); 1449 1450 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL); 1451 if (txq->skb == NULL) { 1452 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); 1453 return -ENOMEM; 1454 } 1455 1456 for (i = 0; i < MWL8K_TX_DESCS; i++) { 1457 struct mwl8k_tx_desc *tx_desc; 1458 int nexti; 1459 1460 tx_desc = txq->txd + i; 1461 nexti = (i + 1) % MWL8K_TX_DESCS; 1462 1463 tx_desc->status = 0; 1464 tx_desc->next_txd_phys_addr = 1465 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); 1466 } 1467 1468 return 0; 1469} 1470 1471static inline void mwl8k_tx_start(struct mwl8k_priv *priv) 1472{ 1473 iowrite32(MWL8K_H2A_INT_PPA_READY, 1474 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1475 iowrite32(MWL8K_H2A_INT_DUMMY, 1476 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1477 ioread32(priv->regs + MWL8K_HIU_INT_CODE); 1478} 1479 1480static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw) 1481{ 1482 struct mwl8k_priv *priv = hw->priv; 1483 int i; 1484 1485 for (i = 0; i < mwl8k_tx_queues(priv); i++) { 1486 struct mwl8k_tx_queue *txq = priv->txq + i; 1487 int fw_owned = 0; 1488 int drv_owned = 0; 1489 int unused = 0; 1490 int desc; 1491 1492 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { 1493 struct mwl8k_tx_desc *tx_desc = txq->txd + desc; 1494 u32 status; 1495 1496 status = le32_to_cpu(tx_desc->status); 1497 if (status & MWL8K_TXD_STATUS_FW_OWNED) 1498 fw_owned++; 1499 else 1500 drv_owned++; 1501 1502 if (tx_desc->pkt_len == 0) 1503 unused++; 1504 } 1505 1506 wiphy_err(hw->wiphy, 1507 "txq[%d] len=%d head=%d tail=%d " 1508 "fw_owned=%d drv_owned=%d unused=%d\n", 1509 i, 1510 txq->len, txq->head, txq->tail, 1511 fw_owned, drv_owned, unused); 1512 } 1513} 1514 1515/* 1516 * Must be called with priv->fw_mutex held and tx queues stopped. 1517 */ 1518#define MWL8K_TX_WAIT_TIMEOUT_MS 5000 1519 1520static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) 1521{ 1522 struct mwl8k_priv *priv = hw->priv; 1523 DECLARE_COMPLETION_ONSTACK(tx_wait); 1524 int retry; 1525 int rc; 1526 1527 might_sleep(); 1528 1529 /* Since fw restart is in progress, allow only the firmware 1530 * commands from the restart code and block the other 1531 * commands since they are going to fail in any case since 1532 * the firmware has crashed 1533 */ 1534 if (priv->hw_restart_in_progress) { 1535 if (priv->hw_restart_owner == current) 1536 return 0; 1537 else 1538 return -EBUSY; 1539 } 1540 1541 if (atomic_read(&priv->watchdog_event_pending)) 1542 return 0; 1543 1544 /* 1545 * The TX queues are stopped at this point, so this test 1546 * doesn't need to take ->tx_lock. 1547 */ 1548 if (!priv->pending_tx_pkts) 1549 return 0; 1550 1551 retry = 1; 1552 rc = 0; 1553 1554 spin_lock_bh(&priv->tx_lock); 1555 priv->tx_wait = &tx_wait; 1556 while (!rc) { 1557 int oldcount; 1558 unsigned long timeout; 1559 1560 oldcount = priv->pending_tx_pkts; 1561 1562 spin_unlock_bh(&priv->tx_lock); 1563 timeout = wait_for_completion_timeout(&tx_wait, 1564 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS)); 1565 1566 if (atomic_read(&priv->watchdog_event_pending)) { 1567 spin_lock_bh(&priv->tx_lock); 1568 priv->tx_wait = NULL; 1569 spin_unlock_bh(&priv->tx_lock); 1570 return 0; 1571 } 1572 1573 spin_lock_bh(&priv->tx_lock); 1574 1575 if (timeout || !priv->pending_tx_pkts) { 1576 WARN_ON(priv->pending_tx_pkts); 1577 if (retry) 1578 wiphy_notice(hw->wiphy, "tx rings drained\n"); 1579 break; 1580 } 1581 1582 if (retry) { 1583 mwl8k_tx_start(priv); 1584 retry = 0; 1585 continue; 1586 } 1587 1588 if (priv->pending_tx_pkts < oldcount) { 1589 wiphy_notice(hw->wiphy, 1590 "waiting for tx rings to drain (%d -> %d pkts)\n", 1591 oldcount, priv->pending_tx_pkts); 1592 retry = 1; 1593 continue; 1594 } 1595 1596 priv->tx_wait = NULL; 1597 1598 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n", 1599 MWL8K_TX_WAIT_TIMEOUT_MS); 1600 mwl8k_dump_tx_rings(hw); 1601 priv->hw_restart_in_progress = true; 1602 ieee80211_queue_work(hw, &priv->fw_reload); 1603 1604 rc = -ETIMEDOUT; 1605 } 1606 priv->tx_wait = NULL; 1607 spin_unlock_bh(&priv->tx_lock); 1608 1609 return rc; 1610} 1611 1612#define MWL8K_TXD_SUCCESS(status) \ 1613 ((status) & (MWL8K_TXD_STATUS_OK | \ 1614 MWL8K_TXD_STATUS_OK_RETRY | \ 1615 MWL8K_TXD_STATUS_OK_MORE_RETRY)) 1616 1617static int mwl8k_tid_queue_mapping(u8 tid) 1618{ 1619 BUG_ON(tid > 7); 1620 1621 switch (tid) { 1622 case 0: 1623 case 3: 1624 return IEEE80211_AC_BE; 1625 break; 1626 case 1: 1627 case 2: 1628 return IEEE80211_AC_BK; 1629 break; 1630 case 4: 1631 case 5: 1632 return IEEE80211_AC_VI; 1633 break; 1634 case 6: 1635 case 7: 1636 return IEEE80211_AC_VO; 1637 break; 1638 default: 1639 return -1; 1640 break; 1641 } 1642} 1643 1644/* The firmware will fill in the rate information 1645 * for each packet that gets queued in the hardware 1646 * and these macros will interpret that info. 1647 */ 1648 1649#define RI_FORMAT(a) (a & 0x0001) 1650#define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3) 1651 1652static int 1653mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force) 1654{ 1655 struct mwl8k_priv *priv = hw->priv; 1656 struct mwl8k_tx_queue *txq = priv->txq + index; 1657 int processed; 1658 1659 processed = 0; 1660 while (txq->len > 0 && limit--) { 1661 int tx; 1662 struct mwl8k_tx_desc *tx_desc; 1663 unsigned long addr; 1664 int size; 1665 struct sk_buff *skb; 1666 struct ieee80211_tx_info *info; 1667 u32 status; 1668 struct ieee80211_sta *sta; 1669 struct mwl8k_sta *sta_info = NULL; 1670 u16 rate_info; 1671 struct ieee80211_hdr *wh; 1672 1673 tx = txq->head; 1674 tx_desc = txq->txd + tx; 1675 1676 status = le32_to_cpu(tx_desc->status); 1677 1678 if (status & MWL8K_TXD_STATUS_FW_OWNED) { 1679 if (!force) 1680 break; 1681 tx_desc->status &= 1682 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); 1683 } 1684 1685 txq->head = (tx + 1) % MWL8K_TX_DESCS; 1686 BUG_ON(txq->len == 0); 1687 txq->len--; 1688 priv->pending_tx_pkts--; 1689 1690 addr = le32_to_cpu(tx_desc->pkt_phys_addr); 1691 size = le16_to_cpu(tx_desc->pkt_len); 1692 skb = txq->skb[tx]; 1693 txq->skb[tx] = NULL; 1694 1695 BUG_ON(skb == NULL); 1696 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); 1697 1698 mwl8k_remove_dma_header(skb, tx_desc->qos_control); 1699 1700 wh = (struct ieee80211_hdr *) skb->data; 1701 1702 /* Mark descriptor as unused */ 1703 tx_desc->pkt_phys_addr = 0; 1704 tx_desc->pkt_len = 0; 1705 1706 info = IEEE80211_SKB_CB(skb); 1707 if (ieee80211_is_data(wh->frame_control)) { 1708 rcu_read_lock(); 1709 sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1, 1710 wh->addr2); 1711 if (sta) { 1712 sta_info = MWL8K_STA(sta); 1713 BUG_ON(sta_info == NULL); 1714 rate_info = le16_to_cpu(tx_desc->rate_info); 1715 /* If rate is < 6.5 Mpbs for an ht station 1716 * do not form an ampdu. If the station is a 1717 * legacy station (format = 0), do not form an 1718 * ampdu 1719 */ 1720 if (RI_RATE_ID_MCS(rate_info) < 1 || 1721 RI_FORMAT(rate_info) == 0) { 1722 sta_info->is_ampdu_allowed = false; 1723 } else { 1724 sta_info->is_ampdu_allowed = true; 1725 } 1726 } 1727 rcu_read_unlock(); 1728 } 1729 1730 ieee80211_tx_info_clear_status(info); 1731 1732 /* Rate control is happening in the firmware. 1733 * Ensure no tx rate is being reported. 1734 */ 1735 info->status.rates[0].idx = -1; 1736 info->status.rates[0].count = 1; 1737 1738 if (MWL8K_TXD_SUCCESS(status)) 1739 info->flags |= IEEE80211_TX_STAT_ACK; 1740 1741 ieee80211_tx_status_irqsafe(hw, skb); 1742 1743 processed++; 1744 } 1745 1746 return processed; 1747} 1748 1749/* must be called only when the card's transmit is completely halted */ 1750static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) 1751{ 1752 struct mwl8k_priv *priv = hw->priv; 1753 struct mwl8k_tx_queue *txq = priv->txq + index; 1754 1755 if (txq->txd == NULL) 1756 return; 1757 1758 mwl8k_txq_reclaim(hw, index, INT_MAX, 1); 1759 1760 kfree(txq->skb); 1761 txq->skb = NULL; 1762 1763 pci_free_consistent(priv->pdev, 1764 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), 1765 txq->txd, txq->txd_dma); 1766 txq->txd = NULL; 1767} 1768 1769/* caller must hold priv->stream_lock when calling the stream functions */ 1770static struct mwl8k_ampdu_stream * 1771mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid) 1772{ 1773 struct mwl8k_ampdu_stream *stream; 1774 struct mwl8k_priv *priv = hw->priv; 1775 int i; 1776 1777 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) { 1778 stream = &priv->ampdu[i]; 1779 if (stream->state == AMPDU_NO_STREAM) { 1780 stream->sta = sta; 1781 stream->state = AMPDU_STREAM_NEW; 1782 stream->tid = tid; 1783 stream->idx = i; 1784 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d", 1785 sta->addr, tid); 1786 return stream; 1787 } 1788 } 1789 return NULL; 1790} 1791 1792static int 1793mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream) 1794{ 1795 int ret; 1796 1797 /* if the stream has already been started, don't start it again */ 1798 if (stream->state != AMPDU_STREAM_NEW) 1799 return 0; 1800 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0); 1801 if (ret) 1802 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: " 1803 "%d\n", stream->sta->addr, stream->tid, ret); 1804 else 1805 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n", 1806 stream->sta->addr, stream->tid); 1807 return ret; 1808} 1809 1810static void 1811mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream) 1812{ 1813 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr, 1814 stream->tid); 1815 memset(stream, 0, sizeof(*stream)); 1816} 1817 1818static struct mwl8k_ampdu_stream * 1819mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid) 1820{ 1821 struct mwl8k_priv *priv = hw->priv; 1822 int i; 1823 1824 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) { 1825 struct mwl8k_ampdu_stream *stream; 1826 stream = &priv->ampdu[i]; 1827 if (stream->state == AMPDU_NO_STREAM) 1828 continue; 1829 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) && 1830 stream->tid == tid) 1831 return stream; 1832 } 1833 return NULL; 1834} 1835 1836#define MWL8K_AMPDU_PACKET_THRESHOLD 64 1837static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid) 1838{ 1839 struct mwl8k_sta *sta_info = MWL8K_STA(sta); 1840 struct tx_traffic_info *tx_stats; 1841 1842 BUG_ON(tid >= MWL8K_MAX_TID); 1843 tx_stats = &sta_info->tx_stats[tid]; 1844 1845 return sta_info->is_ampdu_allowed && 1846 tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD; 1847} 1848 1849static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid) 1850{ 1851 struct mwl8k_sta *sta_info = MWL8K_STA(sta); 1852 struct tx_traffic_info *tx_stats; 1853 1854 BUG_ON(tid >= MWL8K_MAX_TID); 1855 tx_stats = &sta_info->tx_stats[tid]; 1856 1857 if (tx_stats->start_time == 0) 1858 tx_stats->start_time = jiffies; 1859 1860 /* reset the packet count after each second elapses. If the number of 1861 * packets ever exceeds the ampdu_min_traffic threshold, we will allow 1862 * an ampdu stream to be started. 1863 */ 1864 if (jiffies - tx_stats->start_time > HZ) { 1865 tx_stats->pkts = 0; 1866 tx_stats->start_time = 0; 1867 } else 1868 tx_stats->pkts++; 1869} 1870 1871/* The hardware ampdu queues start from 5. 1872 * txpriorities for ampdu queues are 1873 * 5 6 7 0 1 2 3 4 ie., queue 5 is highest 1874 * and queue 3 is lowest (queue 4 is reserved) 1875 */ 1876#define BA_QUEUE 5 1877 1878static void 1879mwl8k_txq_xmit(struct ieee80211_hw *hw, 1880 int index, 1881 struct ieee80211_sta *sta, 1882 struct sk_buff *skb) 1883{ 1884 struct mwl8k_priv *priv = hw->priv; 1885 struct ieee80211_tx_info *tx_info; 1886 struct mwl8k_vif *mwl8k_vif; 1887 struct ieee80211_hdr *wh; 1888 struct mwl8k_tx_queue *txq; 1889 struct mwl8k_tx_desc *tx; 1890 dma_addr_t dma; 1891 u32 txstatus; 1892 u8 txdatarate; 1893 u16 qos; 1894 int txpriority; 1895 u8 tid = 0; 1896 struct mwl8k_ampdu_stream *stream = NULL; 1897 bool start_ba_session = false; 1898 bool mgmtframe = false; 1899 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1900 bool eapol_frame = false; 1901 1902 wh = (struct ieee80211_hdr *)skb->data; 1903 if (ieee80211_is_data_qos(wh->frame_control)) 1904 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); 1905 else 1906 qos = 0; 1907 1908 if (skb->protocol == cpu_to_be16(ETH_P_PAE)) 1909 eapol_frame = true; 1910 1911 if (ieee80211_is_mgmt(wh->frame_control)) 1912 mgmtframe = true; 1913 1914 if (priv->ap_fw) 1915 mwl8k_encapsulate_tx_frame(priv, skb); 1916 else 1917 mwl8k_add_dma_header(priv, skb, 0, 0); 1918 1919 wh = &((struct mwl8k_dma_data *)skb->data)->wh; 1920 1921 tx_info = IEEE80211_SKB_CB(skb); 1922 mwl8k_vif = MWL8K_VIF(tx_info->control.vif); 1923 1924 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1925 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1926 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno); 1927 mwl8k_vif->seqno += 0x10; 1928 } 1929 1930 /* Setup firmware control bit fields for each frame type. */ 1931 txstatus = 0; 1932 txdatarate = 0; 1933 if (ieee80211_is_mgmt(wh->frame_control) || 1934 ieee80211_is_ctl(wh->frame_control)) { 1935 txdatarate = 0; 1936 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP; 1937 } else if (ieee80211_is_data(wh->frame_control)) { 1938 txdatarate = 1; 1939 if (is_multicast_ether_addr(wh->addr1)) 1940 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; 1941 1942 qos &= ~MWL8K_QOS_ACK_POLICY_MASK; 1943 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1944 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK; 1945 else 1946 qos |= MWL8K_QOS_ACK_POLICY_NORMAL; 1947 } 1948 1949 /* Queue ADDBA request in the respective data queue. While setting up 1950 * the ampdu stream, mac80211 queues further packets for that 1951 * particular ra/tid pair. However, packets piled up in the hardware 1952 * for that ra/tid pair will still go out. ADDBA request and the 1953 * related data packets going out from different queues asynchronously 1954 * will cause a shift in the receiver window which might result in 1955 * ampdu packets getting dropped at the receiver after the stream has 1956 * been setup. 1957 */ 1958 if (unlikely(ieee80211_is_action(wh->frame_control) && 1959 mgmt->u.action.category == WLAN_CATEGORY_BACK && 1960 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ && 1961 priv->ap_fw)) { 1962 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 1963 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2; 1964 index = mwl8k_tid_queue_mapping(tid); 1965 } 1966 1967 txpriority = index; 1968 1969 if (priv->ap_fw && sta && sta->ht_cap.ht_supported && !eapol_frame && 1970 ieee80211_is_data_qos(wh->frame_control)) { 1971 tid = qos & 0xf; 1972 mwl8k_tx_count_packet(sta, tid); 1973 spin_lock(&priv->stream_lock); 1974 stream = mwl8k_lookup_stream(hw, sta->addr, tid); 1975 if (stream != NULL) { 1976 if (stream->state == AMPDU_STREAM_ACTIVE) { 1977 WARN_ON(!(qos & MWL8K_QOS_A…
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