/drivers/net/wireless/mwl8k.c

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  1. /*
  2. * drivers/net/wireless/mwl8k.c
  3. * Driver for Marvell TOPDOG 802.11 Wireless cards
  4. *
  5. * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/sched.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/list.h>
  18. #include <linux/pci.h>
  19. #include <linux/delay.h>
  20. #include <linux/completion.h>
  21. #include <linux/etherdevice.h>
  22. #include <linux/slab.h>
  23. #include <net/mac80211.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/firmware.h>
  26. #include <linux/workqueue.h>
  27. #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
  28. #define MWL8K_NAME KBUILD_MODNAME
  29. #define MWL8K_VERSION "0.13"
  30. /* Module parameters */
  31. static bool ap_mode_default;
  32. module_param(ap_mode_default, bool, 0);
  33. MODULE_PARM_DESC(ap_mode_default,
  34. "Set to 1 to make ap mode the default instead of sta mode");
  35. /* Register definitions */
  36. #define MWL8K_HIU_GEN_PTR 0x00000c10
  37. #define MWL8K_MODE_STA 0x0000005a
  38. #define MWL8K_MODE_AP 0x000000a5
  39. #define MWL8K_HIU_INT_CODE 0x00000c14
  40. #define MWL8K_FWSTA_READY 0xf0f1f2f4
  41. #define MWL8K_FWAP_READY 0xf1f2f4a5
  42. #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
  43. #define MWL8K_HIU_SCRATCH 0x00000c40
  44. /* Host->device communications */
  45. #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
  46. #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
  47. #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
  48. #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
  49. #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
  50. #define MWL8K_H2A_INT_DUMMY (1 << 20)
  51. #define MWL8K_H2A_INT_RESET (1 << 15)
  52. #define MWL8K_H2A_INT_DOORBELL (1 << 1)
  53. #define MWL8K_H2A_INT_PPA_READY (1 << 0)
  54. /* Device->host communications */
  55. #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
  56. #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
  57. #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
  58. #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
  59. #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
  60. #define MWL8K_A2H_INT_DUMMY (1 << 20)
  61. #define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
  62. #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
  63. #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
  64. #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
  65. #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
  66. #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
  67. #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
  68. #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
  69. #define MWL8K_A2H_INT_RX_READY (1 << 1)
  70. #define MWL8K_A2H_INT_TX_DONE (1 << 0)
  71. /* HW micro second timer register
  72. * located at offset 0xA600. This
  73. * will be used to timestamp tx
  74. * packets.
  75. */
  76. #define MWL8K_HW_TIMER_REGISTER 0x0000a600
  77. #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
  78. MWL8K_A2H_INT_CHNL_SWITCHED | \
  79. MWL8K_A2H_INT_QUEUE_EMPTY | \
  80. MWL8K_A2H_INT_RADAR_DETECT | \
  81. MWL8K_A2H_INT_RADIO_ON | \
  82. MWL8K_A2H_INT_RADIO_OFF | \
  83. MWL8K_A2H_INT_MAC_EVENT | \
  84. MWL8K_A2H_INT_OPC_DONE | \
  85. MWL8K_A2H_INT_RX_READY | \
  86. MWL8K_A2H_INT_TX_DONE | \
  87. MWL8K_A2H_INT_BA_WATCHDOG)
  88. #define MWL8K_RX_QUEUES 1
  89. #define MWL8K_TX_WMM_QUEUES 4
  90. #define MWL8K_MAX_AMPDU_QUEUES 8
  91. #define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
  92. #define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
  93. /* txpriorities are mapped with hw queues.
  94. * Each hw queue has a txpriority.
  95. */
  96. #define TOTAL_HW_TX_QUEUES 8
  97. /* Each HW queue can have one AMPDU stream.
  98. * But, because one of the hw queue is reserved,
  99. * maximum AMPDU queues that can be created are
  100. * one short of total tx queues.
  101. */
  102. #define MWL8K_NUM_AMPDU_STREAMS (TOTAL_HW_TX_QUEUES - 1)
  103. struct rxd_ops {
  104. int rxd_size;
  105. void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
  106. void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
  107. int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
  108. __le16 *qos, s8 *noise);
  109. };
  110. struct mwl8k_device_info {
  111. char *part_name;
  112. char *helper_image;
  113. char *fw_image_sta;
  114. char *fw_image_ap;
  115. struct rxd_ops *ap_rxd_ops;
  116. u32 fw_api_ap;
  117. };
  118. struct mwl8k_rx_queue {
  119. int rxd_count;
  120. /* hw receives here */
  121. int head;
  122. /* refill descs here */
  123. int tail;
  124. void *rxd;
  125. dma_addr_t rxd_dma;
  126. struct {
  127. struct sk_buff *skb;
  128. DEFINE_DMA_UNMAP_ADDR(dma);
  129. } *buf;
  130. };
  131. struct mwl8k_tx_queue {
  132. /* hw transmits here */
  133. int head;
  134. /* sw appends here */
  135. int tail;
  136. unsigned int len;
  137. struct mwl8k_tx_desc *txd;
  138. dma_addr_t txd_dma;
  139. struct sk_buff **skb;
  140. };
  141. enum {
  142. AMPDU_NO_STREAM,
  143. AMPDU_STREAM_NEW,
  144. AMPDU_STREAM_IN_PROGRESS,
  145. AMPDU_STREAM_ACTIVE,
  146. };
  147. struct mwl8k_ampdu_stream {
  148. struct ieee80211_sta *sta;
  149. u8 tid;
  150. u8 state;
  151. u8 idx;
  152. };
  153. struct mwl8k_priv {
  154. struct ieee80211_hw *hw;
  155. struct pci_dev *pdev;
  156. int irq;
  157. struct mwl8k_device_info *device_info;
  158. void __iomem *sram;
  159. void __iomem *regs;
  160. /* firmware */
  161. const struct firmware *fw_helper;
  162. const struct firmware *fw_ucode;
  163. /* hardware/firmware parameters */
  164. bool ap_fw;
  165. struct rxd_ops *rxd_ops;
  166. struct ieee80211_supported_band band_24;
  167. struct ieee80211_channel channels_24[14];
  168. struct ieee80211_rate rates_24[13];
  169. struct ieee80211_supported_band band_50;
  170. struct ieee80211_channel channels_50[4];
  171. struct ieee80211_rate rates_50[8];
  172. u32 ap_macids_supported;
  173. u32 sta_macids_supported;
  174. /* Ampdu stream information */
  175. u8 num_ampdu_queues;
  176. spinlock_t stream_lock;
  177. struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
  178. struct work_struct watchdog_ba_handle;
  179. /* firmware access */
  180. struct mutex fw_mutex;
  181. struct task_struct *fw_mutex_owner;
  182. struct task_struct *hw_restart_owner;
  183. int fw_mutex_depth;
  184. struct completion *hostcmd_wait;
  185. atomic_t watchdog_event_pending;
  186. /* lock held over TX and TX reap */
  187. spinlock_t tx_lock;
  188. /* TX quiesce completion, protected by fw_mutex and tx_lock */
  189. struct completion *tx_wait;
  190. /* List of interfaces. */
  191. u32 macids_used;
  192. struct list_head vif_list;
  193. /* power management status cookie from firmware */
  194. u32 *cookie;
  195. dma_addr_t cookie_dma;
  196. u16 num_mcaddrs;
  197. u8 hw_rev;
  198. u32 fw_rev;
  199. u32 caps;
  200. /*
  201. * Running count of TX packets in flight, to avoid
  202. * iterating over the transmit rings each time.
  203. */
  204. int pending_tx_pkts;
  205. struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
  206. struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
  207. u32 txq_offset[MWL8K_MAX_TX_QUEUES];
  208. bool radio_on;
  209. bool radio_short_preamble;
  210. bool sniffer_enabled;
  211. bool wmm_enabled;
  212. /* XXX need to convert this to handle multiple interfaces */
  213. bool capture_beacon;
  214. u8 capture_bssid[ETH_ALEN];
  215. struct sk_buff *beacon_skb;
  216. /*
  217. * This FJ worker has to be global as it is scheduled from the
  218. * RX handler. At this point we don't know which interface it
  219. * belongs to until the list of bssids waiting to complete join
  220. * is checked.
  221. */
  222. struct work_struct finalize_join_worker;
  223. /* Tasklet to perform TX reclaim. */
  224. struct tasklet_struct poll_tx_task;
  225. /* Tasklet to perform RX. */
  226. struct tasklet_struct poll_rx_task;
  227. /* Most recently reported noise in dBm */
  228. s8 noise;
  229. /*
  230. * preserve the queue configurations so they can be restored if/when
  231. * the firmware image is swapped.
  232. */
  233. struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
  234. /* To perform the task of reloading the firmware */
  235. struct work_struct fw_reload;
  236. bool hw_restart_in_progress;
  237. /* async firmware loading state */
  238. unsigned fw_state;
  239. char *fw_pref;
  240. char *fw_alt;
  241. bool is_8764;
  242. struct completion firmware_loading_complete;
  243. /* bitmap of running BSSes */
  244. u32 running_bsses;
  245. };
  246. #define MAX_WEP_KEY_LEN 13
  247. #define NUM_WEP_KEYS 4
  248. /* Per interface specific private data */
  249. struct mwl8k_vif {
  250. struct list_head list;
  251. struct ieee80211_vif *vif;
  252. /* Firmware macid for this vif. */
  253. int macid;
  254. /* Non AMPDU sequence number assigned by driver. */
  255. u16 seqno;
  256. /* Saved WEP keys */
  257. struct {
  258. u8 enabled;
  259. u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
  260. } wep_key_conf[NUM_WEP_KEYS];
  261. /* BSSID */
  262. u8 bssid[ETH_ALEN];
  263. /* A flag to indicate is HW crypto is enabled for this bssid */
  264. bool is_hw_crypto_enabled;
  265. };
  266. #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
  267. #define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
  268. struct tx_traffic_info {
  269. u32 start_time;
  270. u32 pkts;
  271. };
  272. #define MWL8K_MAX_TID 8
  273. struct mwl8k_sta {
  274. /* Index into station database. Returned by UPDATE_STADB. */
  275. u8 peer_id;
  276. u8 is_ampdu_allowed;
  277. struct tx_traffic_info tx_stats[MWL8K_MAX_TID];
  278. };
  279. #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
  280. static const struct ieee80211_channel mwl8k_channels_24[] = {
  281. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412, .hw_value = 1, },
  282. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417, .hw_value = 2, },
  283. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422, .hw_value = 3, },
  284. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427, .hw_value = 4, },
  285. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432, .hw_value = 5, },
  286. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437, .hw_value = 6, },
  287. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442, .hw_value = 7, },
  288. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447, .hw_value = 8, },
  289. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452, .hw_value = 9, },
  290. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457, .hw_value = 10, },
  291. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462, .hw_value = 11, },
  292. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467, .hw_value = 12, },
  293. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472, .hw_value = 13, },
  294. { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484, .hw_value = 14, },
  295. };
  296. static const struct ieee80211_rate mwl8k_rates_24[] = {
  297. { .bitrate = 10, .hw_value = 2, },
  298. { .bitrate = 20, .hw_value = 4, },
  299. { .bitrate = 55, .hw_value = 11, },
  300. { .bitrate = 110, .hw_value = 22, },
  301. { .bitrate = 220, .hw_value = 44, },
  302. { .bitrate = 60, .hw_value = 12, },
  303. { .bitrate = 90, .hw_value = 18, },
  304. { .bitrate = 120, .hw_value = 24, },
  305. { .bitrate = 180, .hw_value = 36, },
  306. { .bitrate = 240, .hw_value = 48, },
  307. { .bitrate = 360, .hw_value = 72, },
  308. { .bitrate = 480, .hw_value = 96, },
  309. { .bitrate = 540, .hw_value = 108, },
  310. };
  311. static const struct ieee80211_channel mwl8k_channels_50[] = {
  312. { .band = IEEE80211_BAND_5GHZ, .center_freq = 5180, .hw_value = 36, },
  313. { .band = IEEE80211_BAND_5GHZ, .center_freq = 5200, .hw_value = 40, },
  314. { .band = IEEE80211_BAND_5GHZ, .center_freq = 5220, .hw_value = 44, },
  315. { .band = IEEE80211_BAND_5GHZ, .center_freq = 5240, .hw_value = 48, },
  316. };
  317. static const struct ieee80211_rate mwl8k_rates_50[] = {
  318. { .bitrate = 60, .hw_value = 12, },
  319. { .bitrate = 90, .hw_value = 18, },
  320. { .bitrate = 120, .hw_value = 24, },
  321. { .bitrate = 180, .hw_value = 36, },
  322. { .bitrate = 240, .hw_value = 48, },
  323. { .bitrate = 360, .hw_value = 72, },
  324. { .bitrate = 480, .hw_value = 96, },
  325. { .bitrate = 540, .hw_value = 108, },
  326. };
  327. /* Set or get info from Firmware */
  328. #define MWL8K_CMD_GET 0x0000
  329. #define MWL8K_CMD_SET 0x0001
  330. #define MWL8K_CMD_SET_LIST 0x0002
  331. /* Firmware command codes */
  332. #define MWL8K_CMD_CODE_DNLD 0x0001
  333. #define MWL8K_CMD_GET_HW_SPEC 0x0003
  334. #define MWL8K_CMD_SET_HW_SPEC 0x0004
  335. #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
  336. #define MWL8K_CMD_GET_STAT 0x0014
  337. #define MWL8K_CMD_RADIO_CONTROL 0x001c
  338. #define MWL8K_CMD_RF_TX_POWER 0x001e
  339. #define MWL8K_CMD_TX_POWER 0x001f
  340. #define MWL8K_CMD_RF_ANTENNA 0x0020
  341. #define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
  342. #define MWL8K_CMD_SET_PRE_SCAN 0x0107
  343. #define MWL8K_CMD_SET_POST_SCAN 0x0108
  344. #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
  345. #define MWL8K_CMD_SET_AID 0x010d
  346. #define MWL8K_CMD_SET_RATE 0x0110
  347. #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
  348. #define MWL8K_CMD_RTS_THRESHOLD 0x0113
  349. #define MWL8K_CMD_SET_SLOT 0x0114
  350. #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
  351. #define MWL8K_CMD_SET_WMM_MODE 0x0123
  352. #define MWL8K_CMD_MIMO_CONFIG 0x0125
  353. #define MWL8K_CMD_USE_FIXED_RATE 0x0126
  354. #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
  355. #define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
  356. #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
  357. #define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
  358. #define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */
  359. #define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
  360. #define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
  361. #define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
  362. #define MWL8K_CMD_UPDATE_STADB 0x1123
  363. #define MWL8K_CMD_BASTREAM 0x1125
  364. static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
  365. {
  366. u16 command = le16_to_cpu(cmd);
  367. #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
  368. snprintf(buf, bufsize, "%s", #x);\
  369. return buf;\
  370. } while (0)
  371. switch (command & ~0x8000) {
  372. MWL8K_CMDNAME(CODE_DNLD);
  373. MWL8K_CMDNAME(GET_HW_SPEC);
  374. MWL8K_CMDNAME(SET_HW_SPEC);
  375. MWL8K_CMDNAME(MAC_MULTICAST_ADR);
  376. MWL8K_CMDNAME(GET_STAT);
  377. MWL8K_CMDNAME(RADIO_CONTROL);
  378. MWL8K_CMDNAME(RF_TX_POWER);
  379. MWL8K_CMDNAME(TX_POWER);
  380. MWL8K_CMDNAME(RF_ANTENNA);
  381. MWL8K_CMDNAME(SET_BEACON);
  382. MWL8K_CMDNAME(SET_PRE_SCAN);
  383. MWL8K_CMDNAME(SET_POST_SCAN);
  384. MWL8K_CMDNAME(SET_RF_CHANNEL);
  385. MWL8K_CMDNAME(SET_AID);
  386. MWL8K_CMDNAME(SET_RATE);
  387. MWL8K_CMDNAME(SET_FINALIZE_JOIN);
  388. MWL8K_CMDNAME(RTS_THRESHOLD);
  389. MWL8K_CMDNAME(SET_SLOT);
  390. MWL8K_CMDNAME(SET_EDCA_PARAMS);
  391. MWL8K_CMDNAME(SET_WMM_MODE);
  392. MWL8K_CMDNAME(MIMO_CONFIG);
  393. MWL8K_CMDNAME(USE_FIXED_RATE);
  394. MWL8K_CMDNAME(ENABLE_SNIFFER);
  395. MWL8K_CMDNAME(SET_MAC_ADDR);
  396. MWL8K_CMDNAME(SET_RATEADAPT_MODE);
  397. MWL8K_CMDNAME(BSS_START);
  398. MWL8K_CMDNAME(SET_NEW_STN);
  399. MWL8K_CMDNAME(UPDATE_ENCRYPTION);
  400. MWL8K_CMDNAME(UPDATE_STADB);
  401. MWL8K_CMDNAME(BASTREAM);
  402. MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
  403. default:
  404. snprintf(buf, bufsize, "0x%x", cmd);
  405. }
  406. #undef MWL8K_CMDNAME
  407. return buf;
  408. }
  409. /* Hardware and firmware reset */
  410. static void mwl8k_hw_reset(struct mwl8k_priv *priv)
  411. {
  412. iowrite32(MWL8K_H2A_INT_RESET,
  413. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  414. iowrite32(MWL8K_H2A_INT_RESET,
  415. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  416. msleep(20);
  417. }
  418. /* Release fw image */
  419. static void mwl8k_release_fw(const struct firmware **fw)
  420. {
  421. if (*fw == NULL)
  422. return;
  423. release_firmware(*fw);
  424. *fw = NULL;
  425. }
  426. static void mwl8k_release_firmware(struct mwl8k_priv *priv)
  427. {
  428. mwl8k_release_fw(&priv->fw_ucode);
  429. mwl8k_release_fw(&priv->fw_helper);
  430. }
  431. /* states for asynchronous f/w loading */
  432. static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
  433. enum {
  434. FW_STATE_INIT = 0,
  435. FW_STATE_LOADING_PREF,
  436. FW_STATE_LOADING_ALT,
  437. FW_STATE_ERROR,
  438. };
  439. /* Request fw image */
  440. static int mwl8k_request_fw(struct mwl8k_priv *priv,
  441. const char *fname, const struct firmware **fw,
  442. bool nowait)
  443. {
  444. /* release current image */
  445. if (*fw != NULL)
  446. mwl8k_release_fw(fw);
  447. if (nowait)
  448. return request_firmware_nowait(THIS_MODULE, 1, fname,
  449. &priv->pdev->dev, GFP_KERNEL,
  450. priv, mwl8k_fw_state_machine);
  451. else
  452. return request_firmware(fw, fname, &priv->pdev->dev);
  453. }
  454. static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
  455. bool nowait)
  456. {
  457. struct mwl8k_device_info *di = priv->device_info;
  458. int rc;
  459. if (di->helper_image != NULL) {
  460. if (nowait)
  461. rc = mwl8k_request_fw(priv, di->helper_image,
  462. &priv->fw_helper, true);
  463. else
  464. rc = mwl8k_request_fw(priv, di->helper_image,
  465. &priv->fw_helper, false);
  466. if (rc)
  467. printk(KERN_ERR "%s: Error requesting helper fw %s\n",
  468. pci_name(priv->pdev), di->helper_image);
  469. if (rc || nowait)
  470. return rc;
  471. }
  472. if (nowait) {
  473. /*
  474. * if we get here, no helper image is needed. Skip the
  475. * FW_STATE_INIT state.
  476. */
  477. priv->fw_state = FW_STATE_LOADING_PREF;
  478. rc = mwl8k_request_fw(priv, fw_image,
  479. &priv->fw_ucode,
  480. true);
  481. } else
  482. rc = mwl8k_request_fw(priv, fw_image,
  483. &priv->fw_ucode, false);
  484. if (rc) {
  485. printk(KERN_ERR "%s: Error requesting firmware file %s\n",
  486. pci_name(priv->pdev), fw_image);
  487. mwl8k_release_fw(&priv->fw_helper);
  488. return rc;
  489. }
  490. return 0;
  491. }
  492. struct mwl8k_cmd_pkt {
  493. __le16 code;
  494. __le16 length;
  495. __u8 seq_num;
  496. __u8 macid;
  497. __le16 result;
  498. char payload[0];
  499. } __packed;
  500. /*
  501. * Firmware loading.
  502. */
  503. static int
  504. mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
  505. {
  506. void __iomem *regs = priv->regs;
  507. dma_addr_t dma_addr;
  508. int loops;
  509. dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
  510. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  511. return -ENOMEM;
  512. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  513. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  514. iowrite32(MWL8K_H2A_INT_DOORBELL,
  515. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  516. iowrite32(MWL8K_H2A_INT_DUMMY,
  517. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  518. loops = 1000;
  519. do {
  520. u32 int_code;
  521. if (priv->is_8764) {
  522. int_code = ioread32(regs +
  523. MWL8K_HIU_H2A_INTERRUPT_STATUS);
  524. if (int_code == 0)
  525. break;
  526. } else {
  527. int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
  528. if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
  529. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  530. break;
  531. }
  532. }
  533. cond_resched();
  534. udelay(1);
  535. } while (--loops);
  536. pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
  537. return loops ? 0 : -ETIMEDOUT;
  538. }
  539. static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
  540. const u8 *data, size_t length)
  541. {
  542. struct mwl8k_cmd_pkt *cmd;
  543. int done;
  544. int rc = 0;
  545. cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
  546. if (cmd == NULL)
  547. return -ENOMEM;
  548. cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
  549. cmd->seq_num = 0;
  550. cmd->macid = 0;
  551. cmd->result = 0;
  552. done = 0;
  553. while (length) {
  554. int block_size = length > 256 ? 256 : length;
  555. memcpy(cmd->payload, data + done, block_size);
  556. cmd->length = cpu_to_le16(block_size);
  557. rc = mwl8k_send_fw_load_cmd(priv, cmd,
  558. sizeof(*cmd) + block_size);
  559. if (rc)
  560. break;
  561. done += block_size;
  562. length -= block_size;
  563. }
  564. if (!rc) {
  565. cmd->length = 0;
  566. rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
  567. }
  568. kfree(cmd);
  569. return rc;
  570. }
  571. static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
  572. const u8 *data, size_t length)
  573. {
  574. unsigned char *buffer;
  575. int may_continue, rc = 0;
  576. u32 done, prev_block_size;
  577. buffer = kmalloc(1024, GFP_KERNEL);
  578. if (buffer == NULL)
  579. return -ENOMEM;
  580. done = 0;
  581. prev_block_size = 0;
  582. may_continue = 1000;
  583. while (may_continue > 0) {
  584. u32 block_size;
  585. block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
  586. if (block_size & 1) {
  587. block_size &= ~1;
  588. may_continue--;
  589. } else {
  590. done += prev_block_size;
  591. length -= prev_block_size;
  592. }
  593. if (block_size > 1024 || block_size > length) {
  594. rc = -EOVERFLOW;
  595. break;
  596. }
  597. if (length == 0) {
  598. rc = 0;
  599. break;
  600. }
  601. if (block_size == 0) {
  602. rc = -EPROTO;
  603. may_continue--;
  604. udelay(1);
  605. continue;
  606. }
  607. prev_block_size = block_size;
  608. memcpy(buffer, data + done, block_size);
  609. rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
  610. if (rc)
  611. break;
  612. }
  613. if (!rc && length != 0)
  614. rc = -EREMOTEIO;
  615. kfree(buffer);
  616. return rc;
  617. }
  618. static int mwl8k_load_firmware(struct ieee80211_hw *hw)
  619. {
  620. struct mwl8k_priv *priv = hw->priv;
  621. const struct firmware *fw = priv->fw_ucode;
  622. int rc;
  623. int loops;
  624. if (!memcmp(fw->data, "\x01\x00\x00\x00", 4) && !priv->is_8764) {
  625. const struct firmware *helper = priv->fw_helper;
  626. if (helper == NULL) {
  627. printk(KERN_ERR "%s: helper image needed but none "
  628. "given\n", pci_name(priv->pdev));
  629. return -EINVAL;
  630. }
  631. rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
  632. if (rc) {
  633. printk(KERN_ERR "%s: unable to load firmware "
  634. "helper image\n", pci_name(priv->pdev));
  635. return rc;
  636. }
  637. msleep(20);
  638. rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
  639. } else {
  640. if (priv->is_8764)
  641. rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
  642. else
  643. rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
  644. }
  645. if (rc) {
  646. printk(KERN_ERR "%s: unable to load firmware image\n",
  647. pci_name(priv->pdev));
  648. return rc;
  649. }
  650. iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
  651. loops = 500000;
  652. do {
  653. u32 ready_code;
  654. ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  655. if (ready_code == MWL8K_FWAP_READY) {
  656. priv->ap_fw = true;
  657. break;
  658. } else if (ready_code == MWL8K_FWSTA_READY) {
  659. priv->ap_fw = false;
  660. break;
  661. }
  662. cond_resched();
  663. udelay(1);
  664. } while (--loops);
  665. return loops ? 0 : -ETIMEDOUT;
  666. }
  667. /* DMA header used by firmware and hardware. */
  668. struct mwl8k_dma_data {
  669. __le16 fwlen;
  670. struct ieee80211_hdr wh;
  671. char data[0];
  672. } __packed;
  673. /* Routines to add/remove DMA header from skb. */
  674. static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
  675. {
  676. struct mwl8k_dma_data *tr;
  677. int hdrlen;
  678. tr = (struct mwl8k_dma_data *)skb->data;
  679. hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
  680. if (hdrlen != sizeof(tr->wh)) {
  681. if (ieee80211_is_data_qos(tr->wh.frame_control)) {
  682. memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
  683. *((__le16 *)(tr->data - 2)) = qos;
  684. } else {
  685. memmove(tr->data - hdrlen, &tr->wh, hdrlen);
  686. }
  687. }
  688. if (hdrlen != sizeof(*tr))
  689. skb_pull(skb, sizeof(*tr) - hdrlen);
  690. }
  691. #define REDUCED_TX_HEADROOM 8
  692. static void
  693. mwl8k_add_dma_header(struct mwl8k_priv *priv, struct sk_buff *skb,
  694. int head_pad, int tail_pad)
  695. {
  696. struct ieee80211_hdr *wh;
  697. int hdrlen;
  698. int reqd_hdrlen;
  699. struct mwl8k_dma_data *tr;
  700. /*
  701. * Add a firmware DMA header; the firmware requires that we
  702. * present a 2-byte payload length followed by a 4-address
  703. * header (without QoS field), followed (optionally) by any
  704. * WEP/ExtIV header (but only filled in for CCMP).
  705. */
  706. wh = (struct ieee80211_hdr *)skb->data;
  707. hdrlen = ieee80211_hdrlen(wh->frame_control);
  708. /*
  709. * Check if skb_resize is required because of
  710. * tx_headroom adjustment.
  711. */
  712. if (priv->ap_fw && (hdrlen < (sizeof(struct ieee80211_cts)
  713. + REDUCED_TX_HEADROOM))) {
  714. if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) {
  715. wiphy_err(priv->hw->wiphy,
  716. "Failed to reallocate TX buffer\n");
  717. return;
  718. }
  719. skb->truesize += REDUCED_TX_HEADROOM;
  720. }
  721. reqd_hdrlen = sizeof(*tr) + head_pad;
  722. if (hdrlen != reqd_hdrlen)
  723. skb_push(skb, reqd_hdrlen - hdrlen);
  724. if (ieee80211_is_data_qos(wh->frame_control))
  725. hdrlen -= IEEE80211_QOS_CTL_LEN;
  726. tr = (struct mwl8k_dma_data *)skb->data;
  727. if (wh != &tr->wh)
  728. memmove(&tr->wh, wh, hdrlen);
  729. if (hdrlen != sizeof(tr->wh))
  730. memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
  731. /*
  732. * Firmware length is the length of the fully formed "802.11
  733. * payload". That is, everything except for the 802.11 header.
  734. * This includes all crypto material including the MIC.
  735. */
  736. tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
  737. }
  738. static void mwl8k_encapsulate_tx_frame(struct mwl8k_priv *priv,
  739. struct sk_buff *skb)
  740. {
  741. struct ieee80211_hdr *wh;
  742. struct ieee80211_tx_info *tx_info;
  743. struct ieee80211_key_conf *key_conf;
  744. int data_pad;
  745. int head_pad = 0;
  746. wh = (struct ieee80211_hdr *)skb->data;
  747. tx_info = IEEE80211_SKB_CB(skb);
  748. key_conf = NULL;
  749. if (ieee80211_is_data(wh->frame_control))
  750. key_conf = tx_info->control.hw_key;
  751. /*
  752. * Make sure the packet header is in the DMA header format (4-address
  753. * without QoS), and add head & tail padding when HW crypto is enabled.
  754. *
  755. * We have the following trailer padding requirements:
  756. * - WEP: 4 trailer bytes (ICV)
  757. * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
  758. * - CCMP: 8 trailer bytes (MIC)
  759. */
  760. data_pad = 0;
  761. if (key_conf != NULL) {
  762. head_pad = key_conf->iv_len;
  763. switch (key_conf->cipher) {
  764. case WLAN_CIPHER_SUITE_WEP40:
  765. case WLAN_CIPHER_SUITE_WEP104:
  766. data_pad = 4;
  767. break;
  768. case WLAN_CIPHER_SUITE_TKIP:
  769. data_pad = 12;
  770. break;
  771. case WLAN_CIPHER_SUITE_CCMP:
  772. data_pad = 8;
  773. break;
  774. }
  775. }
  776. mwl8k_add_dma_header(priv, skb, head_pad, data_pad);
  777. }
  778. /*
  779. * Packet reception for 88w8366/88w8764 AP firmware.
  780. */
  781. struct mwl8k_rxd_ap {
  782. __le16 pkt_len;
  783. __u8 sq2;
  784. __u8 rate;
  785. __le32 pkt_phys_addr;
  786. __le32 next_rxd_phys_addr;
  787. __le16 qos_control;
  788. __le16 htsig2;
  789. __le32 hw_rssi_info;
  790. __le32 hw_noise_floor_info;
  791. __u8 noise_floor;
  792. __u8 pad0[3];
  793. __u8 rssi;
  794. __u8 rx_status;
  795. __u8 channel;
  796. __u8 rx_ctrl;
  797. } __packed;
  798. #define MWL8K_AP_RATE_INFO_MCS_FORMAT 0x80
  799. #define MWL8K_AP_RATE_INFO_40MHZ 0x40
  800. #define MWL8K_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
  801. #define MWL8K_AP_RX_CTRL_OWNED_BY_HOST 0x80
  802. /* 8366/8764 AP rx_status bits */
  803. #define MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
  804. #define MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
  805. #define MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
  806. #define MWL8K_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
  807. #define MWL8K_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
  808. static void mwl8k_rxd_ap_init(void *_rxd, dma_addr_t next_dma_addr)
  809. {
  810. struct mwl8k_rxd_ap *rxd = _rxd;
  811. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  812. rxd->rx_ctrl = MWL8K_AP_RX_CTRL_OWNED_BY_HOST;
  813. }
  814. static void mwl8k_rxd_ap_refill(void *_rxd, dma_addr_t addr, int len)
  815. {
  816. struct mwl8k_rxd_ap *rxd = _rxd;
  817. rxd->pkt_len = cpu_to_le16(len);
  818. rxd->pkt_phys_addr = cpu_to_le32(addr);
  819. wmb();
  820. rxd->rx_ctrl = 0;
  821. }
  822. static int
  823. mwl8k_rxd_ap_process(void *_rxd, struct ieee80211_rx_status *status,
  824. __le16 *qos, s8 *noise)
  825. {
  826. struct mwl8k_rxd_ap *rxd = _rxd;
  827. if (!(rxd->rx_ctrl & MWL8K_AP_RX_CTRL_OWNED_BY_HOST))
  828. return -1;
  829. rmb();
  830. memset(status, 0, sizeof(*status));
  831. status->signal = -rxd->rssi;
  832. *noise = -rxd->noise_floor;
  833. if (rxd->rate & MWL8K_AP_RATE_INFO_MCS_FORMAT) {
  834. status->flag |= RX_FLAG_HT;
  835. if (rxd->rate & MWL8K_AP_RATE_INFO_40MHZ)
  836. status->flag |= RX_FLAG_40MHZ;
  837. status->rate_idx = MWL8K_AP_RATE_INFO_RATEID(rxd->rate);
  838. } else {
  839. int i;
  840. for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
  841. if (mwl8k_rates_24[i].hw_value == rxd->rate) {
  842. status->rate_idx = i;
  843. break;
  844. }
  845. }
  846. }
  847. if (rxd->channel > 14) {
  848. status->band = IEEE80211_BAND_5GHZ;
  849. if (!(status->flag & RX_FLAG_HT))
  850. status->rate_idx -= 5;
  851. } else {
  852. status->band = IEEE80211_BAND_2GHZ;
  853. }
  854. status->freq = ieee80211_channel_to_frequency(rxd->channel,
  855. status->band);
  856. *qos = rxd->qos_control;
  857. if ((rxd->rx_status != MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
  858. (rxd->rx_status & MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK) &&
  859. (rxd->rx_status & MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
  860. status->flag |= RX_FLAG_MMIC_ERROR;
  861. return le16_to_cpu(rxd->pkt_len);
  862. }
  863. static struct rxd_ops rxd_ap_ops = {
  864. .rxd_size = sizeof(struct mwl8k_rxd_ap),
  865. .rxd_init = mwl8k_rxd_ap_init,
  866. .rxd_refill = mwl8k_rxd_ap_refill,
  867. .rxd_process = mwl8k_rxd_ap_process,
  868. };
  869. /*
  870. * Packet reception for STA firmware.
  871. */
  872. struct mwl8k_rxd_sta {
  873. __le16 pkt_len;
  874. __u8 link_quality;
  875. __u8 noise_level;
  876. __le32 pkt_phys_addr;
  877. __le32 next_rxd_phys_addr;
  878. __le16 qos_control;
  879. __le16 rate_info;
  880. __le32 pad0[4];
  881. __u8 rssi;
  882. __u8 channel;
  883. __le16 pad1;
  884. __u8 rx_ctrl;
  885. __u8 rx_status;
  886. __u8 pad2[2];
  887. } __packed;
  888. #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
  889. #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
  890. #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
  891. #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
  892. #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
  893. #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
  894. #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
  895. #define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
  896. /* ICV=0 or MIC=1 */
  897. #define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
  898. /* Key is uploaded only in failure case */
  899. #define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
  900. static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
  901. {
  902. struct mwl8k_rxd_sta *rxd = _rxd;
  903. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  904. rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
  905. }
  906. static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
  907. {
  908. struct mwl8k_rxd_sta *rxd = _rxd;
  909. rxd->pkt_len = cpu_to_le16(len);
  910. rxd->pkt_phys_addr = cpu_to_le32(addr);
  911. wmb();
  912. rxd->rx_ctrl = 0;
  913. }
  914. static int
  915. mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
  916. __le16 *qos, s8 *noise)
  917. {
  918. struct mwl8k_rxd_sta *rxd = _rxd;
  919. u16 rate_info;
  920. if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
  921. return -1;
  922. rmb();
  923. rate_info = le16_to_cpu(rxd->rate_info);
  924. memset(status, 0, sizeof(*status));
  925. status->signal = -rxd->rssi;
  926. *noise = -rxd->noise_level;
  927. status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
  928. status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
  929. if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
  930. status->flag |= RX_FLAG_SHORTPRE;
  931. if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
  932. status->flag |= RX_FLAG_40MHZ;
  933. if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
  934. status->flag |= RX_FLAG_SHORT_GI;
  935. if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
  936. status->flag |= RX_FLAG_HT;
  937. if (rxd->channel > 14) {
  938. status->band = IEEE80211_BAND_5GHZ;
  939. if (!(status->flag & RX_FLAG_HT))
  940. status->rate_idx -= 5;
  941. } else {
  942. status->band = IEEE80211_BAND_2GHZ;
  943. }
  944. status->freq = ieee80211_channel_to_frequency(rxd->channel,
  945. status->band);
  946. *qos = rxd->qos_control;
  947. if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
  948. (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
  949. status->flag |= RX_FLAG_MMIC_ERROR;
  950. return le16_to_cpu(rxd->pkt_len);
  951. }
  952. static struct rxd_ops rxd_sta_ops = {
  953. .rxd_size = sizeof(struct mwl8k_rxd_sta),
  954. .rxd_init = mwl8k_rxd_sta_init,
  955. .rxd_refill = mwl8k_rxd_sta_refill,
  956. .rxd_process = mwl8k_rxd_sta_process,
  957. };
  958. #define MWL8K_RX_DESCS 256
  959. #define MWL8K_RX_MAXSZ 3800
  960. static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
  961. {
  962. struct mwl8k_priv *priv = hw->priv;
  963. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  964. int size;
  965. int i;
  966. rxq->rxd_count = 0;
  967. rxq->head = 0;
  968. rxq->tail = 0;
  969. size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
  970. rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
  971. if (rxq->rxd == NULL) {
  972. wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
  973. return -ENOMEM;
  974. }
  975. memset(rxq->rxd, 0, size);
  976. rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
  977. if (rxq->buf == NULL) {
  978. pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
  979. return -ENOMEM;
  980. }
  981. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  982. int desc_size;
  983. void *rxd;
  984. int nexti;
  985. dma_addr_t next_dma_addr;
  986. desc_size = priv->rxd_ops->rxd_size;
  987. rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
  988. nexti = i + 1;
  989. if (nexti == MWL8K_RX_DESCS)
  990. nexti = 0;
  991. next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
  992. priv->rxd_ops->rxd_init(rxd, next_dma_addr);
  993. }
  994. return 0;
  995. }
  996. static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
  997. {
  998. struct mwl8k_priv *priv = hw->priv;
  999. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  1000. int refilled;
  1001. refilled = 0;
  1002. while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
  1003. struct sk_buff *skb;
  1004. dma_addr_t addr;
  1005. int rx;
  1006. void *rxd;
  1007. skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
  1008. if (skb == NULL)
  1009. break;
  1010. addr = pci_map_single(priv->pdev, skb->data,
  1011. MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
  1012. rxq->rxd_count++;
  1013. rx = rxq->tail++;
  1014. if (rxq->tail == MWL8K_RX_DESCS)
  1015. rxq->tail = 0;
  1016. rxq->buf[rx].skb = skb;
  1017. dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
  1018. rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
  1019. priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
  1020. refilled++;
  1021. }
  1022. return refilled;
  1023. }
  1024. /* Must be called only when the card's reception is completely halted */
  1025. static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
  1026. {
  1027. struct mwl8k_priv *priv = hw->priv;
  1028. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  1029. int i;
  1030. if (rxq->rxd == NULL)
  1031. return;
  1032. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  1033. if (rxq->buf[i].skb != NULL) {
  1034. pci_unmap_single(priv->pdev,
  1035. dma_unmap_addr(&rxq->buf[i], dma),
  1036. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  1037. dma_unmap_addr_set(&rxq->buf[i], dma, 0);
  1038. kfree_skb(rxq->buf[i].skb);
  1039. rxq->buf[i].skb = NULL;
  1040. }
  1041. }
  1042. kfree(rxq->buf);
  1043. rxq->buf = NULL;
  1044. pci_free_consistent(priv->pdev,
  1045. MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
  1046. rxq->rxd, rxq->rxd_dma);
  1047. rxq->rxd = NULL;
  1048. }
  1049. /*
  1050. * Scan a list of BSSIDs to process for finalize join.
  1051. * Allows for extension to process multiple BSSIDs.
  1052. */
  1053. static inline int
  1054. mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
  1055. {
  1056. return priv->capture_beacon &&
  1057. ieee80211_is_beacon(wh->frame_control) &&
  1058. ether_addr_equal(wh->addr3, priv->capture_bssid);
  1059. }
  1060. static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
  1061. struct sk_buff *skb)
  1062. {
  1063. struct mwl8k_priv *priv = hw->priv;
  1064. priv->capture_beacon = false;
  1065. memset(priv->capture_bssid, 0, ETH_ALEN);
  1066. /*
  1067. * Use GFP_ATOMIC as rxq_process is called from
  1068. * the primary interrupt handler, memory allocation call
  1069. * must not sleep.
  1070. */
  1071. priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
  1072. if (priv->beacon_skb != NULL)
  1073. ieee80211_queue_work(hw, &priv->finalize_join_worker);
  1074. }
  1075. static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
  1076. u8 *bssid)
  1077. {
  1078. struct mwl8k_vif *mwl8k_vif;
  1079. list_for_each_entry(mwl8k_vif,
  1080. vif_list, list) {
  1081. if (memcmp(bssid, mwl8k_vif->bssid,
  1082. ETH_ALEN) == 0)
  1083. return mwl8k_vif;
  1084. }
  1085. return NULL;
  1086. }
  1087. static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
  1088. {
  1089. struct mwl8k_priv *priv = hw->priv;
  1090. struct mwl8k_vif *mwl8k_vif = NULL;
  1091. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  1092. int processed;
  1093. processed = 0;
  1094. while (rxq->rxd_count && limit--) {
  1095. struct sk_buff *skb;
  1096. void *rxd;
  1097. int pkt_len;
  1098. struct ieee80211_rx_status status;
  1099. struct ieee80211_hdr *wh;
  1100. __le16 qos;
  1101. skb = rxq->buf[rxq->head].skb;
  1102. if (skb == NULL)
  1103. break;
  1104. rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
  1105. pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
  1106. &priv->noise);
  1107. if (pkt_len < 0)
  1108. break;
  1109. rxq->buf[rxq->head].skb = NULL;
  1110. pci_unmap_single(priv->pdev,
  1111. dma_unmap_addr(&rxq->buf[rxq->head], dma),
  1112. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  1113. dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
  1114. rxq->head++;
  1115. if (rxq->head == MWL8K_RX_DESCS)
  1116. rxq->head = 0;
  1117. rxq->rxd_count--;
  1118. wh = &((struct mwl8k_dma_data *)skb->data)->wh;
  1119. /*
  1120. * Check for a pending join operation. Save a
  1121. * copy of the beacon and schedule a tasklet to
  1122. * send a FINALIZE_JOIN command to the firmware.
  1123. */
  1124. if (mwl8k_capture_bssid(priv, (void *)skb->data))
  1125. mwl8k_save_beacon(hw, skb);
  1126. if (ieee80211_has_protected(wh->frame_control)) {
  1127. /* Check if hw crypto has been enabled for
  1128. * this bss. If yes, set the status flags
  1129. * accordingly
  1130. */
  1131. mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
  1132. wh->addr1);
  1133. if (mwl8k_vif != NULL &&
  1134. mwl8k_vif->is_hw_crypto_enabled) {
  1135. /*
  1136. * When MMIC ERROR is encountered
  1137. * by the firmware, payload is
  1138. * dropped and only 32 bytes of
  1139. * mwl8k Firmware header is sent
  1140. * to the host.
  1141. *
  1142. * We need to add four bytes of
  1143. * key information. In it
  1144. * MAC80211 expects keyidx set to
  1145. * 0 for triggering Counter
  1146. * Measure of MMIC failure.
  1147. */
  1148. if (status.flag & RX_FLAG_MMIC_ERROR) {
  1149. struct mwl8k_dma_data *tr;
  1150. tr = (struct mwl8k_dma_data *)skb->data;
  1151. memset((void *)&(tr->data), 0, 4);
  1152. pkt_len += 4;
  1153. }
  1154. if (!ieee80211_is_auth(wh->frame_control))
  1155. status.flag |= RX_FLAG_IV_STRIPPED |
  1156. RX_FLAG_DECRYPTED |
  1157. RX_FLAG_MMIC_STRIPPED;
  1158. }
  1159. }
  1160. skb_put(skb, pkt_len);
  1161. mwl8k_remove_dma_header(skb, qos);
  1162. memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
  1163. ieee80211_rx_irqsafe(hw, skb);
  1164. processed++;
  1165. }
  1166. return processed;
  1167. }
  1168. /*
  1169. * Packet transmission.
  1170. */
  1171. #define MWL8K_TXD_STATUS_OK 0x00000001
  1172. #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
  1173. #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
  1174. #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
  1175. #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
  1176. #define MWL8K_QOS_QLEN_UNSPEC 0xff00
  1177. #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
  1178. #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
  1179. #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
  1180. #define MWL8K_QOS_EOSP 0x0010
  1181. struct mwl8k_tx_desc {
  1182. __le32 status;
  1183. __u8 data_rate;
  1184. __u8 tx_priority;
  1185. __le16 qos_control;
  1186. __le32 pkt_phys_addr;
  1187. __le16 pkt_len;
  1188. __u8 dest_MAC_addr[ETH_ALEN];
  1189. __le32 next_txd_phys_addr;
  1190. __le32 timestamp;
  1191. __le16 rate_info;
  1192. __u8 peer_id;
  1193. __u8 tx_frag_cnt;
  1194. } __packed;
  1195. #define MWL8K_TX_DESCS 128
  1196. static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
  1197. {
  1198. struct mwl8k_priv *priv = hw->priv;
  1199. struct mwl8k_tx_queue *txq = priv->txq + index;
  1200. int size;
  1201. int i;
  1202. txq->len = 0;
  1203. txq->head = 0;
  1204. txq->tail = 0;
  1205. size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
  1206. txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
  1207. if (txq->txd == NULL) {
  1208. wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
  1209. return -ENOMEM;
  1210. }
  1211. memset(txq->txd, 0, size);
  1212. txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
  1213. if (txq->skb == NULL) {
  1214. pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
  1215. return -ENOMEM;
  1216. }
  1217. for (i = 0; i < MWL8K_TX_DESCS; i++) {
  1218. struct mwl8k_tx_desc *tx_desc;
  1219. int nexti;
  1220. tx_desc = txq->txd + i;
  1221. nexti = (i + 1) % MWL8K_TX_DESCS;
  1222. tx_desc->status = 0;
  1223. tx_desc->next_txd_phys_addr =
  1224. cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
  1225. }
  1226. return 0;
  1227. }
  1228. static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
  1229. {
  1230. iowrite32(MWL8K_H2A_INT_PPA_READY,
  1231. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1232. iowrite32(MWL8K_H2A_INT_DUMMY,
  1233. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1234. ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  1235. }
  1236. static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
  1237. {
  1238. struct mwl8k_priv *priv = hw->priv;
  1239. int i;
  1240. for (i = 0; i < mwl8k_tx_queues(priv); i++) {
  1241. struct mwl8k_tx_queue *txq = priv->txq + i;
  1242. int fw_owned = 0;
  1243. int drv_owned = 0;
  1244. int unused = 0;
  1245. int desc;
  1246. for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
  1247. struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
  1248. u32 status;
  1249. status = le32_to_cpu(tx_desc->status);
  1250. if (status & MWL8K_TXD_STATUS_FW_OWNED)
  1251. fw_owned++;
  1252. else
  1253. drv_owned++;
  1254. if (tx_desc->pkt_len == 0)
  1255. unused++;
  1256. }
  1257. wiphy_err(hw->wiphy,
  1258. "txq[%d] len=%d head=%d tail=%d "
  1259. "fw_owned=%d drv_owned=%d unused=%d\n",
  1260. i,
  1261. txq->len, txq->head, txq->tail,
  1262. fw_owned, drv_owned, unused);
  1263. }
  1264. }
  1265. /*
  1266. * Must be called with priv->fw_mutex held and tx queues stopped.
  1267. */
  1268. #define MWL8K_TX_WAIT_TIMEOUT_MS 5000
  1269. static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
  1270. {
  1271. struct mwl8k_priv *priv = hw->priv;
  1272. DECLARE_COMPLETION_ONSTACK(tx_wait);
  1273. int retry;
  1274. int rc;
  1275. might_sleep();
  1276. /* Since fw restart is in progress, allow only the firmware
  1277. * commands from the restart code and block the other
  1278. * commands since they are going to fail in any case since
  1279. * the firmware has crashed
  1280. */
  1281. if (priv->hw_restart_in_progress) {
  1282. if (priv->hw_restart_owner == current)
  1283. return 0;
  1284. else
  1285. return -EBUSY;
  1286. }
  1287. if (atomic_read(&priv->watchdog_event_pending))
  1288. return 0;
  1289. /*
  1290. * The TX queues are stopped at this point, so this test
  1291. * doesn't need to take ->tx_lock.
  1292. */
  1293. if (!priv->pending_tx_pkts)
  1294. return 0;
  1295. retry = 1;
  1296. rc = 0;
  1297. spin_lock_bh(&priv->tx_lock);
  1298. priv->tx_wait = &tx_wait;
  1299. while (!rc) {
  1300. int oldcount;
  1301. unsigned long timeout;
  1302. oldcount = priv->pending_tx_pkts;
  1303. spin_unlock_bh(&priv->tx_lock);
  1304. timeout = wait_for_completion_timeout(&tx_wait,
  1305. msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
  1306. if (atomic_read(&priv->watchdog_event_pending)) {
  1307. spin_lock_bh(&priv->tx_lock);
  1308. priv->tx_wait = NULL;
  1309. spin_unlock_bh(&priv->tx_lock);
  1310. return 0;
  1311. }
  1312. spin_lock_bh(&priv->tx_lock);
  1313. if (timeout || !priv->pending_tx_pkts) {
  1314. WARN_ON(priv->pending_tx_pkts);
  1315. if (retry)
  1316. wiphy_notice(hw->wiphy, "tx rings drained\n");
  1317. break;
  1318. }
  1319. if (retry) {
  1320. mwl8k_tx_start(priv);
  1321. retry = 0;
  1322. continue;
  1323. }
  1324. if (priv->pending_tx_pkts < oldcount) {
  1325. wiphy_notice(hw->wiphy,
  1326. "waiting for tx rings to drain (%d -> %d pkts)\n",
  1327. oldcount, priv->pending_tx_pkts);
  1328. retry = 1;
  1329. continue;
  1330. }
  1331. priv->tx_wait = NULL;
  1332. wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
  1333. MWL8K_TX_WAIT_TIMEOUT_MS);
  1334. mwl8k_dump_tx_rings(hw);
  1335. priv->hw_restart_in_progress = true;
  1336. ieee80211_queue_work(hw, &priv->fw_reload);
  1337. rc = -ETIMEDOUT;
  1338. }
  1339. priv->tx_wait = NULL;
  1340. spin_unlock_bh(&priv->tx_lock);
  1341. return rc;
  1342. }
  1343. #define MWL8K_TXD_SUCCESS(status) \
  1344. ((status) & (MWL8K_TXD_STATUS_OK | \
  1345. MWL8K_TXD_STATUS_OK_RETRY | \
  1346. MWL8K_TXD_STATUS_OK_MORE_RETRY))
  1347. static int mwl8k_tid_queue_mapping(u8 tid)
  1348. {
  1349. BUG_ON(tid > 7);
  1350. switch (tid) {
  1351. case 0:
  1352. case 3:
  1353. return IEEE80211_AC_BE;
  1354. break;
  1355. case 1:
  1356. case 2:
  1357. return IEEE80211_AC_BK;
  1358. break;
  1359. case 4:
  1360. case 5:
  1361. return IEEE80211_AC_VI;
  1362. break;
  1363. case 6:
  1364. case 7:
  1365. return IEEE80211_AC_VO;
  1366. break;
  1367. default:
  1368. return -1;
  1369. break;
  1370. }
  1371. }
  1372. /* The firmware will fill in the rate information
  1373. * for each packet that gets queued in the hardware
  1374. * and these macros will interpret that info.
  1375. */
  1376. #define RI_FORMAT(a) (a & 0x0001)
  1377. #define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3)
  1378. static int
  1379. mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
  1380. {
  1381. struct mwl8k_priv *priv = hw->priv;
  1382. struct mwl8k_tx_queue *txq = priv->txq + index;
  1383. int processed;
  1384. processed = 0;
  1385. while (txq->len > 0 && limit--) {
  1386. int tx;
  1387. struct mwl8k_tx_desc *tx_desc;
  1388. unsigned long addr;
  1389. int size;
  1390. struct sk_buff *skb;
  1391. struct ieee80211_tx_info *info;
  1392. u32 status;
  1393. struct ieee80211_sta *sta;
  1394. struct mwl8k_sta *sta_info = NULL;
  1395. u16 rate_info;
  1396. struct ieee80211_hdr *wh;
  1397. tx = txq->head;
  1398. tx_desc = txq->txd + tx;
  1399. status = le32_to_cpu(tx_desc->status);
  1400. if (status & MWL8K_TXD_STATUS_FW_OWNED) {
  1401. if (!force)
  1402. break;
  1403. tx_desc->status &=
  1404. ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
  1405. }
  1406. txq->head = (tx + 1) % MWL8K_TX_DESCS;
  1407. BUG_ON(txq->len == 0);
  1408. txq->len--;
  1409. priv->pending_tx_pkts--;
  1410. addr = le32_to_cpu(tx_desc->pkt_phys_addr);
  1411. size = le16_to_cpu(tx_desc->pkt_len);
  1412. skb = txq->skb[tx];
  1413. txq->skb[tx] = NULL;
  1414. BUG_ON(skb == NULL);
  1415. pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
  1416. mwl8k_remove_dma_header(skb, tx_desc->qos_control);
  1417. wh = (struct ieee80211_hdr *) skb->data;
  1418. /* Mark descriptor as unused */
  1419. tx_desc->pkt_phys_addr = 0;
  1420. tx_desc->pkt_len = 0;
  1421. info = IEEE80211_SKB_CB(skb);
  1422. if (ieee80211_is_data(wh->frame_control)) {
  1423. rcu_read_lock();
  1424. sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1,
  1425. wh->addr2);
  1426. if (sta) {
  1427. sta_info = MWL8K_STA(sta);
  1428. BUG_ON(sta_info == NULL);
  1429. rate_info = le16_to_cpu(tx_desc->rate_info);
  1430. /* If rate is < 6.5 Mpbs for an ht station
  1431. * do not form an ampdu. If the station is a
  1432. * legacy station (format = 0), do not form an
  1433. * ampdu
  1434. */
  1435. if (RI_RATE_ID_MCS(rate_info) < 1 ||
  1436. RI_FORMAT(rate_info) == 0) {
  1437. sta_info->is_ampdu_allowed = false;
  1438. } else {
  1439. sta_info->is_ampdu_allowed = true;
  1440. }
  1441. }
  1442. rcu_read_unlock();
  1443. }
  1444. ieee80211_tx_info_clear_status(info);
  1445. /* Rate control is happening in the firmware.
  1446. * Ensure no tx rate is being reported.
  1447. */
  1448. info->status.rates[0].idx = -1;
  1449. info->status.rates[0].count = 1;
  1450. if (MWL8K_TXD_SUCCESS(status))
  1451. info->flags |= IEEE80211_TX_STAT_ACK;
  1452. ieee80211_tx_status_irqsafe(hw, skb);
  1453. processed++;
  1454. }
  1455. return processed;
  1456. }
  1457. /* must be called only when the card's transmit is completely halted */
  1458. static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
  1459. {
  1460. struct mwl8k_priv *priv = hw->priv;
  1461. struct mwl8k_tx_queue *txq = priv->txq + index;
  1462. if (txq->txd == NULL)
  1463. return;
  1464. mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
  1465. kfree(txq->skb);
  1466. txq->skb = NULL;
  1467. pci_free_consistent(priv->pdev,
  1468. MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
  1469. txq->txd, txq->txd_dma);
  1470. txq->txd = NULL;
  1471. }
  1472. /* caller must hold priv->stream_lock when calling the stream functions */
  1473. static struct mwl8k_ampdu_stream *
  1474. mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
  1475. {
  1476. struct mwl8k_ampdu_stream *stream;
  1477. struct mwl8k_priv *priv = hw->priv;
  1478. int i;
  1479. for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
  1480. stream = &priv->ampdu[i];
  1481. if (stream->state == AMPDU_NO_STREAM) {
  1482. stream->sta = sta;
  1483. stream->state = AMPDU_STREAM_NEW;
  1484. stream->tid = tid;
  1485. stream->idx = i;
  1486. wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
  1487. sta->addr, tid);
  1488. return stream;
  1489. }
  1490. }
  1491. return NULL;
  1492. }
  1493. static int
  1494. mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
  1495. {
  1496. int ret;
  1497. /* if the stream has already been started, don't start it again */
  1498. if (stream->state != AMPDU_STREAM_NEW)
  1499. return 0;
  1500. ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
  1501. if (ret)
  1502. wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
  1503. "%d\n", stream->sta->addr, stream->tid, ret);
  1504. else
  1505. wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
  1506. stream->sta->addr, stream->tid);
  1507. return ret;
  1508. }
  1509. static void
  1510. mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
  1511. {
  1512. wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
  1513. stream->tid);
  1514. memset(stream, 0, sizeof(*stream));
  1515. }
  1516. static struct mwl8k_ampdu_stream *
  1517. mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
  1518. {
  1519. struct mwl8k_priv *priv = hw->priv;
  1520. int i;
  1521. for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
  1522. struct mwl8k_ampdu_stream *stream;
  1523. stream = &priv->ampdu[i];
  1524. if (stream->state == AMPDU_NO_STREAM)
  1525. continue;
  1526. if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
  1527. stream->tid == tid)
  1528. return stream;
  1529. }
  1530. return NULL;
  1531. }
  1532. #define MWL8K_AMPDU_PACKET_THRESHOLD 64
  1533. static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid)
  1534. {
  1535. struct mwl8k_sta *sta_info = MWL8K_STA(sta);
  1536. struct tx_traffic_info *tx_stats;
  1537. BUG_ON(tid >= MWL8K_MAX_TID);
  1538. tx_stats = &sta_info->tx_stats[tid];
  1539. return sta_info->is_ampdu_allowed &&
  1540. tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD;
  1541. }
  1542. static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid)
  1543. {
  1544. struct mwl8k_sta *sta_info = MWL8K_STA(sta);
  1545. struct tx_traffic_info *tx_stats;
  1546. BUG_ON(tid >= MWL8K_MAX_TID);
  1547. tx_stats = &sta_info->tx_stats[tid];
  1548. if (tx_stats->start_time == 0)
  1549. tx_stats->start_time = jiffies;
  1550. /* reset the packet count after each second elapses. If the number of
  1551. * packets ever exceeds the ampdu_min_traffic threshold, we will allow
  1552. * an ampdu stream to be started.
  1553. */
  1554. if (jiffies - tx_stats->start_time > HZ) {
  1555. tx_stats->pkts = 0;
  1556. tx_stats->start_time = 0;
  1557. } else
  1558. tx_stats->pkts++;
  1559. }
  1560. /* The hardware ampdu queues start from 5.
  1561. * txpriorities for ampdu queues are
  1562. * 5 6 7 0 1 2 3 4 ie., queue 5 is highest
  1563. * and queue 3 is lowest (queue 4 is reserved)
  1564. */
  1565. #define BA_QUEUE 5
  1566. static void
  1567. mwl8k_txq_xmit(struct ieee80211_hw *hw,
  1568. int index,
  1569. struct ieee80211_sta *sta,
  1570. struct sk_buff *skb)
  1571. {
  1572. struct mwl8k_priv *priv = hw->priv;
  1573. struct ieee80211_tx_info *tx_info;
  1574. struct mwl8k_vif *mwl8k_vif;
  1575. struct ieee80211_hdr *wh;
  1576. struct mwl8k_tx_queue *txq;
  1577. struct mwl8k_tx_desc *tx;
  1578. dma_addr_t dma;
  1579. u32 txstatus;
  1580. u8 txdatarate;
  1581. u16 qos;
  1582. int txpriority;
  1583. u8 tid = 0;
  1584. struct mwl8k_ampdu_stream *stream = NULL;
  1585. bool start_ba_session = false;
  1586. bool mgmtframe = false;
  1587. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1588. bool eapol_frame = false;
  1589. wh = (struct ieee80211_hdr *)skb->data;
  1590. if (ieee80211_is_data_qos(wh->frame_control))
  1591. qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
  1592. else
  1593. qos = 0;
  1594. if (skb->protocol == cpu_to_be16(ETH_P_PAE))
  1595. eapol_frame = true;
  1596. if (ieee80211_is_mgmt(wh->frame_control))
  1597. mgmtframe = true;
  1598. if (priv->ap_fw)
  1599. mwl8k_encapsulate_tx_frame(priv, skb);
  1600. else
  1601. mwl8k_add_dma_header(priv, skb, 0, 0);
  1602. wh = &((struct mwl8k_dma_data *)skb->data)->wh;
  1603. tx_info = IEEE80211_SKB_CB(skb);
  1604. mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
  1605. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1606. wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1607. wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
  1608. mwl8k_vif->seqno += 0x10;
  1609. }
  1610. /* Setup firmware control bit fields for each frame type. */
  1611. txstatus = 0;
  1612. txdatarate = 0;
  1613. if (ieee80211_is_mgmt(wh->frame_control) ||
  1614. ieee80211_is_ctl(wh->frame_control)) {
  1615. txdatarate = 0;
  1616. qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
  1617. } else if (ieee80211_is_data(wh->frame_control)) {
  1618. txdatarate = 1;
  1619. if (is_multicast_ether_addr(wh->addr1))
  1620. txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
  1621. qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
  1622. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
  1623. qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
  1624. else
  1625. qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
  1626. }
  1627. /* Queue ADDBA request in the respective data queue. While setting up
  1628. * the ampdu stream, mac80211 queues further packets for that
  1629. * particular ra/tid pair. However, packets piled up in the hardware
  1630. * for that ra/tid pair will still go out. ADDBA request and the
  1631. * related data packets going out from different queues asynchronously
  1632. * will cause a shift in the receiver window which might result in
  1633. * ampdu packets getting dropped at the receiver after the stream has
  1634. * been setup.
  1635. */
  1636. if (unlikely(ieee80211_is_action(wh->frame_control) &&
  1637. mgmt->u.action.category == WLAN_CATEGORY_BACK &&
  1638. mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
  1639. priv->ap_fw)) {
  1640. u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
  1641. tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
  1642. index = mwl8k_tid_queue_mapping(tid);
  1643. }
  1644. txpriority = index;
  1645. if (priv->ap_fw && sta && sta->ht_cap.ht_supported && !eapol_frame &&
  1646. ieee80211_is_data_qos(wh->frame_control)) {
  1647. tid = qos & 0xf;
  1648. mwl8k_tx_count_packet(sta, tid);
  1649. spin_lock(&priv->stream_lock);
  1650. stream = mwl8k_lookup_stream(hw, sta->addr, tid);
  1651. if (stream != NULL) {
  1652. if (stream->state == AMPDU_STREAM_ACTIVE) {
  1653. WARN_ON(!(qos & MWL8K_QOS_A