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/drivers/net/wireless/adm8211.c

http://github.com/mirrors/linux
C | 1996 lines | 1538 code | 340 blank | 118 comment | 205 complexity | 1500db511de567126f07803bba23bcf5 MD5 | raw file

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   1
   2/*
   3 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4 *
   5 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8 * and used with permission.
   9 *
  10 * Much thanks to Infineon-ADMtek for their support of this driver.
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation. See README and COPYING for
  15 * more details.
  16 */
  17
  18#include <linux/init.h>
  19#include <linux/interrupt.h>
  20#include <linux/if.h>
  21#include <linux/skbuff.h>
  22#include <linux/slab.h>
  23#include <linux/etherdevice.h>
  24#include <linux/pci.h>
  25#include <linux/delay.h>
  26#include <linux/crc32.h>
  27#include <linux/eeprom_93cx6.h>
  28#include <linux/module.h>
  29#include <net/mac80211.h>
  30
  31#include "adm8211.h"
  32
  33MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  34MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  35MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  36MODULE_SUPPORTED_DEVICE("ADM8211");
  37MODULE_LICENSE("GPL");
  38
  39static unsigned int tx_ring_size __read_mostly = 16;
  40static unsigned int rx_ring_size __read_mostly = 16;
  41
  42module_param(tx_ring_size, uint, 0);
  43module_param(rx_ring_size, uint, 0);
  44
  45static DEFINE_PCI_DEVICE_TABLE(adm8211_pci_id_table) = {
  46	/* ADMtek ADM8211 */
  47	{ PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  48	{ PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  49	{ PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  50	{ PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  51	{ 0 }
  52};
  53
  54static struct ieee80211_rate adm8211_rates[] = {
  55	{ .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  56	{ .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  57	{ .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  58	{ .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  59	{ .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
  60};
  61
  62static const struct ieee80211_channel adm8211_channels[] = {
  63	{ .center_freq = 2412},
  64	{ .center_freq = 2417},
  65	{ .center_freq = 2422},
  66	{ .center_freq = 2427},
  67	{ .center_freq = 2432},
  68	{ .center_freq = 2437},
  69	{ .center_freq = 2442},
  70	{ .center_freq = 2447},
  71	{ .center_freq = 2452},
  72	{ .center_freq = 2457},
  73	{ .center_freq = 2462},
  74	{ .center_freq = 2467},
  75	{ .center_freq = 2472},
  76	{ .center_freq = 2484},
  77};
  78
  79
  80static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  81{
  82	struct adm8211_priv *priv = eeprom->data;
  83	u32 reg = ADM8211_CSR_READ(SPR);
  84
  85	eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  86	eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  87	eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  88	eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  89}
  90
  91static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  92{
  93	struct adm8211_priv *priv = eeprom->data;
  94	u32 reg = 0x4000 | ADM8211_SPR_SRS;
  95
  96	if (eeprom->reg_data_in)
  97		reg |= ADM8211_SPR_SDI;
  98	if (eeprom->reg_data_out)
  99		reg |= ADM8211_SPR_SDO;
 100	if (eeprom->reg_data_clock)
 101		reg |= ADM8211_SPR_SCLK;
 102	if (eeprom->reg_chip_select)
 103		reg |= ADM8211_SPR_SCS;
 104
 105	ADM8211_CSR_WRITE(SPR, reg);
 106	ADM8211_CSR_READ(SPR);		/* eeprom_delay */
 107}
 108
 109static int adm8211_read_eeprom(struct ieee80211_hw *dev)
 110{
 111	struct adm8211_priv *priv = dev->priv;
 112	unsigned int words, i;
 113	struct ieee80211_chan_range chan_range;
 114	u16 cr49;
 115	struct eeprom_93cx6 eeprom = {
 116		.data		= priv,
 117		.register_read	= adm8211_eeprom_register_read,
 118		.register_write	= adm8211_eeprom_register_write
 119	};
 120
 121	if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
 122		/* 256 * 16-bit = 512 bytes */
 123		eeprom.width = PCI_EEPROM_WIDTH_93C66;
 124		words = 256;
 125	} else {
 126		/* 64 * 16-bit = 128 bytes */
 127		eeprom.width = PCI_EEPROM_WIDTH_93C46;
 128		words = 64;
 129	}
 130
 131	priv->eeprom_len = words * 2;
 132	priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 133	if (!priv->eeprom)
 134		return -ENOMEM;
 135
 136	eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
 137
 138	cr49 = le16_to_cpu(priv->eeprom->cr49);
 139	priv->rf_type = (cr49 >> 3) & 0x7;
 140	switch (priv->rf_type) {
 141	case ADM8211_TYPE_INTERSIL:
 142	case ADM8211_TYPE_RFMD:
 143	case ADM8211_TYPE_MARVEL:
 144	case ADM8211_TYPE_AIROHA:
 145	case ADM8211_TYPE_ADMTEK:
 146		break;
 147
 148	default:
 149		if (priv->pdev->revision < ADM8211_REV_CA)
 150			priv->rf_type = ADM8211_TYPE_RFMD;
 151		else
 152			priv->rf_type = ADM8211_TYPE_AIROHA;
 153
 154		printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 155		       pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 156	}
 157
 158	priv->bbp_type = cr49 & 0x7;
 159	switch (priv->bbp_type) {
 160	case ADM8211_TYPE_INTERSIL:
 161	case ADM8211_TYPE_RFMD:
 162	case ADM8211_TYPE_MARVEL:
 163	case ADM8211_TYPE_AIROHA:
 164	case ADM8211_TYPE_ADMTEK:
 165		break;
 166	default:
 167		if (priv->pdev->revision < ADM8211_REV_CA)
 168			priv->bbp_type = ADM8211_TYPE_RFMD;
 169		else
 170			priv->bbp_type = ADM8211_TYPE_ADMTEK;
 171
 172		printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 173		       pci_name(priv->pdev), cr49 >> 3);
 174	}
 175
 176	if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 177		printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 178		       pci_name(priv->pdev), priv->eeprom->country_code);
 179
 180		chan_range = cranges[2];
 181	} else
 182		chan_range = cranges[priv->eeprom->country_code];
 183
 184	printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 185	       pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 186
 187	BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
 188
 189	memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
 190	priv->band.channels = priv->channels;
 191	priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
 192	priv->band.bitrates = adm8211_rates;
 193	priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
 194
 195	for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 196		if (i < chan_range.min || i > chan_range.max)
 197			priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
 198
 199	switch (priv->eeprom->specific_bbptype) {
 200	case ADM8211_BBP_RFMD3000:
 201	case ADM8211_BBP_RFMD3002:
 202	case ADM8211_BBP_ADM8011:
 203		priv->specific_bbptype = priv->eeprom->specific_bbptype;
 204		break;
 205
 206	default:
 207		if (priv->pdev->revision < ADM8211_REV_CA)
 208			priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 209		else
 210			priv->specific_bbptype = ADM8211_BBP_ADM8011;
 211
 212		printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 213		       pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 214	}
 215
 216	switch (priv->eeprom->specific_rftype) {
 217	case ADM8211_RFMD2948:
 218	case ADM8211_RFMD2958:
 219	case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 220	case ADM8211_MAX2820:
 221	case ADM8211_AL2210L:
 222		priv->transceiver_type = priv->eeprom->specific_rftype;
 223		break;
 224
 225	default:
 226		if (priv->pdev->revision == ADM8211_REV_BA)
 227			priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 228		else if (priv->pdev->revision == ADM8211_REV_CA)
 229			priv->transceiver_type = ADM8211_AL2210L;
 230		else if (priv->pdev->revision == ADM8211_REV_AB)
 231			priv->transceiver_type = ADM8211_RFMD2948;
 232
 233		printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 234		       pci_name(priv->pdev), priv->eeprom->specific_rftype);
 235
 236		break;
 237	}
 238
 239	printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 240               "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 241	       priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 242
 243	return 0;
 244}
 245
 246static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 247				      u32 addr, u32 data)
 248{
 249	struct adm8211_priv *priv = dev->priv;
 250
 251	ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 252			  (priv->pdev->revision < ADM8211_REV_BA ?
 253			   0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 254	ADM8211_CSR_READ(WEPCTL);
 255	msleep(1);
 256
 257	ADM8211_CSR_WRITE(WESK, data);
 258	ADM8211_CSR_READ(WESK);
 259	msleep(1);
 260}
 261
 262static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 263				     unsigned int addr, u8 *buf,
 264				     unsigned int len)
 265{
 266	struct adm8211_priv *priv = dev->priv;
 267	u32 reg = ADM8211_CSR_READ(WEPCTL);
 268	unsigned int i;
 269
 270	if (priv->pdev->revision < ADM8211_REV_BA) {
 271		for (i = 0; i < len; i += 2) {
 272			u16 val = buf[i] | (buf[i + 1] << 8);
 273			adm8211_write_sram(dev, addr + i / 2, val);
 274		}
 275	} else {
 276		for (i = 0; i < len; i += 4) {
 277			u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 278				  (buf[i + 2] << 16) | (buf[i + 3] << 24);
 279			adm8211_write_sram(dev, addr + i / 4, val);
 280		}
 281	}
 282
 283	ADM8211_CSR_WRITE(WEPCTL, reg);
 284}
 285
 286static void adm8211_clear_sram(struct ieee80211_hw *dev)
 287{
 288	struct adm8211_priv *priv = dev->priv;
 289	u32 reg = ADM8211_CSR_READ(WEPCTL);
 290	unsigned int addr;
 291
 292	for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 293		adm8211_write_sram(dev, addr, 0);
 294
 295	ADM8211_CSR_WRITE(WEPCTL, reg);
 296}
 297
 298static int adm8211_get_stats(struct ieee80211_hw *dev,
 299			     struct ieee80211_low_level_stats *stats)
 300{
 301	struct adm8211_priv *priv = dev->priv;
 302
 303	memcpy(stats, &priv->stats, sizeof(*stats));
 304
 305	return 0;
 306}
 307
 308static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 309{
 310	struct adm8211_priv *priv = dev->priv;
 311	unsigned int dirty_tx;
 312
 313	spin_lock(&priv->lock);
 314
 315	for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 316		unsigned int entry = dirty_tx % priv->tx_ring_size;
 317		u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 318		struct ieee80211_tx_info *txi;
 319		struct adm8211_tx_ring_info *info;
 320		struct sk_buff *skb;
 321
 322		if (status & TDES0_CONTROL_OWN ||
 323		    !(status & TDES0_CONTROL_DONE))
 324			break;
 325
 326		info = &priv->tx_buffers[entry];
 327		skb = info->skb;
 328		txi = IEEE80211_SKB_CB(skb);
 329
 330		/* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 331
 332		pci_unmap_single(priv->pdev, info->mapping,
 333				 info->skb->len, PCI_DMA_TODEVICE);
 334
 335		ieee80211_tx_info_clear_status(txi);
 336
 337		skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 338		memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
 339		if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
 340		    !(status & TDES0_STATUS_ES))
 341			txi->flags |= IEEE80211_TX_STAT_ACK;
 342
 343		ieee80211_tx_status_irqsafe(dev, skb);
 344
 345		info->skb = NULL;
 346	}
 347
 348	if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 349		ieee80211_wake_queue(dev, 0);
 350
 351	priv->dirty_tx = dirty_tx;
 352	spin_unlock(&priv->lock);
 353}
 354
 355
 356static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 357{
 358	struct adm8211_priv *priv = dev->priv;
 359	unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 360	u32 status;
 361	unsigned int pktlen;
 362	struct sk_buff *skb, *newskb;
 363	unsigned int limit = priv->rx_ring_size;
 364	u8 rssi, rate;
 365
 366	while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 367		if (!limit--)
 368			break;
 369
 370		status = le32_to_cpu(priv->rx_ring[entry].status);
 371		rate = (status & RDES0_STATUS_RXDR) >> 12;
 372		rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 373			RDES1_STATUS_RSSI;
 374
 375		pktlen = status & RDES0_STATUS_FL;
 376		if (pktlen > RX_PKT_SIZE) {
 377			if (net_ratelimit())
 378				wiphy_debug(dev->wiphy, "frame too long (%d)\n",
 379					    pktlen);
 380			pktlen = RX_PKT_SIZE;
 381		}
 382
 383		if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 384			skb = NULL; /* old buffer will be reused */
 385			/* TODO: update RX error stats */
 386			/* TODO: check RDES0_STATUS_CRC*E */
 387		} else if (pktlen < RX_COPY_BREAK) {
 388			skb = dev_alloc_skb(pktlen);
 389			if (skb) {
 390				pci_dma_sync_single_for_cpu(
 391					priv->pdev,
 392					priv->rx_buffers[entry].mapping,
 393					pktlen, PCI_DMA_FROMDEVICE);
 394				memcpy(skb_put(skb, pktlen),
 395				       skb_tail_pointer(priv->rx_buffers[entry].skb),
 396				       pktlen);
 397				pci_dma_sync_single_for_device(
 398					priv->pdev,
 399					priv->rx_buffers[entry].mapping,
 400					RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 401			}
 402		} else {
 403			newskb = dev_alloc_skb(RX_PKT_SIZE);
 404			if (newskb) {
 405				skb = priv->rx_buffers[entry].skb;
 406				skb_put(skb, pktlen);
 407				pci_unmap_single(
 408					priv->pdev,
 409					priv->rx_buffers[entry].mapping,
 410					RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 411				priv->rx_buffers[entry].skb = newskb;
 412				priv->rx_buffers[entry].mapping =
 413					pci_map_single(priv->pdev,
 414						       skb_tail_pointer(newskb),
 415						       RX_PKT_SIZE,
 416						       PCI_DMA_FROMDEVICE);
 417			} else {
 418				skb = NULL;
 419				/* TODO: update rx dropped stats */
 420			}
 421
 422			priv->rx_ring[entry].buffer1 =
 423				cpu_to_le32(priv->rx_buffers[entry].mapping);
 424		}
 425
 426		priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 427							  RDES0_STATUS_SQL);
 428		priv->rx_ring[entry].length =
 429			cpu_to_le32(RX_PKT_SIZE |
 430				    (entry == priv->rx_ring_size - 1 ?
 431				     RDES1_CONTROL_RER : 0));
 432
 433		if (skb) {
 434			struct ieee80211_rx_status rx_status = {0};
 435
 436			if (priv->pdev->revision < ADM8211_REV_CA)
 437				rx_status.signal = rssi;
 438			else
 439				rx_status.signal = 100 - rssi;
 440
 441			rx_status.rate_idx = rate;
 442
 443			rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
 444			rx_status.band = IEEE80211_BAND_2GHZ;
 445
 446			memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 447			ieee80211_rx_irqsafe(dev, skb);
 448		}
 449
 450		entry = (++priv->cur_rx) % priv->rx_ring_size;
 451	}
 452
 453	/* TODO: check LPC and update stats? */
 454}
 455
 456
 457static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 458{
 459#define ADM8211_INT(x)						\
 460do {								\
 461	if (unlikely(stsr & ADM8211_STSR_ ## x))		\
 462		wiphy_debug(dev->wiphy, "%s\n", #x);		\
 463} while (0)
 464
 465	struct ieee80211_hw *dev = dev_id;
 466	struct adm8211_priv *priv = dev->priv;
 467	u32 stsr = ADM8211_CSR_READ(STSR);
 468	ADM8211_CSR_WRITE(STSR, stsr);
 469	if (stsr == 0xffffffff)
 470		return IRQ_HANDLED;
 471
 472	if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 473		return IRQ_HANDLED;
 474
 475	if (stsr & ADM8211_STSR_RCI)
 476		adm8211_interrupt_rci(dev);
 477	if (stsr & ADM8211_STSR_TCI)
 478		adm8211_interrupt_tci(dev);
 479
 480	ADM8211_INT(PCF);
 481	ADM8211_INT(BCNTC);
 482	ADM8211_INT(GPINT);
 483	ADM8211_INT(ATIMTC);
 484	ADM8211_INT(TSFTF);
 485	ADM8211_INT(TSCZ);
 486	ADM8211_INT(SQL);
 487	ADM8211_INT(WEPTD);
 488	ADM8211_INT(ATIME);
 489	ADM8211_INT(TEIS);
 490	ADM8211_INT(FBE);
 491	ADM8211_INT(REIS);
 492	ADM8211_INT(GPTT);
 493	ADM8211_INT(RPS);
 494	ADM8211_INT(RDU);
 495	ADM8211_INT(TUF);
 496	ADM8211_INT(TPS);
 497
 498	return IRQ_HANDLED;
 499
 500#undef ADM8211_INT
 501}
 502
 503#define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 504static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,	     \
 505					   u16 addr, u32 value) {	     \
 506	struct adm8211_priv *priv = dev->priv;				     \
 507	unsigned int i;							     \
 508	u32 reg, bitbuf;						     \
 509									     \
 510	value &= v_mask;						     \
 511	addr &= a_mask;							     \
 512	bitbuf = (value << v_shift) | (addr << a_shift);		     \
 513									     \
 514	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);		     \
 515	ADM8211_CSR_READ(SYNRF);					     \
 516	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);		     \
 517	ADM8211_CSR_READ(SYNRF);					     \
 518									     \
 519	if (prewrite) {							     \
 520		ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 521		ADM8211_CSR_READ(SYNRF);				     \
 522	}								     \
 523									     \
 524	for (i = 0; i <= bits; i++) {					     \
 525		if (bitbuf & (1 << (bits - i)))				     \
 526			reg = ADM8211_SYNRF_WRITE_SYNDATA_1;		     \
 527		else							     \
 528			reg = ADM8211_SYNRF_WRITE_SYNDATA_0;		     \
 529									     \
 530		ADM8211_CSR_WRITE(SYNRF, reg);				     \
 531		ADM8211_CSR_READ(SYNRF);				     \
 532									     \
 533		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 534		ADM8211_CSR_READ(SYNRF);				     \
 535		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 536		ADM8211_CSR_READ(SYNRF);				     \
 537	}								     \
 538									     \
 539	if (postwrite == 1) {						     \
 540		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 541		ADM8211_CSR_READ(SYNRF);				     \
 542	}								     \
 543	if (postwrite == 2) {						     \
 544		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 545		ADM8211_CSR_READ(SYNRF);				     \
 546	}								     \
 547									     \
 548	ADM8211_CSR_WRITE(SYNRF, 0);					     \
 549	ADM8211_CSR_READ(SYNRF);					     \
 550}
 551
 552WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 553WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 554WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 555WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 556
 557#undef WRITE_SYN
 558
 559static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 560{
 561	struct adm8211_priv *priv = dev->priv;
 562	unsigned int timeout;
 563	u32 reg;
 564
 565	timeout = 10;
 566	while (timeout > 0) {
 567		reg = ADM8211_CSR_READ(BBPCTL);
 568		if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 569			break;
 570		timeout--;
 571		msleep(2);
 572	}
 573
 574	if (timeout == 0) {
 575		wiphy_debug(dev->wiphy,
 576			    "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n",
 577			    addr, data, reg);
 578		return -ETIMEDOUT;
 579	}
 580
 581	switch (priv->bbp_type) {
 582	case ADM8211_TYPE_INTERSIL:
 583		reg = ADM8211_BBPCTL_MMISEL;	/* three wire interface */
 584		break;
 585	case ADM8211_TYPE_RFMD:
 586		reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 587		      (0x01 << 18);
 588		break;
 589	case ADM8211_TYPE_ADMTEK:
 590		reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 591		      (0x05 << 18);
 592		break;
 593	}
 594	reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 595
 596	ADM8211_CSR_WRITE(BBPCTL, reg);
 597
 598	timeout = 10;
 599	while (timeout > 0) {
 600		reg = ADM8211_CSR_READ(BBPCTL);
 601		if (!(reg & ADM8211_BBPCTL_WR))
 602			break;
 603		timeout--;
 604		msleep(2);
 605	}
 606
 607	if (timeout == 0) {
 608		ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 609				  ~ADM8211_BBPCTL_WR);
 610		wiphy_debug(dev->wiphy,
 611			    "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n",
 612			    addr, data, reg);
 613		return -ETIMEDOUT;
 614	}
 615
 616	return 0;
 617}
 618
 619static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 620{
 621	static const u32 adm8211_rfmd2958_reg5[] =
 622		{0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 623		 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 624	static const u32 adm8211_rfmd2958_reg6[] =
 625		{0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 626		 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 627
 628	struct adm8211_priv *priv = dev->priv;
 629	u8 ant_power = priv->ant_power > 0x3F ?
 630		priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 631	u8 tx_power = priv->tx_power > 0x3F ?
 632		priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 633	u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 634		priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 635	u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 636		priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 637	u32 reg;
 638
 639	ADM8211_IDLE();
 640
 641	/* Program synthesizer to new channel */
 642	switch (priv->transceiver_type) {
 643	case ADM8211_RFMD2958:
 644	case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 645		adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 646		adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 647
 648		adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 649			adm8211_rfmd2958_reg5[chan - 1]);
 650		adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 651			adm8211_rfmd2958_reg6[chan - 1]);
 652		break;
 653
 654	case ADM8211_RFMD2948:
 655		adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 656					      SI4126_MAIN_XINDIV2);
 657		adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 658					      SI4126_POWERDOWN_PDIB |
 659					      SI4126_POWERDOWN_PDRB);
 660		adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 661		adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 662					      (chan == 14 ?
 663					       2110 : (2033 + (chan * 5))));
 664		adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 665		adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 666		adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 667		break;
 668
 669	case ADM8211_MAX2820:
 670		adm8211_rf_write_syn_max2820(dev, 0x3,
 671			(chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 672		break;
 673
 674	case ADM8211_AL2210L:
 675		adm8211_rf_write_syn_al2210l(dev, 0x0,
 676			(chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 677		break;
 678
 679	default:
 680		wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n",
 681			    priv->transceiver_type);
 682		break;
 683	}
 684
 685	/* write BBP regs */
 686	if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 687
 688	/* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 689	/* TODO: remove if SMC 2635W doesn't need this */
 690	if (priv->transceiver_type == ADM8211_RFMD2948) {
 691		reg = ADM8211_CSR_READ(GPIO);
 692		reg &= 0xfffc0000;
 693		reg |= ADM8211_CSR_GPIO_EN0;
 694		if (chan != 14)
 695			reg |= ADM8211_CSR_GPIO_O0;
 696		ADM8211_CSR_WRITE(GPIO, reg);
 697	}
 698
 699	if (priv->transceiver_type == ADM8211_RFMD2958) {
 700		/* set PCNT2 */
 701		adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 702		/* set PCNT1 P_DESIRED/MID_BIAS */
 703		reg = le16_to_cpu(priv->eeprom->cr49);
 704		reg >>= 13;
 705		reg <<= 15;
 706		reg |= ant_power << 9;
 707		adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 708		/* set TXRX TX_GAIN */
 709		adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 710			(priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
 711	} else {
 712		reg = ADM8211_CSR_READ(PLCPHD);
 713		reg &= 0xff00ffff;
 714		reg |= tx_power << 18;
 715		ADM8211_CSR_WRITE(PLCPHD, reg);
 716	}
 717
 718	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 719			  ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 720	ADM8211_CSR_READ(SYNRF);
 721	msleep(30);
 722
 723	/* RF3000 BBP */
 724	if (priv->transceiver_type != ADM8211_RFMD2958)
 725		adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 726				  tx_power<<2);
 727	adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 728	adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 729	adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
 730				     priv->eeprom->cr28 : 0);
 731	adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 732
 733	ADM8211_CSR_WRITE(SYNRF, 0);
 734
 735	/* Nothing to do for ADMtek BBP */
 736	} else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 737		wiphy_debug(dev->wiphy, "unsupported BBP type %d\n",
 738			    priv->bbp_type);
 739
 740	ADM8211_RESTORE();
 741
 742	/* update current channel for adhoc (and maybe AP mode) */
 743	reg = ADM8211_CSR_READ(CAP0);
 744	reg &= ~0xF;
 745	reg |= chan;
 746	ADM8211_CSR_WRITE(CAP0, reg);
 747
 748	return 0;
 749}
 750
 751static void adm8211_update_mode(struct ieee80211_hw *dev)
 752{
 753	struct adm8211_priv *priv = dev->priv;
 754
 755	ADM8211_IDLE();
 756
 757	priv->soft_rx_crc = 0;
 758	switch (priv->mode) {
 759	case NL80211_IFTYPE_STATION:
 760		priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 761		priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 762		break;
 763	case NL80211_IFTYPE_ADHOC:
 764		priv->nar &= ~ADM8211_NAR_PR;
 765		priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 766
 767		/* don't trust the error bits on rev 0x20 and up in adhoc */
 768		if (priv->pdev->revision >= ADM8211_REV_BA)
 769			priv->soft_rx_crc = 1;
 770		break;
 771	case NL80211_IFTYPE_MONITOR:
 772		priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 773		priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 774		break;
 775	}
 776
 777	ADM8211_RESTORE();
 778}
 779
 780static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 781{
 782	struct adm8211_priv *priv = dev->priv;
 783
 784	switch (priv->transceiver_type) {
 785	case ADM8211_RFMD2958:
 786	case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 787		/* comments taken from ADMtek vendor driver */
 788
 789		/* Reset RF2958 after power on */
 790		adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 791		/* Initialize RF VCO Core Bias to maximum */
 792		adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 793		/* Initialize IF PLL */
 794		adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 795		/* Initialize IF PLL Coarse Tuning */
 796		adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 797		/* Initialize RF PLL */
 798		adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 799		/* Initialize RF PLL Coarse Tuning */
 800		adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 801		/* Initialize TX gain and filter BW (R9) */
 802		adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 803			(priv->transceiver_type == ADM8211_RFMD2958 ?
 804			 0x10050 : 0x00050));
 805		/* Initialize CAL register */
 806		adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 807		break;
 808
 809	case ADM8211_MAX2820:
 810		adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 811		adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 812		adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 813		adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 814		adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 815		break;
 816
 817	case ADM8211_AL2210L:
 818		adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 819		adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 820		adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 821		adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 822		adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 823		adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 824		adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 825		adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 826		adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 827		adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 828		adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 829		adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 830		break;
 831
 832	case ADM8211_RFMD2948:
 833	default:
 834		break;
 835	}
 836}
 837
 838static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 839{
 840	struct adm8211_priv *priv = dev->priv;
 841	u32 reg;
 842
 843	/* write addresses */
 844	if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 845		ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 846		ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 847		ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 848	} else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 849		   priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 850		/* check specific BBP type */
 851		switch (priv->specific_bbptype) {
 852		case ADM8211_BBP_RFMD3000:
 853		case ADM8211_BBP_RFMD3002:
 854			ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 855			ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 856			break;
 857
 858		case ADM8211_BBP_ADM8011:
 859			ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 860			ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 861
 862			reg = ADM8211_CSR_READ(BBPCTL);
 863			reg &= ~ADM8211_BBPCTL_TYPE;
 864			reg |= 0x5 << 18;
 865			ADM8211_CSR_WRITE(BBPCTL, reg);
 866			break;
 867		}
 868
 869		switch (priv->pdev->revision) {
 870		case ADM8211_REV_CA:
 871			if (priv->transceiver_type == ADM8211_RFMD2958 ||
 872			    priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 873			    priv->transceiver_type == ADM8211_RFMD2948)
 874				ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 875			else if (priv->transceiver_type == ADM8211_MAX2820 ||
 876				 priv->transceiver_type == ADM8211_AL2210L)
 877				ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 878			break;
 879
 880		case ADM8211_REV_BA:
 881			reg  = ADM8211_CSR_READ(MMIRD1);
 882			reg &= 0x0000FFFF;
 883			reg |= 0x7e100000;
 884			ADM8211_CSR_WRITE(MMIRD1, reg);
 885			break;
 886
 887		case ADM8211_REV_AB:
 888		case ADM8211_REV_AF:
 889		default:
 890			ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 891			break;
 892		}
 893
 894		/* For RFMD */
 895		ADM8211_CSR_WRITE(MACTEST, 0x800);
 896	}
 897
 898	adm8211_hw_init_syn(dev);
 899
 900	/* Set RF Power control IF pin to PE1+PHYRST# */
 901	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 902			  ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 903	ADM8211_CSR_READ(SYNRF);
 904	msleep(20);
 905
 906	/* write BBP regs */
 907	if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 908		/* RF3000 BBP */
 909		/* another set:
 910		 * 11: c8
 911		 * 14: 14
 912		 * 15: 50 (chan 1..13; chan 14: d0)
 913		 * 1c: 00
 914		 * 1d: 84
 915		 */
 916		adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 917		/* antenna selection: diversity */
 918		adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 919		adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 920		adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 921		adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 922
 923		if (priv->eeprom->major_version < 2) {
 924			adm8211_write_bbp(dev, 0x1c, 0x00);
 925			adm8211_write_bbp(dev, 0x1d, 0x80);
 926		} else {
 927			if (priv->pdev->revision == ADM8211_REV_BA)
 928				adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 929			else
 930				adm8211_write_bbp(dev, 0x1c, 0x00);
 931
 932			adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 933		}
 934	} else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 935		/* reset baseband */
 936		adm8211_write_bbp(dev, 0x00, 0xFF);
 937		/* antenna selection: diversity */
 938		adm8211_write_bbp(dev, 0x07, 0x0A);
 939
 940		/* TODO: find documentation for this */
 941		switch (priv->transceiver_type) {
 942		case ADM8211_RFMD2958:
 943		case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 944			adm8211_write_bbp(dev, 0x00, 0x00);
 945			adm8211_write_bbp(dev, 0x01, 0x00);
 946			adm8211_write_bbp(dev, 0x02, 0x00);
 947			adm8211_write_bbp(dev, 0x03, 0x00);
 948			adm8211_write_bbp(dev, 0x06, 0x0f);
 949			adm8211_write_bbp(dev, 0x09, 0x00);
 950			adm8211_write_bbp(dev, 0x0a, 0x00);
 951			adm8211_write_bbp(dev, 0x0b, 0x00);
 952			adm8211_write_bbp(dev, 0x0c, 0x00);
 953			adm8211_write_bbp(dev, 0x0f, 0xAA);
 954			adm8211_write_bbp(dev, 0x10, 0x8c);
 955			adm8211_write_bbp(dev, 0x11, 0x43);
 956			adm8211_write_bbp(dev, 0x18, 0x40);
 957			adm8211_write_bbp(dev, 0x20, 0x23);
 958			adm8211_write_bbp(dev, 0x21, 0x02);
 959			adm8211_write_bbp(dev, 0x22, 0x28);
 960			adm8211_write_bbp(dev, 0x23, 0x30);
 961			adm8211_write_bbp(dev, 0x24, 0x2d);
 962			adm8211_write_bbp(dev, 0x28, 0x35);
 963			adm8211_write_bbp(dev, 0x2a, 0x8c);
 964			adm8211_write_bbp(dev, 0x2b, 0x81);
 965			adm8211_write_bbp(dev, 0x2c, 0x44);
 966			adm8211_write_bbp(dev, 0x2d, 0x0A);
 967			adm8211_write_bbp(dev, 0x29, 0x40);
 968			adm8211_write_bbp(dev, 0x60, 0x08);
 969			adm8211_write_bbp(dev, 0x64, 0x01);
 970			break;
 971
 972		case ADM8211_MAX2820:
 973			adm8211_write_bbp(dev, 0x00, 0x00);
 974			adm8211_write_bbp(dev, 0x01, 0x00);
 975			adm8211_write_bbp(dev, 0x02, 0x00);
 976			adm8211_write_bbp(dev, 0x03, 0x00);
 977			adm8211_write_bbp(dev, 0x06, 0x0f);
 978			adm8211_write_bbp(dev, 0x09, 0x05);
 979			adm8211_write_bbp(dev, 0x0a, 0x02);
 980			adm8211_write_bbp(dev, 0x0b, 0x00);
 981			adm8211_write_bbp(dev, 0x0c, 0x0f);
 982			adm8211_write_bbp(dev, 0x0f, 0x55);
 983			adm8211_write_bbp(dev, 0x10, 0x8d);
 984			adm8211_write_bbp(dev, 0x11, 0x43);
 985			adm8211_write_bbp(dev, 0x18, 0x4a);
 986			adm8211_write_bbp(dev, 0x20, 0x20);
 987			adm8211_write_bbp(dev, 0x21, 0x02);
 988			adm8211_write_bbp(dev, 0x22, 0x23);
 989			adm8211_write_bbp(dev, 0x23, 0x30);
 990			adm8211_write_bbp(dev, 0x24, 0x2d);
 991			adm8211_write_bbp(dev, 0x2a, 0x8c);
 992			adm8211_write_bbp(dev, 0x2b, 0x81);
 993			adm8211_write_bbp(dev, 0x2c, 0x44);
 994			adm8211_write_bbp(dev, 0x29, 0x4a);
 995			adm8211_write_bbp(dev, 0x60, 0x2b);
 996			adm8211_write_bbp(dev, 0x64, 0x01);
 997			break;
 998
 999		case ADM8211_AL2210L:
1000			adm8211_write_bbp(dev, 0x00, 0x00);
1001			adm8211_write_bbp(dev, 0x01, 0x00);
1002			adm8211_write_bbp(dev, 0x02, 0x00);
1003			adm8211_write_bbp(dev, 0x03, 0x00);
1004			adm8211_write_bbp(dev, 0x06, 0x0f);
1005			adm8211_write_bbp(dev, 0x07, 0x05);
1006			adm8211_write_bbp(dev, 0x08, 0x03);
1007			adm8211_write_bbp(dev, 0x09, 0x00);
1008			adm8211_write_bbp(dev, 0x0a, 0x00);
1009			adm8211_write_bbp(dev, 0x0b, 0x00);
1010			adm8211_write_bbp(dev, 0x0c, 0x10);
1011			adm8211_write_bbp(dev, 0x0f, 0x55);
1012			adm8211_write_bbp(dev, 0x10, 0x8d);
1013			adm8211_write_bbp(dev, 0x11, 0x43);
1014			adm8211_write_bbp(dev, 0x18, 0x4a);
1015			adm8211_write_bbp(dev, 0x20, 0x20);
1016			adm8211_write_bbp(dev, 0x21, 0x02);
1017			adm8211_write_bbp(dev, 0x22, 0x23);
1018			adm8211_write_bbp(dev, 0x23, 0x30);
1019			adm8211_write_bbp(dev, 0x24, 0x2d);
1020			adm8211_write_bbp(dev, 0x2a, 0xaa);
1021			adm8211_write_bbp(dev, 0x2b, 0x81);
1022			adm8211_write_bbp(dev, 0x2c, 0x44);
1023			adm8211_write_bbp(dev, 0x29, 0xfa);
1024			adm8211_write_bbp(dev, 0x60, 0x2d);
1025			adm8211_write_bbp(dev, 0x64, 0x01);
1026			break;
1027
1028		case ADM8211_RFMD2948:
1029			break;
1030
1031		default:
1032			wiphy_debug(dev->wiphy, "unsupported transceiver %d\n",
1033				    priv->transceiver_type);
1034			break;
1035		}
1036	} else
1037		wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type);
1038
1039	ADM8211_CSR_WRITE(SYNRF, 0);
1040
1041	/* Set RF CAL control source to MAC control */
1042	reg = ADM8211_CSR_READ(SYNCTL);
1043	reg |= ADM8211_SYNCTL_SELCAL;
1044	ADM8211_CSR_WRITE(SYNCTL, reg);
1045
1046	return 0;
1047}
1048
1049/* configures hw beacons/probe responses */
1050static int adm8211_set_rate(struct ieee80211_hw *dev)
1051{
1052	struct adm8211_priv *priv = dev->priv;
1053	u32 reg;
1054	int i = 0;
1055	u8 rate_buf[12] = {0};
1056
1057	/* write supported rates */
1058	if (priv->pdev->revision != ADM8211_REV_BA) {
1059		rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1060		for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1061			rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1062	} else {
1063		/* workaround for rev BA specific bug */
1064		rate_buf[0] = 0x04;
1065		rate_buf[1] = 0x82;
1066		rate_buf[2] = 0x04;
1067		rate_buf[3] = 0x0b;
1068		rate_buf[4] = 0x16;
1069	}
1070
1071	adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1072				 ARRAY_SIZE(adm8211_rates) + 1);
1073
1074	reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1075	reg |= 1 << 15;	/* short preamble */
1076	reg |= 110 << 24;
1077	ADM8211_CSR_WRITE(PLCPHD, reg);
1078
1079	/* MTMLT   = 512 TU (max TX MSDU lifetime)
1080	 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1081	 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1082	ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1083
1084	return 0;
1085}
1086
1087static void adm8211_hw_init(struct ieee80211_hw *dev)
1088{
1089	struct adm8211_priv *priv = dev->priv;
1090	u32 reg;
1091	u8 cline;
1092
1093	reg = ADM8211_CSR_READ(PAR);
1094	reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1095	reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1096
1097	if (!pci_set_mwi(priv->pdev)) {
1098		reg |= 0x1 << 24;
1099		pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1100
1101		switch (cline) {
1102		case  0x8: reg |= (0x1 << 14);
1103			   break;
1104		case 0x16: reg |= (0x2 << 14);
1105			   break;
1106		case 0x32: reg |= (0x3 << 14);
1107			   break;
1108		  default: reg |= (0x0 << 14);
1109			   break;
1110		}
1111	}
1112
1113	ADM8211_CSR_WRITE(PAR, reg);
1114
1115	reg = ADM8211_CSR_READ(CSR_TEST1);
1116	reg &= ~(0xF << 28);
1117	reg |= (1 << 28) | (1 << 31);
1118	ADM8211_CSR_WRITE(CSR_TEST1, reg);
1119
1120	/* lose link after 4 lost beacons */
1121	reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1122	ADM8211_CSR_WRITE(WCSR, reg);
1123
1124	/* Disable APM, enable receive FIFO threshold, and set drain receive
1125	 * threshold to store-and-forward */
1126	reg = ADM8211_CSR_READ(CMDR);
1127	reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1128	reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1129	ADM8211_CSR_WRITE(CMDR, reg);
1130
1131	adm8211_set_rate(dev);
1132
1133	/* 4-bit values:
1134	 * PWR1UP   = 8 * 2 ms
1135	 * PWR0PAPE = 8 us or 5 us
1136	 * PWR1PAPE = 1 us or 3 us
1137	 * PWR0TRSW = 5 us
1138	 * PWR1TRSW = 12 us
1139	 * PWR0PE2  = 13 us
1140	 * PWR1PE2  = 1 us
1141	 * PWR0TXPE = 8 or 6 */
1142	if (priv->pdev->revision < ADM8211_REV_CA)
1143		ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1144	else
1145		ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1146
1147	/* Enable store and forward for transmit */
1148	priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1149	ADM8211_CSR_WRITE(NAR, priv->nar);
1150
1151	/* Reset RF */
1152	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1153	ADM8211_CSR_READ(SYNRF);
1154	msleep(10);
1155	ADM8211_CSR_WRITE(SYNRF, 0);
1156	ADM8211_CSR_READ(SYNRF);
1157	msleep(5);
1158
1159	/* Set CFP Max Duration to 0x10 TU */
1160	reg = ADM8211_CSR_READ(CFPP);
1161	reg &= ~(0xffff << 8);
1162	reg |= 0x0010 << 8;
1163	ADM8211_CSR_WRITE(CFPP, reg);
1164
1165	/* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1166	 * TUCNT = 0x3ff - Tu counter 1024 us  */
1167	ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1168
1169	/* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1170	 * DIFS=50 us, EIFS=100 us */
1171	if (priv->pdev->revision < ADM8211_REV_CA)
1172		ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1173					(50 << 9)  | 100);
1174	else
1175		ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1176					(50 << 9)  | 100);
1177
1178	/* PCNT = 1 (MAC idle time awake/sleep, unit S)
1179	 * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1180	ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1181
1182	/* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1183	ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1184
1185	/* Initialize BBP (and SYN) */
1186	adm8211_hw_init_bbp(dev);
1187
1188	/* make sure interrupts are off */
1189	ADM8211_CSR_WRITE(IER, 0);
1190
1191	/* ACK interrupts */
1192	ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1193
1194	/* Setup WEP (turns it off for now) */
1195	reg = ADM8211_CSR_READ(MACTEST);
1196	reg &= ~(7 << 20);
1197	ADM8211_CSR_WRITE(MACTEST, reg);
1198
1199	reg = ADM8211_CSR_READ(WEPCTL);
1200	reg &= ~ADM8211_WEPCTL_WEPENABLE;
1201	reg |= ADM8211_WEPCTL_WEPRXBYP;
1202	ADM8211_CSR_WRITE(WEPCTL, reg);
1203
1204	/* Clear the missed-packet counter. */
1205	ADM8211_CSR_READ(LPC);
1206}
1207
1208static int adm8211_hw_reset(struct ieee80211_hw *dev)
1209{
1210	struct adm8211_priv *priv = dev->priv;
1211	u32 reg, tmp;
1212	int timeout = 100;
1213
1214	/* Power-on issue */
1215	/* TODO: check if this is necessary */
1216	ADM8211_CSR_WRITE(FRCTL, 0);
1217
1218	/* Reset the chip */
1219	tmp = ADM8211_CSR_READ(PAR);
1220	ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1221
1222	while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1223		msleep(50);
1224
1225	if (timeout <= 0)
1226		return -ETIMEDOUT;
1227
1228	ADM8211_CSR_WRITE(PAR, tmp);
1229
1230	if (priv->pdev->revision == ADM8211_REV_BA &&
1231	    (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1232	     priv->transceiver_type == ADM8211_RFMD2958)) {
1233		reg = ADM8211_CSR_READ(CSR_TEST1);
1234		reg |= (1 << 4) | (1 << 5);
1235		ADM8211_CSR_WRITE(CSR_TEST1, reg);
1236	} else if (priv->pdev->revision == ADM8211_REV_CA) {
1237		reg = ADM8211_CSR_READ(CSR_TEST1);
1238		reg &= ~((1 << 4) | (1 << 5));
1239		ADM8211_CSR_WRITE(CSR_TEST1, reg);
1240	}
1241
1242	ADM8211_CSR_WRITE(FRCTL, 0);
1243
1244	reg = ADM8211_CSR_READ(CSR_TEST0);
1245	reg |= ADM8211_CSR_TEST0_EPRLD;	/* EEPROM Recall */
1246	ADM8211_CSR_WRITE(CSR_TEST0, reg);
1247
1248	adm8211_clear_sram(dev);
1249
1250	return 0;
1251}
1252
1253static u64 adm8211_get_tsft(struct ieee80211_hw *dev,
1254			    struct ieee80211_vif *vif)
1255{
1256	struct adm8211_priv *priv = dev->priv;
1257	u32 tsftl;
1258	u64 tsft;
1259
1260	tsftl = ADM8211_CSR_READ(TSFTL);
1261	tsft = ADM8211_CSR_READ(TSFTH);
1262	tsft <<= 32;
1263	tsft |= tsftl;
1264
1265	return tsft;
1266}
1267
1268static void adm8211_set_interval(struct ieee80211_hw *dev,
1269				 unsigned short bi, unsigned short li)
1270{
1271	struct adm8211_priv *priv = dev->priv;
1272	u32 reg;
1273
1274	/* BP (beacon interval) = data->beacon_interval
1275	 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1276	reg = (bi << 16) | li;
1277	ADM8211_CSR_WRITE(BPLI, reg);
1278}
1279
1280static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1281{
1282	struct adm8211_priv *priv = dev->priv;
1283	u32 reg;
1284
1285	ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1286	reg = ADM8211_CSR_READ(ABDA1);
1287	reg &= 0x0000ffff;
1288	reg |= (bssid[4] << 16) | (bssid[5] << 24);
1289	ADM8211_CSR_WRITE(ABDA1, reg);
1290}
1291
1292static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1293{
1294	struct adm8211_priv *priv = dev->priv;
1295	struct ieee80211_conf *conf = &dev->conf;
1296	int channel =
1297		ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
1298
1299	if (channel != priv->channel) {
1300		priv->channel = channel;
1301		adm8211_rf_set_channel(dev, priv->channel);
1302	}
1303
1304	return 0;
1305}
1306
1307static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1308				     struct ieee80211_vif *vif,
1309				     struct ieee80211_bss_conf *conf,
1310				     u32 changes)
1311{
1312	struct adm8211_priv *priv = dev->priv;
1313
1314	if (!(changes & BSS_CHANGED_BSSID))
1315		return;
1316
1317	if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1318		adm8211_set_bssid(dev, conf->bssid);
1319		memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1320	}
1321}
1322
1323static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1324				     struct netdev_hw_addr_list *mc_list)
1325{
1326	unsigned int bit_nr;
1327	u32 mc_filter[2];
1328	struct netdev_hw_addr *ha;
1329
1330	mc_filter[1] = mc_filter[0] = 0;
1331
1332	netdev_hw_addr_list_for_each(ha, mc_list) {
1333		bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1334
1335		bit_nr &= 0x3F;
1336		mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1337	}
1338
1339	return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1340}
1341
1342static void adm8211_configure_filter(struct ieee80211_hw *dev,
1343				     unsigned int changed_flags,
1344				     unsigned int *total_flags,
1345				     u64 multicast)
1346{
1347	static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1348	struct adm8211_priv *priv = dev->priv;
1349	unsigned int new_flags;
1350	u32 mc_filter[2];
1351
1352	mc_filter[0] = multicast;
1353	mc_filter[1] = multicast >> 32;
1354
1355	new_flags = 0;
1356
1357	if (*total_flags & FIF_PROMISC_IN_BSS) {
1358		new_flags |= FIF_PROMISC_IN_BSS;
1359		priv->nar |= ADM8211_NAR_PR;
1360		priv->nar &= ~ADM8211_NAR_MM;
1361		mc_filter[1] = mc_filter[0] = ~0;
1362	} else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1363		new_flags |= FIF_ALLMULTI;
1364		priv->nar &= ~ADM8211_NAR_PR;
1365		priv->nar |= ADM8211_NAR_MM;
1366		mc_filter[1] = mc_filter[0] = ~0;
1367	} else {
1368		priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1369	}
1370
1371	ADM8211_IDLE_RX();
1372
1373	ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1374	ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1375	ADM8211_CSR_READ(NAR);
1376
1377	if (priv->nar & ADM8211_NAR_PR)
1378		dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1379	else
1380		dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1381
1382	if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1383		adm8211_set_bssid(dev, bcast);
1384	else
1385		adm8211_set_bssid(dev, priv->bssid);
1386
1387	ADM8211_RESTORE();
1388
1389	*total_flags = new_flags;
1390}
1391
1392static int adm8211_add_interface(struct ieee80211_hw *dev,
1393				 struct ieee80211_vif *vif)
1394{
1395	struct adm8211_priv *priv = dev->priv;
1396	if (priv->mode != NL80211_IFTYPE_MONITOR)
1397		return -EOPNOTSUPP;
1398
1399	switch (vif->type) {
1400	case NL80211_IFTYPE_STATION:
1401		priv->mode = vif->type;
1402		break;
1403	default:
1404		return -EOPNOTSUPP;
1405	}
1406
1407	ADM8211_IDLE();
1408
1409	ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1410	ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1411
1412	adm8211_update_mode(dev);
1413
1414	ADM8211_RESTORE();
1415
1416	return 0;
1417}
1418
1419static void adm8211_remove_interface(struct ieee80211_hw *dev,
1420				     struct ieee80211_vif *vif)
1421{
1422	struct adm8211_priv *priv = dev->priv;
1423	priv->mode = NL80211_IFTYPE_MONITOR;
1424}
1425
1426static int adm8211_init_rings(struct ieee80211_hw *dev)
1427{
1428	struct adm8211_priv *priv = dev->priv;
1429	struct adm8211_desc *desc = NULL;
1430	struct adm8211_rx_ring_info *rx_info;
1431	struct adm8211_tx_ring_info *tx_info;
1432	unsigned int i;
1433
1434	for (i = 0; i < priv->rx_ring_size; i++) {
1435		desc = &priv->rx_ring[i];
1436		desc->status = 0;
1437		desc->length = cpu_to_le32(RX_PKT_SIZE);
1438		priv->rx_buffers[i].skb = NULL;
1439	}
1440	/* Mark the end of RX ring; hw returns to base address after this
1441	 * descriptor */
1442	desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1443
1444	for (i = 0; i < priv->rx_ring_size; i++) {
1445		desc = &priv->rx_ring[i];
1446		rx_info = &priv->rx_buffers[i];
1447
1448		rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1449		if (rx_info->skb == NULL)
1450			break;
1451		rx_info->mapping = pci_map_single(priv->pdev,
1452						  skb_tail_pointer(rx_info->skb),
1453						  RX_PKT_SIZE,
1454						  PCI_DMA_FROMDEVICE);
1455		desc->buffer1 = cpu_to_le32(rx_info->mapping);
1456		desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1457	}
1458
1459	/* Setup TX ring. TX buffers descriptors will be filled in as needed */
1460	for (i = 0; i < priv->tx_ring_size; i++) {
1461		desc = &priv->tx_ring[i];
1462		tx_info = &priv->tx_buffers[i];
1463
1464		tx_info->skb = NULL;
1465		tx_info->mapping = 0;
1466		desc->status = 0;
1467	}
1468	desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1469
1470	priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1471	ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1472	ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1473
1474	return 0;
1475}
1476
1477static void adm8211_free_rings(struct ieee80211_hw *dev)
1478{
1479	struct adm8211_priv *priv = dev->priv;
1480	unsigned int i;
1481
1482	for (i = 0; i < priv->rx_ring_size; i++) {
1483		if (!priv->rx_buffers[i].skb)
1484			continue;
1485
1486		pci_unmap_single(
1487			priv->pdev,
1488			priv->rx_buffers[i].mapping,
1489			RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1490
1491		dev_kfree_skb(priv->rx_buffers[i].skb);
1492	}
1493
1494	for (i = 0; i < priv->tx_ring_size; i++) {
1495		if (!priv->tx_buffers[i].skb)
1496			continue;
1497
1498		pci_unmap_single(priv->pdev,
1499				 priv->tx_buffers[i].mapping,
1500				 priv->tx_buffers[i].skb->len,
1501				 PCI_DMA_TODEVICE);
1502
1503		dev_kfree_skb(priv->tx_buffers[i].skb);
1504	}
1505}
1506
1507static int adm8211_start(struct ieee80211_hw *dev)
1508{
1509	struct adm8211_priv *priv = dev->priv;
1510	int retval;
1511
1512	/* Power up MAC and RF chips */
1513	retval = adm8211_hw_reset(dev);
1514	if (retval) {
1515		wiphy_err(dev->wiphy, "hardware reset failed\n");
1516		goto fail;
1517	}
1518
1519	retval = adm8211_init_rings(dev);
1520	if (retval) {
1521		wiphy_err(dev->wiphy, "failed to initialize rings\n");
1522		goto fail;
1523	}
1524
1525	/* Init hardware */
1526	adm8211_hw_init(dev);
1527	adm8211_rf_set_channel(dev, priv->channel);
1528
1529	retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1530			     IRQF_SHARED, "adm8211", dev);
1531	if (retval) {
1532		wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1533		goto fail;
1534	}
1535
1536	ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1537			       ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1538			       ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1539	priv->mode = NL80211_IFTYPE_MONITOR;
1540	adm8211_update_mode(dev);
1541	ADM8211_CSR_WRITE(RDR, 0);
1542
1543	adm8211_set_interval(dev, 100, 10);
1544	return 0;
1545
1546fail:
1547	return retval;
1548}
1549
1550static void adm8211_stop(struct ieee80211_hw *dev)
1551{
1552	struct adm8211_priv *priv = dev->priv;
1553
1554	priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1555	priv->nar = 0;
1556	ADM8211_CSR_WRITE(NAR, 0);
1557	ADM8211_CSR_WRITE(IER, 0);
1558	ADM8211_CSR_READ(NAR);
1559
1560	free_irq(priv->pdev->irq, dev);
1561
1562	adm8211_free_rings(dev);
1563}
1564
1565static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1566				   int plcp_signal, int short_preamble)
1567{
1568	/* Alternative calculation from NetBSD: */
1569
1570/* IEEE 802.11b durations for DSSS PHY in microseconds */
1571#define IEEE80211_DUR_DS_LONG_PREAMBLE	144
1572#define IEEE80211_DUR_DS_SHORT_PREAMBLE	72
1573#define IEEE80211_DUR_DS_FAST_PLCPHDR	24
1574#define IEEE80211_DUR_DS_SLOW_PLCPHDR	48
1575#define IEEE80211_DUR_DS_SLOW_ACK	112
1576#define IEEE80211_DUR_DS_FAST_ACK	56
1577#define IEEE80211_DUR_DS_SLOW_CTS	112
1578#define IEEE80211_DUR_DS_FAST_CTS	56
1579#define IEEE80211_DUR_DS_SLOT		20
1580#define IEEE80211_DUR_DS_SIFS		10
1581
1582	int remainder;
1583
1584	*dur = (80 * (24 + payload_len) + plcp_signal - 1)
1585		/ plcp_signal;
1586
1587	if (plcp_signal <= PLCP_SIGNAL_2M)
1588		/* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1589		*dur += 3 * (IEEE80211_DUR_DS_SIFS +
1590			     IEEE80211_DUR_DS_SHORT_PREAMBLE +
1591			     IEEE80211_DUR_DS_FAST_PLCPHDR) +
1592			     IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1593	else
1594		/* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1595		*dur += 3 * (IEEE80211_DUR_DS_SIFS +
1596			     IEEE80211_DUR_DS_SHORT_PREAMBLE +
1597			     IEEE80211_DUR_DS_FAST_PLCPHDR) +
1598			     IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1599
1600	/* lengthen duration if long preamble */
1601	if (!short_preamble)
1602		*dur +=	3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1603			     IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1604			3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1605			     IEEE80211_DUR_DS_FAST_PLCPHDR);
1606
1607
1608	*plcp = (80 * len) / plcp_signal;
1609	remainder = (80 * len) % plcp_signal;
1610	if (plcp_signal == PLCP_SIGNAL_11M &&
1611	    remainder <= 30 && remainder > 0)
1612		*plcp = (*plcp | 0x8000) + 1;
1613	else if (remainder)
1614		(*plcp)++;
1615}
1616
1617/* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1618static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1619			   u16 plcp_signal,
1620			   size_t hdrlen)
1621{
1622	struct adm8211_priv *priv = dev->priv;
1623	unsigned long flags;
1624	dma_addr_t mapping;
1625	unsigned int entry;
1626	u32 flag;
1627
1628	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1629				 PCI_DMA_TODEVICE);
1630
1631	spin_lock_irqsave(&priv->lock, flags);
1632
1633	if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1634		flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1635	else
1636		flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1637
1638	if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1639		ieee80211_stop_queue(dev, 0);
1640
1641	entry = priv->cur_tx % priv->tx_ring_size;
1642
1643	priv->tx_buffers[entry].skb = skb;
1644	priv->tx_buffers[entry].mapping = mapping;
1645	priv->tx_buffers[entry].hdrlen = hdrlen;
1646	priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1647
1648	if (entry == priv->tx_ring_size - 1)
1649		flag |= TDES1_CONTROL_TER;
1650	priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1651
1652	/* Set TX rate (SIGNAL field in PLCP PPDU format) */
1653	flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1654	priv->tx_ring[entry].status = cpu_to_le32(flag);
1655
1656	priv->cur_tx++;
1657
1658	spin_unlock_irqrestore(&priv->lock, flags);
1659
1660	/* Trigger transmit poll */
1661	ADM8211_CSR_WRITE(TDR, 0);
1662}
1663
1664/* Put adm8211_tx_hdr on skb and transmit */
1665static void adm8211_tx(struct ieee80211_hw *dev,
1666		       struct ieee80211_tx_control *control,
1667		       struct sk_buff *skb)
1668{
1669	struct adm8211_tx_hdr *txhdr;
1670	size_t payload_len, hdrlen;
1671	int plcp, dur, len, plcp_signal, short_preamble;
1672	struct ieee80211_hdr *hdr;
1673	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1674	struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1675	u8 rc_flags;
1676
1677	rc_flags = info->control.rates[0].flags;
1678	short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1679	plcp_signal = txrate->bitrate;
1680
1681	hdr = (struct ieee80211_hdr *)skb->data;
1682	hdrlen = ieee80211_hdrlen(hdr->frame_control);
1683	memcpy(skb->cb, skb->data, hdrlen);
1684	hdr = (struct ieee80211_hdr *)skb->cb;
1685	skb_pull(skb, hdrlen);
1686	payload_len = skb->len;
1687
1688	txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1689	memset(txhdr, 0, sizeof(*txhdr));
1690	memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1691	txhdr->signal = plcp_signal;
1692	txhdr->frame_body_size = cpu_to_le16(payload_len);
1693	txhdr->frame_control = hdr->frame_control;
1694
1695	len = hdrlen + payload_len + FCS_LEN;
1696
1697	txhdr->frag = cpu_to_le16(0x0FFF);
1698	adm8211_calc_durations(&dur, &plcp, payload_len,
1699			       len, plcp_signal, short_preamble);
1700	txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1701	txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1702	txhdr->dur_frag_head = cpu_to_le16(dur);
1703	txhdr->dur_frag_tail = cpu_to_le16(dur);
1704
1705	txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1706
1707	if (short_preamble)
1708		txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1709
1710	if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1711		txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1712
1713	txhdr->retry_limit = info->control.rates[0].count;
1714
1715	adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
1716}
1717
1718static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1719{
1720	struct adm8211_priv *priv = dev->priv;
1721	unsigned int ring_size;
1722
1723	priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1724				   sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1725	if (!priv->rx_buffers)
1726		return -ENOMEM;
1727
1728	priv->tx_buffers = (void *)priv->rx_buffers +
1729			   sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1730
1731	/* Allocate TX/RX descriptors */
1732	ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1733		    sizeof(struct adm8211_desc) * priv->tx_ring_size;
1734	priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1735					     &priv->rx_ring_dma);
1736
1737	if (!priv->rx_ring) {
1738		kfree(priv->rx_buffers);
1739		priv->rx_buffers = NULL;
1740		priv->tx_buffers = NULL;
1741		return -ENOMEM;
1742	}
1743
1744	priv->tx_ring = priv->rx_ring + priv->rx_ring_size;
1745	priv->tx_ring_dma = priv->rx_ring_dma +
1746			    sizeof(struct adm8211_desc) * priv->rx_ring_size;
1747
1748	return 0;
1749}
1750
1751static const struct ieee80211_ops adm8211_ops = {
1752	.tx			= adm8211_tx,
1753	.start			= adm8211_start,
1754	.stop			= adm8211_stop,
1755	.add_interface		= adm8211_add_interface,
1756	.remove_interface	= adm8211_remove_interface,
1757	.config			= adm8211_config,
1758	.bss_info_changed	= adm8211_bss_info_changed,
1759	.prepare_multicast	= adm8211_prepare_multicast,
1760	.configure_filter	= adm8211_configure_filter,
1761	.get_stats		= adm8211_get_stats,
1762	.get_tsf		= adm8211_get_tsft
1763};
1764
1765static int adm8211_probe(struct pci_dev *pdev,
1766				   const struct pci_device_id *id)
1767{
1768	struct ieee80211_hw *dev;
1769	struct adm8211_priv *priv;
1770	unsigned long mem_addr, mem_len;
1771	unsigned int io_addr, io_len;
1772	int err;
1773	u32 reg;
1774	u8 perm_addr[ETH_ALEN];
1775
1776	err = pci_enable_device(pdev);
1777	if (err) {
1778		printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1779		   

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