/drivers/net/wireless/b43/phy_lp.c

http://github.com/mirrors/linux · C · 2730 lines · 2387 code · 275 blank · 68 comment · 315 complexity · 874fdd9736822fec1f659a38550afe91 MD5 · raw file

Large files are truncated click here to view the full file

    

  1. /*
    2. 

    3. 

  3.   Broadcom B43 wireless driver
    4. 

  4.   IEEE 802.11a/g LP-PHY driver
    5. 

    6. 

  6.   Copyright (c) 2008-2009 Michael Buesch <m@bues.ch>
    7. 

  7.   Copyright (c) 2009 G??bor Stefanik <netrolller.3d@gmail.com>
    8. 

    9. 

  9.   This program is free software; you can redistribute it and/or modify
    10. 

  10.   it under the terms of the GNU General Public License as published by
    11. 

  11.   the Free Software Foundation; either version 2 of the License, or
    12. 

  12.   (at your option) any later version.
    13. 

    14. 

  14.   This program is distributed in the hope that it will be useful,
    15. 

  15.   but WITHOUT ANY WARRANTY; without even the implied warranty of
    16. 

  16.   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17. 

  17.   GNU General Public License for more details.
    18. 

    19. 

  19.   You should have received a copy of the GNU General Public License
    20. 

  20.   along with this program; see the file COPYING.  If not, write to
    21. 

  21.   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
    22. 

  22.   Boston, MA 02110-1301, USA.
    23. 

    24. 

  24. */
    25. 

  25. 

  26. #include <linux/slab.h>
    27. 

  27. 

  28. #include "b43.h"
    29. 

  29. #include "main.h"
    30. 

  30. #include "phy_lp.h"
    31. 

  31. #include "phy_common.h"
    32. 

  32. #include "tables_lpphy.h"
    33. 

  33. 

  34. 

  35. static inline u16 channel2freq_lp(u8 channel)
    36. 

  36. {
    37. 

  37. 	if (channel < 14)
    38. 

  38. 		return (2407 + 5 * channel);
    39. 

  39. 	else if (channel == 14)
    40. 

  40. 		return 2484;
    41. 

  41. 	else if (channel < 184)
    42. 

  42. 		return (5000 + 5 * channel);
    43. 

  43. 	else
    44. 

  44. 		return (4000 + 5 * channel);
    45. 

  45. }
    46. 

  46. 

  47. static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
    48. 

  48. {
    49. 

  49. 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
    50. 

  50. 		return 1;
    51. 

  51. 	return 36;
    52. 

  52. }
    53. 

  53. 

  54. static int b43_lpphy_op_allocate(struct b43_wldev *dev)
    55. 

  55. {
    56. 

  56. 	struct b43_phy_lp *lpphy;
    57. 

  57. 

  58. 	lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
    59. 

  59. 	if (!lpphy)
    60. 

  60. 		return -ENOMEM;
    61. 

  61. 	dev->phy.lp = lpphy;
    62. 

  62. 

  63. 	return 0;
    64. 

  64. }
    65. 

  65. 

  66. static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
    67. 

  67. {
    68. 

  68. 	struct b43_phy *phy = &dev->phy;
    69. 

  69. 	struct b43_phy_lp *lpphy = phy->lp;
    70. 

  70. 

  71. 	memset(lpphy, 0, sizeof(*lpphy));
    72. 

  72. 	lpphy->antenna = B43_ANTENNA_DEFAULT;
    73. 

  73. 

  74. 	//TODO
    75. 

  75. }
    76. 

  76. 

  77. static void b43_lpphy_op_free(struct b43_wldev *dev)
    78. 

  78. {
    79. 

  79. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    80. 

  80. 

  81. 	kfree(lpphy);
    82. 

  82. 	dev->phy.lp = NULL;
    83. 

  83. }
    84. 

  84. 

  85. /* http://bcm-v4.sipsolutions.net/802.11/PHY/LP/ReadBandSrom */
    86. 

  86. static void lpphy_read_band_sprom(struct b43_wldev *dev)
    87. 

  87. {
    88. 

  88. 	struct ssb_sprom *sprom = dev->dev->bus_sprom;
    89. 

  89. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    90. 

  90. 	u16 cckpo, maxpwr;
    91. 

  91. 	u32 ofdmpo;
    92. 

  92. 	int i;
    93. 

  93. 

  94. 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
    95. 

  95. 		lpphy->tx_isolation_med_band = sprom->tri2g;
    96. 

  96. 		lpphy->bx_arch = sprom->bxa2g;
    97. 

  97. 		lpphy->rx_pwr_offset = sprom->rxpo2g;
    98. 

  98. 		lpphy->rssi_vf = sprom->rssismf2g;
    99. 

  99. 		lpphy->rssi_vc = sprom->rssismc2g;
    100. 

  100. 		lpphy->rssi_gs = sprom->rssisav2g;
    101. 

  101. 		lpphy->txpa[0] = sprom->pa0b0;
    102. 

  102. 		lpphy->txpa[1] = sprom->pa0b1;
    103. 

  103. 		lpphy->txpa[2] = sprom->pa0b2;
    104. 

  104. 		maxpwr = sprom->maxpwr_bg;
    105. 

  105. 		lpphy->max_tx_pwr_med_band = maxpwr;
    106. 

  106. 		cckpo = sprom->cck2gpo;
    107. 

  107. 		if (cckpo) {
    108. 

  108. 			ofdmpo = sprom->ofdm2gpo;
    109. 

  109. 			for (i = 0; i < 4; i++) {
    110. 

  110. 				lpphy->tx_max_rate[i] =
    111. 

  111. 					maxpwr - (ofdmpo & 0xF) * 2;
    112. 

  112. 				ofdmpo >>= 4;
    113. 

  113. 			}
    114. 

  114. 			ofdmpo = sprom->ofdm2gpo;
    115. 

  115. 			for (i = 4; i < 15; i++) {
    116. 

  116. 				lpphy->tx_max_rate[i] =
    117. 

  117. 					maxpwr - (ofdmpo & 0xF) * 2;
    118. 

  118. 				ofdmpo >>= 4;
    119. 

  119. 			}
    120. 

  120. 		} else {
    121. 

  121. 			u8 opo = sprom->opo;
    122. 

  122. 			for (i = 0; i < 4; i++)
    123. 

  123. 				lpphy->tx_max_rate[i] = maxpwr;
    124. 

  124. 			for (i = 4; i < 15; i++)
    125. 

  125. 				lpphy->tx_max_rate[i] = maxpwr - opo;
    126. 

  126. 		}
    127. 

  127. 	} else { /* 5GHz */
    128. 

  128. 		lpphy->tx_isolation_low_band = sprom->tri5gl;
    129. 

  129. 		lpphy->tx_isolation_med_band = sprom->tri5g;
    130. 

  130. 		lpphy->tx_isolation_hi_band = sprom->tri5gh;
    131. 

  131. 		lpphy->bx_arch = sprom->bxa5g;
    132. 

  132. 		lpphy->rx_pwr_offset = sprom->rxpo5g;
    133. 

  133. 		lpphy->rssi_vf = sprom->rssismf5g;
    134. 

  134. 		lpphy->rssi_vc = sprom->rssismc5g;
    135. 

  135. 		lpphy->rssi_gs = sprom->rssisav5g;
    136. 

  136. 		lpphy->txpa[0] = sprom->pa1b0;
    137. 

  137. 		lpphy->txpa[1] = sprom->pa1b1;
    138. 

  138. 		lpphy->txpa[2] = sprom->pa1b2;
    139. 

  139. 		lpphy->txpal[0] = sprom->pa1lob0;
    140. 

  140. 		lpphy->txpal[1] = sprom->pa1lob1;
    141. 

  141. 		lpphy->txpal[2] = sprom->pa1lob2;
    142. 

  142. 		lpphy->txpah[0] = sprom->pa1hib0;
    143. 

  143. 		lpphy->txpah[1] = sprom->pa1hib1;
    144. 

  144. 		lpphy->txpah[2] = sprom->pa1hib2;
    145. 

  145. 		maxpwr = sprom->maxpwr_al;
    146. 

  146. 		ofdmpo = sprom->ofdm5glpo;
    147. 

  147. 		lpphy->max_tx_pwr_low_band = maxpwr;
    148. 

  148. 		for (i = 4; i < 12; i++) {
    149. 

  149. 			lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
    150. 

  150. 			ofdmpo >>= 4;
    151. 

  151. 		}
    152. 

  152. 		maxpwr = sprom->maxpwr_a;
    153. 

  153. 		ofdmpo = sprom->ofdm5gpo;
    154. 

  154. 		lpphy->max_tx_pwr_med_band = maxpwr;
    155. 

  155. 		for (i = 4; i < 12; i++) {
    156. 

  156. 			lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
    157. 

  157. 			ofdmpo >>= 4;
    158. 

  158. 		}
    159. 

  159. 		maxpwr = sprom->maxpwr_ah;
    160. 

  160. 		ofdmpo = sprom->ofdm5ghpo;
    161. 

  161. 		lpphy->max_tx_pwr_hi_band = maxpwr;
    162. 

  162. 		for (i = 4; i < 12; i++) {
    163. 

  163. 			lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
    164. 

  164. 			ofdmpo >>= 4;
    165. 

  165. 		}
    166. 

  166. 	}
    167. 

  167. }
    168. 

  168. 

  169. static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
    170. 

  170. {
    171. 

  171. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    172. 

  172. 	u16 temp[3];
    173. 

  173. 	u16 isolation;
    174. 

  174. 

  175. 	B43_WARN_ON(dev->phy.rev >= 2);
    176. 

  176. 

  177. 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
    178. 

  178. 		isolation = lpphy->tx_isolation_med_band;
    179. 

  179. 	else if (freq <= 5320)
    180. 

  180. 		isolation = lpphy->tx_isolation_low_band;
    181. 

  181. 	else if (freq <= 5700)
    182. 

  182. 		isolation = lpphy->tx_isolation_med_band;
    183. 

  183. 	else
    184. 

  184. 		isolation = lpphy->tx_isolation_hi_band;
    185. 

  185. 

  186. 	temp[0] = ((isolation - 26) / 12) << 12;
    187. 

  187. 	temp[1] = temp[0] + 0x1000;
    188. 

  188. 	temp[2] = temp[0] + 0x2000;
    189. 

  189. 

  190. 	b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
    191. 

  191. 	b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
    192. 

  192. }
    193. 

  193. 

  194. static void lpphy_table_init(struct b43_wldev *dev)
    195. 

  195. {
    196. 

  196. 	u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
    197. 

  197. 

  198. 	if (dev->phy.rev < 2)
    199. 

  199. 		lpphy_rev0_1_table_init(dev);
    200. 

  200. 	else
    201. 

  201. 		lpphy_rev2plus_table_init(dev);
    202. 

  202. 

  203. 	lpphy_init_tx_gain_table(dev);
    204. 

  204. 

  205. 	if (dev->phy.rev < 2)
    206. 

  206. 		lpphy_adjust_gain_table(dev, freq);
    207. 

  207. }
    208. 

  208. 

  209. static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
    210. 

  210. {
    211. 

  211. 	struct ssb_bus *bus = dev->dev->sdev->bus;
    212. 

  212. 	struct ssb_sprom *sprom = dev->dev->bus_sprom;
    213. 

  213. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    214. 

  214. 	u16 tmp, tmp2;
    215. 

  215. 

  216. 	b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
    217. 

  217. 	b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
    218. 

  218. 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
    219. 

  219. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
    220. 

  220. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
    221. 

  221. 	b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
    222. 

  222. 	b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
    223. 

  223. 	b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
    224. 

  224. 	b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
    225. 

  225. 	b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
    226. 

  226. 	b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
    227. 

  227. 	b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
    228. 

  228. 	b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
    229. 

  229. 	b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
    230. 

  230. 	b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
    231. 

  231. 	b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
    232. 

  232. 	b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180);
    233. 

  233. 	b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00);
    234. 

  234. 	b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
    235. 

  235. 	b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
    236. 

  236. 	b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
    237. 

  237. 	b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
    238. 

  238. 	b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
    239. 

  239. 			0xFF00, lpphy->rx_pwr_offset);
    240. 

  240. 	if ((sprom->boardflags_lo & B43_BFL_FEM) &&
    241. 

  241. 	   ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
    242. 

  242. 	   (sprom->boardflags_hi & B43_BFH_PAREF))) {
    243. 

  243. 		ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
    244. 

  244. 		ssb_pmu_set_ldo_paref(&bus->chipco, true);
    245. 

  245. 		if (dev->phy.rev == 0) {
    246. 

  246. 			b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
    247. 

  247. 					0xFFCF, 0x0010);
    248. 

  248. 		}
    249. 

  249. 		b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
    250. 

  250. 	} else {
    251. 

  251. 		ssb_pmu_set_ldo_paref(&bus->chipco, false);
    252. 

  252. 		b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
    253. 

  253. 				0xFFCF, 0x0020);
    254. 

  254. 		b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
    255. 

  255. 	}
    256. 

  256. 	tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
    257. 

  257. 	b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
    258. 

  258. 	if (sprom->boardflags_hi & B43_BFH_RSSIINV)
    259. 

  259. 		b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
    260. 

  260. 	else
    261. 

  261. 		b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
    262. 

  262. 	b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
    263. 

  263. 	b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
    264. 

  264. 			0xFFF9, (lpphy->bx_arch << 1));
    265. 

  265. 	if (dev->phy.rev == 1 &&
    266. 

  266. 	   (sprom->boardflags_hi & B43_BFH_FEM_BT)) {
    267. 

  267. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
    268. 

  268. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
    269. 

  269. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
    270. 

  270. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
    271. 

  271. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
    272. 

  272. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
    273. 

  273. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
    274. 

  274. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
    275. 

  275. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
    276. 

  276. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
    277. 

  277. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
    278. 

  278. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
    279. 

  279. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
    280. 

  280. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
    281. 

  281. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
    282. 

  282. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
    283. 

  283. 	} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
    284. 

  284. 		   (dev->dev->board_type == SSB_BOARD_BU4312) ||
    285. 

  285. 		   (dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) {
    286. 

  286. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
    287. 

  287. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
    288. 

  288. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
    289. 

  289. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
    290. 

  290. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
    291. 

  291. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
    292. 

  292. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
    293. 

  293. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
    294. 

  294. 	} else if (dev->phy.rev == 1 ||
    295. 

  295. 		  (sprom->boardflags_lo & B43_BFL_FEM)) {
    296. 

  296. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
    297. 

  297. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
    298. 

  298. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
    299. 

  299. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
    300. 

  300. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
    301. 

  301. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
    302. 

  302. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
    303. 

  303. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
    304. 

  304. 	} else {
    305. 

  305. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
    306. 

  306. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
    307. 

  307. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
    308. 

  308. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
    309. 

  309. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
    310. 

  310. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
    311. 

  311. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
    312. 

  312. 		b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
    313. 

  313. 	}
    314. 

  314. 	if (dev->phy.rev == 1 && (sprom->boardflags_hi & B43_BFH_PAREF)) {
    315. 

  315. 		b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
    316. 

  316. 		b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
    317. 

  317. 		b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
    318. 

  318. 		b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
    319. 

  319. 	}
    320. 

  320. 	if ((sprom->boardflags_hi & B43_BFH_FEM_BT) &&
    321. 

  321. 	    (dev->dev->chip_id == 0x5354) &&
    322. 

  322. 	    (dev->dev->chip_pkg == SSB_CHIPPACK_BCM4712S)) {
    323. 

  323. 		b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
    324. 

  324. 		b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
    325. 

  325. 		b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
    326. 

  326. 		//FIXME the Broadcom driver caches & delays this HF write!
    327. 

  327. 		b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
    328. 

  328. 	}
    329. 

  329. 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
    330. 

  330. 		b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
    331. 

  331. 		b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
    332. 

  332. 		b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
    333. 

  333. 		b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
    334. 

  334. 		b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
    335. 

  335. 		b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
    336. 

  336. 		b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
    337. 

  337. 		b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
    338. 

  338. 	} else { /* 5GHz */
    339. 

  339. 		b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
    340. 

  340. 		b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
    341. 

  341. 	}
    342. 

  342. 	if (dev->phy.rev == 1) {
    343. 

  343. 		tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
    344. 

  344. 		tmp2 = (tmp & 0x03E0) >> 5;
    345. 

  345. 		tmp2 |= tmp2 << 5;
    346. 

  346. 		b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
    347. 

  347. 		tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH);
    348. 

  348. 		tmp2 = (tmp & 0x1F00) >> 8;
    349. 

  349. 		tmp2 |= tmp2 << 5;
    350. 

  350. 		b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
    351. 

  351. 		tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
    352. 

  352. 		tmp2 = tmp & 0x00FF;
    353. 

  353. 		tmp2 |= tmp << 8;
    354. 

  354. 		b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
    355. 

  355. 	}
    356. 

  356. }
    357. 

  357. 

  358. static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
    359. 

  359. {
    360. 

  360. 	static const u16 addr[] = {
    361. 

  361. 		B43_PHY_OFDM(0xC1),
    362. 

  362. 		B43_PHY_OFDM(0xC2),
    363. 

  363. 		B43_PHY_OFDM(0xC3),
    364. 

  364. 		B43_PHY_OFDM(0xC4),
    365. 

  365. 		B43_PHY_OFDM(0xC5),
    366. 

  366. 		B43_PHY_OFDM(0xC6),
    367. 

  367. 		B43_PHY_OFDM(0xC7),
    368. 

  368. 		B43_PHY_OFDM(0xC8),
    369. 

  369. 		B43_PHY_OFDM(0xCF),
    370. 

  370. 	};
    371. 

  371. 

  372. 	static const u16 coefs[] = {
    373. 

  373. 		0xDE5E, 0xE832, 0xE331, 0x4D26,
    374. 

  374. 		0x0026, 0x1420, 0x0020, 0xFE08,
    375. 

  375. 		0x0008,
    376. 

  376. 	};
    377. 

  377. 

  378. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    379. 

  379. 	int i;
    380. 

  380. 

  381. 	for (i = 0; i < ARRAY_SIZE(addr); i++) {
    382. 

  382. 		lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
    383. 

  383. 		b43_phy_write(dev, addr[i], coefs[i]);
    384. 

  384. 	}
    385. 

  385. }
    386. 

  386. 

  387. static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
    388. 

  388. {
    389. 

  389. 	static const u16 addr[] = {
    390. 

  390. 		B43_PHY_OFDM(0xC1),
    391. 

  391. 		B43_PHY_OFDM(0xC2),
    392. 

  392. 		B43_PHY_OFDM(0xC3),
    393. 

  393. 		B43_PHY_OFDM(0xC4),
    394. 

  394. 		B43_PHY_OFDM(0xC5),
    395. 

  395. 		B43_PHY_OFDM(0xC6),
    396. 

  396. 		B43_PHY_OFDM(0xC7),
    397. 

  397. 		B43_PHY_OFDM(0xC8),
    398. 

  398. 		B43_PHY_OFDM(0xCF),
    399. 

  399. 	};
    400. 

  400. 

  401. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    402. 

  402. 	int i;
    403. 

  403. 

  404. 	for (i = 0; i < ARRAY_SIZE(addr); i++)
    405. 

  405. 		b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
    406. 

  406. }
    407. 

  407. 

  408. static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
    409. 

  409. {
    410. 

  410. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    411. 

  411. 

  412. 	b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
    413. 

  413. 	b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
    414. 

  414. 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
    415. 

  415. 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
    416. 

  416. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
    417. 

  417. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
    418. 

  418. 	b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
    419. 

  419. 	b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
    420. 

  420. 	b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
    421. 

  421. 	b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
    422. 

  422. 	b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
    423. 

  423. 	b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
    424. 

  424. 	b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
    425. 

  425. 	b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
    426. 

  426. 	b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
    427. 

  427. 	b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
    428. 

  428. 	b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
    429. 

  429. 	if (dev->dev->board_rev >= 0x18) {
    430. 

  430. 		b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
    431. 

  431. 		b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
    432. 

  432. 	} else {
    433. 

  433. 		b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
    434. 

  434. 	}
    435. 

  435. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
    436. 

  436. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
    437. 

  437. 	b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
    438. 

  438. 	b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
    439. 

  439. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
    440. 

  440. 	b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
    441. 

  441. 	b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
    442. 

  442. 	b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
    443. 

  443. 	b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
    444. 

  444. 	b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
    445. 

  445. 	b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
    446. 

  446. 	if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
    447. 

  447. 		b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
    448. 

  448. 		b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
    449. 

  449. 	} else {
    450. 

  450. 		b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
    451. 

  451. 		b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
    452. 

  452. 	}
    453. 

  453. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
    454. 

  454. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
    455. 

  455. 	b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
    456. 

  456. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
    457. 

  457. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
    458. 

  458. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
    459. 

  459. 	b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
    460. 

  460. 	b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
    461. 

  461. 	b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
    462. 

  462. 	b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
    463. 

  463. 

  464. 	if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
    465. 

  465. 		b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
    466. 

  466. 		b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
    467. 

  467. 	}
    468. 

  468. 

  469. 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
    470. 

  470. 		b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
    471. 

  471. 		b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
    472. 

  472. 		b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
    473. 

  473. 		b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
    474. 

  474. 		b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
    475. 

  475. 		b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
    476. 

  476. 	} else /* 5GHz */
    477. 

  477. 		b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
    478. 

  478. 

  479. 	b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
    480. 

  480. 	b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
    481. 

  481. 	b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
    482. 

  482. 	b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
    483. 

  483. 	b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
    484. 

  484. 	b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
    485. 

  485. 	b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
    486. 

  486. 		      0x2000 | ((u16)lpphy->rssi_gs << 10) |
    487. 

  487. 		      ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
    488. 

  488. 

  489. 	if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
    490. 

  490. 		b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
    491. 

  491. 		b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
    492. 

  492. 		b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
    493. 

  493. 	}
    494. 

  494. 

  495. 	lpphy_save_dig_flt_state(dev);
    496. 

  496. }
    497. 

  497. 

  498. static void lpphy_baseband_init(struct b43_wldev *dev)
    499. 

  499. {
    500. 

  500. 	lpphy_table_init(dev);
    501. 

  501. 	if (dev->phy.rev >= 2)
    502. 

  502. 		lpphy_baseband_rev2plus_init(dev);
    503. 

  503. 	else
    504. 

  504. 		lpphy_baseband_rev0_1_init(dev);
    505. 

  505. }
    506. 

  506. 

  507. struct b2062_freqdata {
    508. 

  508. 	u16 freq;
    509. 

  509. 	u8 data[6];
    510. 

  510. };
    511. 

  511. 

  512. /* Initialize the 2062 radio. */
    513. 

  513. static void lpphy_2062_init(struct b43_wldev *dev)
    514. 

  514. {
    515. 

  515. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    516. 

  516. 	struct ssb_bus *bus = dev->dev->sdev->bus;
    517. 

  517. 	u32 crystalfreq, tmp, ref;
    518. 

  518. 	unsigned int i;
    519. 

  519. 	const struct b2062_freqdata *fd = NULL;
    520. 

  520. 

  521. 	static const struct b2062_freqdata freqdata_tab[] = {
    522. 

  522. 		{ .freq = 12000, .data[0] =  6, .data[1] =  6, .data[2] =  6,
    523. 

  523. 				 .data[3] =  6, .data[4] = 10, .data[5] =  6, },
    524. 

  524. 		{ .freq = 13000, .data[0] =  4, .data[1] =  4, .data[2] =  4,
    525. 

  525. 				 .data[3] =  4, .data[4] = 11, .data[5] =  7, },
    526. 

  526. 		{ .freq = 14400, .data[0] =  3, .data[1] =  3, .data[2] =  3,
    527. 

  527. 				 .data[3] =  3, .data[4] = 12, .data[5] =  7, },
    528. 

  528. 		{ .freq = 16200, .data[0] =  3, .data[1] =  3, .data[2] =  3,
    529. 

  529. 				 .data[3] =  3, .data[4] = 13, .data[5] =  8, },
    530. 

  530. 		{ .freq = 18000, .data[0] =  2, .data[1] =  2, .data[2] =  2,
    531. 

  531. 				 .data[3] =  2, .data[4] = 14, .data[5] =  8, },
    532. 

  532. 		{ .freq = 19200, .data[0] =  1, .data[1] =  1, .data[2] =  1,
    533. 

  533. 				 .data[3] =  1, .data[4] = 14, .data[5] =  9, },
    534. 

  534. 	};
    535. 

  535. 

  536. 	b2062_upload_init_table(dev);
    537. 

  537. 

  538. 	b43_radio_write(dev, B2062_N_TX_CTL3, 0);
    539. 

  539. 	b43_radio_write(dev, B2062_N_TX_CTL4, 0);
    540. 

  540. 	b43_radio_write(dev, B2062_N_TX_CTL5, 0);
    541. 

  541. 	b43_radio_write(dev, B2062_N_TX_CTL6, 0);
    542. 

  542. 	b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
    543. 

  543. 	b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
    544. 

  544. 	b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
    545. 

  545. 	b43_radio_write(dev, B2062_N_CALIB_TS, 0);
    546. 

  546. 	if (dev->phy.rev > 0) {
    547. 

  547. 		b43_radio_write(dev, B2062_S_BG_CTL1,
    548. 

  548. 			(b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
    549. 

  549. 	}
    550. 

  550. 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
    551. 

  551. 		b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
    552. 

  552. 	else
    553. 

  553. 		b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
    554. 

  554. 

  555. 	/* Get the crystal freq, in Hz. */
    556. 

  556. 	crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
    557. 

  557. 

  558. 	B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
    559. 

  559. 	B43_WARN_ON(crystalfreq == 0);
    560. 

  560. 

  561. 	if (crystalfreq <= 30000000) {
    562. 

  562. 		lpphy->pdiv = 1;
    563. 

  563. 		b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
    564. 

  564. 	} else {
    565. 

  565. 		lpphy->pdiv = 2;
    566. 

  566. 		b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
    567. 

  567. 	}
    568. 

  568. 

  569. 	tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
    570. 

  570. 	      (2 * crystalfreq)) - 8) & 0xFF;
    571. 

  571. 	b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
    572. 

  572. 

  573. 	tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
    574. 

  574. 	      (32000000 * lpphy->pdiv)) - 1) & 0xFF;
    575. 

  575. 	b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
    576. 

  576. 

  577. 	tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
    578. 

  578. 	      (2000000 * lpphy->pdiv)) - 1) & 0xFF;
    579. 

  579. 	b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
    580. 

  580. 

  581. 	ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
    582. 

  582. 	ref &= 0xFFFF;
    583. 

  583. 	for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
    584. 

  584. 		if (ref < freqdata_tab[i].freq) {
    585. 

  585. 			fd = &freqdata_tab[i];
    586. 

  586. 			break;
    587. 

  587. 		}
    588. 

  588. 	}
    589. 

  589. 	if (!fd)
    590. 

  590. 		fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
    591. 

  591. 	b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
    592. 

  592. 	       fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
    593. 

  593. 

  594. 	b43_radio_write(dev, B2062_S_RFPLL_CTL8,
    595. 

  595. 			((u16)(fd->data[1]) << 4) | fd->data[0]);
    596. 

  596. 	b43_radio_write(dev, B2062_S_RFPLL_CTL9,
    597. 

  597. 			((u16)(fd->data[3]) << 4) | fd->data[2]);
    598. 

  598. 	b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
    599. 

  599. 	b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
    600. 

  600. }
    601. 

  601. 

  602. /* Initialize the 2063 radio. */
    603. 

  603. static void lpphy_2063_init(struct b43_wldev *dev)
    604. 

  604. {
    605. 

  605. 	b2063_upload_init_table(dev);
    606. 

  606. 	b43_radio_write(dev, B2063_LOGEN_SP5, 0);
    607. 

  607. 	b43_radio_set(dev, B2063_COMM8, 0x38);
    608. 

  608. 	b43_radio_write(dev, B2063_REG_SP1, 0x56);
    609. 

  609. 	b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
    610. 

  610. 	b43_radio_write(dev, B2063_PA_SP7, 0);
    611. 

  611. 	b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
    612. 

  612. 	b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
    613. 

  613. 	if (dev->phy.rev == 2) {
    614. 

  614. 		b43_radio_write(dev, B2063_PA_SP3, 0xa0);
    615. 

  615. 		b43_radio_write(dev, B2063_PA_SP4, 0xa0);
    616. 

  616. 		b43_radio_write(dev, B2063_PA_SP2, 0x18);
    617. 

  617. 	} else {
    618. 

  618. 		b43_radio_write(dev, B2063_PA_SP3, 0x20);
    619. 

  619. 		b43_radio_write(dev, B2063_PA_SP2, 0x20);
    620. 

  620. 	}
    621. 

  621. }
    622. 

  622. 

  623. struct lpphy_stx_table_entry {
    624. 

  624. 	u16 phy_offset;
    625. 

  625. 	u16 phy_shift;
    626. 

  626. 	u16 rf_addr;
    627. 

  627. 	u16 rf_shift;
    628. 

  628. 	u16 mask;
    629. 

  629. };
    630. 

  630. 

  631. static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
    632. 

  632. 	{ .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
    633. 

  633. 	{ .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
    634. 

  634. 	{ .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
    635. 

  635. 	{ .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
    636. 

  636. 	{ .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
    637. 

  637. 	{ .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
    638. 

  638. 	{ .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
    639. 

  639. 	{ .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
    640. 

  640. 	{ .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
    641. 

  641. 	{ .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
    642. 

  642. 	{ .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
    643. 

  643. 	{ .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
    644. 

  644. 	{ .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
    645. 

  645. 	{ .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
    646. 

  646. 	{ .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
    647. 

  647. 	{ .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
    648. 

  648. 	{ .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
    649. 

  649. 	{ .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
    650. 

  650. 	{ .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
    651. 

  651. 	{ .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
    652. 

  652. 	{ .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
    653. 

  653. 	{ .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
    654. 

  654. 	{ .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
    655. 

  655. 	{ .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
    656. 

  656. 	{ .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
    657. 

  657. 	{ .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
    658. 

  658. 	{ .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
    659. 

  659. 	{ .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
    660. 

  660. 	{ .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
    661. 

  661. };
    662. 

  662. 

  663. static void lpphy_sync_stx(struct b43_wldev *dev)
    664. 

  664. {
    665. 

  665. 	const struct lpphy_stx_table_entry *e;
    666. 

  666. 	unsigned int i;
    667. 

  667. 	u16 tmp;
    668. 

  668. 

  669. 	for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
    670. 

  670. 		e = &lpphy_stx_table[i];
    671. 

  671. 		tmp = b43_radio_read(dev, e->rf_addr);
    672. 

  672. 		tmp >>= e->rf_shift;
    673. 

  673. 		tmp <<= e->phy_shift;
    674. 

  674. 		b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
    675. 

  675. 				~(e->mask << e->phy_shift), tmp);
    676. 

  676. 	}
    677. 

  677. }
    678. 

  678. 

  679. static void lpphy_radio_init(struct b43_wldev *dev)
    680. 

  680. {
    681. 

  681. 	/* The radio is attached through the 4wire bus. */
    682. 

  682. 	b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
    683. 

  683. 	udelay(1);
    684. 

  684. 	b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
    685. 

  685. 	udelay(1);
    686. 

  686. 

  687. 	if (dev->phy.radio_ver == 0x2062) {
    688. 

  688. 		lpphy_2062_init(dev);
    689. 

  689. 	} else {
    690. 

  690. 		lpphy_2063_init(dev);
    691. 

  691. 		lpphy_sync_stx(dev);
    692. 

  692. 		b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
    693. 

  693. 		b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
    694. 

  694. 		if (dev->dev->chip_id == 0x4325) {
    695. 

  695. 			// TODO SSB PMU recalibration
    696. 

  696. 		}
    697. 

  697. 	}
    698. 

  698. }
    699. 

  699. 

  700. struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
    701. 

  701. 

  702. static void lpphy_set_rc_cap(struct b43_wldev *dev)
    703. 

  703. {
    704. 

  704. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    705. 

  705. 

  706. 	u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
    707. 

  707. 

  708. 	if (dev->phy.rev == 1) //FIXME check channel 14!
    709. 

  709. 		rc_cap = min_t(u8, rc_cap + 5, 15);
    710. 

  710. 

  711. 	b43_radio_write(dev, B2062_N_RXBB_CALIB2,
    712. 

  712. 			max_t(u8, lpphy->rc_cap - 4, 0x80));
    713. 

  713. 	b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
    714. 

  714. 	b43_radio_write(dev, B2062_S_RXG_CNT16,
    715. 

  715. 			((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
    716. 

  716. }
    717. 

  717. 

  718. static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
    719. 

  719. {
    720. 

  720. 	return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
    721. 

  721. }
    722. 

  722. 

  723. static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
    724. 

  724. {
    725. 

  725. 	b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
    726. 

  726. }
    727. 

  727. 

  728. static void lpphy_set_deaf(struct b43_wldev *dev, bool user)
    729. 

  729. {
    730. 

  730. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    731. 

  731. 

  732. 	if (user)
    733. 

  733. 		lpphy->crs_usr_disable = true;
    734. 

  734. 	else
    735. 

  735. 		lpphy->crs_sys_disable = true;
    736. 

  736. 	b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
    737. 

  737. }
    738. 

  738. 

  739. static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
    740. 

  740. {
    741. 

  741. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    742. 

  742. 

  743. 	if (user)
    744. 

  744. 		lpphy->crs_usr_disable = false;
    745. 

  745. 	else
    746. 

  746. 		lpphy->crs_sys_disable = false;
    747. 

  747. 

  748. 	if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) {
    749. 

  749. 		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
    750. 

  750. 			b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
    751. 

  751. 					0xFF1F, 0x60);
    752. 

  752. 		else
    753. 

  753. 			b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
    754. 

  754. 					0xFF1F, 0x20);
    755. 

  755. 	}
    756. 

  756. }
    757. 

  757. 

  758. static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx)
    759. 

  759. {
    760. 

  760. 	u16 trsw = (tx << 1) | rx;
    761. 

  761. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw);
    762. 

  762. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
    763. 

  763. }
    764. 

  764. 

  765. static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
    766. 

  766. {
    767. 

  767. 	lpphy_set_deaf(dev, user);
    768. 

  768. 	lpphy_set_trsw_over(dev, false, true);
    769. 

  769. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
    770. 

  770. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
    771. 

  771. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
    772. 

  772. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
    773. 

  773. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
    774. 

  774. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
    775. 

  775. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
    776. 

  776. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
    777. 

  777. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
    778. 

  778. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
    779. 

  779. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
    780. 

  780. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
    781. 

  781. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
    782. 

  782. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
    783. 

  783. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
    784. 

  784. 	b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
    785. 

  785. 	b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
    786. 

  786. 	b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
    787. 

  787. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
    788. 

  788. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
    789. 

  789. 	b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
    790. 

  790. 	b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
    791. 

  791. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
    792. 

  792. }
    793. 

  793. 

  794. static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
    795. 

  795. {
    796. 

  796. 	lpphy_clear_deaf(dev, user);
    797. 

  797. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
    798. 

  798. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
    799. 

  799. }
    800. 

  800. 

  801. struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
    802. 

  802. 

  803. static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
    804. 

  804. {
    805. 

  805. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
    806. 

  806. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
    807. 

  807. 	b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
    808. 

  808. 	if (dev->phy.rev >= 2) {
    809. 

  809. 		b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
    810. 

  810. 		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
    811. 

  811. 			b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
    812. 

  812. 			b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
    813. 

  813. 		}
    814. 

  814. 	} else {
    815. 

  815. 		b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
    816. 

  816. 	}
    817. 

  817. }
    818. 

  818. 

  819. static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
    820. 

  820. {
    821. 

  821. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
    822. 

  822. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
    823. 

  823. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
    824. 

  824. 	if (dev->phy.rev >= 2) {
    825. 

  825. 		b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
    826. 

  826. 		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
    827. 

  827. 			b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
    828. 

  828. 			b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
    829. 

  829. 		}
    830. 

  830. 	} else {
    831. 

  831. 		b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
    832. 

  832. 	}
    833. 

  833. }
    834. 

  834. 

  835. static void lpphy_disable_tx_gain_override(struct b43_wldev *dev)
    836. 

  836. {
    837. 

  837. 	if (dev->phy.rev < 2)
    838. 

  838. 		b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
    839. 

  839. 	else {
    840. 

  840. 		b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F);
    841. 

  841. 		b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF);
    842. 

  842. 	}
    843. 

  843. 	b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF);
    844. 

  844. }
    845. 

  845. 

  846. static void lpphy_enable_tx_gain_override(struct b43_wldev *dev)
    847. 

  847. {
    848. 

  848. 	if (dev->phy.rev < 2)
    849. 

  849. 		b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
    850. 

  850. 	else {
    851. 

  851. 		b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80);
    852. 

  852. 		b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000);
    853. 

  853. 	}
    854. 

  854. 	b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40);
    855. 

  855. }
    856. 

  856. 

  857. static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
    858. 

  858. {
    859. 

  859. 	struct lpphy_tx_gains gains;
    860. 

  860. 	u16 tmp;
    861. 

  861. 

  862. 	gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
    863. 

  863. 	if (dev->phy.rev < 2) {
    864. 

  864. 		tmp = b43_phy_read(dev,
    865. 

  865. 				   B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
    866. 

  866. 		gains.gm = tmp & 0x0007;
    867. 

  867. 		gains.pga = (tmp & 0x0078) >> 3;
    868. 

  868. 		gains.pad = (tmp & 0x780) >> 7;
    869. 

  869. 	} else {
    870. 

  870. 		tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
    871. 

  871. 		gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
    872. 

  872. 		gains.gm = tmp & 0xFF;
    873. 

  873. 		gains.pga = (tmp >> 8) & 0xFF;
    874. 

  874. 	}
    875. 

  875. 

  876. 	return gains;
    877. 

  877. }
    878. 

  878. 

  879. static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
    880. 

  880. {
    881. 

  881. 	u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
    882. 

  882. 	ctl |= dac << 7;
    883. 

  883. 	b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
    884. 

  884. }
    885. 

  885. 

  886. static u16 lpphy_get_pa_gain(struct b43_wldev *dev)
    887. 

  887. {
    888. 

  888. 	return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F;
    889. 

  889. }
    890. 

  890. 

  891. static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain)
    892. 

  892. {
    893. 

  893. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6);
    894. 

  894. 	b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8);
    895. 

  895. }
    896. 

  896. 

  897. static void lpphy_set_tx_gains(struct b43_wldev *dev,
    898. 

  898. 			       struct lpphy_tx_gains gains)
    899. 

  899. {
    900. 

  900. 	u16 rf_gain, pa_gain;
    901. 

  901. 

  902. 	if (dev->phy.rev < 2) {
    903. 

  903. 		rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
    904. 

  904. 		b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
    905. 

  905. 				0xF800, rf_gain);
    906. 

  906. 	} else {
    907. 

  907. 		pa_gain = lpphy_get_pa_gain(dev);
    908. 

  908. 		b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
    909. 

  909. 			      (gains.pga << 8) | gains.gm);
    910. 

  910. 		/*
    911. 

  911. 		 * SPEC FIXME The spec calls for (pa_gain << 8) here, but that
    912. 

  912. 		 * conflicts with the spec for set_pa_gain! Vendor driver bug?
    913. 

  913. 		 */
    914. 

  914. 		b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
    915. 

  915. 				0x8000, gains.pad | (pa_gain << 6));
    916. 

  916. 		b43_phy_write(dev, B43_PHY_OFDM(0xFC),
    917. 

  917. 			      (gains.pga << 8) | gains.gm);
    918. 

  918. 		b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
    919. 

  919. 				0x8000, gains.pad | (pa_gain << 8));
    920. 

  920. 	}
    921. 

  921. 	lpphy_set_dac_gain(dev, gains.dac);
    922. 

  922. 	lpphy_enable_tx_gain_override(dev);
    923. 

  923. }
    924. 

  924. 

  925. static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
    926. 

  926. {
    927. 

  927. 	u16 trsw = gain & 0x1;
    928. 

  928. 	u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
    929. 

  929. 	u16 ext_lna = (gain & 2) >> 1;
    930. 

  930. 

  931. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
    932. 

  932. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
    933. 

  933. 			0xFBFF, ext_lna << 10);
    934. 

  934. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
    935. 

  935. 			0xF7FF, ext_lna << 11);
    936. 

  936. 	b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
    937. 

  937. }
    938. 

  938. 

  939. static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
    940. 

  940. {
    941. 

  941. 	u16 low_gain = gain & 0xFFFF;
    942. 

  942. 	u16 high_gain = (gain >> 16) & 0xF;
    943. 

  943. 	u16 ext_lna = (gain >> 21) & 0x1;
    944. 

  944. 	u16 trsw = ~(gain >> 20) & 0x1;
    945. 

  945. 	u16 tmp;
    946. 

  946. 

  947. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
    948. 

  948. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
    949. 

  949. 			0xFDFF, ext_lna << 9);
    950. 

  950. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
    951. 

  951. 			0xFBFF, ext_lna << 10);
    952. 

  952. 	b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
    953. 

  953. 	b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
    954. 

  954. 	if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
    955. 

  955. 		tmp = (gain >> 2) & 0x3;
    956. 

  956. 		b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
    957. 

  957. 				0xE7FF, tmp<<11);
    958. 

  958. 		b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
    959. 

  959. 	}
    960. 

  960. }
    961. 

  961. 

  962. static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
    963. 

  963. {
    964. 

  964. 	if (dev->phy.rev < 2)
    965. 

  965. 		lpphy_rev0_1_set_rx_gain(dev, gain);
    966. 

  966. 	else
    967. 

  967. 		lpphy_rev2plus_set_rx_gain(dev, gain);
    968. 

  968. 	lpphy_enable_rx_gain_override(dev);
    969. 

  969. }
    970. 

  970. 

  971. static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
    972. 

  972. {
    973. 

  973. 	u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
    974. 

  974. 	lpphy_set_rx_gain(dev, gain);
    975. 

  975. }
    976. 

  976. 

  977. static void lpphy_stop_ddfs(struct b43_wldev *dev)
    978. 

  978. {
    979. 

  979. 	b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
    980. 

  980. 	b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
    981. 

  981. }
    982. 

  982. 

  983. static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
    984. 

  984. 			   int incr1, int incr2, int scale_idx)
    985. 

  985. {
    986. 

  986. 	lpphy_stop_ddfs(dev);
    987. 

  987. 	b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
    988. 

  988. 	b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
    989. 

  989. 	b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
    990. 

  990. 	b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
    991. 

  991. 	b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
    992. 

  992. 	b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
    993. 

  993. 	b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
    994. 

  994. 	b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
    995. 

  995. 	b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
    996. 

  996. 	b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20);
    997. 

  997. }
    998. 

  998. 

  999. static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
    1000. 

  1000. 			   struct lpphy_iq_est *iq_est)
    1001. 

  1001. {
    1002. 

  1002. 	int i;
    1003. 

  1003. 

  1004. 	b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
    1005. 

  1005. 	b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
    1006. 

  1006. 	b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
    1007. 

  1007. 	b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
    1008. 

  1008. 	b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200);
    1009. 

  1009. 

  1010. 	for (i = 0; i < 500; i++) {
    1011. 

  1011. 		if (!(b43_phy_read(dev,
    1012. 

  1012. 				B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
    1013. 

  1013. 			break;
    1014. 

  1014. 		msleep(1);
    1015. 

  1015. 	}
    1016. 

  1016. 

  1017. 	if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
    1018. 

  1018. 		b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
    1019. 

  1019. 		return false;
    1020. 

  1020. 	}
    1021. 

  1021. 

  1022. 	iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
    1023. 

  1023. 	iq_est->iq_prod <<= 16;
    1024. 

  1024. 	iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
    1025. 

  1025. 

  1026. 	iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
    1027. 

  1027. 	iq_est->i_pwr <<= 16;
    1028. 

  1028. 	iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
    1029. 

  1029. 

  1030. 	iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
    1031. 

  1031. 	iq_est->q_pwr <<= 16;
    1032. 

  1032. 	iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
    1033. 

  1033. 

  1034. 	b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
    1035. 

  1035. 	return true;
    1036. 

  1036. }
    1037. 

  1037. 

  1038. static int lpphy_loopback(struct b43_wldev *dev)
    1039. 

  1039. {
    1040. 

  1040. 	struct lpphy_iq_est iq_est;
    1041. 

  1041. 	int i, index = -1;
    1042. 

  1042. 	u32 tmp;
    1043. 

  1043. 

  1044. 	memset(&iq_est, 0, sizeof(iq_est));
    1045. 

  1045. 

  1046. 	lpphy_set_trsw_over(dev, true, true);
    1047. 

  1047. 	b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
    1048. 

  1048. 	b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
    1049. 

  1049. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
    1050. 

  1050. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
    1051. 

  1051. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
    1052. 

  1052. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
    1053. 

  1053. 	b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
    1054. 

  1054. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
    1055. 

  1055. 	b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
    1056. 

  1056. 	for (i = 0; i < 32; i++) {
    1057. 

  1057. 		lpphy_set_rx_gain_by_index(dev, i);
    1058. 

  1058. 		lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
    1059. 

  1059. 		if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
    1060. 

  1060. 			continue;
    1061. 

  1061. 		tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
    1062. 

  1062. 		if ((tmp > 4000) && (tmp < 10000)) {
    1063. 

  1063. 			index = i;
    1064. 

  1064. 			break;
    1065. 

  1065. 		}
    1066. 

  1066. 	}
    1067. 

  1067. 	lpphy_stop_ddfs(dev);
    1068. 

  1068. 	return index;
    1069. 

  1069. }
    1070. 

  1070. 

  1071. /* Fixed-point division algorithm using only integer math. */
    1072. 

  1072. static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
    1073. 

  1073. {
    1074. 

  1074. 	u32 quotient, remainder;
    1075. 

  1075. 

  1076. 	if (divisor == 0)
    1077. 

  1077. 		return 0;
    1078. 

  1078. 

  1079. 	quotient = dividend / divisor;
    1080. 

  1080. 	remainder = dividend % divisor;
    1081. 

  1081. 

  1082. 	while (precision > 0) {
    1083. 

  1083. 		quotient <<= 1;
    1084. 

  1084. 		if (remainder << 1 >= divisor) {
    1085. 

  1085. 			quotient++;
    1086. 

  1086. 			remainder = (remainder << 1) - divisor;
    1087. 

  1087. 		}
    1088. 

  1088. 		precision--;
    1089. 

  1089. 	}
    1090. 

  1090. 

  1091. 	if (remainder << 1 >= divisor)
    1092. 

  1092. 		quotient++;
    1093. 

  1093. 

  1094. 	return quotient;
    1095. 

  1095. }
    1096. 

  1096. 

  1097. /* Read the TX power control mode from hardware. */
    1098. 

  1098. static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
    1099. 

  1099. {
    1100. 

  1100. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    1101. 

  1101. 	u16 ctl;
    1102. 

  1102. 

  1103. 	ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
    1104. 

  1104. 	switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
    1105. 

  1105. 	case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
    1106. 

  1106. 		lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
    1107. 

  1107. 		break;
    1108. 

  1108. 	case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
    1109. 

  1109. 		lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
    1110. 

  1110. 		break;
    1111. 

  1111. 	case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
    1112. 

  1112. 		lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
    1113. 

  1113. 		break;
    1114. 

  1114. 	default:
    1115. 

  1115. 		lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
    1116. 

  1116. 		B43_WARN_ON(1);
    1117. 

  1117. 		break;
    1118. 

  1118. 	}
    1119. 

  1119. }
    1120. 

  1120. 

  1121. /* Set the TX power control mode in hardware. */
    1122. 

  1122. static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
    1123. 

  1123. {
    1124. 

  1124. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    1125. 

  1125. 	u16 ctl;
    1126. 

  1126. 

  1127. 	switch (lpphy->txpctl_mode) {
    1128. 

  1128. 	case B43_LPPHY_TXPCTL_OFF:
    1129. 

  1129. 		ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
    1130. 

  1130. 		break;
    1131. 

  1131. 	case B43_LPPHY_TXPCTL_HW:
    1132. 

  1132. 		ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
    1133. 

  1133. 		break;
    1134. 

  1134. 	case B43_LPPHY_TXPCTL_SW:
    1135. 

  1135. 		ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
    1136. 

  1136. 		break;
    1137. 

  1137. 	default:
    1138. 

  1138. 		ctl = 0;
    1139. 

  1139. 		B43_WARN_ON(1);
    1140. 

  1140. 	}
    1141. 

  1141. 	b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
    1142. 

  1142. 			~B43_LPPHY_TX_PWR_CTL_CMD_MODE & 0xFFFF, ctl);
    1143. 

  1143. }
    1144. 

  1144. 

  1145. static void lpphy_set_tx_power_control(struct b43_wldev *dev,
    1146. 

  1146. 				       enum b43_lpphy_txpctl_mode mode)
    1147. 

  1147. {
    1148. 

  1148. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    1149. 

  1149. 	enum b43_lpphy_txpctl_mode oldmode;
    1150. 

  1150. 

  1151. 	lpphy_read_tx_pctl_mode_from_hardware(dev);
    1152. 

  1152. 	oldmode = lpphy->txpctl_mode;
    1153. 

  1153. 	if (oldmode == mode)
    1154. 

  1154. 		return;
    1155. 

  1155. 	lpphy->txpctl_mode = mode;
    1156. 

  1156. 

  1157. 	if (oldmode == B43_LPPHY_TXPCTL_HW) {
    1158. 

  1158. 		//TODO Update TX Power NPT
    1159. 

  1159. 		//TODO Clear all TX Power offsets
    1160. 

  1160. 	} else {
    1161. 

  1161. 		if (mode == B43_LPPHY_TXPCTL_HW) {
    1162. 

  1162. 			//TODO Recalculate target TX power
    1163. 

  1163. 			b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
    1164. 

  1164. 					0xFF80, lpphy->tssi_idx);
    1165. 

  1165. 			b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
    1166. 

  1166. 					0x8FFF, ((u16)lpphy->tssi_npt << 16));
    1167. 

  1167. 			//TODO Set "TSSI Transmit Count" variable to total transmitted frame count
    1168. 

  1168. 			lpphy_disable_tx_gain_override(dev);
    1169. 

  1169. 			lpphy->tx_pwr_idx_over = -1;
    1170. 

  1170. 		}
    1171. 

  1171. 	}
    1172. 

  1172. 	if (dev->phy.rev >= 2) {
    1173. 

  1173. 		if (mode == B43_LPPHY_TXPCTL_HW)
    1174. 

  1174. 			b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2);
    1175. 

  1175. 		else
    1176. 

  1176. 			b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
    1177. 

  1177. 	}
    1178. 

  1178. 	lpphy_write_tx_pctl_mode_to_hardware(dev);
    1179. 

  1179. }
    1180. 

  1180. 

  1181. static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
    1182. 

  1182. 				       unsigned int new_channel);
    1183. 

  1183. 

  1184. static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
    1185. 

  1185. {
    1186. 

  1186. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    1187. 

  1187. 	struct lpphy_iq_est iq_est;
    1188. 

  1188. 	struct lpphy_tx_gains tx_gains;
    1189. 

  1189. 	static const u32 ideal_pwr_table[21] = {
    1190. 

  1190. 		0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
    1191. 

  1191. 		0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
    1192. 

  1192. 		0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
    1193. 

  1193. 		0x0004c, 0x0002c, 0x0001a,
    1194. 

  1194. 	};
    1195. 

  1195. 	bool old_txg_ovr;
    1196. 

  1196. 	u8 old_bbmult;
    1197. 

  1197. 	u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
    1198. 

  1198. 	    old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
    1199. 

  1199. 	enum b43_lpphy_txpctl_mode old_txpctl;
    1200. 

  1200. 	u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
    1201. 

  1201. 	int loopback, i, j, inner_sum, err;
    1202. 

  1202. 

  1203. 	memset(&iq_est, 0, sizeof(iq_est));
    1204. 

  1204. 

  1205. 	err = b43_lpphy_op_switch_channel(dev, 7);
    1206. 

  1206. 	if (err) {
    1207. 

  1207. 		b43dbg(dev->wl,
    1208. 

  1208. 		       "RC calib: Failed to switch to channel 7, error = %d\n",
    1209. 

  1209. 		       err);
    1210. 

  1210. 	}
    1211. 

  1211. 	old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
    1212. 

  1212. 	old_bbmult = lpphy_get_bb_mult(dev);
    1213. 

  1213. 	if (old_txg_ovr)
    1214. 

  1214. 		tx_gains = lpphy_get_tx_gains(dev);
    1215. 

  1215. 	old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
    1216. 

  1216. 	old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
    1217. 

  1217. 	old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
    1218. 

  1218. 	old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
    1219. 

  1219. 	old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
    1220. 

  1220. 	old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
    1221. 

  1221. 	old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
    1222. 

  1222. 	lpphy_read_tx_pctl_mode_from_hardware(dev);
    1223. 

  1223. 	old_txpctl = lpphy->txpctl_mode;
    1224. 

  1224. 

  1225. 	lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
    1226. 

  1226. 	lpphy_disable_crs(dev, true);
    1227. 

  1227. 	loopback = lpphy_loopback(dev);
    1228. 

  1228. 	if (loopback == -1)
    1229. 

  1229. 		goto finish;
    1230. 

  1230. 	lpphy_set_rx_gain_by_index(dev, loopback);
    1231. 

  1231. 	b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
    1232. 

  1232. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
    1233. 

  1233. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
    1234. 

  1234. 	b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
    1235. 

  1235. 	for (i = 128; i <= 159; i++) {
    1236. 

  1236. 		b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
    1237. 

  1237. 		inner_sum = 0;
    1238. 

  1238. 		for (j = 5; j <= 25; j++) {
    1239. 

  1239. 			lpphy_run_ddfs(dev, 1, 1, j, j, 0);
    1240. 

  1240. 			if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
    1241. 

  1241. 				goto finish;
    1242. 

  1242. 			mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
    1243. 

  1243. 			if (j == 5)
    1244. 

  1244. 				tmp = mean_sq_pwr;
    1245. 

  1245. 			ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
    1246. 

  1246. 			normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
    1247. 

  1247. 			mean_sq_pwr = ideal_pwr - normal_pwr;
    1248. 

  1248. 			mean_sq_pwr *= mean_sq_pwr;
    1249. 

  1249. 			inner_sum += mean_sq_pwr;
    1250. 

  1250. 			if ((i == 128) || (inner_sum < mean_sq_pwr_min)) {
    1251. 

  1251. 				lpphy->rc_cap = i;
    1252. 

  1252. 				mean_sq_pwr_min = inner_sum;
    1253. 

  1253. 			}
    1254. 

  1254. 		}
    1255. 

  1255. 	}
    1256. 

  1256. 	lpphy_stop_ddfs(dev);
    1257. 

  1257. 

  1258. finish:
    1259. 

  1259. 	lpphy_restore_crs(dev, true);
    1260. 

  1260. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
    1261. 

  1261. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
    1262. 

  1262. 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
    1263. 

  1263. 	b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
    1264. 

  1264. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
    1265. 

  1265. 	b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
    1266. 

  1266. 	b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
    1267. 

  1267. 

  1268. 	lpphy_set_bb_mult(dev, old_bbmult);
    1269. 

  1269. 	if (old_txg_ovr) {
    1270. 

  1270. 		/*
    1271. 

  1271. 		 * SPEC FIXME: The specs say "get_tx_gains" here, which is
    1272. 

  1272. 		 * illogical. According to lwfinger, vendor driver v4.150.10.5
    1273. 

  1273. 		 * has a Set here, while v4.174.64.19 has a Get - regression in
    1274. 

  1274. 		 * the vendor driver? This should be tested this once the code
    1275. 

  1275. 		 * is testable.
    1276. 

  1276. 		 */
    1277. 

  1277. 		lpphy_set_tx_gains(dev, tx_gains);
    1278. 

  1278. 	}
    1279. 

  1279. 	lpphy_set_tx_power_control(dev, old_txpctl);
    1280. 

  1280. 	if (lpphy->rc_cap)
    1281. 

  1281. 		lpphy_set_rc_cap(dev);
    1282. 

  1282. }
    1283. 

  1283. 

  1284. static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
    1285. 

  1285. {
    1286. 

  1286. 	struct ssb_bus *bus = dev->dev->sdev->bus;
    1287. 

  1287. 	u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
    1288. 

  1288. 	u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
    1289. 

  1289. 	int i;
    1290. 

  1290. 

  1291. 	b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
    1292. 

  1292. 	b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
    1293. 

  1293. 	b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
    1294. 

  1294. 	b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
    1295. 

  1295. 	b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
    1296. 

  1296. 	b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
    1297. 

  1297. 	b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
    1298. 

  1298. 	b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
    1299. 

  1299. 	b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
    1300. 

  1300. 

  1301. 	for (i = 0; i < 10000; i++) {
    1302. 

  1302. 		if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
    1303. 

  1303. 			break;
    1304. 

  1304. 		msleep(1);
    1305. 

  1305. 	}
    1306. 

  1306. 

  1307. 	if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
    1308. 

  1308. 		b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
    1309. 

  1309. 

  1310. 	tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
    1311. 

  1311. 

  1312. 	b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
    1313. 

  1313. 	b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
    1314. 

  1314. 	b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
    1315. 

  1315. 	b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
    1316. 

  1316. 	b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
    1317. 

  1317. 

  1318. 	if (crystal_freq == 24000000) {
    1319. 

  1319. 		b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
    1320. 

  1320. 		b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
    1321. 

  1321. 	} else {
    1322. 

  1322. 		b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
    1323. 

  1323. 		b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
    1324. 

  1324. 	}
    1325. 

  1325. 

  1326. 	b43_radio_write(dev, B2063_PA_SP7, 0x7D);
    1327. 

  1327. 

  1328. 	for (i = 0; i < 10000; i++) {
    1329. 

  1329. 		if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
    1330. 

  1330. 			break;
    1331. 

  1331. 		msleep(1);
    1332. 

  1332. 	}
    1333. 

  1333. 

  1334. 	if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
    1335. 

  1335. 		b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
    1336. 

  1336. 

  1337. 	b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
    1338. 

  1338. }
    1339. 

  1339. 

  1340. static void lpphy_calibrate_rc(struct b43_wldev *dev)
    1341. 

  1341. {
    1342. 

  1342. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    1343. 

  1343. 

  1344. 	if (dev->phy.rev >= 2) {
    1345. 

  1345. 		lpphy_rev2plus_rc_calib(dev);
    1346. 

  1346. 	} else if (!lpphy->rc_cap) {
    1347. 

  1347. 		if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
    1348. 

  1348. 			lpphy_rev0_1_rc_calib(dev);
    1349. 

  1349. 	} else {
    1350. 

  1350. 		lpphy_set_rc_cap(dev);
    1351. 

  1351. 	}
    1352. 

  1352. }
    1353. 

  1353. 

  1354. static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
    1355. 

  1355. {
    1356. 

  1356. 	if (dev->phy.rev >= 2)
    1357. 

  1357. 		return; // rev2+ doesn't support antenna diversity
    1358. 

  1358. 

  1359. 	if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
    1360. 

  1360. 		return;
    1361. 

  1361. 

  1362. 	b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
    1363. 

  1363. 

  1364. 	b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
    1365. 

  1365. 	b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
    1366. 

  1366. 

  1367. 	b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
    1368. 

  1368. 

  1369. 	dev->phy.lp->antenna = antenna;
    1370. 

  1370. }
    1371. 

  1371. 

  1372. static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b)
    1373. 

  1373. {
    1374. 

  1374. 	u16 tmp[2];
    1375. 

  1375. 

  1376. 	tmp[0] = a;
    1377. 

  1377. 	tmp[1] = b;
    1378. 

  1378. 	b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp);
    1379. 

  1379. }
    1380. 

  1380. 

  1381. static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
    1382. 

  1382. {
    1383. 

  1383. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    1384. 

  1384. 	struct lpphy_tx_gains gains;
    1385. 

  1385. 	u32 iq_comp, tx_gain, coeff, rf_power;
    1386. 

  1386. 

  1387. 	lpphy->tx_pwr_idx_over = index;
    1388. 

  1388. 	lpphy_read_tx_pctl_mode_from_hardware(dev);
    1389. 

  1389. 	if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
    1390. 

  1390. 		lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
    1391. 

  1391. 	if (dev->phy.rev >= 2) {
    1392. 

  1392. 		iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320));
    1393. 

  1393. 		tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192));
    1394. 

  1394. 		gains.pad = (tx_gain >> 16) & 0xFF;
    1395. 

  1395. 		gains.gm = tx_gain & 0xFF;
    1396. 

  1396. 		gains.pga = (tx_gain >> 8) & 0xFF;
    1397. 

  1397. 		gains.dac = (iq_comp >> 28) & 0xFF;
    1398. 

  1398. 		lpphy_set_tx_gains(dev, gains);
    1399. 

  1399. 	} else {
    1400. 

  1400. 		iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320));
    1401. 

  1401. 		tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192));
    1402. 

  1402. 		b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
    1403. 

  1403. 				0xF800, (tx_gain >> 4) & 0x7FFF);
    1404. 

  1404. 		lpphy_set_dac_gain(dev, tx_gain & 0x7);
    1405. 

  1405. 		lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F);
    1406. 

  1406. 	}
    1407. 

  1407. 	lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF);
    1408. 

  1408. 	lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF);
    1409. 

  1409. 	if (dev->phy.rev >= 2) {
    1410. 

  1410. 		coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448));
    1411. 

  1411. 	} else {
    1412. 

  1412. 		coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448));
    1413. 

  1413. 	}
    1414. 

  1414. 	b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF);
    1415. 

  1415. 	if (dev->phy.rev >= 2) {
    1416. 

  1416. 		rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576));
    1417. 

  1417. 		b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00,
    1418. 

  1418. 				rf_power & 0xFFFF);//SPEC FIXME mask & set != 0
    1419. 

  1419. 	}
    1420. 

  1420. 	lpphy_enable_tx_gain_override(dev);
    1421. 

  1421. }
    1422. 

  1422. 

  1423. static void lpphy_btcoex_override(struct b43_wldev *dev)
    1424. 

  1424. {
    1425. 

  1425. 	b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
    1426. 

  1426. 	b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
    1427. 

  1427. }
    1428. 

  1428. 

  1429. static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
    1430. 

  1430. 					 bool blocked)
    1431. 

  1431. {
    1432. 

  1432. 	//TODO check MAC control register
    1433. 

  1433. 	if (blocked) {
    1434. 

  1434. 		if (dev->phy.rev >= 2) {
    1435. 

  1435. 			b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF);
    1436. 

  1436. 			b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
    1437. 

  1437. 			b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF);
    1438. 

  1438. 			b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF);
    1439. 

  1439. 			b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808);
    1440. 

  1440. 		} else {
    1441. 

  1441. 			b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF);
    1442. 

  1442. 			b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
    1443. 

  1443. 			b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF);
    1444. 

  1444. 			b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018);
    1445. 

  1445. 		}
    1446. 

  1446. 	} else {
    1447. 

  1447. 		b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF);
    1448. 

  1448. 		if (dev->phy.rev >= 2)
    1449. 

  1449. 			b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7);
    1450. 

  1450. 		else
    1451. 

  1451. 			b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7);
    1452. 

  1452. 	}
    1453. 

  1453. }
    1454. 

  1454. 

  1455. /* This was previously called lpphy_japan_filter */
    1456. 

  1456. static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
    1457. 

  1457. {
    1458. 

  1458. 	struct b43_phy_lp *lpphy = dev->phy.lp;
    1459. 

  1459. 	u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
    1460. 

  1460. 

  1461. 	if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
    1462. 

  1462. 		b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
    1463. 

  1463. 		if ((dev->phy.rev == 1) && (lpphy->rc_cap))
    1464. 

  1464. 			lpphy_set_rc_cap(dev);
    1465. 

  1465. 	} else {
    1466. 

  1466. 		b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
    1467. 

  1467. 	}
    1468. 

  1468. }
    1469. 

  1469. 

  1470. sta…
    1471.