PageRenderTime 108ms CodeModel.GetById 17ms app.highlight 79ms RepoModel.GetById 1ms app.codeStats 1ms

/drivers/net/wireless/rt2x00/rt2400pci.c

http://github.com/mirrors/linux
C | 1855 lines | 1277 code | 267 blank | 311 comment | 116 complexity | 88c6c4c71e6ce1bc677dd39fe61786b6 MD5 | raw file

Large files files are truncated, but you can click here to view the full file

   1/*
   2	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3	<http://rt2x00.serialmonkey.com>
   4
   5	This program is free software; you can redistribute it and/or modify
   6	it under the terms of the GNU General Public License as published by
   7	the Free Software Foundation; either version 2 of the License, or
   8	(at your option) any later version.
   9
  10	This program is distributed in the hope that it will be useful,
  11	but WITHOUT ANY WARRANTY; without even the implied warranty of
  12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13	GNU General Public License for more details.
  14
  15	You should have received a copy of the GNU General Public License
  16	along with this program; if not, write to the
  17	Free Software Foundation, Inc.,
  18	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19 */
  20
  21/*
  22	Module: rt2400pci
  23	Abstract: rt2400pci device specific routines.
  24	Supported chipsets: RT2460.
  25 */
  26
  27#include <linux/delay.h>
  28#include <linux/etherdevice.h>
  29#include <linux/init.h>
  30#include <linux/kernel.h>
  31#include <linux/module.h>
  32#include <linux/pci.h>
  33#include <linux/eeprom_93cx6.h>
  34#include <linux/slab.h>
  35
  36#include "rt2x00.h"
  37#include "rt2x00mmio.h"
  38#include "rt2x00pci.h"
  39#include "rt2400pci.h"
  40
  41/*
  42 * Register access.
  43 * All access to the CSR registers will go through the methods
  44 * rt2x00mmio_register_read and rt2x00mmio_register_write.
  45 * BBP and RF register require indirect register access,
  46 * and use the CSR registers BBPCSR and RFCSR to achieve this.
  47 * These indirect registers work with busy bits,
  48 * and we will try maximal REGISTER_BUSY_COUNT times to access
  49 * the register while taking a REGISTER_BUSY_DELAY us delay
  50 * between each attempt. When the busy bit is still set at that time,
  51 * the access attempt is considered to have failed,
  52 * and we will print an error.
  53 */
  54#define WAIT_FOR_BBP(__dev, __reg) \
  55	rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  56#define WAIT_FOR_RF(__dev, __reg) \
  57	rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  58
  59static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  60				const unsigned int word, const u8 value)
  61{
  62	u32 reg;
  63
  64	mutex_lock(&rt2x00dev->csr_mutex);
  65
  66	/*
  67	 * Wait until the BBP becomes available, afterwards we
  68	 * can safely write the new data into the register.
  69	 */
  70	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  71		reg = 0;
  72		rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  73		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  74		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  75		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  76
  77		rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  78	}
  79
  80	mutex_unlock(&rt2x00dev->csr_mutex);
  81}
  82
  83static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  84			       const unsigned int word, u8 *value)
  85{
  86	u32 reg;
  87
  88	mutex_lock(&rt2x00dev->csr_mutex);
  89
  90	/*
  91	 * Wait until the BBP becomes available, afterwards we
  92	 * can safely write the read request into the register.
  93	 * After the data has been written, we wait until hardware
  94	 * returns the correct value, if at any time the register
  95	 * doesn't become available in time, reg will be 0xffffffff
  96	 * which means we return 0xff to the caller.
  97	 */
  98	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99		reg = 0;
 100		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 101		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 102		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 103
 104		rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
 105
 106		WAIT_FOR_BBP(rt2x00dev, &reg);
 107	}
 108
 109	*value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 110
 111	mutex_unlock(&rt2x00dev->csr_mutex);
 112}
 113
 114static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 115			       const unsigned int word, const u32 value)
 116{
 117	u32 reg;
 118
 119	mutex_lock(&rt2x00dev->csr_mutex);
 120
 121	/*
 122	 * Wait until the RF becomes available, afterwards we
 123	 * can safely write the new data into the register.
 124	 */
 125	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 126		reg = 0;
 127		rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 128		rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 129		rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 130		rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 131
 132		rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
 133		rt2x00_rf_write(rt2x00dev, word, value);
 134	}
 135
 136	mutex_unlock(&rt2x00dev->csr_mutex);
 137}
 138
 139static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 140{
 141	struct rt2x00_dev *rt2x00dev = eeprom->data;
 142	u32 reg;
 143
 144	rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
 145
 146	eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 147	eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 148	eeprom->reg_data_clock =
 149	    !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 150	eeprom->reg_chip_select =
 151	    !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 152}
 153
 154static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 155{
 156	struct rt2x00_dev *rt2x00dev = eeprom->data;
 157	u32 reg = 0;
 158
 159	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 160	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 161	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 162			   !!eeprom->reg_data_clock);
 163	rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 164			   !!eeprom->reg_chip_select);
 165
 166	rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
 167}
 168
 169#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 170static const struct rt2x00debug rt2400pci_rt2x00debug = {
 171	.owner	= THIS_MODULE,
 172	.csr	= {
 173		.read		= rt2x00mmio_register_read,
 174		.write		= rt2x00mmio_register_write,
 175		.flags		= RT2X00DEBUGFS_OFFSET,
 176		.word_base	= CSR_REG_BASE,
 177		.word_size	= sizeof(u32),
 178		.word_count	= CSR_REG_SIZE / sizeof(u32),
 179	},
 180	.eeprom	= {
 181		.read		= rt2x00_eeprom_read,
 182		.write		= rt2x00_eeprom_write,
 183		.word_base	= EEPROM_BASE,
 184		.word_size	= sizeof(u16),
 185		.word_count	= EEPROM_SIZE / sizeof(u16),
 186	},
 187	.bbp	= {
 188		.read		= rt2400pci_bbp_read,
 189		.write		= rt2400pci_bbp_write,
 190		.word_base	= BBP_BASE,
 191		.word_size	= sizeof(u8),
 192		.word_count	= BBP_SIZE / sizeof(u8),
 193	},
 194	.rf	= {
 195		.read		= rt2x00_rf_read,
 196		.write		= rt2400pci_rf_write,
 197		.word_base	= RF_BASE,
 198		.word_size	= sizeof(u32),
 199		.word_count	= RF_SIZE / sizeof(u32),
 200	},
 201};
 202#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 203
 204static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 205{
 206	u32 reg;
 207
 208	rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
 209	return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 210}
 211
 212#ifdef CONFIG_RT2X00_LIB_LEDS
 213static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 214				     enum led_brightness brightness)
 215{
 216	struct rt2x00_led *led =
 217	    container_of(led_cdev, struct rt2x00_led, led_dev);
 218	unsigned int enabled = brightness != LED_OFF;
 219	u32 reg;
 220
 221	rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 222
 223	if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 224		rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 225	else if (led->type == LED_TYPE_ACTIVITY)
 226		rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 227
 228	rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 229}
 230
 231static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 232			       unsigned long *delay_on,
 233			       unsigned long *delay_off)
 234{
 235	struct rt2x00_led *led =
 236	    container_of(led_cdev, struct rt2x00_led, led_dev);
 237	u32 reg;
 238
 239	rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 240	rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 241	rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 242	rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 243
 244	return 0;
 245}
 246
 247static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
 248			       struct rt2x00_led *led,
 249			       enum led_type type)
 250{
 251	led->rt2x00dev = rt2x00dev;
 252	led->type = type;
 253	led->led_dev.brightness_set = rt2400pci_brightness_set;
 254	led->led_dev.blink_set = rt2400pci_blink_set;
 255	led->flags = LED_INITIALIZED;
 256}
 257#endif /* CONFIG_RT2X00_LIB_LEDS */
 258
 259/*
 260 * Configuration handlers.
 261 */
 262static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 263				    const unsigned int filter_flags)
 264{
 265	u32 reg;
 266
 267	/*
 268	 * Start configuration steps.
 269	 * Note that the version error will always be dropped
 270	 * since there is no filter for it at this time.
 271	 */
 272	rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 273	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 274			   !(filter_flags & FIF_FCSFAIL));
 275	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 276			   !(filter_flags & FIF_PLCPFAIL));
 277	rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 278			   !(filter_flags & FIF_CONTROL));
 279	rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 280			   !(filter_flags & FIF_PROMISC_IN_BSS));
 281	rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 282			   !(filter_flags & FIF_PROMISC_IN_BSS) &&
 283			   !rt2x00dev->intf_ap_count);
 284	rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 285	rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 286}
 287
 288static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 289				  struct rt2x00_intf *intf,
 290				  struct rt2x00intf_conf *conf,
 291				  const unsigned int flags)
 292{
 293	unsigned int bcn_preload;
 294	u32 reg;
 295
 296	if (flags & CONFIG_UPDATE_TYPE) {
 297		/*
 298		 * Enable beacon config
 299		 */
 300		bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 301		rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
 302		rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 303		rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
 304
 305		/*
 306		 * Enable synchronisation.
 307		 */
 308		rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 309		rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 310		rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 311	}
 312
 313	if (flags & CONFIG_UPDATE_MAC)
 314		rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
 315					       conf->mac, sizeof(conf->mac));
 316
 317	if (flags & CONFIG_UPDATE_BSSID)
 318		rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
 319					       conf->bssid,
 320					       sizeof(conf->bssid));
 321}
 322
 323static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 324				 struct rt2x00lib_erp *erp,
 325				 u32 changed)
 326{
 327	int preamble_mask;
 328	u32 reg;
 329
 330	/*
 331	 * When short preamble is enabled, we should set bit 0x08
 332	 */
 333	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 334		preamble_mask = erp->short_preamble << 3;
 335
 336		rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
 337		rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
 338		rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
 339		rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 340		rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 341		rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
 342
 343		rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
 344		rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 345		rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 346		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 347				   GET_DURATION(ACK_SIZE, 10));
 348		rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
 349
 350		rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
 351		rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 352		rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 353		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 354				   GET_DURATION(ACK_SIZE, 20));
 355		rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
 356
 357		rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
 358		rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 359		rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 360		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 361				   GET_DURATION(ACK_SIZE, 55));
 362		rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
 363
 364		rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
 365		rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 366		rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 367		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 368				   GET_DURATION(ACK_SIZE, 110));
 369		rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
 370	}
 371
 372	if (changed & BSS_CHANGED_BASIC_RATES)
 373		rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 374
 375	if (changed & BSS_CHANGED_ERP_SLOT) {
 376		rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 377		rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 378		rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 379
 380		rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
 381		rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 382		rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 383		rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
 384
 385		rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
 386		rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 387		rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 388		rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
 389	}
 390
 391	if (changed & BSS_CHANGED_BEACON_INT) {
 392		rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
 393		rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 394				   erp->beacon_int * 16);
 395		rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 396				   erp->beacon_int * 16);
 397		rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
 398	}
 399}
 400
 401static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
 402				 struct antenna_setup *ant)
 403{
 404	u8 r1;
 405	u8 r4;
 406
 407	/*
 408	 * We should never come here because rt2x00lib is supposed
 409	 * to catch this and send us the correct antenna explicitely.
 410	 */
 411	BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 412	       ant->tx == ANTENNA_SW_DIVERSITY);
 413
 414	rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 415	rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 416
 417	/*
 418	 * Configure the TX antenna.
 419	 */
 420	switch (ant->tx) {
 421	case ANTENNA_HW_DIVERSITY:
 422		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 423		break;
 424	case ANTENNA_A:
 425		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 426		break;
 427	case ANTENNA_B:
 428	default:
 429		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 430		break;
 431	}
 432
 433	/*
 434	 * Configure the RX antenna.
 435	 */
 436	switch (ant->rx) {
 437	case ANTENNA_HW_DIVERSITY:
 438		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 439		break;
 440	case ANTENNA_A:
 441		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 442		break;
 443	case ANTENNA_B:
 444	default:
 445		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 446		break;
 447	}
 448
 449	rt2400pci_bbp_write(rt2x00dev, 4, r4);
 450	rt2400pci_bbp_write(rt2x00dev, 1, r1);
 451}
 452
 453static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 454				     struct rf_channel *rf)
 455{
 456	/*
 457	 * Switch on tuning bits.
 458	 */
 459	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 460	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 461
 462	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 463	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 464	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 465
 466	/*
 467	 * RF2420 chipset don't need any additional actions.
 468	 */
 469	if (rt2x00_rf(rt2x00dev, RF2420))
 470		return;
 471
 472	/*
 473	 * For the RT2421 chipsets we need to write an invalid
 474	 * reference clock rate to activate auto_tune.
 475	 * After that we set the value back to the correct channel.
 476	 */
 477	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 478	rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 479	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 480
 481	msleep(1);
 482
 483	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 484	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 485	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 486
 487	msleep(1);
 488
 489	/*
 490	 * Switch off tuning bits.
 491	 */
 492	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 493	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 494
 495	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 496	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 497
 498	/*
 499	 * Clear false CRC during channel switch.
 500	 */
 501	rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
 502}
 503
 504static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 505{
 506	rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 507}
 508
 509static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 510					 struct rt2x00lib_conf *libconf)
 511{
 512	u32 reg;
 513
 514	rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 515	rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 516			   libconf->conf->long_frame_max_tx_count);
 517	rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 518			   libconf->conf->short_frame_max_tx_count);
 519	rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 520}
 521
 522static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
 523				struct rt2x00lib_conf *libconf)
 524{
 525	enum dev_state state =
 526	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
 527		STATE_SLEEP : STATE_AWAKE;
 528	u32 reg;
 529
 530	if (state == STATE_SLEEP) {
 531		rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 532		rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 533				   (rt2x00dev->beacon_int - 20) * 16);
 534		rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 535				   libconf->conf->listen_interval - 1);
 536
 537		/* We must first disable autowake before it can be enabled */
 538		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 539		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 540
 541		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 542		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 543	} else {
 544		rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 545		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 546		rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 547	}
 548
 549	rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 550}
 551
 552static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 553			     struct rt2x00lib_conf *libconf,
 554			     const unsigned int flags)
 555{
 556	if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 557		rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 558	if (flags & IEEE80211_CONF_CHANGE_POWER)
 559		rt2400pci_config_txpower(rt2x00dev,
 560					 libconf->conf->power_level);
 561	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 562		rt2400pci_config_retry_limit(rt2x00dev, libconf);
 563	if (flags & IEEE80211_CONF_CHANGE_PS)
 564		rt2400pci_config_ps(rt2x00dev, libconf);
 565}
 566
 567static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 568				const int cw_min, const int cw_max)
 569{
 570	u32 reg;
 571
 572	rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 573	rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 574	rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 575	rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 576}
 577
 578/*
 579 * Link tuning
 580 */
 581static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 582				 struct link_qual *qual)
 583{
 584	u32 reg;
 585	u8 bbp;
 586
 587	/*
 588	 * Update FCS error count from register.
 589	 */
 590	rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
 591	qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 592
 593	/*
 594	 * Update False CCA count from register.
 595	 */
 596	rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 597	qual->false_cca = bbp;
 598}
 599
 600static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 601				     struct link_qual *qual, u8 vgc_level)
 602{
 603	if (qual->vgc_level_reg != vgc_level) {
 604		rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
 605		qual->vgc_level = vgc_level;
 606		qual->vgc_level_reg = vgc_level;
 607	}
 608}
 609
 610static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 611				  struct link_qual *qual)
 612{
 613	rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
 614}
 615
 616static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 617				 struct link_qual *qual, const u32 count)
 618{
 619	/*
 620	 * The link tuner should not run longer then 60 seconds,
 621	 * and should run once every 2 seconds.
 622	 */
 623	if (count > 60 || !(count & 1))
 624		return;
 625
 626	/*
 627	 * Base r13 link tuning on the false cca count.
 628	 */
 629	if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
 630		rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
 631	else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
 632		rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
 633}
 634
 635/*
 636 * Queue handlers.
 637 */
 638static void rt2400pci_start_queue(struct data_queue *queue)
 639{
 640	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 641	u32 reg;
 642
 643	switch (queue->qid) {
 644	case QID_RX:
 645		rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 646		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
 647		rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 648		break;
 649	case QID_BEACON:
 650		rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 651		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 652		rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 653		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
 654		rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 655		break;
 656	default:
 657		break;
 658	}
 659}
 660
 661static void rt2400pci_kick_queue(struct data_queue *queue)
 662{
 663	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 664	u32 reg;
 665
 666	switch (queue->qid) {
 667	case QID_AC_VO:
 668		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 669		rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
 670		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 671		break;
 672	case QID_AC_VI:
 673		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 674		rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
 675		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 676		break;
 677	case QID_ATIM:
 678		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 679		rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
 680		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 681		break;
 682	default:
 683		break;
 684	}
 685}
 686
 687static void rt2400pci_stop_queue(struct data_queue *queue)
 688{
 689	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 690	u32 reg;
 691
 692	switch (queue->qid) {
 693	case QID_AC_VO:
 694	case QID_AC_VI:
 695	case QID_ATIM:
 696		rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 697		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 698		rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 699		break;
 700	case QID_RX:
 701		rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 702		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
 703		rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 704		break;
 705	case QID_BEACON:
 706		rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 707		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 708		rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 709		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 710		rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 711
 712		/*
 713		 * Wait for possibly running tbtt tasklets.
 714		 */
 715		tasklet_kill(&rt2x00dev->tbtt_tasklet);
 716		break;
 717	default:
 718		break;
 719	}
 720}
 721
 722/*
 723 * Initialization functions.
 724 */
 725static bool rt2400pci_get_entry_state(struct queue_entry *entry)
 726{
 727	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 728	u32 word;
 729
 730	if (entry->queue->qid == QID_RX) {
 731		rt2x00_desc_read(entry_priv->desc, 0, &word);
 732
 733		return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 734	} else {
 735		rt2x00_desc_read(entry_priv->desc, 0, &word);
 736
 737		return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 738		        rt2x00_get_field32(word, TXD_W0_VALID));
 739	}
 740}
 741
 742static void rt2400pci_clear_entry(struct queue_entry *entry)
 743{
 744	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 745	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 746	u32 word;
 747
 748	if (entry->queue->qid == QID_RX) {
 749		rt2x00_desc_read(entry_priv->desc, 2, &word);
 750		rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
 751		rt2x00_desc_write(entry_priv->desc, 2, word);
 752
 753		rt2x00_desc_read(entry_priv->desc, 1, &word);
 754		rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 755		rt2x00_desc_write(entry_priv->desc, 1, word);
 756
 757		rt2x00_desc_read(entry_priv->desc, 0, &word);
 758		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 759		rt2x00_desc_write(entry_priv->desc, 0, word);
 760	} else {
 761		rt2x00_desc_read(entry_priv->desc, 0, &word);
 762		rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 763		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 764		rt2x00_desc_write(entry_priv->desc, 0, word);
 765	}
 766}
 767
 768static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 769{
 770	struct queue_entry_priv_mmio *entry_priv;
 771	u32 reg;
 772
 773	/*
 774	 * Initialize registers.
 775	 */
 776	rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
 777	rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 778	rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 779	rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
 780	rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 781	rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
 782
 783	entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 784	rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
 785	rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 786			   entry_priv->desc_dma);
 787	rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
 788
 789	entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 790	rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
 791	rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 792			   entry_priv->desc_dma);
 793	rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
 794
 795	entry_priv = rt2x00dev->atim->entries[0].priv_data;
 796	rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
 797	rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 798			   entry_priv->desc_dma);
 799	rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
 800
 801	entry_priv = rt2x00dev->bcn->entries[0].priv_data;
 802	rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
 803	rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 804			   entry_priv->desc_dma);
 805	rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
 806
 807	rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
 808	rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 809	rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 810	rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
 811
 812	entry_priv = rt2x00dev->rx->entries[0].priv_data;
 813	rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
 814	rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 815			   entry_priv->desc_dma);
 816	rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
 817
 818	return 0;
 819}
 820
 821static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 822{
 823	u32 reg;
 824
 825	rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
 826	rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
 827	rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 828	rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
 829
 830	rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
 831	rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 832	rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 833	rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 834	rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
 835
 836	rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
 837	rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 838			   (rt2x00dev->rx->data_size / 128));
 839	rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
 840
 841	rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 842	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 843	rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 844	rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 845	rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 846	rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 847	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 848	rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 849	rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 850	rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 851
 852	rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000);
 853
 854	rt2x00mmio_register_read(rt2x00dev, ARCSR0, &reg);
 855	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 856	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 857	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 858	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 859	rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg);
 860
 861	rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
 862	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 863	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 864	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 865	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 866	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 867	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 868	rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
 869
 870	rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 871
 872	if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 873		return -EBUSY;
 874
 875	rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223);
 876	rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
 877
 878	rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
 879	rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 880	rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
 881
 882	rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
 883	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 884	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 885	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 886	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 887	rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
 888
 889	rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
 890	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 891	rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 892	rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 893	rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
 894
 895	rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
 896	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 897	rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 898	rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
 899
 900	/*
 901	 * We must clear the FCS and FIFO error count.
 902	 * These registers are cleared on read,
 903	 * so we may pass a useless variable to store the value.
 904	 */
 905	rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
 906	rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
 907
 908	return 0;
 909}
 910
 911static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 912{
 913	unsigned int i;
 914	u8 value;
 915
 916	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 917		rt2400pci_bbp_read(rt2x00dev, 0, &value);
 918		if ((value != 0xff) && (value != 0x00))
 919			return 0;
 920		udelay(REGISTER_BUSY_DELAY);
 921	}
 922
 923	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
 924	return -EACCES;
 925}
 926
 927static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 928{
 929	unsigned int i;
 930	u16 eeprom;
 931	u8 reg_id;
 932	u8 value;
 933
 934	if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 935		return -EACCES;
 936
 937	rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 938	rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 939	rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 940	rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 941	rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 942	rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 943	rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 944	rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 945	rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 946	rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 947	rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 948	rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 949	rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 950	rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 951
 952	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 953		rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 954
 955		if (eeprom != 0xffff && eeprom != 0x0000) {
 956			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 957			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 958			rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 959		}
 960	}
 961
 962	return 0;
 963}
 964
 965/*
 966 * Device state switch handlers.
 967 */
 968static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 969				 enum dev_state state)
 970{
 971	int mask = (state == STATE_RADIO_IRQ_OFF);
 972	u32 reg;
 973	unsigned long flags;
 974
 975	/*
 976	 * When interrupts are being enabled, the interrupt registers
 977	 * should clear the register to assure a clean state.
 978	 */
 979	if (state == STATE_RADIO_IRQ_ON) {
 980		rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
 981		rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
 982	}
 983
 984	/*
 985	 * Only toggle the interrupts bits we are going to use.
 986	 * Non-checked interrupt bits are disabled by default.
 987	 */
 988	spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 989
 990	rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
 991	rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 992	rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 993	rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 994	rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 995	rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 996	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
 997
 998	spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 999
1000	if (state == STATE_RADIO_IRQ_OFF) {
1001		/*
1002		 * Ensure that all tasklets are finished before
1003		 * disabling the interrupts.
1004		 */
1005		tasklet_kill(&rt2x00dev->txstatus_tasklet);
1006		tasklet_kill(&rt2x00dev->rxdone_tasklet);
1007		tasklet_kill(&rt2x00dev->tbtt_tasklet);
1008	}
1009}
1010
1011static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1012{
1013	/*
1014	 * Initialize all registers.
1015	 */
1016	if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1017		     rt2400pci_init_registers(rt2x00dev) ||
1018		     rt2400pci_init_bbp(rt2x00dev)))
1019		return -EIO;
1020
1021	return 0;
1022}
1023
1024static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1025{
1026	/*
1027	 * Disable power
1028	 */
1029	rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1030}
1031
1032static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1033			       enum dev_state state)
1034{
1035	u32 reg, reg2;
1036	unsigned int i;
1037	char put_to_sleep;
1038	char bbp_state;
1039	char rf_state;
1040
1041	put_to_sleep = (state != STATE_AWAKE);
1042
1043	rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
1044	rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1045	rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1046	rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1047	rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1048	rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1049
1050	/*
1051	 * Device is not guaranteed to be in the requested state yet.
1052	 * We must wait until the register indicates that the
1053	 * device has entered the correct state.
1054	 */
1055	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1056		rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
1057		bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1058		rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1059		if (bbp_state == state && rf_state == state)
1060			return 0;
1061		rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1062		msleep(10);
1063	}
1064
1065	return -EBUSY;
1066}
1067
1068static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1069				      enum dev_state state)
1070{
1071	int retval = 0;
1072
1073	switch (state) {
1074	case STATE_RADIO_ON:
1075		retval = rt2400pci_enable_radio(rt2x00dev);
1076		break;
1077	case STATE_RADIO_OFF:
1078		rt2400pci_disable_radio(rt2x00dev);
1079		break;
1080	case STATE_RADIO_IRQ_ON:
1081	case STATE_RADIO_IRQ_OFF:
1082		rt2400pci_toggle_irq(rt2x00dev, state);
1083		break;
1084	case STATE_DEEP_SLEEP:
1085	case STATE_SLEEP:
1086	case STATE_STANDBY:
1087	case STATE_AWAKE:
1088		retval = rt2400pci_set_state(rt2x00dev, state);
1089		break;
1090	default:
1091		retval = -ENOTSUPP;
1092		break;
1093	}
1094
1095	if (unlikely(retval))
1096		rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1097			   state, retval);
1098
1099	return retval;
1100}
1101
1102/*
1103 * TX descriptor initialization
1104 */
1105static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1106				    struct txentry_desc *txdesc)
1107{
1108	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1109	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1110	__le32 *txd = entry_priv->desc;
1111	u32 word;
1112
1113	/*
1114	 * Start writing the descriptor words.
1115	 */
1116	rt2x00_desc_read(txd, 1, &word);
1117	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1118	rt2x00_desc_write(txd, 1, word);
1119
1120	rt2x00_desc_read(txd, 2, &word);
1121	rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1122	rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1123	rt2x00_desc_write(txd, 2, word);
1124
1125	rt2x00_desc_read(txd, 3, &word);
1126	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1127	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1128	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1129	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1130	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1131	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1132	rt2x00_desc_write(txd, 3, word);
1133
1134	rt2x00_desc_read(txd, 4, &word);
1135	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1136			   txdesc->u.plcp.length_low);
1137	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1138	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1139	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1140			   txdesc->u.plcp.length_high);
1141	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1142	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1143	rt2x00_desc_write(txd, 4, word);
1144
1145	/*
1146	 * Writing TXD word 0 must the last to prevent a race condition with
1147	 * the device, whereby the device may take hold of the TXD before we
1148	 * finished updating it.
1149	 */
1150	rt2x00_desc_read(txd, 0, &word);
1151	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1152	rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1153	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1154			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1155	rt2x00_set_field32(&word, TXD_W0_ACK,
1156			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1157	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1158			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1159	rt2x00_set_field32(&word, TXD_W0_RTS,
1160			   test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1161	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1162	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1163			   test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1164	rt2x00_desc_write(txd, 0, word);
1165
1166	/*
1167	 * Register descriptor details in skb frame descriptor.
1168	 */
1169	skbdesc->desc = txd;
1170	skbdesc->desc_len = TXD_DESC_SIZE;
1171}
1172
1173/*
1174 * TX data initialization
1175 */
1176static void rt2400pci_write_beacon(struct queue_entry *entry,
1177				   struct txentry_desc *txdesc)
1178{
1179	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1180	u32 reg;
1181
1182	/*
1183	 * Disable beaconing while we are reloading the beacon data,
1184	 * otherwise we might be sending out invalid data.
1185	 */
1186	rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1187	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1188	rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1189
1190	if (rt2x00queue_map_txskb(entry)) {
1191		rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1192		goto out;
1193	}
1194	/*
1195	 * Enable beaconing again.
1196	 */
1197	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1198	/*
1199	 * Write the TX descriptor for the beacon.
1200	 */
1201	rt2400pci_write_tx_desc(entry, txdesc);
1202
1203	/*
1204	 * Dump beacon to userspace through debugfs.
1205	 */
1206	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1207out:
1208	/*
1209	 * Enable beaconing again.
1210	 */
1211	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1212	rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1213}
1214
1215/*
1216 * RX control handlers
1217 */
1218static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1219				  struct rxdone_entry_desc *rxdesc)
1220{
1221	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1222	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1223	u32 word0;
1224	u32 word2;
1225	u32 word3;
1226	u32 word4;
1227	u64 tsf;
1228	u32 rx_low;
1229	u32 rx_high;
1230
1231	rt2x00_desc_read(entry_priv->desc, 0, &word0);
1232	rt2x00_desc_read(entry_priv->desc, 2, &word2);
1233	rt2x00_desc_read(entry_priv->desc, 3, &word3);
1234	rt2x00_desc_read(entry_priv->desc, 4, &word4);
1235
1236	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1237		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1238	if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1239		rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1240
1241	/*
1242	 * We only get the lower 32bits from the timestamp,
1243	 * to get the full 64bits we must complement it with
1244	 * the timestamp from get_tsf().
1245	 * Note that when a wraparound of the lower 32bits
1246	 * has occurred between the frame arrival and the get_tsf()
1247	 * call, we must decrease the higher 32bits with 1 to get
1248	 * to correct value.
1249	 */
1250	tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1251	rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1252	rx_high = upper_32_bits(tsf);
1253
1254	if ((u32)tsf <= rx_low)
1255		rx_high--;
1256
1257	/*
1258	 * Obtain the status about this packet.
1259	 * The signal is the PLCP value, and needs to be stripped
1260	 * of the preamble bit (0x08).
1261	 */
1262	rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1263	rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1264	rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1265	    entry->queue->rt2x00dev->rssi_offset;
1266	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1267
1268	rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1269	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1270		rxdesc->dev_flags |= RXDONE_MY_BSS;
1271}
1272
1273/*
1274 * Interrupt functions.
1275 */
1276static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1277			     const enum data_queue_qid queue_idx)
1278{
1279	struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1280	struct queue_entry_priv_mmio *entry_priv;
1281	struct queue_entry *entry;
1282	struct txdone_entry_desc txdesc;
1283	u32 word;
1284
1285	while (!rt2x00queue_empty(queue)) {
1286		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1287		entry_priv = entry->priv_data;
1288		rt2x00_desc_read(entry_priv->desc, 0, &word);
1289
1290		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1291		    !rt2x00_get_field32(word, TXD_W0_VALID))
1292			break;
1293
1294		/*
1295		 * Obtain the status about this packet.
1296		 */
1297		txdesc.flags = 0;
1298		switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1299		case 0: /* Success */
1300		case 1: /* Success with retry */
1301			__set_bit(TXDONE_SUCCESS, &txdesc.flags);
1302			break;
1303		case 2: /* Failure, excessive retries */
1304			__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1305			/* Don't break, this is a failed frame! */
1306		default: /* Failure */
1307			__set_bit(TXDONE_FAILURE, &txdesc.flags);
1308		}
1309		txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1310
1311		rt2x00lib_txdone(entry, &txdesc);
1312	}
1313}
1314
1315static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1316					      struct rt2x00_field32 irq_field)
1317{
1318	u32 reg;
1319
1320	/*
1321	 * Enable a single interrupt. The interrupt mask register
1322	 * access needs locking.
1323	 */
1324	spin_lock_irq(&rt2x00dev->irqmask_lock);
1325
1326	rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1327	rt2x00_set_field32(&reg, irq_field, 0);
1328	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1329
1330	spin_unlock_irq(&rt2x00dev->irqmask_lock);
1331}
1332
1333static void rt2400pci_txstatus_tasklet(unsigned long data)
1334{
1335	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1336	u32 reg;
1337
1338	/*
1339	 * Handle all tx queues.
1340	 */
1341	rt2400pci_txdone(rt2x00dev, QID_ATIM);
1342	rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1343	rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1344
1345	/*
1346	 * Enable all TXDONE interrupts again.
1347	 */
1348	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1349		spin_lock_irq(&rt2x00dev->irqmask_lock);
1350
1351		rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1352		rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1353		rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1354		rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1355		rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1356
1357		spin_unlock_irq(&rt2x00dev->irqmask_lock);
1358	}
1359}
1360
1361static void rt2400pci_tbtt_tasklet(unsigned long data)
1362{
1363	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1364	rt2x00lib_beacondone(rt2x00dev);
1365	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1366		rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1367}
1368
1369static void rt2400pci_rxdone_tasklet(unsigned long data)
1370{
1371	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1372	if (rt2x00mmio_rxdone(rt2x00dev))
1373		tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1374	else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1375		rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1376}
1377
1378static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1379{
1380	struct rt2x00_dev *rt2x00dev = dev_instance;
1381	u32 reg, mask;
1382
1383	/*
1384	 * Get the interrupt sources & saved to local variable.
1385	 * Write register value back to clear pending interrupts.
1386	 */
1387	rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1388	rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1389
1390	if (!reg)
1391		return IRQ_NONE;
1392
1393	if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1394		return IRQ_HANDLED;
1395
1396	mask = reg;
1397
1398	/*
1399	 * Schedule tasklets for interrupt handling.
1400	 */
1401	if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1402		tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1403
1404	if (rt2x00_get_field32(reg, CSR7_RXDONE))
1405		tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1406
1407	if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1408	    rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1409	    rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1410		tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1411		/*
1412		 * Mask out all txdone interrupts.
1413		 */
1414		rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1415		rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1416		rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1417	}
1418
1419	/*
1420	 * Disable all interrupts for which a tasklet was scheduled right now,
1421	 * the tasklet will reenable the appropriate interrupts.
1422	 */
1423	spin_lock(&rt2x00dev->irqmask_lock);
1424
1425	rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1426	reg |= mask;
1427	rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1428
1429	spin_unlock(&rt2x00dev->irqmask_lock);
1430
1431
1432
1433	return IRQ_HANDLED;
1434}
1435
1436/*
1437 * Device probe functions.
1438 */
1439static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1440{
1441	struct eeprom_93cx6 eeprom;
1442	u32 reg;
1443	u16 word;
1444	u8 *mac;
1445
1446	rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
1447
1448	eeprom.data = rt2x00dev;
1449	eeprom.register_read = rt2400pci_eepromregister_read;
1450	eeprom.register_write = rt2400pci_eepromregister_write;
1451	eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1452	    PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1453	eeprom.reg_data_in = 0;
1454	eeprom.reg_data_out = 0;
1455	eeprom.reg_data_clock = 0;
1456	eeprom.reg_chip_select = 0;
1457
1458	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1459			       EEPROM_SIZE / sizeof(u16));
1460
1461	/*
1462	 * Start validation of the data that has been read.
1463	 */
1464	mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1465	if (!is_valid_ether_addr(mac)) {
1466		eth_random_addr(mac);
1467		rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
1468	}
1469
1470	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1471	if (word == 0xffff) {
1472		rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n");
1473		return -EINVAL;
1474	}
1475
1476	return 0;
1477}
1478
1479static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1480{
1481	u32 reg;
1482	u16 value;
1483	u16 eeprom;
1484
1485	/*
1486	 * Read EEPROM word for configuration.
1487	 */
1488	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1489
1490	/*
1491	 * Identify RF chipset.
1492	 */
1493	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1494	rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
1495	rt2x00_set_chip(rt2x00dev, RT2460, value,
1496			rt2x00_get_field32(reg, CSR0_REVISION));
1497
1498	if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1499		rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1500		return -ENODEV;
1501	}
1502
1503	/*
1504	 * Identify default antenna configuration.
1505	 */
1506	rt2x00dev->default_ant.tx =
1507	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1508	rt2x00dev->default_ant.rx =
1509	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1510
1511	/*
1512	 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1513	 * I am not 100% sure about this, but the legacy drivers do not
1514	 * indicate antenna swapping in software is required when
1515	 * diversity is enabled.
1516	 */
1517	if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1518		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1519	if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1520		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1521
1522	/*
1523	 * Store led mode, for correct led behaviour.
1524	 */
1525#ifdef CONFIG_RT2X00_LIB_LEDS
1526	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1527
1528	rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1529	if (value == LED_MODE_TXRX_ACTIVITY ||
1530	    value == LED_MODE_DEFAULT ||
1531	    value == LED_MODE_ASUS)
1532		rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1533				   LED_TYPE_ACTIVITY);
1534#endif /* CONFIG_RT2X00_LIB_LEDS */
1535
1536	/*
1537	 * Detect if this device has an hardware controlled radio.
1538	 */
1539	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1540		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1541
1542	/*
1543	 * Check if the BBP tuning should be enabled.
1544	 */
1545	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1546		__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1547
1548	return 0;
1549}
1550
1551/*
1552 * RF value list for RF2420 & RF2421
1553 * Supports: 2.4 GHz
1554 */
1555static const struct rf_channel rf_vals_b[] = {
1556	{ 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1557	{ 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1558	{ 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1559	{ 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1560	{ 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1561	{ 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1562	{ 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1563	{ 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1564	{ 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1565	{ 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1566	{ 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1567	{ 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1568	{ 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1569	{ 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1570};
1571
1572static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1573{
1574	struct hw_mode_spec *spec = &rt2x00dev->spec;
1575	struct channel_info *info;
1576	char *tx_power;
1577	unsigned int i;
1578
1579	/*
1580	 * Initialize all hw fields.
1581	 */
1582	rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1583			       IEEE80211_HW_SIGNAL_DBM |
1584			       IEEE80211_HW_SUPPORTS_PS |
1585			       IEEE80211_HW_PS_NULLFUNC_STACK;
1586
1587	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1588	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1589				rt2x00_eeprom_addr(rt2x00dev,
1590						   EEPROM_MAC_ADDR_0));
1591
1592	/*
1593	 * Initialize hw_mode information.
1594	 */
1595	spec->supported_bands = SUPPORT_BAND_2GHZ;
1596	spec->supported_rates = SUPPORT_RATE_CCK;
1597
1598	spec->num_channels = ARRAY_SIZE(rf_vals_b);
1599	spec->channels = rf_vals_b;
1600
1601	/*
1602	 * Create channel information array
1603	 */
1604	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1605	if (!info)
1606		return -ENOMEM;
1607
1608	spec->channels_info = info;
1609
1610	tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1611	for (i = 0; i < 14; i++) {
1612		info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1613		info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1614	}
1615
1616	return 0;
1617}
1618
1619static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1620{
1621	int retval;
1622	u32 reg;
1623
1624	/*
1625	 * Allocate eeprom data.
1626	 */
1627	retval = rt2400pci_validate_eeprom(rt2x00dev);
1628	if (retval)
1629		return retval;
1630
1631	retval = rt2400pci_init_eeprom(rt2x00dev);
1632	if (retval)
1633		return retval;
1634
1635	/*
1636	 * Enable rfkill polling by setting GPIO direction of the
1637	 * rfkill switch GPIO pin correctly.
1638	 */
1639	rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
1640	rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1641	rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1642
1643	/*
1644	 * Initialize hw specifications.
1645	 */
1646	retval = rt2400pci_probe_hw_mode(rt2x00dev);
1647	if (retval)
1648		return retval;
1649
1650	/*
1651	 * This device requires the atim queue and DMA-mapped skbs.
1652	 */
1653	__set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1654	__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1655	__set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1656
1657	/*
1658	 * Set the rssi offset.
1659	 */
1660	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1661
1662	return 0;
1663}
1664
1665/*
1666 * IEEE80211 stack callback functions.
1667 */
1668static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1669			     struct ieee80211_vif *vif, u16 queue,
1670			     const struct ieee80211_tx_queue_params *params)
1671{
1672	struct rt2x00_dev *rt2x00dev = hw->priv;
1673
1674	/*
1675	 * We don't support variating cw_min and cw_max variables
1676	 * per queue. So by default we only configure the TX queue,
1677	 * and ignore all other configurations.
1678	 */
1679	if (queue != 0)
1680		return -EINVAL;
1681
1682	if (rt2x00mac_conf_tx(hw, vif, queue, params))
1683		return -EINVAL;
1684
1685	/*
1686	 * Write configuration to register.
1687	 */
1688	rt2400pci_config_cw(rt2x00dev,
1689			    rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1690
1691	return 0;
1692}
1693
1694static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1695			     struct ieee80211_vif *vif)
1696{
1697	struct rt2x00_dev *rt2x00dev = hw->priv;
1698	u64 tsf;
1699	u32 reg;
1700
1701	rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
1702	tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1703	rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
1704	tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1705
1706	re

Large files files are truncated, but you can click here to view the full file