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/drivers/net/wireless/zd1211rw/zd_chip.c

http://github.com/mirrors/linux
C | 1561 lines | 1258 code | 221 blank | 82 comment | 125 complexity | 7021063742855d92bf584c3c63f0f95c MD5 | raw file
   1/* ZD1211 USB-WLAN driver for Linux
   2 *
   3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
   4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 */
  20
  21/* This file implements all the hardware specific functions for the ZD1211
  22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
  23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
  24 */
  25
  26#include <linux/kernel.h>
  27#include <linux/errno.h>
  28#include <linux/slab.h>
  29
  30#include "zd_def.h"
  31#include "zd_chip.h"
  32#include "zd_mac.h"
  33#include "zd_rf.h"
  34
  35void zd_chip_init(struct zd_chip *chip,
  36	         struct ieee80211_hw *hw,
  37		 struct usb_interface *intf)
  38{
  39	memset(chip, 0, sizeof(*chip));
  40	mutex_init(&chip->mutex);
  41	zd_usb_init(&chip->usb, hw, intf);
  42	zd_rf_init(&chip->rf);
  43}
  44
  45void zd_chip_clear(struct zd_chip *chip)
  46{
  47	ZD_ASSERT(!mutex_is_locked(&chip->mutex));
  48	zd_usb_clear(&chip->usb);
  49	zd_rf_clear(&chip->rf);
  50	mutex_destroy(&chip->mutex);
  51	ZD_MEMCLEAR(chip, sizeof(*chip));
  52}
  53
  54static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
  55{
  56	u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
  57	return scnprintf(buffer, size, "%02x-%02x-%02x",
  58		         addr[0], addr[1], addr[2]);
  59}
  60
  61/* Prints an identifier line, which will support debugging. */
  62static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
  63{
  64	int i = 0;
  65
  66	i = scnprintf(buffer, size, "zd1211%s chip ",
  67		      zd_chip_is_zd1211b(chip) ? "b" : "");
  68	i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
  69	i += scnprintf(buffer+i, size-i, " ");
  70	i += scnprint_mac_oui(chip, buffer+i, size-i);
  71	i += scnprintf(buffer+i, size-i, " ");
  72	i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
  73	i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
  74		chip->patch_cck_gain ? 'g' : '-',
  75		chip->patch_cr157 ? '7' : '-',
  76		chip->patch_6m_band_edge ? '6' : '-',
  77		chip->new_phy_layout ? 'N' : '-',
  78		chip->al2230s_bit ? 'S' : '-');
  79	return i;
  80}
  81
  82static void print_id(struct zd_chip *chip)
  83{
  84	char buffer[80];
  85
  86	scnprint_id(chip, buffer, sizeof(buffer));
  87	buffer[sizeof(buffer)-1] = 0;
  88	dev_info(zd_chip_dev(chip), "%s\n", buffer);
  89}
  90
  91static zd_addr_t inc_addr(zd_addr_t addr)
  92{
  93	u16 a = (u16)addr;
  94	/* Control registers use byte addressing, but everything else uses word
  95	 * addressing. */
  96	if ((a & 0xf000) == CR_START)
  97		a += 2;
  98	else
  99		a += 1;
 100	return (zd_addr_t)a;
 101}
 102
 103/* Read a variable number of 32-bit values. Parameter count is not allowed to
 104 * exceed USB_MAX_IOREAD32_COUNT.
 105 */
 106int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
 107		 unsigned int count)
 108{
 109	int r;
 110	int i;
 111	zd_addr_t a16[USB_MAX_IOREAD32_COUNT * 2];
 112	u16 v16[USB_MAX_IOREAD32_COUNT * 2];
 113	unsigned int count16;
 114
 115	if (count > USB_MAX_IOREAD32_COUNT)
 116		return -EINVAL;
 117
 118	/* Use stack for values and addresses. */
 119	count16 = 2 * count;
 120	BUG_ON(count16 * sizeof(zd_addr_t) > sizeof(a16));
 121	BUG_ON(count16 * sizeof(u16) > sizeof(v16));
 122
 123	for (i = 0; i < count; i++) {
 124		int j = 2*i;
 125		/* We read the high word always first. */
 126		a16[j] = inc_addr(addr[i]);
 127		a16[j+1] = addr[i];
 128	}
 129
 130	r = zd_ioread16v_locked(chip, v16, a16, count16);
 131	if (r) {
 132		dev_dbg_f(zd_chip_dev(chip),
 133			  "error: zd_ioread16v_locked. Error number %d\n", r);
 134		return r;
 135	}
 136
 137	for (i = 0; i < count; i++) {
 138		int j = 2*i;
 139		values[i] = (v16[j] << 16) | v16[j+1];
 140	}
 141
 142	return 0;
 143}
 144
 145static int _zd_iowrite32v_async_locked(struct zd_chip *chip,
 146				       const struct zd_ioreq32 *ioreqs,
 147				       unsigned int count)
 148{
 149	int i, j, r;
 150	struct zd_ioreq16 ioreqs16[USB_MAX_IOWRITE32_COUNT * 2];
 151	unsigned int count16;
 152
 153	/* Use stack for values and addresses. */
 154
 155	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 156
 157	if (count == 0)
 158		return 0;
 159	if (count > USB_MAX_IOWRITE32_COUNT)
 160		return -EINVAL;
 161
 162	count16 = 2 * count;
 163	BUG_ON(count16 * sizeof(struct zd_ioreq16) > sizeof(ioreqs16));
 164
 165	for (i = 0; i < count; i++) {
 166		j = 2*i;
 167		/* We write the high word always first. */
 168		ioreqs16[j].value   = ioreqs[i].value >> 16;
 169		ioreqs16[j].addr    = inc_addr(ioreqs[i].addr);
 170		ioreqs16[j+1].value = ioreqs[i].value;
 171		ioreqs16[j+1].addr  = ioreqs[i].addr;
 172	}
 173
 174	r = zd_usb_iowrite16v_async(&chip->usb, ioreqs16, count16);
 175#ifdef DEBUG
 176	if (r) {
 177		dev_dbg_f(zd_chip_dev(chip),
 178			  "error %d in zd_usb_write16v\n", r);
 179	}
 180#endif /* DEBUG */
 181	return r;
 182}
 183
 184int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
 185			  unsigned int count)
 186{
 187	int r;
 188
 189	zd_usb_iowrite16v_async_start(&chip->usb);
 190	r = _zd_iowrite32v_async_locked(chip, ioreqs, count);
 191	if (r) {
 192		zd_usb_iowrite16v_async_end(&chip->usb, 0);
 193		return r;
 194	}
 195	return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
 196}
 197
 198int zd_iowrite16a_locked(struct zd_chip *chip,
 199                  const struct zd_ioreq16 *ioreqs, unsigned int count)
 200{
 201	int r;
 202	unsigned int i, j, t, max;
 203
 204	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 205	zd_usb_iowrite16v_async_start(&chip->usb);
 206
 207	for (i = 0; i < count; i += j + t) {
 208		t = 0;
 209		max = count-i;
 210		if (max > USB_MAX_IOWRITE16_COUNT)
 211			max = USB_MAX_IOWRITE16_COUNT;
 212		for (j = 0; j < max; j++) {
 213			if (!ioreqs[i+j].addr) {
 214				t = 1;
 215				break;
 216			}
 217		}
 218
 219		r = zd_usb_iowrite16v_async(&chip->usb, &ioreqs[i], j);
 220		if (r) {
 221			zd_usb_iowrite16v_async_end(&chip->usb, 0);
 222			dev_dbg_f(zd_chip_dev(chip),
 223				  "error zd_usb_iowrite16v. Error number %d\n",
 224				  r);
 225			return r;
 226		}
 227	}
 228
 229	return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
 230}
 231
 232/* Writes a variable number of 32 bit registers. The functions will split
 233 * that in several USB requests. A split can be forced by inserting an IO
 234 * request with an zero address field.
 235 */
 236int zd_iowrite32a_locked(struct zd_chip *chip,
 237	          const struct zd_ioreq32 *ioreqs, unsigned int count)
 238{
 239	int r;
 240	unsigned int i, j, t, max;
 241
 242	zd_usb_iowrite16v_async_start(&chip->usb);
 243
 244	for (i = 0; i < count; i += j + t) {
 245		t = 0;
 246		max = count-i;
 247		if (max > USB_MAX_IOWRITE32_COUNT)
 248			max = USB_MAX_IOWRITE32_COUNT;
 249		for (j = 0; j < max; j++) {
 250			if (!ioreqs[i+j].addr) {
 251				t = 1;
 252				break;
 253			}
 254		}
 255
 256		r = _zd_iowrite32v_async_locked(chip, &ioreqs[i], j);
 257		if (r) {
 258			zd_usb_iowrite16v_async_end(&chip->usb, 0);
 259			dev_dbg_f(zd_chip_dev(chip),
 260				"error _zd_iowrite32v_locked."
 261				" Error number %d\n", r);
 262			return r;
 263		}
 264	}
 265
 266	return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
 267}
 268
 269int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
 270{
 271	int r;
 272
 273	mutex_lock(&chip->mutex);
 274	r = zd_ioread16_locked(chip, value, addr);
 275	mutex_unlock(&chip->mutex);
 276	return r;
 277}
 278
 279int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
 280{
 281	int r;
 282
 283	mutex_lock(&chip->mutex);
 284	r = zd_ioread32_locked(chip, value, addr);
 285	mutex_unlock(&chip->mutex);
 286	return r;
 287}
 288
 289int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
 290{
 291	int r;
 292
 293	mutex_lock(&chip->mutex);
 294	r = zd_iowrite16_locked(chip, value, addr);
 295	mutex_unlock(&chip->mutex);
 296	return r;
 297}
 298
 299int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
 300{
 301	int r;
 302
 303	mutex_lock(&chip->mutex);
 304	r = zd_iowrite32_locked(chip, value, addr);
 305	mutex_unlock(&chip->mutex);
 306	return r;
 307}
 308
 309int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
 310	          u32 *values, unsigned int count)
 311{
 312	int r;
 313
 314	mutex_lock(&chip->mutex);
 315	r = zd_ioread32v_locked(chip, values, addresses, count);
 316	mutex_unlock(&chip->mutex);
 317	return r;
 318}
 319
 320int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
 321	          unsigned int count)
 322{
 323	int r;
 324
 325	mutex_lock(&chip->mutex);
 326	r = zd_iowrite32a_locked(chip, ioreqs, count);
 327	mutex_unlock(&chip->mutex);
 328	return r;
 329}
 330
 331static int read_pod(struct zd_chip *chip, u8 *rf_type)
 332{
 333	int r;
 334	u32 value;
 335
 336	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 337	r = zd_ioread32_locked(chip, &value, E2P_POD);
 338	if (r)
 339		goto error;
 340	dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
 341
 342	/* FIXME: AL2230 handling (Bit 7 in POD) */
 343	*rf_type = value & 0x0f;
 344	chip->pa_type = (value >> 16) & 0x0f;
 345	chip->patch_cck_gain = (value >> 8) & 0x1;
 346	chip->patch_cr157 = (value >> 13) & 0x1;
 347	chip->patch_6m_band_edge = (value >> 21) & 0x1;
 348	chip->new_phy_layout = (value >> 31) & 0x1;
 349	chip->al2230s_bit = (value >> 7) & 0x1;
 350	chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
 351	chip->supports_tx_led = 1;
 352	if (value & (1 << 24)) { /* LED scenario */
 353		if (value & (1 << 29))
 354			chip->supports_tx_led = 0;
 355	}
 356
 357	dev_dbg_f(zd_chip_dev(chip),
 358		"RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
 359		"patch 6M %d new PHY %d link LED%d tx led %d\n",
 360		zd_rf_name(*rf_type), *rf_type,
 361		chip->pa_type, chip->patch_cck_gain,
 362		chip->patch_cr157, chip->patch_6m_band_edge,
 363		chip->new_phy_layout,
 364		chip->link_led == LED1 ? 1 : 2,
 365		chip->supports_tx_led);
 366	return 0;
 367error:
 368	*rf_type = 0;
 369	chip->pa_type = 0;
 370	chip->patch_cck_gain = 0;
 371	chip->patch_cr157 = 0;
 372	chip->patch_6m_band_edge = 0;
 373	chip->new_phy_layout = 0;
 374	return r;
 375}
 376
 377static int zd_write_mac_addr_common(struct zd_chip *chip, const u8 *mac_addr,
 378				    const struct zd_ioreq32 *in_reqs,
 379				    const char *type)
 380{
 381	int r;
 382	struct zd_ioreq32 reqs[2] = {in_reqs[0], in_reqs[1]};
 383
 384	if (mac_addr) {
 385		reqs[0].value = (mac_addr[3] << 24)
 386			      | (mac_addr[2] << 16)
 387			      | (mac_addr[1] <<  8)
 388			      |  mac_addr[0];
 389		reqs[1].value = (mac_addr[5] <<  8)
 390			      |  mac_addr[4];
 391		dev_dbg_f(zd_chip_dev(chip), "%s addr %pM\n", type, mac_addr);
 392	} else {
 393		dev_dbg_f(zd_chip_dev(chip), "set NULL %s\n", type);
 394	}
 395
 396	mutex_lock(&chip->mutex);
 397	r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
 398	mutex_unlock(&chip->mutex);
 399	return r;
 400}
 401
 402/* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
 403 *              CR_MAC_ADDR_P2 must be overwritten
 404 */
 405int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
 406{
 407	static const struct zd_ioreq32 reqs[2] = {
 408		[0] = { .addr = CR_MAC_ADDR_P1 },
 409		[1] = { .addr = CR_MAC_ADDR_P2 },
 410	};
 411
 412	return zd_write_mac_addr_common(chip, mac_addr, reqs, "mac");
 413}
 414
 415int zd_write_bssid(struct zd_chip *chip, const u8 *bssid)
 416{
 417	static const struct zd_ioreq32 reqs[2] = {
 418		[0] = { .addr = CR_BSSID_P1 },
 419		[1] = { .addr = CR_BSSID_P2 },
 420	};
 421
 422	return zd_write_mac_addr_common(chip, bssid, reqs, "bssid");
 423}
 424
 425int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
 426{
 427	int r;
 428	u32 value;
 429
 430	mutex_lock(&chip->mutex);
 431	r = zd_ioread32_locked(chip, &value, E2P_SUBID);
 432	mutex_unlock(&chip->mutex);
 433	if (r)
 434		return r;
 435
 436	*regdomain = value >> 16;
 437	dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
 438
 439	return 0;
 440}
 441
 442static int read_values(struct zd_chip *chip, u8 *values, size_t count,
 443	               zd_addr_t e2p_addr, u32 guard)
 444{
 445	int r;
 446	int i;
 447	u32 v;
 448
 449	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 450	for (i = 0;;) {
 451		r = zd_ioread32_locked(chip, &v,
 452			               (zd_addr_t)((u16)e2p_addr+i/2));
 453		if (r)
 454			return r;
 455		v -= guard;
 456		if (i+4 < count) {
 457			values[i++] = v;
 458			values[i++] = v >>  8;
 459			values[i++] = v >> 16;
 460			values[i++] = v >> 24;
 461			continue;
 462		}
 463		for (;i < count; i++)
 464			values[i] = v >> (8*(i%3));
 465		return 0;
 466	}
 467}
 468
 469static int read_pwr_cal_values(struct zd_chip *chip)
 470{
 471	return read_values(chip, chip->pwr_cal_values,
 472		        E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
 473			0);
 474}
 475
 476static int read_pwr_int_values(struct zd_chip *chip)
 477{
 478	return read_values(chip, chip->pwr_int_values,
 479		        E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
 480			E2P_PWR_INT_GUARD);
 481}
 482
 483static int read_ofdm_cal_values(struct zd_chip *chip)
 484{
 485	int r;
 486	int i;
 487	static const zd_addr_t addresses[] = {
 488		E2P_36M_CAL_VALUE1,
 489		E2P_48M_CAL_VALUE1,
 490		E2P_54M_CAL_VALUE1,
 491	};
 492
 493	for (i = 0; i < 3; i++) {
 494		r = read_values(chip, chip->ofdm_cal_values[i],
 495				E2P_CHANNEL_COUNT, addresses[i], 0);
 496		if (r)
 497			return r;
 498	}
 499	return 0;
 500}
 501
 502static int read_cal_int_tables(struct zd_chip *chip)
 503{
 504	int r;
 505
 506	r = read_pwr_cal_values(chip);
 507	if (r)
 508		return r;
 509	r = read_pwr_int_values(chip);
 510	if (r)
 511		return r;
 512	r = read_ofdm_cal_values(chip);
 513	if (r)
 514		return r;
 515	return 0;
 516}
 517
 518/* phy means physical registers */
 519int zd_chip_lock_phy_regs(struct zd_chip *chip)
 520{
 521	int r;
 522	u32 tmp;
 523
 524	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 525	r = zd_ioread32_locked(chip, &tmp, CR_REG1);
 526	if (r) {
 527		dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
 528		return r;
 529	}
 530
 531	tmp &= ~UNLOCK_PHY_REGS;
 532
 533	r = zd_iowrite32_locked(chip, tmp, CR_REG1);
 534	if (r)
 535		dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
 536	return r;
 537}
 538
 539int zd_chip_unlock_phy_regs(struct zd_chip *chip)
 540{
 541	int r;
 542	u32 tmp;
 543
 544	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 545	r = zd_ioread32_locked(chip, &tmp, CR_REG1);
 546	if (r) {
 547		dev_err(zd_chip_dev(chip),
 548			"error ioread32(CR_REG1): %d\n", r);
 549		return r;
 550	}
 551
 552	tmp |= UNLOCK_PHY_REGS;
 553
 554	r = zd_iowrite32_locked(chip, tmp, CR_REG1);
 555	if (r)
 556		dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
 557	return r;
 558}
 559
 560/* ZD_CR157 can be optionally patched by the EEPROM for original ZD1211 */
 561static int patch_cr157(struct zd_chip *chip)
 562{
 563	int r;
 564	u16 value;
 565
 566	if (!chip->patch_cr157)
 567		return 0;
 568
 569	r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
 570	if (r)
 571		return r;
 572
 573	dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
 574	return zd_iowrite32_locked(chip, value >> 8, ZD_CR157);
 575}
 576
 577/*
 578 * 6M band edge can be optionally overwritten for certain RF's
 579 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
 580 * bit (for AL2230, AL2230S)
 581 */
 582static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
 583{
 584	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 585	if (!chip->patch_6m_band_edge)
 586		return 0;
 587
 588	return zd_rf_patch_6m_band_edge(&chip->rf, channel);
 589}
 590
 591/* Generic implementation of 6M band edge patching, used by most RFs via
 592 * zd_rf_generic_patch_6m() */
 593int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
 594{
 595	struct zd_ioreq16 ioreqs[] = {
 596		{ ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
 597		{ ZD_CR47,  0x1e },
 598	};
 599
 600	/* FIXME: Channel 11 is not the edge for all regulatory domains. */
 601	if (channel == 1 || channel == 11)
 602		ioreqs[0].value = 0x12;
 603
 604	dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
 605	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 606}
 607
 608static int zd1211_hw_reset_phy(struct zd_chip *chip)
 609{
 610	static const struct zd_ioreq16 ioreqs[] = {
 611		{ ZD_CR0,   0x0a }, { ZD_CR1,   0x06 }, { ZD_CR2,   0x26 },
 612		{ ZD_CR3,   0x38 }, { ZD_CR4,   0x80 }, { ZD_CR9,   0xa0 },
 613		{ ZD_CR10,  0x81 }, { ZD_CR11,  0x00 }, { ZD_CR12,  0x7f },
 614		{ ZD_CR13,  0x8c }, { ZD_CR14,  0x80 }, { ZD_CR15,  0x3d },
 615		{ ZD_CR16,  0x20 }, { ZD_CR17,  0x1e }, { ZD_CR18,  0x0a },
 616		{ ZD_CR19,  0x48 }, { ZD_CR20,  0x0c }, { ZD_CR21,  0x0c },
 617		{ ZD_CR22,  0x23 }, { ZD_CR23,  0x90 }, { ZD_CR24,  0x14 },
 618		{ ZD_CR25,  0x40 }, { ZD_CR26,  0x10 }, { ZD_CR27,  0x19 },
 619		{ ZD_CR28,  0x7f }, { ZD_CR29,  0x80 }, { ZD_CR30,  0x4b },
 620		{ ZD_CR31,  0x60 }, { ZD_CR32,  0x43 }, { ZD_CR33,  0x08 },
 621		{ ZD_CR34,  0x06 }, { ZD_CR35,  0x0a }, { ZD_CR36,  0x00 },
 622		{ ZD_CR37,  0x00 }, { ZD_CR38,  0x38 }, { ZD_CR39,  0x0c },
 623		{ ZD_CR40,  0x84 }, { ZD_CR41,  0x2a }, { ZD_CR42,  0x80 },
 624		{ ZD_CR43,  0x10 }, { ZD_CR44,  0x12 }, { ZD_CR46,  0xff },
 625		{ ZD_CR47,  0x1E }, { ZD_CR48,  0x26 }, { ZD_CR49,  0x5b },
 626		{ ZD_CR64,  0xd0 }, { ZD_CR65,  0x04 }, { ZD_CR66,  0x58 },
 627		{ ZD_CR67,  0xc9 }, { ZD_CR68,  0x88 }, { ZD_CR69,  0x41 },
 628		{ ZD_CR70,  0x23 }, { ZD_CR71,  0x10 }, { ZD_CR72,  0xff },
 629		{ ZD_CR73,  0x32 }, { ZD_CR74,  0x30 }, { ZD_CR75,  0x65 },
 630		{ ZD_CR76,  0x41 }, { ZD_CR77,  0x1b }, { ZD_CR78,  0x30 },
 631		{ ZD_CR79,  0x68 }, { ZD_CR80,  0x64 }, { ZD_CR81,  0x64 },
 632		{ ZD_CR82,  0x00 }, { ZD_CR83,  0x00 }, { ZD_CR84,  0x00 },
 633		{ ZD_CR85,  0x02 }, { ZD_CR86,  0x00 }, { ZD_CR87,  0x00 },
 634		{ ZD_CR88,  0xff }, { ZD_CR89,  0xfc }, { ZD_CR90,  0x00 },
 635		{ ZD_CR91,  0x00 }, { ZD_CR92,  0x00 }, { ZD_CR93,  0x08 },
 636		{ ZD_CR94,  0x00 }, { ZD_CR95,  0x00 }, { ZD_CR96,  0xff },
 637		{ ZD_CR97,  0xe7 }, { ZD_CR98,  0x00 }, { ZD_CR99,  0x00 },
 638		{ ZD_CR100, 0x00 }, { ZD_CR101, 0xae }, { ZD_CR102, 0x02 },
 639		{ ZD_CR103, 0x00 }, { ZD_CR104, 0x03 }, { ZD_CR105, 0x65 },
 640		{ ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, { ZD_CR108, 0x0a },
 641		{ ZD_CR109, 0xaa }, { ZD_CR110, 0xaa }, { ZD_CR111, 0x25 },
 642		{ ZD_CR112, 0x25 }, { ZD_CR113, 0x00 }, { ZD_CR119, 0x1e },
 643		{ ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
 644		{ },
 645		{ ZD_CR5,   0x00 }, { ZD_CR6,   0x00 }, { ZD_CR7,   0x00 },
 646		{ ZD_CR8,   0x00 }, { ZD_CR9,   0x20 }, { ZD_CR12,  0xf0 },
 647		{ ZD_CR20,  0x0e }, { ZD_CR21,  0x0e }, { ZD_CR27,  0x10 },
 648		{ ZD_CR44,  0x33 }, { ZD_CR47,  0x1E }, { ZD_CR83,  0x24 },
 649		{ ZD_CR84,  0x04 }, { ZD_CR85,  0x00 }, { ZD_CR86,  0x0C },
 650		{ ZD_CR87,  0x12 }, { ZD_CR88,  0x0C }, { ZD_CR89,  0x00 },
 651		{ ZD_CR90,  0x10 }, { ZD_CR91,  0x08 }, { ZD_CR93,  0x00 },
 652		{ ZD_CR94,  0x01 }, { ZD_CR95,  0x00 }, { ZD_CR96,  0x50 },
 653		{ ZD_CR97,  0x37 }, { ZD_CR98,  0x35 }, { ZD_CR101, 0x13 },
 654		{ ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
 655		{ ZD_CR105, 0x12 }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
 656		{ ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
 657		{ ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
 658		{ ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR120, 0x4f },
 659		{ ZD_CR125, 0xaa }, { ZD_CR127, 0x03 }, { ZD_CR128, 0x14 },
 660		{ ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, { ZD_CR131, 0x0C },
 661		{ ZD_CR136, 0xdf }, { ZD_CR137, 0x40 }, { ZD_CR138, 0xa0 },
 662		{ ZD_CR139, 0xb0 }, { ZD_CR140, 0x99 }, { ZD_CR141, 0x82 },
 663		{ ZD_CR142, 0x54 }, { ZD_CR143, 0x1c }, { ZD_CR144, 0x6c },
 664		{ ZD_CR147, 0x07 }, { ZD_CR148, 0x4c }, { ZD_CR149, 0x50 },
 665		{ ZD_CR150, 0x0e }, { ZD_CR151, 0x18 }, { ZD_CR160, 0xfe },
 666		{ ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
 667		{ ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
 668		{ ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
 669		{ ZD_CR170, 0xba }, { ZD_CR171, 0xba },
 670		/* Note: ZD_CR204 must lead the ZD_CR203 */
 671		{ ZD_CR204, 0x7d },
 672		{ },
 673		{ ZD_CR203, 0x30 },
 674	};
 675
 676	int r, t;
 677
 678	dev_dbg_f(zd_chip_dev(chip), "\n");
 679
 680	r = zd_chip_lock_phy_regs(chip);
 681	if (r)
 682		goto out;
 683
 684	r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 685	if (r)
 686		goto unlock;
 687
 688	r = patch_cr157(chip);
 689unlock:
 690	t = zd_chip_unlock_phy_regs(chip);
 691	if (t && !r)
 692		r = t;
 693out:
 694	return r;
 695}
 696
 697static int zd1211b_hw_reset_phy(struct zd_chip *chip)
 698{
 699	static const struct zd_ioreq16 ioreqs[] = {
 700		{ ZD_CR0,   0x14 }, { ZD_CR1,   0x06 }, { ZD_CR2,   0x26 },
 701		{ ZD_CR3,   0x38 }, { ZD_CR4,   0x80 }, { ZD_CR9,   0xe0 },
 702		{ ZD_CR10,  0x81 },
 703		/* power control { { ZD_CR11,  1 << 6 }, */
 704		{ ZD_CR11,  0x00 },
 705		{ ZD_CR12,  0xf0 }, { ZD_CR13,  0x8c }, { ZD_CR14,  0x80 },
 706		{ ZD_CR15,  0x3d }, { ZD_CR16,  0x20 }, { ZD_CR17,  0x1e },
 707		{ ZD_CR18,  0x0a }, { ZD_CR19,  0x48 },
 708		{ ZD_CR20,  0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
 709		{ ZD_CR21,  0x0e }, { ZD_CR22,  0x23 }, { ZD_CR23,  0x90 },
 710		{ ZD_CR24,  0x14 }, { ZD_CR25,  0x40 }, { ZD_CR26,  0x10 },
 711		{ ZD_CR27,  0x10 }, { ZD_CR28,  0x7f }, { ZD_CR29,  0x80 },
 712		{ ZD_CR30,  0x4b }, /* ASIC/FWT, no jointly decoder */
 713		{ ZD_CR31,  0x60 }, { ZD_CR32,  0x43 }, { ZD_CR33,  0x08 },
 714		{ ZD_CR34,  0x06 }, { ZD_CR35,  0x0a }, { ZD_CR36,  0x00 },
 715		{ ZD_CR37,  0x00 }, { ZD_CR38,  0x38 }, { ZD_CR39,  0x0c },
 716		{ ZD_CR40,  0x84 }, { ZD_CR41,  0x2a }, { ZD_CR42,  0x80 },
 717		{ ZD_CR43,  0x10 }, { ZD_CR44,  0x33 }, { ZD_CR46,  0xff },
 718		{ ZD_CR47,  0x1E }, { ZD_CR48,  0x26 }, { ZD_CR49,  0x5b },
 719		{ ZD_CR64,  0xd0 }, { ZD_CR65,  0x04 }, { ZD_CR66,  0x58 },
 720		{ ZD_CR67,  0xc9 }, { ZD_CR68,  0x88 }, { ZD_CR69,  0x41 },
 721		{ ZD_CR70,  0x23 }, { ZD_CR71,  0x10 }, { ZD_CR72,  0xff },
 722		{ ZD_CR73,  0x32 }, { ZD_CR74,  0x30 }, { ZD_CR75,  0x65 },
 723		{ ZD_CR76,  0x41 }, { ZD_CR77,  0x1b }, { ZD_CR78,  0x30 },
 724		{ ZD_CR79,  0xf0 }, { ZD_CR80,  0x64 }, { ZD_CR81,  0x64 },
 725		{ ZD_CR82,  0x00 }, { ZD_CR83,  0x24 }, { ZD_CR84,  0x04 },
 726		{ ZD_CR85,  0x00 }, { ZD_CR86,  0x0c }, { ZD_CR87,  0x12 },
 727		{ ZD_CR88,  0x0c }, { ZD_CR89,  0x00 }, { ZD_CR90,  0x58 },
 728		{ ZD_CR91,  0x04 }, { ZD_CR92,  0x00 }, { ZD_CR93,  0x00 },
 729		{ ZD_CR94,  0x01 },
 730		{ ZD_CR95,  0x20 }, /* ZD1211B */
 731		{ ZD_CR96,  0x50 }, { ZD_CR97,  0x37 }, { ZD_CR98,  0x35 },
 732		{ ZD_CR99,  0x00 }, { ZD_CR100, 0x01 }, { ZD_CR101, 0x13 },
 733		{ ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
 734		{ ZD_CR105, 0x12 }, { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 },
 735		{ ZD_CR108, 0x0a }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
 736		{ ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
 737		{ ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
 738		{ ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x1e },
 739		{ ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
 740		{ ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
 741		{ ZD_CR131, 0x0c }, { ZD_CR136, 0xdf }, { ZD_CR137, 0xa0 },
 742		{ ZD_CR138, 0xa8 }, { ZD_CR139, 0xb4 }, { ZD_CR140, 0x98 },
 743		{ ZD_CR141, 0x82 }, { ZD_CR142, 0x53 }, { ZD_CR143, 0x1c },
 744		{ ZD_CR144, 0x6c }, { ZD_CR147, 0x07 }, { ZD_CR148, 0x40 },
 745		{ ZD_CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
 746		{ ZD_CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
 747		{ ZD_CR151, 0x18 }, { ZD_CR159, 0x70 }, { ZD_CR160, 0xfe },
 748		{ ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
 749		{ ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
 750		{ ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
 751		{ ZD_CR170, 0xba }, { ZD_CR171, 0xba },
 752		/* Note: ZD_CR204 must lead the ZD_CR203 */
 753		{ ZD_CR204, 0x7d },
 754		{},
 755		{ ZD_CR203, 0x30 },
 756	};
 757
 758	int r, t;
 759
 760	dev_dbg_f(zd_chip_dev(chip), "\n");
 761
 762	r = zd_chip_lock_phy_regs(chip);
 763	if (r)
 764		goto out;
 765
 766	r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 767	t = zd_chip_unlock_phy_regs(chip);
 768	if (t && !r)
 769		r = t;
 770out:
 771	return r;
 772}
 773
 774static int hw_reset_phy(struct zd_chip *chip)
 775{
 776	return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
 777		                  zd1211_hw_reset_phy(chip);
 778}
 779
 780static int zd1211_hw_init_hmac(struct zd_chip *chip)
 781{
 782	static const struct zd_ioreq32 ioreqs[] = {
 783		{ CR_ZD1211_RETRY_MAX,		ZD1211_RETRY_COUNT },
 784		{ CR_RX_THRESHOLD,		0x000c0640 },
 785	};
 786
 787	dev_dbg_f(zd_chip_dev(chip), "\n");
 788	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 789	return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 790}
 791
 792static int zd1211b_hw_init_hmac(struct zd_chip *chip)
 793{
 794	static const struct zd_ioreq32 ioreqs[] = {
 795		{ CR_ZD1211B_RETRY_MAX,		ZD1211B_RETRY_COUNT },
 796		{ CR_ZD1211B_CWIN_MAX_MIN_AC0,	0x007f003f },
 797		{ CR_ZD1211B_CWIN_MAX_MIN_AC1,	0x007f003f },
 798		{ CR_ZD1211B_CWIN_MAX_MIN_AC2,  0x003f001f },
 799		{ CR_ZD1211B_CWIN_MAX_MIN_AC3,  0x001f000f },
 800		{ CR_ZD1211B_AIFS_CTL1,		0x00280028 },
 801		{ CR_ZD1211B_AIFS_CTL2,		0x008C003C },
 802		{ CR_ZD1211B_TXOP,		0x01800824 },
 803		{ CR_RX_THRESHOLD,		0x000c0eff, },
 804	};
 805
 806	dev_dbg_f(zd_chip_dev(chip), "\n");
 807	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 808	return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 809}
 810
 811static int hw_init_hmac(struct zd_chip *chip)
 812{
 813	int r;
 814	static const struct zd_ioreq32 ioreqs[] = {
 815		{ CR_ACK_TIMEOUT_EXT,		0x20 },
 816		{ CR_ADDA_MBIAS_WARMTIME,	0x30000808 },
 817		{ CR_SNIFFER_ON,		0 },
 818		{ CR_RX_FILTER,			STA_RX_FILTER },
 819		{ CR_GROUP_HASH_P1,		0x00 },
 820		{ CR_GROUP_HASH_P2,		0x80000000 },
 821		{ CR_REG1,			0xa4 },
 822		{ CR_ADDA_PWR_DWN,		0x7f },
 823		{ CR_BCN_PLCP_CFG,		0x00f00401 },
 824		{ CR_PHY_DELAY,			0x00 },
 825		{ CR_ACK_TIMEOUT_EXT,		0x80 },
 826		{ CR_ADDA_PWR_DWN,		0x00 },
 827		{ CR_ACK_TIME_80211,		0x100 },
 828		{ CR_RX_PE_DELAY,		0x70 },
 829		{ CR_PS_CTRL,			0x10000000 },
 830		{ CR_RTS_CTS_RATE,		0x02030203 },
 831		{ CR_AFTER_PNP,			0x1 },
 832		{ CR_WEP_PROTECT,		0x114 },
 833		{ CR_IFS_VALUE,			IFS_VALUE_DEFAULT },
 834		{ CR_CAM_MODE,			MODE_AP_WDS},
 835	};
 836
 837	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 838	r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 839	if (r)
 840		return r;
 841
 842	return zd_chip_is_zd1211b(chip) ?
 843		zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
 844}
 845
 846struct aw_pt_bi {
 847	u32 atim_wnd_period;
 848	u32 pre_tbtt;
 849	u32 beacon_interval;
 850};
 851
 852static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
 853{
 854	int r;
 855	static const zd_addr_t aw_pt_bi_addr[] =
 856		{ CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
 857	u32 values[3];
 858
 859	r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
 860		         ARRAY_SIZE(aw_pt_bi_addr));
 861	if (r) {
 862		memset(s, 0, sizeof(*s));
 863		return r;
 864	}
 865
 866	s->atim_wnd_period = values[0];
 867	s->pre_tbtt = values[1];
 868	s->beacon_interval = values[2];
 869	return 0;
 870}
 871
 872static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
 873{
 874	struct zd_ioreq32 reqs[3];
 875	u16 b_interval = s->beacon_interval & 0xffff;
 876
 877	if (b_interval <= 5)
 878		b_interval = 5;
 879	if (s->pre_tbtt < 4 || s->pre_tbtt >= b_interval)
 880		s->pre_tbtt = b_interval - 1;
 881	if (s->atim_wnd_period >= s->pre_tbtt)
 882		s->atim_wnd_period = s->pre_tbtt - 1;
 883
 884	reqs[0].addr = CR_ATIM_WND_PERIOD;
 885	reqs[0].value = s->atim_wnd_period;
 886	reqs[1].addr = CR_PRE_TBTT;
 887	reqs[1].value = s->pre_tbtt;
 888	reqs[2].addr = CR_BCN_INTERVAL;
 889	reqs[2].value = (s->beacon_interval & ~0xffff) | b_interval;
 890
 891	return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
 892}
 893
 894
 895static int set_beacon_interval(struct zd_chip *chip, u16 interval,
 896			       u8 dtim_period, int type)
 897{
 898	int r;
 899	struct aw_pt_bi s;
 900	u32 b_interval, mode_flag;
 901
 902	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 903
 904	if (interval > 0) {
 905		switch (type) {
 906		case NL80211_IFTYPE_ADHOC:
 907		case NL80211_IFTYPE_MESH_POINT:
 908			mode_flag = BCN_MODE_IBSS;
 909			break;
 910		case NL80211_IFTYPE_AP:
 911			mode_flag = BCN_MODE_AP;
 912			break;
 913		default:
 914			mode_flag = 0;
 915			break;
 916		}
 917	} else {
 918		dtim_period = 0;
 919		mode_flag = 0;
 920	}
 921
 922	b_interval = mode_flag | (dtim_period << 16) | interval;
 923
 924	r = zd_iowrite32_locked(chip, b_interval, CR_BCN_INTERVAL);
 925	if (r)
 926		return r;
 927	r = get_aw_pt_bi(chip, &s);
 928	if (r)
 929		return r;
 930	return set_aw_pt_bi(chip, &s);
 931}
 932
 933int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period,
 934			   int type)
 935{
 936	int r;
 937
 938	mutex_lock(&chip->mutex);
 939	r = set_beacon_interval(chip, interval, dtim_period, type);
 940	mutex_unlock(&chip->mutex);
 941	return r;
 942}
 943
 944static int hw_init(struct zd_chip *chip)
 945{
 946	int r;
 947
 948	dev_dbg_f(zd_chip_dev(chip), "\n");
 949	ZD_ASSERT(mutex_is_locked(&chip->mutex));
 950	r = hw_reset_phy(chip);
 951	if (r)
 952		return r;
 953
 954	r = hw_init_hmac(chip);
 955	if (r)
 956		return r;
 957
 958	return set_beacon_interval(chip, 100, 0, NL80211_IFTYPE_UNSPECIFIED);
 959}
 960
 961static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
 962{
 963	return (zd_addr_t)((u16)chip->fw_regs_base + offset);
 964}
 965
 966#ifdef DEBUG
 967static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
 968	           const char *addr_string)
 969{
 970	int r;
 971	u32 value;
 972
 973	r = zd_ioread32_locked(chip, &value, addr);
 974	if (r) {
 975		dev_dbg_f(zd_chip_dev(chip),
 976			"error reading %s. Error number %d\n", addr_string, r);
 977		return r;
 978	}
 979
 980	dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
 981		addr_string, (unsigned int)value);
 982	return 0;
 983}
 984
 985static int test_init(struct zd_chip *chip)
 986{
 987	int r;
 988
 989	r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
 990	if (r)
 991		return r;
 992	r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
 993	if (r)
 994		return r;
 995	return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
 996}
 997
 998static void dump_fw_registers(struct zd_chip *chip)
 999{
1000	const zd_addr_t addr[4] = {
1001		fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
1002		fw_reg_addr(chip, FW_REG_USB_SPEED),
1003		fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
1004		fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1005	};
1006
1007	int r;
1008	u16 values[4];
1009
1010	r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1011		         ARRAY_SIZE(addr));
1012	if (r) {
1013		dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1014			 r);
1015		return;
1016	}
1017
1018	dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1019	dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1020	dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1021	dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1022}
1023#endif /* DEBUG */
1024
1025static int print_fw_version(struct zd_chip *chip)
1026{
1027	struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy;
1028	int r;
1029	u16 version;
1030
1031	r = zd_ioread16_locked(chip, &version,
1032		fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
1033	if (r)
1034		return r;
1035
1036	dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1037
1038	snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
1039			"%04hx", version);
1040
1041	return 0;
1042}
1043
1044static int set_mandatory_rates(struct zd_chip *chip, int gmode)
1045{
1046	u32 rates;
1047	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1048	/* This sets the mandatory rates, which only depend from the standard
1049	 * that the device is supporting. Until further notice we should try
1050	 * to support 802.11g also for full speed USB.
1051	 */
1052	if (!gmode)
1053		rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1054	else
1055		rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1056			CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1057
1058	return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1059}
1060
1061int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1062				    int preamble)
1063{
1064	u32 value = 0;
1065
1066	dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1067	value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1068	value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1069
1070	/* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1071	value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1072	value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1073	value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1074	value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1075
1076	return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1077}
1078
1079int zd_chip_enable_hwint(struct zd_chip *chip)
1080{
1081	int r;
1082
1083	mutex_lock(&chip->mutex);
1084	r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1085	mutex_unlock(&chip->mutex);
1086	return r;
1087}
1088
1089static int disable_hwint(struct zd_chip *chip)
1090{
1091	return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1092}
1093
1094int zd_chip_disable_hwint(struct zd_chip *chip)
1095{
1096	int r;
1097
1098	mutex_lock(&chip->mutex);
1099	r = disable_hwint(chip);
1100	mutex_unlock(&chip->mutex);
1101	return r;
1102}
1103
1104static int read_fw_regs_offset(struct zd_chip *chip)
1105{
1106	int r;
1107
1108	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1109	r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1110		               FWRAW_REGS_ADDR);
1111	if (r)
1112		return r;
1113	dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1114		  (u16)chip->fw_regs_base);
1115
1116	return 0;
1117}
1118
1119/* Read mac address using pre-firmware interface */
1120int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1121{
1122	dev_dbg_f(zd_chip_dev(chip), "\n");
1123	return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1124		ETH_ALEN);
1125}
1126
1127int zd_chip_init_hw(struct zd_chip *chip)
1128{
1129	int r;
1130	u8 rf_type;
1131
1132	dev_dbg_f(zd_chip_dev(chip), "\n");
1133
1134	mutex_lock(&chip->mutex);
1135
1136#ifdef DEBUG
1137	r = test_init(chip);
1138	if (r)
1139		goto out;
1140#endif
1141	r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1142	if (r)
1143		goto out;
1144
1145	r = read_fw_regs_offset(chip);
1146	if (r)
1147		goto out;
1148
1149	/* GPI is always disabled, also in the other driver.
1150	 */
1151	r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1152	if (r)
1153		goto out;
1154	r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1155	if (r)
1156		goto out;
1157	/* Currently we support IEEE 802.11g for full and high speed USB.
1158	 * It might be discussed, whether we should support pure b mode for
1159	 * full speed USB.
1160	 */
1161	r = set_mandatory_rates(chip, 1);
1162	if (r)
1163		goto out;
1164	/* Disabling interrupts is certainly a smart thing here.
1165	 */
1166	r = disable_hwint(chip);
1167	if (r)
1168		goto out;
1169	r = read_pod(chip, &rf_type);
1170	if (r)
1171		goto out;
1172	r = hw_init(chip);
1173	if (r)
1174		goto out;
1175	r = zd_rf_init_hw(&chip->rf, rf_type);
1176	if (r)
1177		goto out;
1178
1179	r = print_fw_version(chip);
1180	if (r)
1181		goto out;
1182
1183#ifdef DEBUG
1184	dump_fw_registers(chip);
1185	r = test_init(chip);
1186	if (r)
1187		goto out;
1188#endif /* DEBUG */
1189
1190	r = read_cal_int_tables(chip);
1191	if (r)
1192		goto out;
1193
1194	print_id(chip);
1195out:
1196	mutex_unlock(&chip->mutex);
1197	return r;
1198}
1199
1200static int update_pwr_int(struct zd_chip *chip, u8 channel)
1201{
1202	u8 value = chip->pwr_int_values[channel - 1];
1203	return zd_iowrite16_locked(chip, value, ZD_CR31);
1204}
1205
1206static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1207{
1208	u8 value = chip->pwr_cal_values[channel-1];
1209	return zd_iowrite16_locked(chip, value, ZD_CR68);
1210}
1211
1212static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1213{
1214	struct zd_ioreq16 ioreqs[3];
1215
1216	ioreqs[0].addr = ZD_CR67;
1217	ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1218	ioreqs[1].addr = ZD_CR66;
1219	ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1220	ioreqs[2].addr = ZD_CR65;
1221	ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1222
1223	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1224}
1225
1226static int update_channel_integration_and_calibration(struct zd_chip *chip,
1227	                                              u8 channel)
1228{
1229	int r;
1230
1231	if (!zd_rf_should_update_pwr_int(&chip->rf))
1232		return 0;
1233
1234	r = update_pwr_int(chip, channel);
1235	if (r)
1236		return r;
1237	if (zd_chip_is_zd1211b(chip)) {
1238		static const struct zd_ioreq16 ioreqs[] = {
1239			{ ZD_CR69, 0x28 },
1240			{},
1241			{ ZD_CR69, 0x2a },
1242		};
1243
1244		r = update_ofdm_cal(chip, channel);
1245		if (r)
1246			return r;
1247		r = update_pwr_cal(chip, channel);
1248		if (r)
1249			return r;
1250		r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1251		if (r)
1252			return r;
1253	}
1254
1255	return 0;
1256}
1257
1258/* The CCK baseband gain can be optionally patched by the EEPROM */
1259static int patch_cck_gain(struct zd_chip *chip)
1260{
1261	int r;
1262	u32 value;
1263
1264	if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1265		return 0;
1266
1267	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1268	r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1269	if (r)
1270		return r;
1271	dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1272	return zd_iowrite16_locked(chip, value & 0xff, ZD_CR47);
1273}
1274
1275int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1276{
1277	int r, t;
1278
1279	mutex_lock(&chip->mutex);
1280	r = zd_chip_lock_phy_regs(chip);
1281	if (r)
1282		goto out;
1283	r = zd_rf_set_channel(&chip->rf, channel);
1284	if (r)
1285		goto unlock;
1286	r = update_channel_integration_and_calibration(chip, channel);
1287	if (r)
1288		goto unlock;
1289	r = patch_cck_gain(chip);
1290	if (r)
1291		goto unlock;
1292	r = patch_6m_band_edge(chip, channel);
1293	if (r)
1294		goto unlock;
1295	r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1296unlock:
1297	t = zd_chip_unlock_phy_regs(chip);
1298	if (t && !r)
1299		r = t;
1300out:
1301	mutex_unlock(&chip->mutex);
1302	return r;
1303}
1304
1305u8 zd_chip_get_channel(struct zd_chip *chip)
1306{
1307	u8 channel;
1308
1309	mutex_lock(&chip->mutex);
1310	channel = chip->rf.channel;
1311	mutex_unlock(&chip->mutex);
1312	return channel;
1313}
1314
1315int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1316{
1317	const zd_addr_t a[] = {
1318		fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1319		CR_LED,
1320	};
1321
1322	int r;
1323	u16 v[ARRAY_SIZE(a)];
1324	struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1325		[0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1326		[1] = { CR_LED },
1327	};
1328	u16 other_led;
1329
1330	mutex_lock(&chip->mutex);
1331	r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1332	if (r)
1333		goto out;
1334
1335	other_led = chip->link_led == LED1 ? LED2 : LED1;
1336
1337	switch (status) {
1338	case ZD_LED_OFF:
1339		ioreqs[0].value = FW_LINK_OFF;
1340		ioreqs[1].value = v[1] & ~(LED1|LED2);
1341		break;
1342	case ZD_LED_SCANNING:
1343		ioreqs[0].value = FW_LINK_OFF;
1344		ioreqs[1].value = v[1] & ~other_led;
1345		if (get_seconds() % 3 == 0) {
1346			ioreqs[1].value &= ~chip->link_led;
1347		} else {
1348			ioreqs[1].value |= chip->link_led;
1349		}
1350		break;
1351	case ZD_LED_ASSOCIATED:
1352		ioreqs[0].value = FW_LINK_TX;
1353		ioreqs[1].value = v[1] & ~other_led;
1354		ioreqs[1].value |= chip->link_led;
1355		break;
1356	default:
1357		r = -EINVAL;
1358		goto out;
1359	}
1360
1361	if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1362		r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1363		if (r)
1364			goto out;
1365	}
1366	r = 0;
1367out:
1368	mutex_unlock(&chip->mutex);
1369	return r;
1370}
1371
1372int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1373{
1374	int r;
1375
1376	if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1377		return -EINVAL;
1378
1379	mutex_lock(&chip->mutex);
1380	r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1381	mutex_unlock(&chip->mutex);
1382	return r;
1383}
1384
1385static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1386{
1387	return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1388}
1389
1390/**
1391 * zd_rx_rate - report zd-rate
1392 * @rx_frame - received frame
1393 * @rx_status - rx_status as given by the device
1394 *
1395 * This function converts the rate as encoded in the received packet to the
1396 * zd-rate, we are using on other places in the driver.
1397 */
1398u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1399{
1400	u8 zd_rate;
1401	if (status->frame_status & ZD_RX_OFDM) {
1402		zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1403	} else {
1404		switch (zd_cck_plcp_header_signal(rx_frame)) {
1405		case ZD_CCK_PLCP_SIGNAL_1M:
1406			zd_rate = ZD_CCK_RATE_1M;
1407			break;
1408		case ZD_CCK_PLCP_SIGNAL_2M:
1409			zd_rate = ZD_CCK_RATE_2M;
1410			break;
1411		case ZD_CCK_PLCP_SIGNAL_5M5:
1412			zd_rate = ZD_CCK_RATE_5_5M;
1413			break;
1414		case ZD_CCK_PLCP_SIGNAL_11M:
1415			zd_rate = ZD_CCK_RATE_11M;
1416			break;
1417		default:
1418			zd_rate = 0;
1419		}
1420	}
1421
1422	return zd_rate;
1423}
1424
1425int zd_chip_switch_radio_on(struct zd_chip *chip)
1426{
1427	int r;
1428
1429	mutex_lock(&chip->mutex);
1430	r = zd_switch_radio_on(&chip->rf);
1431	mutex_unlock(&chip->mutex);
1432	return r;
1433}
1434
1435int zd_chip_switch_radio_off(struct zd_chip *chip)
1436{
1437	int r;
1438
1439	mutex_lock(&chip->mutex);
1440	r = zd_switch_radio_off(&chip->rf);
1441	mutex_unlock(&chip->mutex);
1442	return r;
1443}
1444
1445int zd_chip_enable_int(struct zd_chip *chip)
1446{
1447	int r;
1448
1449	mutex_lock(&chip->mutex);
1450	r = zd_usb_enable_int(&chip->usb);
1451	mutex_unlock(&chip->mutex);
1452	return r;
1453}
1454
1455void zd_chip_disable_int(struct zd_chip *chip)
1456{
1457	mutex_lock(&chip->mutex);
1458	zd_usb_disable_int(&chip->usb);
1459	mutex_unlock(&chip->mutex);
1460
1461	/* cancel pending interrupt work */
1462	cancel_work_sync(&zd_chip_to_mac(chip)->process_intr);
1463}
1464
1465int zd_chip_enable_rxtx(struct zd_chip *chip)
1466{
1467	int r;
1468
1469	mutex_lock(&chip->mutex);
1470	zd_usb_enable_tx(&chip->usb);
1471	r = zd_usb_enable_rx(&chip->usb);
1472	zd_tx_watchdog_enable(&chip->usb);
1473	mutex_unlock(&chip->mutex);
1474	return r;
1475}
1476
1477void zd_chip_disable_rxtx(struct zd_chip *chip)
1478{
1479	mutex_lock(&chip->mutex);
1480	zd_tx_watchdog_disable(&chip->usb);
1481	zd_usb_disable_rx(&chip->usb);
1482	zd_usb_disable_tx(&chip->usb);
1483	mutex_unlock(&chip->mutex);
1484}
1485
1486int zd_rfwritev_locked(struct zd_chip *chip,
1487	               const u32* values, unsigned int count, u8 bits)
1488{
1489	int r;
1490	unsigned int i;
1491
1492	for (i = 0; i < count; i++) {
1493		r = zd_rfwrite_locked(chip, values[i], bits);
1494		if (r)
1495			return r;
1496	}
1497
1498	return 0;
1499}
1500
1501/*
1502 * We can optionally program the RF directly through CR regs, if supported by
1503 * the hardware. This is much faster than the older method.
1504 */
1505int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1506{
1507	const struct zd_ioreq16 ioreqs[] = {
1508		{ ZD_CR244, (value >> 16) & 0xff },
1509		{ ZD_CR243, (value >>  8) & 0xff },
1510		{ ZD_CR242,  value        & 0xff },
1511	};
1512	ZD_ASSERT(mutex_is_locked(&chip->mutex));
1513	return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1514}
1515
1516int zd_rfwritev_cr_locked(struct zd_chip *chip,
1517	                  const u32 *values, unsigned int count)
1518{
1519	int r;
1520	unsigned int i;
1521
1522	for (i = 0; i < count; i++) {
1523		r = zd_rfwrite_cr_locked(chip, values[i]);
1524		if (r)
1525			return r;
1526	}
1527
1528	return 0;
1529}
1530
1531int zd_chip_set_multicast_hash(struct zd_chip *chip,
1532	                       struct zd_mc_hash *hash)
1533{
1534	const struct zd_ioreq32 ioreqs[] = {
1535		{ CR_GROUP_HASH_P1, hash->low },
1536		{ CR_GROUP_HASH_P2, hash->high },
1537	};
1538
1539	return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1540}
1541
1542u64 zd_chip_get_tsf(struct zd_chip *chip)
1543{
1544	int r;
1545	static const zd_addr_t aw_pt_bi_addr[] =
1546		{ CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1547	u32 values[2];
1548	u64 tsf;
1549
1550	mutex_lock(&chip->mutex);
1551	r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1552	                        ARRAY_SIZE(aw_pt_bi_addr));
1553	mutex_unlock(&chip->mutex);
1554	if (r)
1555		return 0;
1556
1557	tsf = values[1];
1558	tsf = (tsf << 32) | values[0];
1559
1560	return tsf;
1561}