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/drivers/net/wireless/ath/ath6kl/target.h

http://github.com/mirrors/linux
C Header | 356 lines | 181 code | 70 blank | 105 comment | 2 complexity | ebc1caff52fd207cf287efd33d2f8b55 MD5 | raw file
  1/*
  2 * Copyright (c) 2004-2010 Atheros Communications Inc.
  3 * Copyright (c) 2011 Qualcomm Atheros, Inc.
  4 *
  5 * Permission to use, copy, modify, and/or distribute this software for any
  6 * purpose with or without fee is hereby granted, provided that the above
  7 * copyright notice and this permission notice appear in all copies.
  8 *
  9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 16 */
 17
 18#ifndef TARGET_H
 19#define TARGET_H
 20
 21#define AR6003_BOARD_DATA_SZ		1024
 22#define AR6003_BOARD_EXT_DATA_SZ	768
 23#define AR6003_BOARD_EXT_DATA_SZ_V2	1024
 24
 25#define AR6004_BOARD_DATA_SZ     6144
 26#define AR6004_BOARD_EXT_DATA_SZ 0
 27
 28#define RESET_CONTROL_ADDRESS		0x00004000
 29#define RESET_CONTROL_COLD_RST		0x00000100
 30#define RESET_CONTROL_MBOX_RST		0x00000004
 31
 32#define CPU_CLOCK_STANDARD_S		0
 33#define CPU_CLOCK_STANDARD		0x00000003
 34#define CPU_CLOCK_ADDRESS		0x00000020
 35
 36#define CLOCK_CONTROL_ADDRESS		0x00000028
 37#define CLOCK_CONTROL_LF_CLK32_S	2
 38#define CLOCK_CONTROL_LF_CLK32		0x00000004
 39
 40#define SYSTEM_SLEEP_ADDRESS		0x000000c4
 41#define SYSTEM_SLEEP_DISABLE_S		0
 42#define SYSTEM_SLEEP_DISABLE		0x00000001
 43
 44#define LPO_CAL_ADDRESS			0x000000e0
 45#define LPO_CAL_ENABLE_S		20
 46#define LPO_CAL_ENABLE			0x00100000
 47
 48#define GPIO_PIN9_ADDRESS		0x0000004c
 49#define GPIO_PIN10_ADDRESS		0x00000050
 50#define GPIO_PIN11_ADDRESS		0x00000054
 51#define GPIO_PIN12_ADDRESS		0x00000058
 52#define GPIO_PIN13_ADDRESS		0x0000005c
 53
 54#define HOST_INT_STATUS_ADDRESS		0x00000400
 55#define HOST_INT_STATUS_ERROR_S		7
 56#define HOST_INT_STATUS_ERROR		0x00000080
 57
 58#define HOST_INT_STATUS_CPU_S		6
 59#define HOST_INT_STATUS_CPU		0x00000040
 60
 61#define HOST_INT_STATUS_COUNTER_S	4
 62#define HOST_INT_STATUS_COUNTER		0x00000010
 63
 64#define CPU_INT_STATUS_ADDRESS		0x00000401
 65
 66#define ERROR_INT_STATUS_ADDRESS	0x00000402
 67#define ERROR_INT_STATUS_WAKEUP_S	2
 68#define ERROR_INT_STATUS_WAKEUP		0x00000004
 69
 70#define ERROR_INT_STATUS_RX_UNDERFLOW_S	1
 71#define ERROR_INT_STATUS_RX_UNDERFLOW	0x00000002
 72
 73#define ERROR_INT_STATUS_TX_OVERFLOW_S	0
 74#define ERROR_INT_STATUS_TX_OVERFLOW	0x00000001
 75
 76#define COUNTER_INT_STATUS_ADDRESS	0x00000403
 77#define COUNTER_INT_STATUS_COUNTER_S	0
 78#define COUNTER_INT_STATUS_COUNTER	0x000000ff
 79
 80#define RX_LOOKAHEAD_VALID_ADDRESS	0x00000405
 81
 82#define INT_STATUS_ENABLE_ADDRESS	0x00000418
 83#define INT_STATUS_ENABLE_ERROR_S	7
 84#define INT_STATUS_ENABLE_ERROR		0x00000080
 85
 86#define INT_STATUS_ENABLE_CPU_S		6
 87#define INT_STATUS_ENABLE_CPU		0x00000040
 88
 89#define INT_STATUS_ENABLE_INT_S		5
 90#define INT_STATUS_ENABLE_INT		0x00000020
 91#define INT_STATUS_ENABLE_COUNTER_S	4
 92#define INT_STATUS_ENABLE_COUNTER	0x00000010
 93
 94#define INT_STATUS_ENABLE_MBOX_DATA_S	0
 95#define INT_STATUS_ENABLE_MBOX_DATA	0x0000000f
 96
 97#define CPU_INT_STATUS_ENABLE_ADDRESS	0x00000419
 98#define CPU_INT_STATUS_ENABLE_BIT_S	0
 99#define CPU_INT_STATUS_ENABLE_BIT	0x000000ff
100
101#define ERROR_STATUS_ENABLE_ADDRESS		0x0000041a
102#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S	1
103#define ERROR_STATUS_ENABLE_RX_UNDERFLOW	0x00000002
104
105#define ERROR_STATUS_ENABLE_TX_OVERFLOW_S	0
106#define ERROR_STATUS_ENABLE_TX_OVERFLOW		0x00000001
107
108#define COUNTER_INT_STATUS_ENABLE_ADDRESS	0x0000041b
109#define COUNTER_INT_STATUS_ENABLE_BIT_S		0
110#define COUNTER_INT_STATUS_ENABLE_BIT		0x000000ff
111
112#define COUNT_ADDRESS			0x00000420
113
114#define COUNT_DEC_ADDRESS		0x00000440
115
116#define WINDOW_DATA_ADDRESS		0x00000474
117#define WINDOW_WRITE_ADDR_ADDRESS	0x00000478
118#define WINDOW_READ_ADDR_ADDRESS	0x0000047c
119#define CPU_DBG_SEL_ADDRESS		0x00000483
120#define CPU_DBG_ADDRESS			0x00000484
121
122#define LOCAL_SCRATCH_ADDRESS		0x000000c0
123#define ATH6KL_OPTION_SLEEP_DISABLE	0x08
124
125#define RTC_BASE_ADDRESS		0x00004000
126#define GPIO_BASE_ADDRESS		0x00014000
127#define MBOX_BASE_ADDRESS		0x00018000
128#define ANALOG_INTF_BASE_ADDRESS	0x0001c000
129
130/* real name of the register is unknown */
131#define ATH6KL_ANALOG_PLL_REGISTER	(ANALOG_INTF_BASE_ADDRESS + 0x284)
132
133#define SM(f, v)	(((v) << f##_S) & f)
134#define MS(f, v)	(((v) & f) >> f##_S)
135
136/*
137 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
138 * host_interest structure.
139 *
140 * Host Interest is shared between Host and Target in order to coordinate
141 * between the two, and is intended to remain constant (with additions only
142 * at the end).
143 */
144#define ATH6KL_AR6003_HI_START_ADDR           0x00540600
145#define ATH6KL_AR6004_HI_START_ADDR           0x00400800
146
147/*
148 * These are items that the Host may need to access
149 * via BMI or via the Diagnostic Window. The position
150 * of items in this structure must remain constant.
151 * across firmware revisions!
152 *
153 * Types for each item must be fixed size across target and host platforms.
154 * The structure is used only to calculate offset for each register with
155 * HI_ITEM() macro, no values are stored to it.
156 *
157 * More items may be added at the end.
158 */
159struct host_interest {
160	/*
161	 * Pointer to application-defined area, if any.
162	 * Set by Target application during startup.
163	 */
164	u32 hi_app_host_interest;                      /* 0x00 */
165
166	/* Pointer to register dump area, valid after Target crash. */
167	u32 hi_failure_state;                          /* 0x04 */
168
169	/* Pointer to debug logging header */
170	u32 hi_dbglog_hdr;                             /* 0x08 */
171
172	u32 hi_unused1;                       /* 0x0c */
173
174	/*
175	 * General-purpose flag bits, similar to ATH6KL_OPTION_* flags.
176	 * Can be used by application rather than by OS.
177	 */
178	u32 hi_option_flag;                            /* 0x10 */
179
180	/*
181	 * Boolean that determines whether or not to
182	 * display messages on the serial port.
183	 */
184	u32 hi_serial_enable;                          /* 0x14 */
185
186	/* Start address of DataSet index, if any */
187	u32 hi_dset_list_head;                         /* 0x18 */
188
189	/* Override Target application start address */
190	u32 hi_app_start;                              /* 0x1c */
191
192	/* Clock and voltage tuning */
193	u32 hi_skip_clock_init;                        /* 0x20 */
194	u32 hi_core_clock_setting;                     /* 0x24 */
195	u32 hi_cpu_clock_setting;                      /* 0x28 */
196	u32 hi_system_sleep_setting;                   /* 0x2c */
197	u32 hi_xtal_control_setting;                   /* 0x30 */
198	u32 hi_pll_ctrl_setting_24ghz;                 /* 0x34 */
199	u32 hi_pll_ctrl_setting_5ghz;                  /* 0x38 */
200	u32 hi_ref_voltage_trim_setting;               /* 0x3c */
201	u32 hi_clock_info;                             /* 0x40 */
202
203	/*
204	 * Flash configuration overrides, used only
205	 * when firmware is not executing from flash.
206	 * (When using flash, modify the global variables
207	 * with equivalent names.)
208	 */
209	u32 hi_bank0_addr_value;                       /* 0x44 */
210	u32 hi_bank0_read_value;                       /* 0x48 */
211	u32 hi_bank0_write_value;                      /* 0x4c */
212	u32 hi_bank0_config_value;                     /* 0x50 */
213
214	/* Pointer to Board Data  */
215	u32 hi_board_data;                             /* 0x54 */
216	u32 hi_board_data_initialized;                 /* 0x58 */
217
218	u32 hi_dset_ram_index_tbl;                     /* 0x5c */
219
220	u32 hi_desired_baud_rate;                      /* 0x60 */
221	u32 hi_dbglog_config;                          /* 0x64 */
222	u32 hi_end_ram_reserve_sz;                     /* 0x68 */
223	u32 hi_mbox_io_block_sz;                       /* 0x6c */
224
225	u32 hi_num_bpatch_streams;                     /* 0x70 -- unused */
226	u32 hi_mbox_isr_yield_limit;                   /* 0x74 */
227
228	u32 hi_refclk_hz;                              /* 0x78 */
229	u32 hi_ext_clk_detected;                       /* 0x7c */
230	u32 hi_dbg_uart_txpin;                         /* 0x80 */
231	u32 hi_dbg_uart_rxpin;                         /* 0x84 */
232	u32 hi_hci_uart_baud;                          /* 0x88 */
233	u32 hi_hci_uart_pin_assignments;               /* 0x8C */
234	/*
235	 * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts
236	 * pin
237	 */
238	u32 hi_hci_uart_baud_scale_val;                /* 0x90 */
239	u32 hi_hci_uart_baud_step_val;                 /* 0x94 */
240
241	u32 hi_allocram_start;                         /* 0x98 */
242	u32 hi_allocram_sz;                            /* 0x9c */
243	u32 hi_hci_bridge_flags;                       /* 0xa0 */
244	u32 hi_hci_uart_support_pins;                  /* 0xa4 */
245	/*
246	 * NOTE: byte [0] = RESET pin (bit 7 is polarity),
247	 * bytes[1]..bytes[3] are for future use
248	 */
249	u32 hi_hci_uart_pwr_mgmt_params;               /* 0xa8 */
250	/*
251	 * 0xa8   - [1]: 0 = UART FC active low, 1 = UART FC active high
252	 *      [31:16]: wakeup timeout in ms
253	 */
254
255	/* Pointer to extended board data */
256	u32 hi_board_ext_data;                /* 0xac */
257	u32 hi_board_ext_data_config;         /* 0xb0 */
258
259	/*
260	 * Bit [0]  :   valid
261	 * Bit[31:16:   size
262	 */
263	/*
264	 * hi_reset_flag is used to do some stuff when target reset.
265	 * such as restore app_start after warm reset or
266	 * preserve host Interest area, or preserve ROM data, literals etc.
267	 */
268	u32 hi_reset_flag;                            /* 0xb4 */
269	/* indicate hi_reset_flag is valid */
270	u32 hi_reset_flag_valid;                      /* 0xb8 */
271	u32 hi_hci_uart_pwr_mgmt_params_ext;           /* 0xbc */
272	/*
273	 * 0xbc - [31:0]: idle timeout in ms
274	 */
275	/* ACS flags */
276	u32 hi_acs_flags;                              /* 0xc0 */
277	u32 hi_console_flags;                          /* 0xc4 */
278	u32 hi_nvram_state;                            /* 0xc8 */
279	u32 hi_option_flag2;                           /* 0xcc */
280
281	/* If non-zero, override values sent to Host in WMI_READY event. */
282	u32 hi_sw_version_override;                    /* 0xd0 */
283	u32 hi_abi_version_override;                   /* 0xd4 */
284
285	/*
286	 * Percentage of high priority RX traffic to total expected RX traffic -
287	 * applicable only to ar6004
288	 */
289	u32 hi_hp_rx_traffic_ratio;                    /* 0xd8 */
290
291	/* test applications flags */
292	u32 hi_test_apps_related;                      /* 0xdc */
293	/* location of test script */
294	u32 hi_ota_testscript;                         /* 0xe0 */
295	/* location of CAL data */
296	u32 hi_cal_data;                               /* 0xe4 */
297	/* Number of packet log buffers */
298	u32 hi_pktlog_num_buffers;                     /* 0xe8 */
299
300} __packed;
301
302#define HI_ITEM(item)  offsetof(struct host_interest, item)
303
304#define HI_OPTION_MAC_ADDR_METHOD_SHIFT	3
305
306#define HI_OPTION_FW_MODE_IBSS    0x0
307#define HI_OPTION_FW_MODE_BSS_STA 0x1
308#define HI_OPTION_FW_MODE_AP      0x2
309
310#define HI_OPTION_FW_SUBMODE_NONE      0x0
311#define HI_OPTION_FW_SUBMODE_P2PDEV    0x1
312#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2
313#define HI_OPTION_FW_SUBMODE_P2PGO     0x3
314
315#define HI_OPTION_NUM_DEV_SHIFT   0x9
316
317#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
318
319/* Fw Mode/SubMode Mask
320|------------------------------------------------------------------------------|
321|   SUB   |   SUB   |   SUB   |  SUB    |         |         |         |
322| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
323|   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)
324|------------------------------------------------------------------------------|
325*/
326#define HI_OPTION_FW_MODE_BITS	       0x2
327#define HI_OPTION_FW_MODE_SHIFT        0xC
328
329#define HI_OPTION_FW_SUBMODE_BITS      0x2
330#define HI_OPTION_FW_SUBMODE_SHIFT     0x14
331
332/* Convert a Target virtual address into a Target physical address */
333#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
334#define AR6004_VTOP(vaddr) (vaddr)
335
336#define TARG_VTOP(target_type, vaddr) \
337	(((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
338	(((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0))
339
340#define ATH6KL_FWLOG_PAYLOAD_SIZE		1500
341
342struct ath6kl_dbglog_buf {
343	__le32 next;
344	__le32 buffer_addr;
345	__le32 bufsize;
346	__le32 length;
347	__le32 count;
348	__le32 free;
349} __packed;
350
351struct ath6kl_dbglog_hdr {
352	__le32 dbuf_addr;
353	__le32 dropped;
354} __packed;
355
356#endif