/drivers/net/wireless/ath/ath9k/mac.h

http://github.com/mirrors/linux · C Header · 753 lines · 627 code · 84 blank · 42 comment · 0 complexity · 7496099f232ed14274c0abd0ae78ce8c MD5 · raw file

  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef MAC_H
  17. #define MAC_H
  18. #include <net/cfg80211.h>
  19. #define set11nTries(_series, _index) \
  20. (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
  21. #define set11nRate(_series, _index) \
  22. (SM((_series)[_index].Rate, AR_XmitRate##_index))
  23. #define set11nPktDurRTSCTS(_series, _index) \
  24. (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
  25. ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
  26. AR_RTSCTSQual##_index : 0))
  27. #define set11nRateFlags(_series, _index) \
  28. (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
  29. AR_2040_##_index : 0) \
  30. |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
  31. AR_GI##_index : 0) \
  32. |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \
  33. AR_STBC##_index : 0) \
  34. |SM((_series)[_index].ChSel, AR_ChainSel##_index))
  35. #define CCK_SIFS_TIME 10
  36. #define CCK_PREAMBLE_BITS 144
  37. #define CCK_PLCP_BITS 48
  38. #define OFDM_SIFS_TIME 16
  39. #define OFDM_PREAMBLE_TIME 20
  40. #define OFDM_PLCP_BITS 22
  41. #define OFDM_SYMBOL_TIME 4
  42. #define OFDM_SIFS_TIME_HALF 32
  43. #define OFDM_PREAMBLE_TIME_HALF 40
  44. #define OFDM_PLCP_BITS_HALF 22
  45. #define OFDM_SYMBOL_TIME_HALF 8
  46. #define OFDM_SIFS_TIME_QUARTER 64
  47. #define OFDM_PREAMBLE_TIME_QUARTER 80
  48. #define OFDM_PLCP_BITS_QUARTER 22
  49. #define OFDM_SYMBOL_TIME_QUARTER 16
  50. #define INIT_AIFS 2
  51. #define INIT_CWMIN 15
  52. #define INIT_CWMIN_11B 31
  53. #define INIT_CWMAX 1023
  54. #define INIT_SH_RETRY 10
  55. #define INIT_LG_RETRY 10
  56. #define INIT_SSH_RETRY 32
  57. #define INIT_SLG_RETRY 32
  58. #define ATH9K_TXERR_XRETRY 0x01
  59. #define ATH9K_TXERR_FILT 0x02
  60. #define ATH9K_TXERR_FIFO 0x04
  61. #define ATH9K_TXERR_XTXOP 0x08
  62. #define ATH9K_TXERR_TIMER_EXPIRED 0x10
  63. #define ATH9K_TX_ACKED 0x20
  64. #define ATH9K_TX_FLUSH 0x40
  65. #define ATH9K_TXERR_MASK \
  66. (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
  67. ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH)
  68. #define ATH9K_TX_BA 0x01
  69. #define ATH9K_TX_PWRMGMT 0x02
  70. #define ATH9K_TX_DESC_CFG_ERR 0x04
  71. #define ATH9K_TX_DATA_UNDERRUN 0x08
  72. #define ATH9K_TX_DELIM_UNDERRUN 0x10
  73. #define ATH9K_TX_SW_FILTERED 0x80
  74. /* 64 bytes */
  75. #define MIN_TX_FIFO_THRESHOLD 0x1
  76. /*
  77. * Single stream device AR9285 and AR9271 require 2 KB
  78. * to work around a hardware issue, all other devices
  79. * have can use the max 4 KB limit.
  80. */
  81. #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
  82. struct ath_tx_status {
  83. u32 ts_tstamp;
  84. u16 ts_seqnum;
  85. u8 ts_status;
  86. u8 ts_rateindex;
  87. int8_t ts_rssi;
  88. u8 ts_shortretry;
  89. u8 ts_longretry;
  90. u8 ts_virtcol;
  91. u8 ts_flags;
  92. int8_t ts_rssi_ctl0;
  93. int8_t ts_rssi_ctl1;
  94. int8_t ts_rssi_ctl2;
  95. int8_t ts_rssi_ext0;
  96. int8_t ts_rssi_ext1;
  97. int8_t ts_rssi_ext2;
  98. u8 qid;
  99. u16 desc_id;
  100. u8 tid;
  101. u32 ba_low;
  102. u32 ba_high;
  103. u32 evm0;
  104. u32 evm1;
  105. u32 evm2;
  106. u32 duration;
  107. };
  108. struct ath_rx_status {
  109. u32 rs_tstamp;
  110. u16 rs_datalen;
  111. u8 rs_status;
  112. u8 rs_phyerr;
  113. int8_t rs_rssi;
  114. u8 rs_keyix;
  115. u8 rs_rate;
  116. u8 rs_antenna;
  117. u8 rs_more;
  118. int8_t rs_rssi_ctl[3];
  119. int8_t rs_rssi_ext[3];
  120. u8 rs_isaggr;
  121. u8 rs_firstaggr;
  122. u8 rs_moreaggr;
  123. u8 rs_num_delims;
  124. u8 rs_flags;
  125. bool is_mybeacon;
  126. u32 evm0;
  127. u32 evm1;
  128. u32 evm2;
  129. u32 evm3;
  130. u32 evm4;
  131. u16 enc_flags;
  132. enum rate_info_bw bw;
  133. };
  134. struct ath_htc_rx_status {
  135. __be64 rs_tstamp;
  136. __be16 rs_datalen;
  137. u8 rs_status;
  138. u8 rs_phyerr;
  139. int8_t rs_rssi;
  140. int8_t rs_rssi_ctl[3];
  141. int8_t rs_rssi_ext[3];
  142. u8 rs_keyix;
  143. u8 rs_rate;
  144. u8 rs_antenna;
  145. u8 rs_more;
  146. u8 rs_isaggr;
  147. u8 rs_moreaggr;
  148. u8 rs_num_delims;
  149. u8 rs_flags;
  150. u8 rs_dummy;
  151. /* FIXME: evm* never used? */
  152. __be32 evm0;
  153. __be32 evm1;
  154. __be32 evm2;
  155. };
  156. #define ATH9K_RXERR_CRC 0x01
  157. #define ATH9K_RXERR_PHY 0x02
  158. #define ATH9K_RXERR_FIFO 0x04
  159. #define ATH9K_RXERR_DECRYPT 0x08
  160. #define ATH9K_RXERR_MIC 0x10
  161. #define ATH9K_RXERR_KEYMISS 0x20
  162. #define ATH9K_RXERR_CORRUPT_DESC 0x40
  163. #define ATH9K_RX_MORE 0x01
  164. #define ATH9K_RX_MORE_AGGR 0x02
  165. #define ATH9K_RX_GI 0x04
  166. #define ATH9K_RX_2040 0x08
  167. #define ATH9K_RX_DELIM_CRC_PRE 0x10
  168. #define ATH9K_RX_DELIM_CRC_POST 0x20
  169. #define ATH9K_RX_DECRYPT_BUSY 0x40
  170. #define ATH9K_RXKEYIX_INVALID ((u8)-1)
  171. #define ATH9K_TXKEYIX_INVALID ((u8)-1)
  172. enum ath9k_phyerr {
  173. ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */
  174. ATH9K_PHYERR_TIMING = 1, /* Timing error */
  175. ATH9K_PHYERR_PARITY = 2, /* Illegal parity */
  176. ATH9K_PHYERR_RATE = 3, /* Illegal rate */
  177. ATH9K_PHYERR_LENGTH = 4, /* Illegal length */
  178. ATH9K_PHYERR_RADAR = 5, /* Radar detect */
  179. ATH9K_PHYERR_SERVICE = 6, /* Illegal service */
  180. ATH9K_PHYERR_TOR = 7, /* Transmit override receive */
  181. ATH9K_PHYERR_OFDM_TIMING = 17,
  182. ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18,
  183. ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19,
  184. ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,
  185. ATH9K_PHYERR_OFDM_POWER_DROP = 21,
  186. ATH9K_PHYERR_OFDM_SERVICE = 22,
  187. ATH9K_PHYERR_OFDM_RESTART = 23,
  188. ATH9K_PHYERR_CCK_BLOCKER = 24,
  189. ATH9K_PHYERR_CCK_TIMING = 25,
  190. ATH9K_PHYERR_CCK_HEADER_CRC = 26,
  191. ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27,
  192. ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 28,
  193. ATH9K_PHYERR_CCK_POWER_DROP = 29,
  194. ATH9K_PHYERR_CCK_SERVICE = 30,
  195. ATH9K_PHYERR_CCK_RESTART = 31,
  196. ATH9K_PHYERR_HT_CRC_ERROR = 32,
  197. ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 33,
  198. ATH9K_PHYERR_HT_RATE_ILLEGAL = 34,
  199. ATH9K_PHYERR_HT_ZLF = 35,
  200. ATH9K_PHYERR_FALSE_RADAR_EXT = 36,
  201. ATH9K_PHYERR_GREEN_FIELD = 37,
  202. ATH9K_PHYERR_SPECTRAL = 38,
  203. ATH9K_PHYERR_MAX = 39,
  204. };
  205. struct ath_desc {
  206. u32 ds_link;
  207. u32 ds_data;
  208. u32 ds_ctl0;
  209. u32 ds_ctl1;
  210. u32 ds_hw[20];
  211. void *ds_vdata;
  212. } __packed __aligned(4);
  213. #define ATH9K_TXDESC_NOACK 0x0002
  214. #define ATH9K_TXDESC_RTSENA 0x0004
  215. #define ATH9K_TXDESC_CTSENA 0x0008
  216. /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
  217. * the descriptor its marked on. We take a tx interrupt to reap
  218. * descriptors when the h/w hits an EOL condition or
  219. * when the descriptor is specifically marked to generate
  220. * an interrupt with this flag. Descriptors should be
  221. * marked periodically to insure timely replenishing of the
  222. * supply needed for sending frames. Defering interrupts
  223. * reduces system load and potentially allows more concurrent
  224. * work to be done but if done to aggressively can cause
  225. * senders to backup. When the hardware queue is left too
  226. * large rate control information may also be too out of
  227. * date. An Alternative for this is TX interrupt mitigation
  228. * but this needs more testing. */
  229. #define ATH9K_TXDESC_INTREQ 0x0010
  230. #define ATH9K_TXDESC_VEOL 0x0020
  231. #define ATH9K_TXDESC_EXT_ONLY 0x0040
  232. #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
  233. #define ATH9K_TXDESC_VMF 0x0100
  234. #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
  235. #define ATH9K_TXDESC_LOWRXCHAIN 0x0400
  236. #define ATH9K_TXDESC_LDPC 0x0800
  237. #define ATH9K_TXDESC_CLRDMASK 0x1000
  238. #define ATH9K_TXDESC_PAPRD 0x70000
  239. #define ATH9K_TXDESC_PAPRD_S 16
  240. #define ATH9K_RXDESC_INTREQ 0x0020
  241. struct ar5416_desc {
  242. u32 ds_link;
  243. u32 ds_data;
  244. u32 ds_ctl0;
  245. u32 ds_ctl1;
  246. union {
  247. struct {
  248. u32 ctl2;
  249. u32 ctl3;
  250. u32 ctl4;
  251. u32 ctl5;
  252. u32 ctl6;
  253. u32 ctl7;
  254. u32 ctl8;
  255. u32 ctl9;
  256. u32 ctl10;
  257. u32 ctl11;
  258. u32 status0;
  259. u32 status1;
  260. u32 status2;
  261. u32 status3;
  262. u32 status4;
  263. u32 status5;
  264. u32 status6;
  265. u32 status7;
  266. u32 status8;
  267. u32 status9;
  268. } tx;
  269. struct {
  270. u32 status0;
  271. u32 status1;
  272. u32 status2;
  273. u32 status3;
  274. u32 status4;
  275. u32 status5;
  276. u32 status6;
  277. u32 status7;
  278. u32 status8;
  279. } rx;
  280. } u;
  281. } __packed __aligned(4);
  282. #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
  283. #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
  284. #define ds_ctl2 u.tx.ctl2
  285. #define ds_ctl3 u.tx.ctl3
  286. #define ds_ctl4 u.tx.ctl4
  287. #define ds_ctl5 u.tx.ctl5
  288. #define ds_ctl6 u.tx.ctl6
  289. #define ds_ctl7 u.tx.ctl7
  290. #define ds_ctl8 u.tx.ctl8
  291. #define ds_ctl9 u.tx.ctl9
  292. #define ds_ctl10 u.tx.ctl10
  293. #define ds_ctl11 u.tx.ctl11
  294. #define ds_txstatus0 u.tx.status0
  295. #define ds_txstatus1 u.tx.status1
  296. #define ds_txstatus2 u.tx.status2
  297. #define ds_txstatus3 u.tx.status3
  298. #define ds_txstatus4 u.tx.status4
  299. #define ds_txstatus5 u.tx.status5
  300. #define ds_txstatus6 u.tx.status6
  301. #define ds_txstatus7 u.tx.status7
  302. #define ds_txstatus8 u.tx.status8
  303. #define ds_txstatus9 u.tx.status9
  304. #define ds_rxstatus0 u.rx.status0
  305. #define ds_rxstatus1 u.rx.status1
  306. #define ds_rxstatus2 u.rx.status2
  307. #define ds_rxstatus3 u.rx.status3
  308. #define ds_rxstatus4 u.rx.status4
  309. #define ds_rxstatus5 u.rx.status5
  310. #define ds_rxstatus6 u.rx.status6
  311. #define ds_rxstatus7 u.rx.status7
  312. #define ds_rxstatus8 u.rx.status8
  313. #define AR_FrameLen 0x00000fff
  314. #define AR_VirtMoreFrag 0x00001000
  315. #define AR_TxCtlRsvd00 0x0000e000
  316. #define AR_XmitPower0 0x003f0000
  317. #define AR_XmitPower0_S 16
  318. #define AR_XmitPower1 0x3f000000
  319. #define AR_XmitPower1_S 24
  320. #define AR_XmitPower2 0x3f000000
  321. #define AR_XmitPower2_S 24
  322. #define AR_XmitPower3 0x3f000000
  323. #define AR_XmitPower3_S 24
  324. #define AR_RTSEnable 0x00400000
  325. #define AR_VEOL 0x00800000
  326. #define AR_ClrDestMask 0x01000000
  327. #define AR_TxCtlRsvd01 0x1e000000
  328. #define AR_TxIntrReq 0x20000000
  329. #define AR_DestIdxValid 0x40000000
  330. #define AR_CTSEnable 0x80000000
  331. #define AR_TxMore 0x00001000
  332. #define AR_DestIdx 0x000fe000
  333. #define AR_DestIdx_S 13
  334. #define AR_FrameType 0x00f00000
  335. #define AR_FrameType_S 20
  336. #define AR_NoAck 0x01000000
  337. #define AR_InsertTS 0x02000000
  338. #define AR_CorruptFCS 0x04000000
  339. #define AR_ExtOnly 0x08000000
  340. #define AR_ExtAndCtl 0x10000000
  341. #define AR_MoreAggr 0x20000000
  342. #define AR_IsAggr 0x40000000
  343. #define AR_BurstDur 0x00007fff
  344. #define AR_BurstDur_S 0
  345. #define AR_DurUpdateEna 0x00008000
  346. #define AR_XmitDataTries0 0x000f0000
  347. #define AR_XmitDataTries0_S 16
  348. #define AR_XmitDataTries1 0x00f00000
  349. #define AR_XmitDataTries1_S 20
  350. #define AR_XmitDataTries2 0x0f000000
  351. #define AR_XmitDataTries2_S 24
  352. #define AR_XmitDataTries3 0xf0000000
  353. #define AR_XmitDataTries3_S 28
  354. #define AR_XmitRate0 0x000000ff
  355. #define AR_XmitRate0_S 0
  356. #define AR_XmitRate1 0x0000ff00
  357. #define AR_XmitRate1_S 8
  358. #define AR_XmitRate2 0x00ff0000
  359. #define AR_XmitRate2_S 16
  360. #define AR_XmitRate3 0xff000000
  361. #define AR_XmitRate3_S 24
  362. #define AR_PacketDur0 0x00007fff
  363. #define AR_PacketDur0_S 0
  364. #define AR_RTSCTSQual0 0x00008000
  365. #define AR_PacketDur1 0x7fff0000
  366. #define AR_PacketDur1_S 16
  367. #define AR_RTSCTSQual1 0x80000000
  368. #define AR_PacketDur2 0x00007fff
  369. #define AR_PacketDur2_S 0
  370. #define AR_RTSCTSQual2 0x00008000
  371. #define AR_PacketDur3 0x7fff0000
  372. #define AR_PacketDur3_S 16
  373. #define AR_RTSCTSQual3 0x80000000
  374. #define AR_AggrLen 0x0000ffff
  375. #define AR_AggrLen_S 0
  376. #define AR_TxCtlRsvd60 0x00030000
  377. #define AR_PadDelim 0x03fc0000
  378. #define AR_PadDelim_S 18
  379. #define AR_EncrType 0x0c000000
  380. #define AR_EncrType_S 26
  381. #define AR_TxCtlRsvd61 0xf0000000
  382. #define AR_LDPC 0x80000000
  383. #define AR_2040_0 0x00000001
  384. #define AR_GI0 0x00000002
  385. #define AR_ChainSel0 0x0000001c
  386. #define AR_ChainSel0_S 2
  387. #define AR_2040_1 0x00000020
  388. #define AR_GI1 0x00000040
  389. #define AR_ChainSel1 0x00000380
  390. #define AR_ChainSel1_S 7
  391. #define AR_2040_2 0x00000400
  392. #define AR_GI2 0x00000800
  393. #define AR_ChainSel2 0x00007000
  394. #define AR_ChainSel2_S 12
  395. #define AR_2040_3 0x00008000
  396. #define AR_GI3 0x00010000
  397. #define AR_ChainSel3 0x000e0000
  398. #define AR_ChainSel3_S 17
  399. #define AR_RTSCTSRate 0x0ff00000
  400. #define AR_RTSCTSRate_S 20
  401. #define AR_STBC0 0x10000000
  402. #define AR_STBC1 0x20000000
  403. #define AR_STBC2 0x40000000
  404. #define AR_STBC3 0x80000000
  405. #define AR_TxRSSIAnt00 0x000000ff
  406. #define AR_TxRSSIAnt00_S 0
  407. #define AR_TxRSSIAnt01 0x0000ff00
  408. #define AR_TxRSSIAnt01_S 8
  409. #define AR_TxRSSIAnt02 0x00ff0000
  410. #define AR_TxRSSIAnt02_S 16
  411. #define AR_TxStatusRsvd00 0x3f000000
  412. #define AR_TxBaStatus 0x40000000
  413. #define AR_TxStatusRsvd01 0x80000000
  414. /*
  415. * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
  416. * transmitted successfully. If clear, no ACK or BA was received to indicate
  417. * successful transmission when we were expecting an ACK or BA.
  418. */
  419. #define AR_FrmXmitOK 0x00000001
  420. #define AR_ExcessiveRetries 0x00000002
  421. #define AR_FIFOUnderrun 0x00000004
  422. #define AR_Filtered 0x00000008
  423. #define AR_RTSFailCnt 0x000000f0
  424. #define AR_RTSFailCnt_S 4
  425. #define AR_DataFailCnt 0x00000f00
  426. #define AR_DataFailCnt_S 8
  427. #define AR_VirtRetryCnt 0x0000f000
  428. #define AR_VirtRetryCnt_S 12
  429. #define AR_TxDelimUnderrun 0x00010000
  430. #define AR_TxDataUnderrun 0x00020000
  431. #define AR_DescCfgErr 0x00040000
  432. #define AR_TxTimerExpired 0x00080000
  433. #define AR_TxStatusRsvd10 0xfff00000
  434. #define AR_SendTimestamp ds_txstatus2
  435. #define AR_BaBitmapLow ds_txstatus3
  436. #define AR_BaBitmapHigh ds_txstatus4
  437. #define AR_TxRSSIAnt10 0x000000ff
  438. #define AR_TxRSSIAnt10_S 0
  439. #define AR_TxRSSIAnt11 0x0000ff00
  440. #define AR_TxRSSIAnt11_S 8
  441. #define AR_TxRSSIAnt12 0x00ff0000
  442. #define AR_TxRSSIAnt12_S 16
  443. #define AR_TxRSSICombined 0xff000000
  444. #define AR_TxRSSICombined_S 24
  445. #define AR_TxTid 0xf0000000
  446. #define AR_TxTid_S 28
  447. #define AR_TxEVM0 ds_txstatus5
  448. #define AR_TxEVM1 ds_txstatus6
  449. #define AR_TxEVM2 ds_txstatus7
  450. #define AR_TxDone 0x00000001
  451. #define AR_SeqNum 0x00001ffe
  452. #define AR_SeqNum_S 1
  453. #define AR_TxStatusRsvd80 0x0001e000
  454. #define AR_TxOpExceeded 0x00020000
  455. #define AR_TxStatusRsvd81 0x001c0000
  456. #define AR_FinalTxIdx 0x00600000
  457. #define AR_FinalTxIdx_S 21
  458. #define AR_TxStatusRsvd82 0x01800000
  459. #define AR_PowerMgmt 0x02000000
  460. #define AR_TxStatusRsvd83 0xfc000000
  461. #define AR_RxCTLRsvd00 0xffffffff
  462. #define AR_RxCtlRsvd00 0x00001000
  463. #define AR_RxIntrReq 0x00002000
  464. #define AR_RxCtlRsvd01 0xffffc000
  465. #define AR_RxRSSIAnt00 0x000000ff
  466. #define AR_RxRSSIAnt00_S 0
  467. #define AR_RxRSSIAnt01 0x0000ff00
  468. #define AR_RxRSSIAnt01_S 8
  469. #define AR_RxRSSIAnt02 0x00ff0000
  470. #define AR_RxRSSIAnt02_S 16
  471. #define AR_RxRate 0xff000000
  472. #define AR_RxRate_S 24
  473. #define AR_RxStatusRsvd00 0xff000000
  474. #define AR_DataLen 0x00000fff
  475. #define AR_RxMore 0x00001000
  476. #define AR_NumDelim 0x003fc000
  477. #define AR_NumDelim_S 14
  478. #define AR_RxStatusRsvd10 0xff800000
  479. #define AR_RcvTimestamp ds_rxstatus2
  480. #define AR_GI 0x00000001
  481. #define AR_2040 0x00000002
  482. #define AR_Parallel40 0x00000004
  483. #define AR_Parallel40_S 2
  484. #define AR_STBC 0x00000008 /* on ar9280 and later */
  485. #define AR_RxStatusRsvd30 0x000000f0
  486. #define AR_RxAntenna 0xffffff00
  487. #define AR_RxAntenna_S 8
  488. #define AR_RxRSSIAnt10 0x000000ff
  489. #define AR_RxRSSIAnt10_S 0
  490. #define AR_RxRSSIAnt11 0x0000ff00
  491. #define AR_RxRSSIAnt11_S 8
  492. #define AR_RxRSSIAnt12 0x00ff0000
  493. #define AR_RxRSSIAnt12_S 16
  494. #define AR_RxRSSICombined 0xff000000
  495. #define AR_RxRSSICombined_S 24
  496. #define AR_RxEVM0 ds_rxstatus4
  497. #define AR_RxEVM1 ds_rxstatus5
  498. #define AR_RxEVM2 ds_rxstatus6
  499. #define AR_RxDone 0x00000001
  500. #define AR_RxFrameOK 0x00000002
  501. #define AR_CRCErr 0x00000004
  502. #define AR_DecryptCRCErr 0x00000008
  503. #define AR_PHYErr 0x00000010
  504. #define AR_MichaelErr 0x00000020
  505. #define AR_PreDelimCRCErr 0x00000040
  506. #define AR_RxStatusRsvd70 0x00000080
  507. #define AR_RxKeyIdxValid 0x00000100
  508. #define AR_KeyIdx 0x0000fe00
  509. #define AR_KeyIdx_S 9
  510. #define AR_PHYErrCode 0x0000ff00
  511. #define AR_PHYErrCode_S 8
  512. #define AR_RxMoreAggr 0x00010000
  513. #define AR_RxAggr 0x00020000
  514. #define AR_PostDelimCRCErr 0x00040000
  515. #define AR_RxStatusRsvd71 0x3ff80000
  516. #define AR_RxFirstAggr 0x20000000
  517. #define AR_DecryptBusyErr 0x40000000
  518. #define AR_KeyMiss 0x80000000
  519. enum ath9k_tx_queue {
  520. ATH9K_TX_QUEUE_INACTIVE = 0,
  521. ATH9K_TX_QUEUE_DATA,
  522. ATH9K_TX_QUEUE_BEACON,
  523. ATH9K_TX_QUEUE_CAB,
  524. ATH9K_TX_QUEUE_UAPSD,
  525. ATH9K_TX_QUEUE_PSPOLL
  526. };
  527. #define ATH9K_NUM_TX_QUEUES 10
  528. /* Used as a queue subtype instead of a WMM AC */
  529. #define ATH9K_WME_UPSD 4
  530. enum ath9k_tx_queue_flags {
  531. TXQ_FLAG_TXINT_ENABLE = 0x0001,
  532. TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
  533. TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
  534. TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
  535. TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
  536. TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
  537. TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
  538. TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
  539. };
  540. #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
  541. #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
  542. #define ATH9K_DECOMP_MASK_SIZE 128
  543. enum ath9k_pkt_type {
  544. ATH9K_PKT_TYPE_NORMAL = 0,
  545. ATH9K_PKT_TYPE_ATIM,
  546. ATH9K_PKT_TYPE_PSPOLL,
  547. ATH9K_PKT_TYPE_BEACON,
  548. ATH9K_PKT_TYPE_PROBE_RESP,
  549. ATH9K_PKT_TYPE_CHIRP,
  550. ATH9K_PKT_TYPE_GRP_POLL,
  551. };
  552. struct ath9k_tx_queue_info {
  553. u32 tqi_ver;
  554. enum ath9k_tx_queue tqi_type;
  555. int tqi_subtype;
  556. enum ath9k_tx_queue_flags tqi_qflags;
  557. u32 tqi_priority;
  558. u32 tqi_aifs;
  559. u32 tqi_cwmin;
  560. u32 tqi_cwmax;
  561. u16 tqi_shretry;
  562. u16 tqi_lgretry;
  563. u32 tqi_cbrPeriod;
  564. u32 tqi_cbrOverflowLimit;
  565. u32 tqi_burstTime;
  566. u32 tqi_readyTime;
  567. u32 tqi_physCompBuf;
  568. u32 tqi_intFlags;
  569. };
  570. enum ath9k_rx_filter {
  571. ATH9K_RX_FILTER_UCAST = 0x00000001,
  572. ATH9K_RX_FILTER_MCAST = 0x00000002,
  573. ATH9K_RX_FILTER_BCAST = 0x00000004,
  574. ATH9K_RX_FILTER_CONTROL = 0x00000008,
  575. ATH9K_RX_FILTER_BEACON = 0x00000010,
  576. ATH9K_RX_FILTER_PROM = 0x00000020,
  577. ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
  578. ATH9K_RX_FILTER_PHYERR = 0x00000100,
  579. ATH9K_RX_FILTER_MYBEACON = 0x00000200,
  580. ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
  581. ATH9K_RX_FILTER_COMP_BA = 0x00000800,
  582. ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,
  583. ATH9K_RX_FILTER_PSPOLL = 0x00004000,
  584. ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
  585. ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
  586. ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000,
  587. ATH9K_RX_FILTER_4ADDRESS = 0x00100000,
  588. };
  589. #define ATH9K_RATESERIES_RTS_CTS 0x0001
  590. #define ATH9K_RATESERIES_2040 0x0002
  591. #define ATH9K_RATESERIES_HALFGI 0x0004
  592. #define ATH9K_RATESERIES_STBC 0x0008
  593. struct ath9k_11n_rate_series {
  594. u32 Tries;
  595. u32 Rate;
  596. u32 PktDuration;
  597. u32 ChSel;
  598. u32 RateFlags;
  599. };
  600. enum aggr_type {
  601. AGGR_BUF_NONE,
  602. AGGR_BUF_FIRST,
  603. AGGR_BUF_MIDDLE,
  604. AGGR_BUF_LAST,
  605. };
  606. enum ath9k_key_type {
  607. ATH9K_KEY_TYPE_CLEAR,
  608. ATH9K_KEY_TYPE_WEP,
  609. ATH9K_KEY_TYPE_AES,
  610. ATH9K_KEY_TYPE_TKIP,
  611. };
  612. struct ath_tx_info {
  613. u8 qcu;
  614. bool is_first;
  615. bool is_last;
  616. enum aggr_type aggr;
  617. u8 ndelim;
  618. u16 aggr_len;
  619. dma_addr_t link;
  620. int pkt_len;
  621. u32 flags;
  622. dma_addr_t buf_addr[4];
  623. int buf_len[4];
  624. struct ath9k_11n_rate_series rates[4];
  625. u8 rtscts_rate;
  626. bool dur_update;
  627. enum ath9k_pkt_type type;
  628. enum ath9k_key_type keytype;
  629. u8 keyix;
  630. u8 txpower[4];
  631. };
  632. struct ath_hw;
  633. struct ath9k_channel;
  634. enum ath9k_int;
  635. u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
  636. void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
  637. void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
  638. u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
  639. bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
  640. bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);
  641. void ath9k_hw_abort_tx_dma(struct ath_hw *ah);
  642. bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
  643. const struct ath9k_tx_queue_info *qinfo);
  644. bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
  645. struct ath9k_tx_queue_info *qinfo);
  646. int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
  647. const struct ath9k_tx_queue_info *qinfo);
  648. bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
  649. bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
  650. int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
  651. struct ath_rx_status *rs);
  652. void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
  653. u32 size, u32 flags);
  654. bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
  655. void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
  656. void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
  657. void ath9k_hw_abortpcurecv(struct ath_hw *ah);
  658. bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset);
  659. int ath9k_hw_beaconq_setup(struct ath_hw *ah);
  660. void ath9k_hw_set_tx_filter(struct ath_hw *ah, u8 destidx, bool set);
  661. /* Interrupt Handling */
  662. bool ath9k_hw_intrpend(struct ath_hw *ah);
  663. void ath9k_hw_set_interrupts(struct ath_hw *ah);
  664. void ath9k_hw_enable_interrupts(struct ath_hw *ah);
  665. void ath9k_hw_disable_interrupts(struct ath_hw *ah);
  666. void ath9k_hw_kill_interrupts(struct ath_hw *ah);
  667. void ath9k_hw_resume_interrupts(struct ath_hw *ah);
  668. void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
  669. #endif /* MAC_H */