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/drivers/net/wireless/ath/ath9k/ar9003_phy.c

http://github.com/mirrors/linux
C | 2180 lines | 1619 code | 288 blank | 273 comment | 258 complexity | 76d476ff4467dcccd566ea88e6f84260 MD5 | raw file

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   1/*
   2 * Copyright (c) 2010-2011 Atheros Communications Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#include <linux/export.h>
  18#include "hw.h"
  19#include "ar9003_phy.h"
  20#include "ar9003_eeprom.h"
  21
  22#define AR9300_OFDM_RATES	8
  23#define AR9300_HT_SS_RATES	8
  24#define AR9300_HT_DS_RATES	8
  25#define AR9300_HT_TS_RATES	8
  26
  27#define AR9300_11NA_OFDM_SHIFT		0
  28#define AR9300_11NA_HT_SS_SHIFT		8
  29#define AR9300_11NA_HT_DS_SHIFT		16
  30#define AR9300_11NA_HT_TS_SHIFT		24
  31
  32#define AR9300_11NG_OFDM_SHIFT		4
  33#define AR9300_11NG_HT_SS_SHIFT		12
  34#define AR9300_11NG_HT_DS_SHIFT		20
  35#define AR9300_11NG_HT_TS_SHIFT		28
  36
  37static const int firstep_table[] =
  38/* level:  0   1   2   3   4   5   6   7   8  */
  39	{ -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  40
  41static const int cycpwrThr1_table[] =
  42/* level:  0   1   2   3   4   5   6   7   8  */
  43	{ -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  44
  45/*
  46 * register values to turn OFDM weak signal detection OFF
  47 */
  48static const int m1ThreshLow_off = 127;
  49static const int m2ThreshLow_off = 127;
  50static const int m1Thresh_off = 127;
  51static const int m2Thresh_off = 127;
  52static const int m2CountThr_off =  31;
  53static const int m2CountThrLow_off =  63;
  54static const int m1ThreshLowExt_off = 127;
  55static const int m2ThreshLowExt_off = 127;
  56static const int m1ThreshExt_off = 127;
  57static const int m2ThreshExt_off = 127;
  58
  59static const u8 ofdm2pwr[] = {
  60	ALL_TARGET_LEGACY_6_24,
  61	ALL_TARGET_LEGACY_6_24,
  62	ALL_TARGET_LEGACY_6_24,
  63	ALL_TARGET_LEGACY_6_24,
  64	ALL_TARGET_LEGACY_6_24,
  65	ALL_TARGET_LEGACY_36,
  66	ALL_TARGET_LEGACY_48,
  67	ALL_TARGET_LEGACY_54
  68};
  69
  70static const u8 mcs2pwr_ht20[] = {
  71	ALL_TARGET_HT20_0_8_16,
  72	ALL_TARGET_HT20_1_3_9_11_17_19,
  73	ALL_TARGET_HT20_1_3_9_11_17_19,
  74	ALL_TARGET_HT20_1_3_9_11_17_19,
  75	ALL_TARGET_HT20_4,
  76	ALL_TARGET_HT20_5,
  77	ALL_TARGET_HT20_6,
  78	ALL_TARGET_HT20_7,
  79	ALL_TARGET_HT20_0_8_16,
  80	ALL_TARGET_HT20_1_3_9_11_17_19,
  81	ALL_TARGET_HT20_1_3_9_11_17_19,
  82	ALL_TARGET_HT20_1_3_9_11_17_19,
  83	ALL_TARGET_HT20_12,
  84	ALL_TARGET_HT20_13,
  85	ALL_TARGET_HT20_14,
  86	ALL_TARGET_HT20_15,
  87	ALL_TARGET_HT20_0_8_16,
  88	ALL_TARGET_HT20_1_3_9_11_17_19,
  89	ALL_TARGET_HT20_1_3_9_11_17_19,
  90	ALL_TARGET_HT20_1_3_9_11_17_19,
  91	ALL_TARGET_HT20_20,
  92	ALL_TARGET_HT20_21,
  93	ALL_TARGET_HT20_22,
  94	ALL_TARGET_HT20_23
  95};
  96
  97static const u8 mcs2pwr_ht40[] = {
  98	ALL_TARGET_HT40_0_8_16,
  99	ALL_TARGET_HT40_1_3_9_11_17_19,
 100	ALL_TARGET_HT40_1_3_9_11_17_19,
 101	ALL_TARGET_HT40_1_3_9_11_17_19,
 102	ALL_TARGET_HT40_4,
 103	ALL_TARGET_HT40_5,
 104	ALL_TARGET_HT40_6,
 105	ALL_TARGET_HT40_7,
 106	ALL_TARGET_HT40_0_8_16,
 107	ALL_TARGET_HT40_1_3_9_11_17_19,
 108	ALL_TARGET_HT40_1_3_9_11_17_19,
 109	ALL_TARGET_HT40_1_3_9_11_17_19,
 110	ALL_TARGET_HT40_12,
 111	ALL_TARGET_HT40_13,
 112	ALL_TARGET_HT40_14,
 113	ALL_TARGET_HT40_15,
 114	ALL_TARGET_HT40_0_8_16,
 115	ALL_TARGET_HT40_1_3_9_11_17_19,
 116	ALL_TARGET_HT40_1_3_9_11_17_19,
 117	ALL_TARGET_HT40_1_3_9_11_17_19,
 118	ALL_TARGET_HT40_20,
 119	ALL_TARGET_HT40_21,
 120	ALL_TARGET_HT40_22,
 121	ALL_TARGET_HT40_23,
 122};
 123
 124/**
 125 * ar9003_hw_set_channel - set channel on single-chip device
 126 * @ah: atheros hardware structure
 127 * @chan:
 128 *
 129 * This is the function to change channel on single-chip devices, that is
 130 * for AR9300 family of chipsets.
 131 *
 132 * This function takes the channel value in MHz and sets
 133 * hardware channel value. Assumes writes have been enabled to analog bus.
 134 *
 135 * Actual Expression,
 136 *
 137 * For 2GHz channel,
 138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
 139 * (freq_ref = 40MHz)
 140 *
 141 * For 5GHz channel,
 142 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
 143 * (freq_ref = 40MHz/(24>>amodeRefSel))
 144 *
 145 * For 5GHz channels which are 5MHz spaced,
 146 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
 147 * (freq_ref = 40MHz)
 148 */
 149static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 150{
 151	u16 bMode, fracMode = 0, aModeRefSel = 0;
 152	u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
 153	struct chan_centers centers;
 154	int loadSynthChannel;
 155
 156	ath9k_hw_get_channel_centers(ah, chan, &centers);
 157	freq = centers.synth_center;
 158
 159	if (freq < 4800) {     /* 2 GHz, fractional mode */
 160		if (AR_SREV_9330(ah) || AR_SREV_9485(ah) ||
 161		    AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
 162		    AR_SREV_9561(ah) || AR_SREV_9565(ah)) {
 163			if (ah->is_clk_25mhz)
 164				div = 75;
 165			else
 166				div = 120;
 167
 168			channelSel = (freq * 4) / div;
 169			chan_frac = (((freq * 4) % div) * 0x20000) / div;
 170			channelSel = (channelSel << 17) | chan_frac;
 171		} else if (AR_SREV_9340(ah)) {
 172			if (ah->is_clk_25mhz) {
 173				channelSel = (freq * 2) / 75;
 174				chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 175				channelSel = (channelSel << 17) | chan_frac;
 176			} else {
 177				channelSel = CHANSEL_2G(freq) >> 1;
 178			}
 179		} else {
 180			channelSel = CHANSEL_2G(freq);
 181		}
 182		/* Set to 2G mode */
 183		bMode = 1;
 184	} else {
 185		if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
 186		     AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
 187		    ah->is_clk_25mhz) {
 188			channelSel = freq / 75;
 189			chan_frac = ((freq % 75) * 0x20000) / 75;
 190			channelSel = (channelSel << 17) | chan_frac;
 191		} else {
 192			channelSel = CHANSEL_5G(freq);
 193			/* Doubler is ON, so, divide channelSel by 2. */
 194			channelSel >>= 1;
 195		}
 196		/* Set to 5G mode */
 197		bMode = 0;
 198	}
 199
 200	/* Enable fractional mode for all channels */
 201	fracMode = 1;
 202	aModeRefSel = 0;
 203	loadSynthChannel = 0;
 204
 205	reg32 = (bMode << 29);
 206	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 207
 208	/* Enable Long shift Select for Synthesizer */
 209	REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 210		      AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 211
 212	/* Program Synth. setting */
 213	reg32 = (channelSel << 2) | (fracMode << 30) |
 214		(aModeRefSel << 28) | (loadSynthChannel << 31);
 215	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 216
 217	/* Toggle Load Synth channel bit */
 218	loadSynthChannel = 1;
 219	reg32 = (channelSel << 2) | (fracMode << 30) |
 220		(aModeRefSel << 28) | (loadSynthChannel << 31);
 221	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 222
 223	ah->curchan = chan;
 224
 225	return 0;
 226}
 227
 228/**
 229 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 230 * @ah: atheros hardware structure
 231 * @chan:
 232 *
 233 * For single-chip solutions. Converts to baseband spur frequency given the
 234 * input channel frequency and compute register settings below.
 235 *
 236 * Spur mitigation for MRC CCK
 237 */
 238static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 239					    struct ath9k_channel *chan)
 240{
 241	static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 242	int cur_bb_spur, negative = 0, cck_spur_freq;
 243	int i;
 244	int range, max_spur_cnts, synth_freq;
 245	u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
 246
 247	/*
 248	 * Need to verify range +/- 10 MHz in control channel, otherwise spur
 249	 * is out-of-band and can be ignored.
 250	 */
 251
 252	if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 253	    AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
 254		if (spur_fbin_ptr[0] == 0) /* No spur */
 255			return;
 256		max_spur_cnts = 5;
 257		if (IS_CHAN_HT40(chan)) {
 258			range = 19;
 259			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 260					   AR_PHY_GC_DYN2040_PRI_CH) == 0)
 261				synth_freq = chan->channel + 10;
 262			else
 263				synth_freq = chan->channel - 10;
 264		} else {
 265			range = 10;
 266			synth_freq = chan->channel;
 267		}
 268	} else {
 269		range = AR_SREV_9462(ah) ? 5 : 10;
 270		max_spur_cnts = 4;
 271		synth_freq = chan->channel;
 272	}
 273
 274	for (i = 0; i < max_spur_cnts; i++) {
 275		if (AR_SREV_9462(ah) && (i == 0 || i == 3))
 276			continue;
 277
 278		negative = 0;
 279		if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 280		    AR_SREV_9550(ah) || AR_SREV_9561(ah))
 281			cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
 282							 IS_CHAN_2GHZ(chan));
 283		else
 284			cur_bb_spur = spur_freq[i];
 285
 286		cur_bb_spur -= synth_freq;
 287		if (cur_bb_spur < 0) {
 288			negative = 1;
 289			cur_bb_spur = -cur_bb_spur;
 290		}
 291		if (cur_bb_spur < range) {
 292			cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 293
 294			if (negative == 1)
 295				cck_spur_freq = -cck_spur_freq;
 296
 297			cck_spur_freq = cck_spur_freq & 0xfffff;
 298
 299			REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 300				      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 301			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 302				      AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 303			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 304				      AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 305				      0x2);
 306			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 307				      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 308				      0x1);
 309			REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 310				      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 311				      cck_spur_freq);
 312
 313			return;
 314		}
 315	}
 316
 317	REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 318		      AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 319	REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 320		      AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 321	REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 322		      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 323}
 324
 325/* Clean all spur register fields */
 326static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 327{
 328	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 329		      AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 330	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 331		      AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 332	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 333		      AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 334	REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 335		      AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 336	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 337		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 338	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 339		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 340	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 341		      AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 342	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 343		      AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 344	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 345		      AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 346
 347	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 348		      AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 349	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 350		      AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 351	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 352		      AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 353	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 354		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 355	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 356		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 357	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 358		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 359	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 360		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 361	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 362		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 363	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 364		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 365	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 366		      AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 367}
 368
 369static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 370				int freq_offset,
 371				int spur_freq_sd,
 372				int spur_delta_phase,
 373				int spur_subchannel_sd,
 374				int range,
 375				int synth_freq)
 376{
 377	int mask_index = 0;
 378
 379	/* OFDM Spur mitigation */
 380	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 381		 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 382	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 383		      AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 384	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 385		      AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 386	REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 387		      AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 388	REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 389		      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 390
 391	if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
 392		REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 393			      AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 394
 395	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 396		      AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 397	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 398		      AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 399	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 400		      AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 401
 402	if (!AR_SREV_9340(ah) &&
 403	    REG_READ_FIELD(ah, AR_PHY_MODE,
 404			   AR_PHY_MODE_DYNAMIC) == 0x1)
 405		REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 406			      AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 407
 408	mask_index = (freq_offset << 4) / 5;
 409	if (mask_index < 0)
 410		mask_index = mask_index - 1;
 411
 412	mask_index = mask_index & 0x7f;
 413
 414	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 415		      AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 416	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 417		      AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 418	REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 419		      AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 420	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 421		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 422	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 423		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 424	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 425		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 426	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 427		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 428	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 429		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 430	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 431		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 432	REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 433		      AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 434}
 435
 436static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
 437				     int freq_offset)
 438{
 439	int mask_index = 0;
 440
 441	mask_index = (freq_offset << 4) / 5;
 442	if (mask_index < 0)
 443		mask_index = mask_index - 1;
 444
 445	mask_index = mask_index & 0x7f;
 446
 447	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 448		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
 449		      mask_index);
 450
 451	/* A == B */
 452	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 453		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
 454		      mask_index);
 455
 456	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 457		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
 458		      mask_index);
 459	REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 460		      AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
 461	REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 462		      AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
 463
 464	/* A == B */
 465	REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 466		      AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 467}
 468
 469static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 470				     struct ath9k_channel *chan,
 471				     int freq_offset,
 472				     int range,
 473				     int synth_freq)
 474{
 475	int spur_freq_sd = 0;
 476	int spur_subchannel_sd = 0;
 477	int spur_delta_phase = 0;
 478
 479	if (IS_CHAN_HT40(chan)) {
 480		if (freq_offset < 0) {
 481			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 482					   AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 483				spur_subchannel_sd = 1;
 484			else
 485				spur_subchannel_sd = 0;
 486
 487			spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 488
 489		} else {
 490			if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 491			    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 492				spur_subchannel_sd = 0;
 493			else
 494				spur_subchannel_sd = 1;
 495
 496			spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 497
 498		}
 499
 500		spur_delta_phase = (freq_offset << 17) / 5;
 501
 502	} else {
 503		spur_subchannel_sd = 0;
 504		spur_freq_sd = (freq_offset << 9) /11;
 505		spur_delta_phase = (freq_offset << 18) / 5;
 506	}
 507
 508	spur_freq_sd = spur_freq_sd & 0x3ff;
 509	spur_delta_phase = spur_delta_phase & 0xfffff;
 510
 511	ar9003_hw_spur_ofdm(ah,
 512			    freq_offset,
 513			    spur_freq_sd,
 514			    spur_delta_phase,
 515			    spur_subchannel_sd,
 516			    range, synth_freq);
 517}
 518
 519/* Spur mitigation for OFDM */
 520static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 521					 struct ath9k_channel *chan)
 522{
 523	int synth_freq;
 524	int range = 10;
 525	int freq_offset = 0;
 526	int mode;
 527	u8* spurChansPtr;
 528	unsigned int i;
 529	struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 530
 531	if (IS_CHAN_5GHZ(chan)) {
 532		spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 533		mode = 0;
 534	}
 535	else {
 536		spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 537		mode = 1;
 538	}
 539
 540	if (spurChansPtr[0] == 0)
 541		return; /* No spur in the mode */
 542
 543	if (IS_CHAN_HT40(chan)) {
 544		range = 19;
 545		if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 546				   AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 547			synth_freq = chan->channel - 10;
 548		else
 549			synth_freq = chan->channel + 10;
 550	} else {
 551		range = 10;
 552		synth_freq = chan->channel;
 553	}
 554
 555	ar9003_hw_spur_ofdm_clear(ah);
 556
 557	for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 558		freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
 559		freq_offset -= synth_freq;
 560		if (abs(freq_offset) < range) {
 561			ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
 562						 range, synth_freq);
 563
 564			if (AR_SREV_9565(ah) && (i < 4)) {
 565				freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
 566								 mode);
 567				freq_offset -= synth_freq;
 568				if (abs(freq_offset) < range)
 569					ar9003_hw_spur_ofdm_9565(ah, freq_offset);
 570			}
 571
 572			break;
 573		}
 574	}
 575}
 576
 577static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 578				    struct ath9k_channel *chan)
 579{
 580	if (!AR_SREV_9565(ah))
 581		ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 582	ar9003_hw_spur_mitigate_ofdm(ah, chan);
 583}
 584
 585static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
 586					     struct ath9k_channel *chan)
 587{
 588	u32 pll;
 589
 590	pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
 591
 592	if (chan && IS_CHAN_HALF_RATE(chan))
 593		pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
 594	else if (chan && IS_CHAN_QUARTER_RATE(chan))
 595		pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
 596
 597	pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
 598
 599	return pll;
 600}
 601
 602static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 603					 struct ath9k_channel *chan)
 604{
 605	u32 pll;
 606
 607	pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 608
 609	if (chan && IS_CHAN_HALF_RATE(chan))
 610		pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 611	else if (chan && IS_CHAN_QUARTER_RATE(chan))
 612		pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 613
 614	pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 615
 616	return pll;
 617}
 618
 619static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 620				       struct ath9k_channel *chan)
 621{
 622	u32 phymode;
 623	u32 enableDacFifo = 0;
 624
 625	enableDacFifo =
 626		(REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 627
 628	/* Enable 11n HT, 20 MHz */
 629	phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 630
 631	if (!AR_SREV_9561(ah))
 632		phymode |= AR_PHY_GC_SINGLE_HT_LTF1;
 633
 634	/* Configure baseband for dynamic 20/40 operation */
 635	if (IS_CHAN_HT40(chan)) {
 636		phymode |= AR_PHY_GC_DYN2040_EN;
 637		/* Configure control (primary) channel at +-10MHz */
 638		if (IS_CHAN_HT40PLUS(chan))
 639			phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 640
 641	}
 642
 643	/* make sure we preserve INI settings */
 644	phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 645	/* turn off Green Field detection for STA for now */
 646	phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 647
 648	REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 649
 650	/* Configure MAC for 20/40 operation */
 651	ath9k_hw_set11nmac2040(ah, chan);
 652
 653	/* global transmit timeout (25 TUs default)*/
 654	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 655	/* carrier sense timeout */
 656	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 657}
 658
 659static void ar9003_hw_init_bb(struct ath_hw *ah,
 660			      struct ath9k_channel *chan)
 661{
 662	u32 synthDelay;
 663
 664	/*
 665	 * Wait for the frequency synth to settle (synth goes on
 666	 * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 667	 * Value is in 100ns increments.
 668	 */
 669	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 670
 671	/* Activate the PHY (includes baseband activate + synthesizer on) */
 672	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 673	ath9k_hw_synth_delay(ah, chan, synthDelay);
 674}
 675
 676void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 677{
 678	if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 679		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 680			    AR_PHY_SWAP_ALT_CHAIN);
 681
 682	REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 683	REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 684
 685	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 686		tx = 3;
 687
 688	REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 689}
 690
 691/*
 692 * Override INI values with chip specific configuration.
 693 */
 694static void ar9003_hw_override_ini(struct ath_hw *ah)
 695{
 696	u32 val;
 697
 698	/*
 699	 * Set the RX_ABORT and RX_DIS and clear it only after
 700	 * RXE is set for MAC. This prevents frames with
 701	 * corrupted descriptor status.
 702	 */
 703	REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 704
 705	/*
 706	 * For AR9280 and above, there is a new feature that allows
 707	 * Multicast search based on both MAC Address and Key ID. By default,
 708	 * this feature is enabled. But since the driver is not using this
 709	 * feature, we switch it off; otherwise multicast search based on
 710	 * MAC addr only will fail.
 711	 */
 712	val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 713	val |= AR_AGG_WEP_ENABLE_FIX |
 714	       AR_AGG_WEP_ENABLE |
 715	       AR_PCU_MISC_MODE2_CFP_IGNORE;
 716	REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
 717
 718	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 719		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 720			  AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 721
 722		if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 723				   AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 724			ah->enabled_cals |= TX_IQ_CAL;
 725		else
 726			ah->enabled_cals &= ~TX_IQ_CAL;
 727
 728	}
 729
 730	if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 731		ah->enabled_cals |= TX_CL_CAL;
 732	else
 733		ah->enabled_cals &= ~TX_CL_CAL;
 734
 735	if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
 736	    AR_SREV_9561(ah)) {
 737		if (ah->is_clk_25mhz) {
 738			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
 739			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
 740			REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
 741		} else {
 742			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
 743			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
 744			REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
 745		}
 746		udelay(100);
 747	}
 748}
 749
 750static void ar9003_hw_prog_ini(struct ath_hw *ah,
 751			       struct ar5416IniArray *iniArr,
 752			       int column)
 753{
 754	unsigned int i, regWrites = 0;
 755
 756	/* New INI format: Array may be undefined (pre, core, post arrays) */
 757	if (!iniArr->ia_array)
 758		return;
 759
 760	/*
 761	 * New INI format: Pre, core, and post arrays for a given subsystem
 762	 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 763	 * the array is non-modal and force the column to 1.
 764	 */
 765	if (column >= iniArr->ia_columns)
 766		column = 1;
 767
 768	for (i = 0; i < iniArr->ia_rows; i++) {
 769		u32 reg = INI_RA(iniArr, i, 0);
 770		u32 val = INI_RA(iniArr, i, column);
 771
 772		REG_WRITE(ah, reg, val);
 773
 774		DO_DELAY(regWrites);
 775	}
 776}
 777
 778static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
 779					    struct ath9k_channel *chan)
 780{
 781	int ret;
 782
 783	if (IS_CHAN_2GHZ(chan)) {
 784		if (IS_CHAN_HT40(chan))
 785			return 7;
 786		else
 787			return 8;
 788	}
 789
 790	if (chan->channel <= 5350)
 791		ret = 1;
 792	else if ((chan->channel > 5350) && (chan->channel <= 5600))
 793		ret = 3;
 794	else
 795		ret = 5;
 796
 797	if (IS_CHAN_HT40(chan))
 798		ret++;
 799
 800	return ret;
 801}
 802
 803static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
 804					    struct ath9k_channel *chan)
 805{
 806	if (IS_CHAN_2GHZ(chan)) {
 807		if (IS_CHAN_HT40(chan))
 808			return 1;
 809		else
 810			return 2;
 811	}
 812
 813	return 0;
 814}
 815
 816static void ar9003_doubler_fix(struct ath_hw *ah)
 817{
 818	if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
 819		REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
 820			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 821			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 822		REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
 823			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 824			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 825		REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
 826			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 827			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
 828
 829		udelay(200);
 830
 831		REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
 832			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 833		REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
 834			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 835		REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
 836			    AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
 837
 838		udelay(1);
 839
 840		REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
 841			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 842		REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
 843			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 844		REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
 845			      AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
 846
 847		udelay(200);
 848
 849		REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
 850			      AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
 851
 852		REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
 853			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 854			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 855		REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
 856			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 857			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 858		REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
 859			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
 860			1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
 861	}
 862}
 863
 864static int ar9003_hw_process_ini(struct ath_hw *ah,
 865				 struct ath9k_channel *chan)
 866{
 867	unsigned int regWrites = 0, i;
 868	u32 modesIndex;
 869
 870	if (IS_CHAN_5GHZ(chan))
 871		modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
 872	else
 873		modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
 874
 875	/*
 876	 * SOC, MAC, BB, RADIO initvals.
 877	 */
 878	for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 879		ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 880		ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 881		ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 882		ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 883		if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
 884			ar9003_hw_prog_ini(ah,
 885					   &ah->ini_radio_post_sys2ant,
 886					   modesIndex);
 887	}
 888
 889	ar9003_doubler_fix(ah);
 890
 891	/*
 892	 * RXGAIN initvals.
 893	 */
 894	REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 895
 896	if (AR_SREV_9462_20_OR_LATER(ah)) {
 897		/*
 898		 * CUS217 mix LNA mode.
 899		 */
 900		if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
 901			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
 902					1, regWrites);
 903			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 904					modesIndex, regWrites);
 905		}
 906
 907		/*
 908		 * 5G-XLNA
 909		 */
 910		if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
 911		    (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
 912			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
 913					modesIndex, regWrites);
 914		}
 915	}
 916
 917	if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
 918		REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
 919				regWrites);
 920
 921	if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
 922		REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
 923				modesIndex, regWrites);
 924	/*
 925	 * TXGAIN initvals.
 926	 */
 927	if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
 928		int modes_txgain_index = 1;
 929
 930		if (AR_SREV_9550(ah))
 931			modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
 932
 933		if (AR_SREV_9561(ah))
 934			modes_txgain_index =
 935				ar9561_hw_get_modes_txgain_index(ah, chan);
 936
 937		if (modes_txgain_index < 0)
 938			return -EINVAL;
 939
 940		REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
 941				regWrites);
 942	} else {
 943		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 944	}
 945
 946	/*
 947	 * For 5GHz channels requiring Fast Clock, apply
 948	 * different modal values.
 949	 */
 950	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 951		REG_WRITE_ARRAY(&ah->iniModesFastClock,
 952				modesIndex, regWrites);
 953
 954	/*
 955	 * Clock frequency initvals.
 956	 */
 957	REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 958
 959	/*
 960	 * JAPAN regulatory.
 961	 */
 962	if (chan->channel == 2484) {
 963		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 964
 965		if (AR_SREV_9531(ah))
 966			REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
 967				      AR_PHY_FLC_PWR_THRESH, 0);
 968	}
 969
 970	ah->modes_index = modesIndex;
 971	ar9003_hw_override_ini(ah);
 972	ar9003_hw_set_channel_regs(ah, chan);
 973	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 974	ath9k_hw_apply_txpower(ah, chan, false);
 975
 976	return 0;
 977}
 978
 979static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 980				 struct ath9k_channel *chan)
 981{
 982	u32 rfMode = 0;
 983
 984	if (chan == NULL)
 985		return;
 986
 987	if (IS_CHAN_2GHZ(chan))
 988		rfMode |= AR_PHY_MODE_DYNAMIC;
 989	else
 990		rfMode |= AR_PHY_MODE_OFDM;
 991
 992	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 993		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 994
 995	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
 996		REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
 997			      AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
 998
 999	REG_WRITE(ah, AR_PHY_MODE, rfMode);
1000}
1001
1002static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
1003{
1004	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1005}
1006
1007static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
1008				      struct ath9k_channel *chan)
1009{
1010	u32 coef_scaled, ds_coef_exp, ds_coef_man;
1011	u32 clockMhzScaled = 0x64000000;
1012	struct chan_centers centers;
1013
1014	/*
1015	 * half and quarter rate can divide the scaled clock by 2 or 4
1016	 * scale for selected channel bandwidth
1017	 */
1018	if (IS_CHAN_HALF_RATE(chan))
1019		clockMhzScaled = clockMhzScaled >> 1;
1020	else if (IS_CHAN_QUARTER_RATE(chan))
1021		clockMhzScaled = clockMhzScaled >> 2;
1022
1023	/*
1024	 * ALGO -> coef = 1e8/fcarrier*fclock/40;
1025	 * scaled coef to provide precision for this floating calculation
1026	 */
1027	ath9k_hw_get_channel_centers(ah, chan, &centers);
1028	coef_scaled = clockMhzScaled / centers.synth_center;
1029
1030	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1031				      &ds_coef_exp);
1032
1033	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1034		      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1035	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1036		      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1037
1038	/*
1039	 * For Short GI,
1040	 * scaled coeff is 9/10 that of normal coeff
1041	 */
1042	coef_scaled = (9 * coef_scaled) / 10;
1043
1044	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1045				      &ds_coef_exp);
1046
1047	/* for short gi */
1048	REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1049		      AR_PHY_SGI_DSC_MAN, ds_coef_man);
1050	REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1051		      AR_PHY_SGI_DSC_EXP, ds_coef_exp);
1052}
1053
1054static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1055{
1056	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1057	return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1058			     AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1059}
1060
1061/*
1062 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1063 * Read the phy active delay register. Value is in 100ns increments.
1064 */
1065static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1066{
1067	u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1068
1069	ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
1070
1071	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1072}
1073
1074static bool ar9003_hw_ani_control(struct ath_hw *ah,
1075				  enum ath9k_ani_cmd cmd, int param)
1076{
1077	struct ath_common *common = ath9k_hw_common(ah);
1078	struct ath9k_channel *chan = ah->curchan;
1079	struct ar5416AniState *aniState = &ah->ani;
1080	int m1ThreshLow, m2ThreshLow;
1081	int m1Thresh, m2Thresh;
1082	int m2CountThr, m2CountThrLow;
1083	int m1ThreshLowExt, m2ThreshLowExt;
1084	int m1ThreshExt, m2ThreshExt;
1085	s32 value, value2;
1086
1087	switch (cmd & ah->ani_function) {
1088	case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1089		/*
1090		 * on == 1 means ofdm weak signal detection is ON
1091		 * on == 1 is the default, for less noise immunity
1092		 *
1093		 * on == 0 means ofdm weak signal detection is OFF
1094		 * on == 0 means more noise imm
1095		 */
1096		u32 on = param ? 1 : 0;
1097
1098		if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1099			goto skip_ws_det;
1100
1101		m1ThreshLow = on ?
1102			aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1103		m2ThreshLow = on ?
1104			aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1105		m1Thresh = on ?
1106			aniState->iniDef.m1Thresh : m1Thresh_off;
1107		m2Thresh = on ?
1108			aniState->iniDef.m2Thresh : m2Thresh_off;
1109		m2CountThr = on ?
1110			aniState->iniDef.m2CountThr : m2CountThr_off;
1111		m2CountThrLow = on ?
1112			aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1113		m1ThreshLowExt = on ?
1114			aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1115		m2ThreshLowExt = on ?
1116			aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1117		m1ThreshExt = on ?
1118			aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1119		m2ThreshExt = on ?
1120			aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1121
1122		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1123			      AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1124			      m1ThreshLow);
1125		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1126			      AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1127			      m2ThreshLow);
1128		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1129			      AR_PHY_SFCORR_M1_THRESH,
1130			      m1Thresh);
1131		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1132			      AR_PHY_SFCORR_M2_THRESH,
1133			      m2Thresh);
1134		REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1135			      AR_PHY_SFCORR_M2COUNT_THR,
1136			      m2CountThr);
1137		REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1138			      AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1139			      m2CountThrLow);
1140		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1141			      AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1142			      m1ThreshLowExt);
1143		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1144			      AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1145			      m2ThreshLowExt);
1146		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1147			      AR_PHY_SFCORR_EXT_M1_THRESH,
1148			      m1ThreshExt);
1149		REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1150			      AR_PHY_SFCORR_EXT_M2_THRESH,
1151			      m2ThreshExt);
1152skip_ws_det:
1153		if (on)
1154			REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1155				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1156		else
1157			REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1158				    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1159
1160		if (on != aniState->ofdmWeakSigDetect) {
1161			ath_dbg(common, ANI,
1162				"** ch %d: ofdm weak signal: %s=>%s\n",
1163				chan->channel,
1164				aniState->ofdmWeakSigDetect ?
1165				"on" : "off",
1166				on ? "on" : "off");
1167			if (on)
1168				ah->stats.ast_ani_ofdmon++;
1169			else
1170				ah->stats.ast_ani_ofdmoff++;
1171			aniState->ofdmWeakSigDetect = on;
1172		}
1173		break;
1174	}
1175	case ATH9K_ANI_FIRSTEP_LEVEL:{
1176		u32 level = param;
1177
1178		if (level >= ARRAY_SIZE(firstep_table)) {
1179			ath_dbg(common, ANI,
1180				"ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1181				level, ARRAY_SIZE(firstep_table));
1182			return false;
1183		}
1184
1185		/*
1186		 * make register setting relative to default
1187		 * from INI file & cap value
1188		 */
1189		value = firstep_table[level] -
1190			firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1191			aniState->iniDef.firstep;
1192		if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1193			value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1194		if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1195			value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1196		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1197			      AR_PHY_FIND_SIG_FIRSTEP,
1198			      value);
1199		/*
1200		 * we need to set first step low register too
1201		 * make register setting relative to default
1202		 * from INI file & cap value
1203		 */
1204		value2 = firstep_table[level] -
1205			 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1206			 aniState->iniDef.firstepLow;
1207		if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1208			value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1209		if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1210			value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1211
1212		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1213			      AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1214
1215		if (level != aniState->firstepLevel) {
1216			ath_dbg(common, ANI,
1217				"** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1218				chan->channel,
1219				aniState->firstepLevel,
1220				level,
1221				ATH9K_ANI_FIRSTEP_LVL,
1222				value,
1223				aniState->iniDef.firstep);
1224			ath_dbg(common, ANI,
1225				"** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1226				chan->channel,
1227				aniState->firstepLevel,
1228				level,
1229				ATH9K_ANI_FIRSTEP_LVL,
1230				value2,
1231				aniState->iniDef.firstepLow);
1232			if (level > aniState->firstepLevel)
1233				ah->stats.ast_ani_stepup++;
1234			else if (level < aniState->firstepLevel)
1235				ah->stats.ast_ani_stepdown++;
1236			aniState->firstepLevel = level;
1237		}
1238		break;
1239	}
1240	case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1241		u32 level = param;
1242
1243		if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1244			ath_dbg(common, ANI,
1245				"ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1246				level, ARRAY_SIZE(cycpwrThr1_table));
1247			return false;
1248		}
1249		/*
1250		 * make register setting relative to default
1251		 * from INI file & cap value
1252		 */
1253		value = cycpwrThr1_table[level] -
1254			cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1255			aniState->iniDef.cycpwrThr1;
1256		if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1257			value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1258		if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1259			value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1260		REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1261			      AR_PHY_TIMING5_CYCPWR_THR1,
1262			      value);
1263
1264		/*
1265		 * set AR_PHY_EXT_CCA for extension channel
1266		 * make register setting relative to default
1267		 * from INI file & cap value
1268		 */
1269		value2 = cycpwrThr1_table[level] -
1270			 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1271			 aniState->iniDef.cycpwrThr1Ext;
1272		if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1273			value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1274		if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1275			value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1276		REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1277			      AR_PHY_EXT_CYCPWR_THR1, value2);
1278
1279		if (level != aniState->spurImmunityLevel) {
1280			ath_dbg(common, ANI,
1281				"** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1282				chan->channel,
1283				aniState->spurImmunityLevel,
1284				level,
1285				ATH9K_ANI_SPUR_IMMUNE_LVL,
1286				value,
1287				aniState->iniDef.cycpwrThr1);
1288			ath_dbg(common, ANI,
1289				"** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1290				chan->channel,
1291				aniState->spurImmunityLevel,
1292				level,
1293				ATH9K_ANI_SPUR_IMMUNE_LVL,
1294				value2,
1295				aniState->iniDef.cycpwrThr1Ext);
1296			if (level > aniState->spurImmunityLevel)
1297				ah->stats.ast_ani_spurup++;
1298			else if (level < aniState->spurImmunityLevel)
1299				ah->stats.ast_ani_spurdown++;
1300			aniState->spurImmunityLevel = level;
1301		}
1302		break;
1303	}
1304	case ATH9K_ANI_MRC_CCK:{
1305		/*
1306		 * is_on == 1 means MRC CCK ON (default, less noise imm)
1307		 * is_on == 0 means MRC CCK is OFF (more noise imm)
1308		 */
1309		bool is_on = param ? 1 : 0;
1310
1311		if (ah->caps.rx_chainmask == 1)
1312			break;
1313
1314		REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1315			      AR_PHY_MRC_CCK_ENABLE, is_on);
1316		REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1317			      AR_PHY_MRC_CCK_MUX_REG, is_on);
1318		if (is_on != aniState->mrcCCK) {
1319			ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1320				chan->channel,
1321				aniState->mrcCCK ? "on" : "off",
1322				is_on ? "on" : "off");
1323			if (is_on)
1324				ah->stats.ast_ani_ccklow++;
1325			else
1326				ah->stats.ast_ani_cckhigh++;
1327			aniState->mrcCCK = is_on;
1328		}
1329	break;
1330	}
1331	default:
1332		ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1333		return false;
1334	}
1335
1336	ath_dbg(common, ANI,
1337		"ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1338		aniState->spurImmunityLevel,
1339		aniState->ofdmWeakSigDetect ? "on" : "off",
1340		aniState->firstepLevel,
1341		aniState->mrcCCK ? "on" : "off",
1342		aniState->listenTime,
1343		aniState->ofdmPhyErrCount,
1344		aniState->cckPhyErrCount);
1345	return true;
1346}
1347
1348static void ar9003_hw_do_getnf(struct ath_hw *ah,
1349			      int16_t nfarray[NUM_NF_READINGS])
1350{
1351#define AR_PHY_CH_MINCCA_PWR	0x1FF00000
1352#define AR_PHY_CH_MINCCA_PWR_S	20
1353#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1354#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1355
1356	int16_t nf;
1357	int i;
1358
1359	for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1360		if (ah->rxchainmask & BIT(i)) {
1361			nf = MS(REG_READ(ah, ah->nf_regs[i]),
1362					 AR_PHY_CH_MINCCA_PWR);
1363			nfarray[i] = sign_extend32(nf, 8);
1364
1365			if (IS_CHAN_HT40(ah->curchan)) {
1366				u8 ext_idx = AR9300_MAX_CHAINS + i;
1367
1368				nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1369						 AR_PHY_CH_EXT_MINCCA_PWR);
1370				nfarray[ext_idx] = sign_extend32(nf, 8);
1371			}
1372		}
1373	}
1374}
1375
1376static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1377{
1378	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1379	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1380	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1381	ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1382	ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1383	ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1384
1385	if (AR_SREV_9330(ah))
1386		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1387
1388	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1389		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1390		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1391		ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1392		ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1393	}
1394}
1395
1396/*
1397 * Initialize the ANI register values with default (ini) values.
1398 * This routine is called during a (full) hardware reset after
1399 * all the registers are initialised from the INI.
1400 */
1401static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1402{
1403	struct ar5416AniState *aniState;
1404	struct ath_common *common = ath9k_hw_common(ah);
1405	struct ath9k_channel *chan = ah->curchan;
1406	struct ath9k_ani_default *iniDef;
1407	u32 val;
1408
1409	aniState = &ah->ani;
1410	iniDef = &aniState->iniDef;
1411
1412	ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1413		ah->hw_version.macVersion,
1414		ah->hw_version.macRev,
1415		ah->opmode,
1416		chan->channel);
1417
1418	val = REG_READ(ah, AR_PHY_SFCORR);
1419	iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1420	iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1421	iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1422
1423	val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1424	iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1425	iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1426	iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1427
1428	val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1429	iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1430	iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1431	iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1432	iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1433	iniDef->firstep = REG_READ_FIELD(ah,
1434					 AR_PHY_FIND_SIG,
1435					 AR_PHY_FIND_SIG_FIRSTEP);
1436	iniDef->firstepLow = REG_READ_FIELD(ah,
1437					    AR_PHY_FIND_SIG_LOW,
1438					    AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1439	iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1440					    AR_PHY_TIMING5,
1441					    AR_PHY_TIMING5_CYCPWR_THR1);
1442	iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1443					       AR_PHY_EXT_CCA,
1444					       AR_PHY_EXT_CYCPWR_THR1);
1445
1446	/* these levels just got reset to defaults by the INI */
1447	aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1448	aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1449	aniState->ofdmWeakSigDetect = true;
1450	aniState->mrcCCK = true;
1451}
1452
1453static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1454				       struct ath_hw_radar_conf *conf)
1455{
1456	unsigned int regWrites = 0;
1457	u32 radar_0 = 0, radar_1;
1458
1459	if (!conf) {
1460		REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1461		return;
1462	}
1463
1464	radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1465	radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1466	radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1467	radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1468	radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1469	radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1470
1471	radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1472	radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1473		     AR_PHY_RADAR_1_RELPWR_THRESH);
1474	radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1475	radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1476	radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1477	radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1478	radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1479
1480	REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1481	REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1482	if (conf->ext_channel)
1483		REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1484	else
1485		REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1486
1487	if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1488		REG_WRITE_ARRAY(&ah->ini_dfs,
1489				IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1490	}
1491}
1492
1493static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1494{
1495	struct ath_hw_radar_conf *conf = &ah->radar_conf;
1496
1497	conf->fir_power = -28;
1498	conf->radar_rssi = 0;
1499	conf->pulse_height = 10;
1500	conf->pulse_rssi = 15;
1501	conf->pulse_inband = 8;
1502	conf->pulse_maxlen = 255;
1503	conf->pulse_inband_step = 12;
1504	conf->radar_inband = 8;
1505}
1506
1507static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1508					   struct ath_hw_antcomb_conf *antconf)
1509{
1510	u32 regval;
1511
1512	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1513	antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1514				  AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1515	antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1516				 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1517	antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1518				  AR_PHY_ANT_FAST_DIV_BIAS_S;
1519
1520	if (AR_SREV_9330_11(ah)) {
1521		antconf->lna1_lna2_switch_delta = -1;
1522		antconf->lna1_lna2_delta = -9;
1523		antconf->div_group = 1;
1524	} else if (AR_SREV_9485(ah)) {
1525		antconf->lna1_lna2_switch_delta = -1;
1526		antconf->lna1_lna2_delta = -9;
1527		antconf->div_group = 2;
1528	} else if (AR_SREV_9565(ah)) {
1529		antconf->lna1_lna2_switch_delta = 3;
1530		antconf->lna1_lna2_delta = -9;
1531		antconf->div_group = 3;
1532	} else {
1533		antconf->lna1_lna2_switch_delta = -1;
1534		antconf->lna1_lna2_delta = -3;
1535		antconf->div_group = 0;
1536	}
1537}
1538
1539static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1540				   struct ath_hw_antcomb_conf *antconf)
1541{
1542	u32 regval;
1543
1544	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1545	regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1546		    AR_PHY_ANT_DIV_ALT_LNACONF |
1547		    AR_PHY_ANT_FAST_DIV_BIAS |
1548		    AR_PHY_ANT_DIV_MAIN_GAINTB |
1549		    AR_PHY_ANT_DIV_ALT_GAINTB);
1550	regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1551		   & AR_PHY_ANT_DIV_MAIN_LNACONF);
1552	regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1553		   & AR_PHY_ANT_DIV_ALT_LNACONF);
1554	regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1555		   & AR_PHY_ANT_FAST_DIV_BIAS);
1556	regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1557		   & AR_PHY_ANT_DIV_MAIN_GAINTB);
1558	regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1559		   & AR_PHY_ANT_DIV_ALT_GAINTB);
1560
1561	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1562}
1563
1564#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1565
1566static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1567{
1568	struct ath9k_hw_capabilities *pCap = &ah->caps;
1569	u8 ant_div_ctl1;
1570	u32 regval;
1571
1572	if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1573		return;
1574
1575	if (AR_SREV_9485(ah)) {
1576		regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1577						 IS_CHAN_2GHZ(ah->curchan));
1578		if (enable) {
1579			regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1580			regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1581		}
1582		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1583			      AR_SWITCH_TABLE_COM2_ALL, regval);
1584	}
1585
1586	ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1587
1588	/*
1589	 * Set MAIN/ALT LNA conf.
1590	 * Set MAIN/ALT gain_tb.
1591	 */
1592	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1593	regval &= (~AR_ANT_DIV_CTRL_ALL);
1594	regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1595	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1596
1597	if (AR_SREV_9485_11_OR_LATER(ah)) {
1598		/*
1599		 * Enable LNA diversity.
1600		 */
1601		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1602		regval &= ~AR_PHY_ANT_DIV_LNADIV;
1603		regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1604		if (enable)
1605			regval |= AR_ANT_DIV_ENABLE;
1606
1607		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1608
1609		/*
1610		 * Enable fast antenna diversity.
1611		 */
1612		regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1613		regval &= ~AR_FAST_DIV_ENABLE;
1614		regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1615		if (enable)
1616			regval |= AR_FAST_DIV_ENABLE;
1617
1618		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1619
1620		if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1621			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1622			regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1623				     AR_PHY_ANT_DIV_ALT_LNACONF |
1624				     AR_PHY_ANT_DIV_ALT_GAINTB |
1625				     AR_PHY_ANT_DIV_MAIN_GAINTB));
1626			/*
1627			 * Set MAIN to LNA1 and ALT to LNA2 at the
1628			 * beginning.
1629			 */
1630			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1631				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1632			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1633				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
1634			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1635		}
1636	} else if (AR_SREV_9565(ah)) {
1637		if (enable) {
1638			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1639				    AR_ANT_DIV_ENABLE);
1640			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1641				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
1642			REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1643				    AR_FAST_DIV_ENABLE);
1644			REG_SET_BIT(ah, AR_PHY_RESTART,
1645				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1646			REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1647				    AR_BTCOEX_WL_LNADIV_FORCE_ON);
1648		} else {
1649			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1650				    AR_ANT_DIV_ENABLE);
1651			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1652				    (1 << AR_PHY_ANT_SW_RX_PROT_S));
1653			REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1654				    AR_FAST_DIV_ENABLE);
1655			REG_CLR_BIT(ah, AR_PHY_RESTART,
1656				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1657			REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1658				    AR_BTCOEX_WL_LNADIV_FORCE_ON);
1659
1660			regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1661			regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1662				    AR_PHY_ANT_DIV_ALT_LNACONF |
1663				    AR_PHY_ANT_DIV_MAIN_GAINTB |
1664				    AR_PHY_ANT_DIV_ALT_GAINTB);
1665			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1666				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1667			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1668				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
1669			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1670		}
1671	}
1672}
1673
1674#endif
1675
1676static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1677				      struct ath9k_channel *chan,
1678				      u8 *ini_reloaded)
1679{
1680	unsigned int regWrites = 0;
1681	u32 modesIndex, txgain_index;
1682
1683	if (IS_CHAN_5GHZ(chan))
1684		modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1685	else
1686		modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1687
1688	txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1689
1690	if (modesIndex == ah->modes_index) {
1691		*ini_reloaded = false;
1692		goto set_rfmode;
1693	}
1694
1695	ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1696	ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1697	ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1698	ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1699
1700	if (AR_SREV_9462_20_OR_LATER(ah))
1701		ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1702				   modesIndex);
1703
1704	REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
1705
1706	if (AR_SREV_9462_20_OR_LATER(ah)) {
1707		/*
1708		 * CUS217 mix LNA mode.
1709		 */
1710		if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1711			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1712					1, regWrites);
1713			REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1714					modesIndex, regWrites);
1715		}
1716	}
1717
1718	/*
1719	 * For 5GHz channels requiring Fast Clock, apply
1720	 * different modal values.
1721	 */
1722	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1723		REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1724
1725	if (AR_SREV_9565(ah))
1726		REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1727
1728	/*
1729	 * JAPAN regulatory.
1730	 */
1731	if (chan->channel == 2484)
1732		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1733
1734	ah->modes_index = modesIndex;
1735	*ini_reloaded = true;
1736
1737set_rfmode:
1738	ar9003_hw_set_rfmode(ah, chan);
1739	return 0;
1740}
1741
1742static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1743					   struct ath_spec_scan *param)
1744{
1745	u8 count;
1746
1747	if (!param->enabled) {
1748		REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1749			    AR_PHY_SPECTRAL_SCAN_ENABLE);
1750		return;
1751	}
1752
1753	REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1754	REG_SET_BIT(ah, AR_PHY_SP

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