/drivers/ide/slc90e66.c

http://github.com/mirrors/linux · C · 182 lines · 143 code · 26 blank · 13 comment · 17 complexity · af7e7a5a0a66a5b05105925dbce0a86d MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
  4. * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
  5. *
  6. * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
  7. * but this keeps the ISA-Bridge and slots alive.
  8. *
  9. */
  10. #include <linux/types.h>
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/pci.h>
  14. #include <linux/ide.h>
  15. #include <linux/init.h>
  16. #define DRV_NAME "slc90e66"
  17. static DEFINE_SPINLOCK(slc90e66_lock);
  18. static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  19. {
  20. struct pci_dev *dev = to_pci_dev(hwif->dev);
  21. int is_slave = drive->dn & 1;
  22. int master_port = hwif->channel ? 0x42 : 0x40;
  23. int slave_port = 0x44;
  24. unsigned long flags;
  25. u16 master_data;
  26. u8 slave_data;
  27. int control = 0;
  28. const u8 pio = drive->pio_mode - XFER_PIO_0;
  29. /* ISP RTC */
  30. static const u8 timings[][2] = {
  31. { 0, 0 },
  32. { 0, 0 },
  33. { 1, 0 },
  34. { 2, 1 },
  35. { 2, 3 }, };
  36. spin_lock_irqsave(&slc90e66_lock, flags);
  37. pci_read_config_word(dev, master_port, &master_data);
  38. if (pio > 1)
  39. control |= 1; /* Programmable timing on */
  40. if (drive->media == ide_disk)
  41. control |= 4; /* Prefetch, post write */
  42. if (ide_pio_need_iordy(drive, pio))
  43. control |= 2; /* IORDY */
  44. if (is_slave) {
  45. master_data |= 0x4000;
  46. master_data &= ~0x0070;
  47. if (pio > 1) {
  48. /* Set PPE, IE and TIME */
  49. master_data |= control << 4;
  50. }
  51. pci_read_config_byte(dev, slave_port, &slave_data);
  52. slave_data &= hwif->channel ? 0x0f : 0xf0;
  53. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  54. (hwif->channel ? 4 : 0);
  55. } else {
  56. master_data &= ~0x3307;
  57. if (pio > 1) {
  58. /* enable PPE, IE and TIME */
  59. master_data |= control;
  60. }
  61. master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  62. }
  63. pci_write_config_word(dev, master_port, master_data);
  64. if (is_slave)
  65. pci_write_config_byte(dev, slave_port, slave_data);
  66. spin_unlock_irqrestore(&slc90e66_lock, flags);
  67. }
  68. static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  69. {
  70. struct pci_dev *dev = to_pci_dev(hwif->dev);
  71. u8 maslave = hwif->channel ? 0x42 : 0x40;
  72. int sitre = 0, a_speed = 7 << (drive->dn * 4);
  73. int u_speed = 0, u_flag = 1 << drive->dn;
  74. u16 reg4042, reg44, reg48, reg4a;
  75. const u8 speed = drive->dma_mode;
  76. pci_read_config_word(dev, maslave, &reg4042);
  77. sitre = (reg4042 & 0x4000) ? 1 : 0;
  78. pci_read_config_word(dev, 0x44, &reg44);
  79. pci_read_config_word(dev, 0x48, &reg48);
  80. pci_read_config_word(dev, 0x4a, &reg4a);
  81. if (speed >= XFER_UDMA_0) {
  82. u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
  83. if (!(reg48 & u_flag))
  84. pci_write_config_word(dev, 0x48, reg48|u_flag);
  85. if ((reg4a & a_speed) != u_speed) {
  86. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  87. pci_read_config_word(dev, 0x4a, &reg4a);
  88. pci_write_config_word(dev, 0x4a, reg4a|u_speed);
  89. }
  90. } else {
  91. const u8 mwdma_to_pio[] = { 0, 3, 4 };
  92. if (reg48 & u_flag)
  93. pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
  94. if (reg4a & a_speed)
  95. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  96. if (speed >= XFER_MW_DMA_0)
  97. drive->pio_mode =
  98. mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
  99. else
  100. drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
  101. slc90e66_set_pio_mode(hwif, drive);
  102. }
  103. }
  104. static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
  105. {
  106. struct pci_dev *dev = to_pci_dev(hwif->dev);
  107. u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
  108. pci_read_config_byte(dev, 0x47, &reg47);
  109. /* bit[0(1)]: 0:80, 1:40 */
  110. return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
  111. }
  112. static const struct ide_port_ops slc90e66_port_ops = {
  113. .set_pio_mode = slc90e66_set_pio_mode,
  114. .set_dma_mode = slc90e66_set_dma_mode,
  115. .cable_detect = slc90e66_cable_detect,
  116. };
  117. static const struct ide_port_info slc90e66_chipset = {
  118. .name = DRV_NAME,
  119. .enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
  120. .port_ops = &slc90e66_port_ops,
  121. .pio_mask = ATA_PIO4,
  122. .swdma_mask = ATA_SWDMA2_ONLY,
  123. .mwdma_mask = ATA_MWDMA12_ONLY,
  124. .udma_mask = ATA_UDMA4,
  125. };
  126. static int slc90e66_init_one(struct pci_dev *dev,
  127. const struct pci_device_id *id)
  128. {
  129. return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
  130. }
  131. static const struct pci_device_id slc90e66_pci_tbl[] = {
  132. { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
  133. { 0, },
  134. };
  135. MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
  136. static struct pci_driver slc90e66_pci_driver = {
  137. .name = "SLC90e66_IDE",
  138. .id_table = slc90e66_pci_tbl,
  139. .probe = slc90e66_init_one,
  140. .remove = ide_pci_remove,
  141. .suspend = ide_pci_suspend,
  142. .resume = ide_pci_resume,
  143. };
  144. static int __init slc90e66_ide_init(void)
  145. {
  146. return ide_pci_register_driver(&slc90e66_pci_driver);
  147. }
  148. static void __exit slc90e66_ide_exit(void)
  149. {
  150. pci_unregister_driver(&slc90e66_pci_driver);
  151. }
  152. module_init(slc90e66_ide_init);
  153. module_exit(slc90e66_ide_exit);
  154. MODULE_AUTHOR("Andre Hedrick");
  155. MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
  156. MODULE_LICENSE("GPL");