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/drivers/ide/hpt366.c

http://github.com/mirrors/linux
C | 1545 lines | 1004 code | 196 blank | 345 comment | 127 complexity | 024f15014175aaaacb9f6ea56483016c MD5 | raw file
   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
   4 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
   5 * Portions Copyright (C) 2003		Red Hat Inc
   6 * Portions Copyright (C) 2007		Bartlomiej Zolnierkiewicz
   7 * Portions Copyright (C) 2005-2009	MontaVista Software, Inc.
   8 *
   9 * Thanks to HighPoint Technologies for their assistance, and hardware.
  10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12 * development and support.
  13 *
  14 *
  15 * HighPoint has its own drivers (open source except for the RAID part)
  16 * available from http://www.highpoint-tech.com/USA_new/service_support.htm 
  17 * This may be useful to anyone wanting to work on this driver, however  do not
  18 * trust  them too much since the code tends to become less and less meaningful
  19 * as the time passes... :-/
  20 *
  21 * Note that final HPT370 support was done by force extraction of GPL.
  22 *
  23 * - add function for getting/setting power status of drive
  24 * - the HPT370's state machine can get confused. reset it before each dma 
  25 *   xfer to prevent that from happening.
  26 * - reset state engine whenever we get an error.
  27 * - check for busmaster state at end of dma. 
  28 * - use new highpoint timings.
  29 * - detect bus speed using highpoint register.
  30 * - use pll if we don't have a clock table. added a 66MHz table that's
  31 *   just 2x the 33MHz table.
  32 * - removed turnaround. NOTE: we never want to switch between pll and
  33 *   pci clocks as the chip can glitch in those cases. the highpoint
  34 *   approved workaround slows everything down too much to be useful. in
  35 *   addition, we would have to serialize access to each chip.
  36 * 	Adrian Sun <a.sun@sun.com>
  37 *
  38 * add drive timings for 66MHz PCI bus,
  39 * fix ATA Cable signal detection, fix incorrect /proc info
  40 * add /proc display for per-drive PIO/DMA/UDMA mode and
  41 * per-channel ATA-33/66 Cable detect.
  42 * 	Duncan Laurie <void@sun.com>
  43 *
  44 * fixup /proc output for multiple controllers
  45 *	Tim Hockin <thockin@sun.com>
  46 *
  47 * On hpt366: 
  48 * Reset the hpt366 on error, reset on dma
  49 * Fix disabling Fast Interrupt hpt366.
  50 * 	Mike Waychison <crlf@sun.com>
  51 *
  52 * Added support for 372N clocking and clock switching. The 372N needs
  53 * different clocks on read/write. This requires overloading rw_disk and
  54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55 * keeping me sane. 
  56 *		Alan Cox <alan@lxorguk.ukuu.org.uk>
  57 *
  58 * - fix the clock turnaround code: it was writing to the wrong ports when
  59 *   called for the secondary channel, caching the current clock mode per-
  60 *   channel caused the cached register value to get out of sync with the
  61 *   actual one, the channels weren't serialized, the turnaround shouldn't
  62 *   be done on 66 MHz PCI bus
  63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
  64 *   does not allow for this speed anyway
  65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
  66 *   their primary channel is kind of virtual, it isn't tied to any pins)
  67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
  68 *   HPT37x chip family; save space by introducing the separate transfer mode
  69 *   table in which the mode lookup is done
  70 * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  71 *   the wrong PCI frequency since DPLL has already been calibrated by BIOS;
  72 *   read it only from the function 0 of HPT374 chips
  73 * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  74 *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  75 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  76 *   they tamper with its fields
  77 * - pass  to the init_setup handlers a copy of the ide_pci_device_t structure
  78 *   since they may tamper with its fields
  79 * - prefix the driver startup messages with the real chip name
  80 * - claim the extra 240 bytes of I/O space for all chips
  81 * - optimize the UltraDMA filtering and the drive list lookup code
  82 * - use pci_get_slot() to get to the function 1 of HPT36x/374
  83 * - cache offset of the channel's misc. control registers (MCRs) being used
  84 *   throughout the driver
  85 * - only touch the relevant MCR when detecting the cable type on HPT374's
  86 *   function 1
  87 * - rename all the register related variables consistently
  88 * - move all the interrupt twiddling code from the speedproc handlers into
  89 *   init_hwif_hpt366(), also grouping all the DMA related code together there
  90 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
  91 *   separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
  92 *   when setting an UltraDMA mode
  93 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
  94 *   the best possible one
  95 * - clean up DMA timeout handling for HPT370
  96 * - switch to using the enumeration type to differ between the numerous chip
  97 *   variants, matching PCI device/revision ID with the chip type early, at the
  98 *   init_setup stage
  99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
 100 *   stop duplicating it for each channel by storing the pointer in the pci_dev
 101 *   structure: first, at the init_setup stage, point it to a static "template"
 102 *   with only the chip type and its specific base DPLL frequency, the highest
 103 *   UltraDMA mode, and the chip settings table pointer filled,  then, at the
 104 *   init_chipset stage, allocate per-chip instance  and fill it with the rest
 105 *   of the necessary information
 106 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
 107 *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
 108 *   frequency
 109 * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
 110 *   anything  newer than HPT370/A (except HPT374 that is not capable of this
 111 *   mode according to the manual)
 112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
 113 *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
 114 *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
 115 *   the register setting lists into the table indexed by the clock selected
 116 * - set the correct hwif->ultra_mask for each individual chip
 117 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
 118 * - stop resetting HPT370's state machine before each DMA transfer as that has
 119 *   caused more harm than good
 120 *	Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
 121 */
 122
 123#include <linux/types.h>
 124#include <linux/module.h>
 125#include <linux/kernel.h>
 126#include <linux/delay.h>
 127#include <linux/blkdev.h>
 128#include <linux/interrupt.h>
 129#include <linux/pci.h>
 130#include <linux/init.h>
 131#include <linux/ide.h>
 132#include <linux/slab.h>
 133
 134#include <linux/uaccess.h>
 135#include <asm/io.h>
 136
 137#define DRV_NAME "hpt366"
 138
 139/* various tuning parameters */
 140#undef	HPT_RESET_STATE_ENGINE
 141#undef	HPT_DELAY_INTERRUPT
 142
 143static const char *bad_ata100_5[] = {
 144	"IBM-DTLA-307075",
 145	"IBM-DTLA-307060",
 146	"IBM-DTLA-307045",
 147	"IBM-DTLA-307030",
 148	"IBM-DTLA-307020",
 149	"IBM-DTLA-307015",
 150	"IBM-DTLA-305040",
 151	"IBM-DTLA-305030",
 152	"IBM-DTLA-305020",
 153	"IC35L010AVER07-0",
 154	"IC35L020AVER07-0",
 155	"IC35L030AVER07-0",
 156	"IC35L040AVER07-0",
 157	"IC35L060AVER07-0",
 158	"WDC AC310200R",
 159	NULL
 160};
 161
 162static const char *bad_ata66_4[] = {
 163	"IBM-DTLA-307075",
 164	"IBM-DTLA-307060",
 165	"IBM-DTLA-307045",
 166	"IBM-DTLA-307030",
 167	"IBM-DTLA-307020",
 168	"IBM-DTLA-307015",
 169	"IBM-DTLA-305040",
 170	"IBM-DTLA-305030",
 171	"IBM-DTLA-305020",
 172	"IC35L010AVER07-0",
 173	"IC35L020AVER07-0",
 174	"IC35L030AVER07-0",
 175	"IC35L040AVER07-0",
 176	"IC35L060AVER07-0",
 177	"WDC AC310200R",
 178	"MAXTOR STM3320620A",
 179	NULL
 180};
 181
 182static const char *bad_ata66_3[] = {
 183	"WDC AC310200R",
 184	NULL
 185};
 186
 187static const char *bad_ata33[] = {
 188	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 189	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 190	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 191	"Maxtor 90510D4",
 192	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 193	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 194	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 195	NULL
 196};
 197
 198static u8 xfer_speeds[] = {
 199	XFER_UDMA_6,
 200	XFER_UDMA_5,
 201	XFER_UDMA_4,
 202	XFER_UDMA_3,
 203	XFER_UDMA_2,
 204	XFER_UDMA_1,
 205	XFER_UDMA_0,
 206
 207	XFER_MW_DMA_2,
 208	XFER_MW_DMA_1,
 209	XFER_MW_DMA_0,
 210
 211	XFER_PIO_4,
 212	XFER_PIO_3,
 213	XFER_PIO_2,
 214	XFER_PIO_1,
 215	XFER_PIO_0
 216};
 217
 218/* Key for bus clock timings
 219 * 36x   37x
 220 * bits  bits
 221 * 0:3	 0:3	data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 222 *		cycles = value + 1
 223 * 4:7	 4:8	data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 224 *		cycles = value + 1
 225 * 8:11  9:12	cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 226 *		register access.
 227 * 12:15 13:17	cmd_low_time. Active time of DIOW_/DIOR_ during task file
 228 *		register access.
 229 * 16:18 18:20	udma_cycle_time. Clock cycles for UDMA xfer.
 230 * -	 21	CLK frequency: 0=ATA clock, 1=dual ATA clock.
 231 * 19:21 22:24	pre_high_time. Time to initialize the 1st cycle for PIO and
 232 *		MW DMA xfer.
 233 * 22:24 25:27	cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 234 *		task file register access.
 235 * 28	 28	UDMA enable.
 236 * 29	 29	DMA  enable.
 237 * 30	 30	PIO MST enable. If set, the chip is in bus master mode during
 238 *		PIO xfer.
 239 * 31	 31	FIFO enable.
 240 */
 241
 242static u32 forty_base_hpt36x[] = {
 243	/* XFER_UDMA_6 */	0x900fd943,
 244	/* XFER_UDMA_5 */	0x900fd943,
 245	/* XFER_UDMA_4 */	0x900fd943,
 246	/* XFER_UDMA_3 */	0x900ad943,
 247	/* XFER_UDMA_2 */	0x900bd943,
 248	/* XFER_UDMA_1 */	0x9008d943,
 249	/* XFER_UDMA_0 */	0x9008d943,
 250
 251	/* XFER_MW_DMA_2 */	0xa008d943,
 252	/* XFER_MW_DMA_1 */	0xa010d955,
 253	/* XFER_MW_DMA_0 */	0xa010d9fc,
 254
 255	/* XFER_PIO_4 */	0xc008d963,
 256	/* XFER_PIO_3 */	0xc010d974,
 257	/* XFER_PIO_2 */	0xc010d997,
 258	/* XFER_PIO_1 */	0xc010d9c7,
 259	/* XFER_PIO_0 */	0xc018d9d9
 260};
 261
 262static u32 thirty_three_base_hpt36x[] = {
 263	/* XFER_UDMA_6 */	0x90c9a731,
 264	/* XFER_UDMA_5 */	0x90c9a731,
 265	/* XFER_UDMA_4 */	0x90c9a731,
 266	/* XFER_UDMA_3 */	0x90cfa731,
 267	/* XFER_UDMA_2 */	0x90caa731,
 268	/* XFER_UDMA_1 */	0x90cba731,
 269	/* XFER_UDMA_0 */	0x90c8a731,
 270
 271	/* XFER_MW_DMA_2 */	0xa0c8a731,
 272	/* XFER_MW_DMA_1 */	0xa0c8a732,	/* 0xa0c8a733 */
 273	/* XFER_MW_DMA_0 */	0xa0c8a797,
 274
 275	/* XFER_PIO_4 */	0xc0c8a731,
 276	/* XFER_PIO_3 */	0xc0c8a742,
 277	/* XFER_PIO_2 */	0xc0d0a753,
 278	/* XFER_PIO_1 */	0xc0d0a7a3,	/* 0xc0d0a793 */
 279	/* XFER_PIO_0 */	0xc0d0a7aa	/* 0xc0d0a7a7 */
 280};
 281
 282static u32 twenty_five_base_hpt36x[] = {
 283	/* XFER_UDMA_6 */	0x90c98521,
 284	/* XFER_UDMA_5 */	0x90c98521,
 285	/* XFER_UDMA_4 */	0x90c98521,
 286	/* XFER_UDMA_3 */	0x90cf8521,
 287	/* XFER_UDMA_2 */	0x90cf8521,
 288	/* XFER_UDMA_1 */	0x90cb8521,
 289	/* XFER_UDMA_0 */	0x90cb8521,
 290
 291	/* XFER_MW_DMA_2 */	0xa0ca8521,
 292	/* XFER_MW_DMA_1 */	0xa0ca8532,
 293	/* XFER_MW_DMA_0 */	0xa0ca8575,
 294
 295	/* XFER_PIO_4 */	0xc0ca8521,
 296	/* XFER_PIO_3 */	0xc0ca8532,
 297	/* XFER_PIO_2 */	0xc0ca8542,
 298	/* XFER_PIO_1 */	0xc0d08572,
 299	/* XFER_PIO_0 */	0xc0d08585
 300};
 301
 302/*
 303 * The following are the new timing tables with PIO mode data/taskfile transfer
 304 * overclocking fixed...
 305 */
 306
 307/* This table is taken from the HPT370 data manual rev. 1.02 */
 308static u32 thirty_three_base_hpt37x[] = {
 309	/* XFER_UDMA_6 */	0x16455031,	/* 0x16655031 ?? */
 310	/* XFER_UDMA_5 */	0x16455031,
 311	/* XFER_UDMA_4 */	0x16455031,
 312	/* XFER_UDMA_3 */	0x166d5031,
 313	/* XFER_UDMA_2 */	0x16495031,
 314	/* XFER_UDMA_1 */	0x164d5033,
 315	/* XFER_UDMA_0 */	0x16515097,
 316
 317	/* XFER_MW_DMA_2 */	0x26515031,
 318	/* XFER_MW_DMA_1 */	0x26515033,
 319	/* XFER_MW_DMA_0 */	0x26515097,
 320
 321	/* XFER_PIO_4 */	0x06515021,
 322	/* XFER_PIO_3 */	0x06515022,
 323	/* XFER_PIO_2 */	0x06515033,
 324	/* XFER_PIO_1 */	0x06915065,
 325	/* XFER_PIO_0 */	0x06d1508a
 326};
 327
 328static u32 fifty_base_hpt37x[] = {
 329	/* XFER_UDMA_6 */	0x1a861842,
 330	/* XFER_UDMA_5 */	0x1a861842,
 331	/* XFER_UDMA_4 */	0x1aae1842,
 332	/* XFER_UDMA_3 */	0x1a8e1842,
 333	/* XFER_UDMA_2 */	0x1a0e1842,
 334	/* XFER_UDMA_1 */	0x1a161854,
 335	/* XFER_UDMA_0 */	0x1a1a18ea,
 336
 337	/* XFER_MW_DMA_2 */	0x2a821842,
 338	/* XFER_MW_DMA_1 */	0x2a821854,
 339	/* XFER_MW_DMA_0 */	0x2a8218ea,
 340
 341	/* XFER_PIO_4 */	0x0a821842,
 342	/* XFER_PIO_3 */	0x0a821843,
 343	/* XFER_PIO_2 */	0x0a821855,
 344	/* XFER_PIO_1 */	0x0ac218a8,
 345	/* XFER_PIO_0 */	0x0b02190c
 346};
 347
 348static u32 sixty_six_base_hpt37x[] = {
 349	/* XFER_UDMA_6 */	0x1c86fe62,
 350	/* XFER_UDMA_5 */	0x1caefe62,	/* 0x1c8afe62 */
 351	/* XFER_UDMA_4 */	0x1c8afe62,
 352	/* XFER_UDMA_3 */	0x1c8efe62,
 353	/* XFER_UDMA_2 */	0x1c92fe62,
 354	/* XFER_UDMA_1 */	0x1c9afe62,
 355	/* XFER_UDMA_0 */	0x1c82fe62,
 356
 357	/* XFER_MW_DMA_2 */	0x2c82fe62,
 358	/* XFER_MW_DMA_1 */	0x2c82fe66,
 359	/* XFER_MW_DMA_0 */	0x2c82ff2e,
 360
 361	/* XFER_PIO_4 */	0x0c82fe62,
 362	/* XFER_PIO_3 */	0x0c82fe84,
 363	/* XFER_PIO_2 */	0x0c82fea6,
 364	/* XFER_PIO_1 */	0x0d02ff26,
 365	/* XFER_PIO_0 */	0x0d42ff7f
 366};
 367
 368#define HPT371_ALLOW_ATA133_6		1
 369#define HPT302_ALLOW_ATA133_6		1
 370#define HPT372_ALLOW_ATA133_6		1
 371#define HPT370_ALLOW_ATA100_5		0
 372#define HPT366_ALLOW_ATA66_4		1
 373#define HPT366_ALLOW_ATA66_3		1
 374
 375/* Supported ATA clock frequencies */
 376enum ata_clock {
 377	ATA_CLOCK_25MHZ,
 378	ATA_CLOCK_33MHZ,
 379	ATA_CLOCK_40MHZ,
 380	ATA_CLOCK_50MHZ,
 381	ATA_CLOCK_66MHZ,
 382	NUM_ATA_CLOCKS
 383};
 384
 385struct hpt_timings {
 386	u32 pio_mask;
 387	u32 dma_mask;
 388	u32 ultra_mask;
 389	u32 *clock_table[NUM_ATA_CLOCKS];
 390};
 391
 392/*
 393 *	Hold all the HighPoint chip information in one place.
 394 */
 395
 396struct hpt_info {
 397	char *chip_name;	/* Chip name */
 398	u8 chip_type;		/* Chip type */
 399	u8 udma_mask;		/* Allowed UltraDMA modes mask. */
 400	u8 dpll_clk;		/* DPLL clock in MHz */
 401	u8 pci_clk;		/* PCI  clock in MHz */
 402	struct hpt_timings *timings; /* Chipset timing data */
 403	u8 clock;		/* ATA clock selected */
 404};
 405
 406/* Supported HighPoint chips */
 407enum {
 408	HPT36x,
 409	HPT370,
 410	HPT370A,
 411	HPT374,
 412	HPT372,
 413	HPT372A,
 414	HPT302,
 415	HPT371,
 416	HPT372N,
 417	HPT302N,
 418	HPT371N
 419};
 420
 421static struct hpt_timings hpt36x_timings = {
 422	.pio_mask	= 0xc1f8ffff,
 423	.dma_mask	= 0x303800ff,
 424	.ultra_mask	= 0x30070000,
 425	.clock_table	= {
 426		[ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
 427		[ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
 428		[ATA_CLOCK_40MHZ] = forty_base_hpt36x,
 429		[ATA_CLOCK_50MHZ] = NULL,
 430		[ATA_CLOCK_66MHZ] = NULL
 431	}
 432};
 433
 434static struct hpt_timings hpt37x_timings = {
 435	.pio_mask	= 0xcfc3ffff,
 436	.dma_mask	= 0x31c001ff,
 437	.ultra_mask	= 0x303c0000,
 438	.clock_table	= {
 439		[ATA_CLOCK_25MHZ] = NULL,
 440		[ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
 441		[ATA_CLOCK_40MHZ] = NULL,
 442		[ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
 443		[ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
 444	}
 445};
 446
 447static const struct hpt_info hpt36x = {
 448	.chip_name	= "HPT36x",
 449	.chip_type	= HPT36x,
 450	.udma_mask	= HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
 451	.dpll_clk	= 0,	/* no DPLL */
 452	.timings	= &hpt36x_timings
 453};
 454
 455static const struct hpt_info hpt370 = {
 456	.chip_name	= "HPT370",
 457	.chip_type	= HPT370,
 458	.udma_mask	= HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
 459	.dpll_clk	= 48,
 460	.timings	= &hpt37x_timings
 461};
 462
 463static const struct hpt_info hpt370a = {
 464	.chip_name	= "HPT370A",
 465	.chip_type	= HPT370A,
 466	.udma_mask	= HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
 467	.dpll_clk	= 48,
 468	.timings	= &hpt37x_timings
 469};
 470
 471static const struct hpt_info hpt374 = {
 472	.chip_name	= "HPT374",
 473	.chip_type	= HPT374,
 474	.udma_mask	= ATA_UDMA5,
 475	.dpll_clk	= 48,
 476	.timings	= &hpt37x_timings
 477};
 478
 479static const struct hpt_info hpt372 = {
 480	.chip_name	= "HPT372",
 481	.chip_type	= HPT372,
 482	.udma_mask	= HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 483	.dpll_clk	= 55,
 484	.timings	= &hpt37x_timings
 485};
 486
 487static const struct hpt_info hpt372a = {
 488	.chip_name	= "HPT372A",
 489	.chip_type	= HPT372A,
 490	.udma_mask	= HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 491	.dpll_clk	= 66,
 492	.timings	= &hpt37x_timings
 493};
 494
 495static const struct hpt_info hpt302 = {
 496	.chip_name	= "HPT302",
 497	.chip_type	= HPT302,
 498	.udma_mask	= HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 499	.dpll_clk	= 66,
 500	.timings	= &hpt37x_timings
 501};
 502
 503static const struct hpt_info hpt371 = {
 504	.chip_name	= "HPT371",
 505	.chip_type	= HPT371,
 506	.udma_mask	= HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 507	.dpll_clk	= 66,
 508	.timings	= &hpt37x_timings
 509};
 510
 511static const struct hpt_info hpt372n = {
 512	.chip_name	= "HPT372N",
 513	.chip_type	= HPT372N,
 514	.udma_mask	= HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 515	.dpll_clk	= 77,
 516	.timings	= &hpt37x_timings
 517};
 518
 519static const struct hpt_info hpt302n = {
 520	.chip_name	= "HPT302N",
 521	.chip_type	= HPT302N,
 522	.udma_mask	= HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 523	.dpll_clk	= 77,
 524	.timings	= &hpt37x_timings
 525};
 526
 527static const struct hpt_info hpt371n = {
 528	.chip_name	= "HPT371N",
 529	.chip_type	= HPT371N,
 530	.udma_mask	= HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
 531	.dpll_clk	= 77,
 532	.timings	= &hpt37x_timings
 533};
 534
 535static bool check_in_drive_list(ide_drive_t *drive, const char **list)
 536{
 537	return match_string(list, -1, (char *)&drive->id[ATA_ID_PROD]) >= 0;
 538}
 539
 540static struct hpt_info *hpt3xx_get_info(struct device *dev)
 541{
 542	struct ide_host *host	= dev_get_drvdata(dev);
 543	struct hpt_info *info	= (struct hpt_info *)host->host_priv;
 544
 545	return dev == host->dev[1] ? info + 1 : info;
 546}
 547
 548/*
 549 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
 550 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
 551 */
 552
 553static u8 hpt3xx_udma_filter(ide_drive_t *drive)
 554{
 555	ide_hwif_t *hwif	= drive->hwif;
 556	struct hpt_info *info	= hpt3xx_get_info(hwif->dev);
 557	u8 mask 		= hwif->ultra_mask;
 558
 559	switch (info->chip_type) {
 560	case HPT36x:
 561		if (!HPT366_ALLOW_ATA66_4 ||
 562		    check_in_drive_list(drive, bad_ata66_4))
 563			mask = ATA_UDMA3;
 564
 565		if (!HPT366_ALLOW_ATA66_3 ||
 566		    check_in_drive_list(drive, bad_ata66_3))
 567			mask = ATA_UDMA2;
 568		break;
 569	case HPT370:
 570		if (!HPT370_ALLOW_ATA100_5 ||
 571		    check_in_drive_list(drive, bad_ata100_5))
 572			mask = ATA_UDMA4;
 573		break;
 574	case HPT370A:
 575		if (!HPT370_ALLOW_ATA100_5 ||
 576		    check_in_drive_list(drive, bad_ata100_5))
 577			return ATA_UDMA4;
 578		/* fall through */
 579	case HPT372 :
 580	case HPT372A:
 581	case HPT372N:
 582	case HPT374 :
 583		if (ata_id_is_sata(drive->id))
 584			mask &= ~0x0e;
 585		/* fall through */
 586	default:
 587		return mask;
 588	}
 589
 590	return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
 591}
 592
 593static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
 594{
 595	ide_hwif_t *hwif	= drive->hwif;
 596	struct hpt_info *info	= hpt3xx_get_info(hwif->dev);
 597
 598	switch (info->chip_type) {
 599	case HPT372 :
 600	case HPT372A:
 601	case HPT372N:
 602	case HPT374 :
 603		if (ata_id_is_sata(drive->id))
 604			return 0x00;
 605		/* fall through */
 606	default:
 607		return 0x07;
 608	}
 609}
 610
 611static u32 get_speed_setting(u8 speed, struct hpt_info *info)
 612{
 613	int i;
 614
 615	/*
 616	 * Lookup the transfer mode table to get the index into
 617	 * the timing table.
 618	 *
 619	 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 620	 */
 621	for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 622		if (xfer_speeds[i] == speed)
 623			break;
 624
 625	return info->timings->clock_table[info->clock][i];
 626}
 627
 628static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 629{
 630	struct pci_dev *dev	= to_pci_dev(hwif->dev);
 631	struct hpt_info *info	= hpt3xx_get_info(hwif->dev);
 632	struct hpt_timings *t	= info->timings;
 633	u8  itr_addr		= 0x40 + (drive->dn * 4);
 634	u32 old_itr		= 0;
 635	const u8 speed		= drive->dma_mode;
 636	u32 new_itr		= get_speed_setting(speed, info);
 637	u32 itr_mask		= speed < XFER_MW_DMA_0 ? t->pio_mask :
 638				 (speed < XFER_UDMA_0   ? t->dma_mask :
 639							  t->ultra_mask);
 640
 641	pci_read_config_dword(dev, itr_addr, &old_itr);
 642	new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
 643	/*
 644	 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
 645	 * to avoid problems handling I/O errors later
 646	 */
 647	new_itr &= ~0xc0000000;
 648
 649	pci_write_config_dword(dev, itr_addr, new_itr);
 650}
 651
 652static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 653{
 654	drive->dma_mode = drive->pio_mode;
 655	hpt3xx_set_mode(hwif, drive);
 656}
 657
 658static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
 659{
 660	ide_hwif_t *hwif	= drive->hwif;
 661	struct pci_dev	*dev	= to_pci_dev(hwif->dev);
 662	struct hpt_info *info	= hpt3xx_get_info(hwif->dev);
 663
 664	if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
 665		return;
 666
 667	if (info->chip_type >= HPT370) {
 668		u8 scr1 = 0;
 669
 670		pci_read_config_byte(dev, 0x5a, &scr1);
 671		if (((scr1 & 0x10) >> 4) != mask) {
 672			if (mask)
 673				scr1 |=  0x10;
 674			else
 675				scr1 &= ~0x10;
 676			pci_write_config_byte(dev, 0x5a, scr1);
 677		}
 678	} else if (mask)
 679		disable_irq(hwif->irq);
 680	else
 681		enable_irq(hwif->irq);
 682}
 683
 684/*
 685 * This is specific to the HPT366 UDMA chipset
 686 * by HighPoint|Triones Technologies, Inc.
 687 */
 688static void hpt366_dma_lost_irq(ide_drive_t *drive)
 689{
 690	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
 691	u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
 692
 693	pci_read_config_byte(dev, 0x50, &mcr1);
 694	pci_read_config_byte(dev, 0x52, &mcr3);
 695	pci_read_config_byte(dev, 0x5a, &scr1);
 696	printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
 697		drive->name, __func__, mcr1, mcr3, scr1);
 698	if (scr1 & 0x10)
 699		pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 700	ide_dma_lost_irq(drive);
 701}
 702
 703static void hpt370_clear_engine(ide_drive_t *drive)
 704{
 705	ide_hwif_t *hwif = drive->hwif;
 706	struct pci_dev *dev = to_pci_dev(hwif->dev);
 707
 708	pci_write_config_byte(dev, hwif->select_data, 0x37);
 709	udelay(10);
 710}
 711
 712static void hpt370_irq_timeout(ide_drive_t *drive)
 713{
 714	ide_hwif_t *hwif	= drive->hwif;
 715	struct pci_dev *dev	= to_pci_dev(hwif->dev);
 716	u16 bfifo		= 0;
 717	u8  dma_cmd;
 718
 719	pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
 720	printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
 721
 722	/* get DMA command mode */
 723	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 724	/* stop DMA */
 725	outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
 726	hpt370_clear_engine(drive);
 727}
 728
 729static void hpt370_dma_start(ide_drive_t *drive)
 730{
 731#ifdef HPT_RESET_STATE_ENGINE
 732	hpt370_clear_engine(drive);
 733#endif
 734	ide_dma_start(drive);
 735}
 736
 737static int hpt370_dma_end(ide_drive_t *drive)
 738{
 739	ide_hwif_t *hwif	= drive->hwif;
 740	u8  dma_stat		= inb(hwif->dma_base + ATA_DMA_STATUS);
 741
 742	if (dma_stat & ATA_DMA_ACTIVE) {
 743		/* wait a little */
 744		udelay(20);
 745		dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 746		if (dma_stat & ATA_DMA_ACTIVE)
 747			hpt370_irq_timeout(drive);
 748	}
 749	return ide_dma_end(drive);
 750}
 751
 752/* returns 1 if DMA IRQ issued, 0 otherwise */
 753static int hpt374_dma_test_irq(ide_drive_t *drive)
 754{
 755	ide_hwif_t *hwif	= drive->hwif;
 756	struct pci_dev *dev	= to_pci_dev(hwif->dev);
 757	u16 bfifo		= 0;
 758	u8  dma_stat;
 759
 760	pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
 761	if (bfifo & 0x1FF) {
 762//		printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 763		return 0;
 764	}
 765
 766	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 767	/* return 1 if INTR asserted */
 768	if (dma_stat & ATA_DMA_INTR)
 769		return 1;
 770
 771	return 0;
 772}
 773
 774static int hpt374_dma_end(ide_drive_t *drive)
 775{
 776	ide_hwif_t *hwif	= drive->hwif;
 777	struct pci_dev *dev	= to_pci_dev(hwif->dev);
 778	u8 mcr	= 0, mcr_addr	= hwif->select_data;
 779	u8 bwsr = 0, mask	= hwif->channel ? 0x02 : 0x01;
 780
 781	pci_read_config_byte(dev, 0x6a, &bwsr);
 782	pci_read_config_byte(dev, mcr_addr, &mcr);
 783	if (bwsr & mask)
 784		pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
 785	return ide_dma_end(drive);
 786}
 787
 788/**
 789 *	hpt3xxn_set_clock	-	perform clock switching dance
 790 *	@hwif: hwif to switch
 791 *	@mode: clocking mode (0x21 for write, 0x23 otherwise)
 792 *
 793 *	Switch the DPLL clock on the HPT3xxN devices. This is a	right mess.
 794 */
 795
 796static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 797{
 798	unsigned long base = hwif->extra_base;
 799	u8 scr2 = inb(base + 0x6b);
 800
 801	if ((scr2 & 0x7f) == mode)
 802		return;
 803
 804	/* Tristate the bus */
 805	outb(0x80, base + 0x63);
 806	outb(0x80, base + 0x67);
 807
 808	/* Switch clock and reset channels */
 809	outb(mode, base + 0x6b);
 810	outb(0xc0, base + 0x69);
 811
 812	/*
 813	 * Reset the state machines.
 814	 * NOTE: avoid accidentally enabling the disabled channels.
 815	 */
 816	outb(inb(base + 0x60) | 0x32, base + 0x60);
 817	outb(inb(base + 0x64) | 0x32, base + 0x64);
 818
 819	/* Complete reset */
 820	outb(0x00, base + 0x69);
 821
 822	/* Reconnect channels to bus */
 823	outb(0x00, base + 0x63);
 824	outb(0x00, base + 0x67);
 825}
 826
 827/**
 828 *	hpt3xxn_rw_disk		-	prepare for I/O
 829 *	@drive: drive for command
 830 *	@rq: block request structure
 831 *
 832 *	This is called when a disk I/O is issued to HPT3xxN.
 833 *	We need it because of the clock switching.
 834 */
 835
 836static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 837{
 838	hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
 839}
 840
 841/**
 842 *	hpt37x_calibrate_dpll	-	calibrate the DPLL
 843 *	@dev: PCI device
 844 *
 845 *	Perform a calibration cycle on the DPLL.
 846 *	Returns 1 if this succeeds
 847 */
 848static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
 849{
 850	u32 dpll = (f_high << 16) | f_low | 0x100;
 851	u8  scr2;
 852	int i;
 853
 854	pci_write_config_dword(dev, 0x5c, dpll);
 855
 856	/* Wait for oscillator ready */
 857	for(i = 0; i < 0x5000; ++i) {
 858		udelay(50);
 859		pci_read_config_byte(dev, 0x5b, &scr2);
 860		if (scr2 & 0x80)
 861			break;
 862	}
 863	/* See if it stays ready (we'll just bail out if it's not yet) */
 864	for(i = 0; i < 0x1000; ++i) {
 865		pci_read_config_byte(dev, 0x5b, &scr2);
 866		/* DPLL destabilized? */
 867		if(!(scr2 & 0x80))
 868			return 0;
 869	}
 870	/* Turn off tuning, we have the DPLL set */
 871	pci_read_config_dword (dev, 0x5c, &dpll);
 872	pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
 873	return 1;
 874}
 875
 876static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
 877{
 878	struct ide_host *host	= pci_get_drvdata(dev);
 879	struct hpt_info *info	= host->host_priv + (&dev->dev == host->dev[1]);
 880	u8  chip_type		= info->chip_type;
 881	u8  new_mcr, old_mcr	= 0;
 882
 883	/*
 884	 * Disable the "fast interrupt" prediction.  Don't hold off
 885	 * on interrupts. (== 0x01 despite what the docs say)
 886	 */
 887	pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
 888
 889	if (chip_type >= HPT374)
 890		new_mcr = old_mcr & ~0x07;
 891	else if (chip_type >= HPT370) {
 892		new_mcr = old_mcr;
 893		new_mcr &= ~0x02;
 894#ifdef HPT_DELAY_INTERRUPT
 895		new_mcr &= ~0x01;
 896#else
 897		new_mcr |=  0x01;
 898#endif
 899	} else					/* HPT366 and HPT368  */
 900		new_mcr = old_mcr & ~0x80;
 901
 902	if (new_mcr != old_mcr)
 903		pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
 904}
 905
 906static int init_chipset_hpt366(struct pci_dev *dev)
 907{
 908	unsigned long io_base	= pci_resource_start(dev, 4);
 909	struct hpt_info *info	= hpt3xx_get_info(&dev->dev);
 910	const char *name	= DRV_NAME;
 911	u8 pci_clk,  dpll_clk	= 0;	/* PCI and DPLL clock in MHz */
 912	u8 chip_type;
 913	enum ata_clock	clock;
 914
 915	chip_type = info->chip_type;
 916
 917	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 918	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 919	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 920	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 921
 922	/*
 923	 * First, try to estimate the PCI clock frequency...
 924	 */
 925	if (chip_type >= HPT370) {
 926		u8  scr1  = 0;
 927		u16 f_cnt = 0;
 928		u32 temp  = 0;
 929
 930		/* Interrupt force enable. */
 931		pci_read_config_byte(dev, 0x5a, &scr1);
 932		if (scr1 & 0x10)
 933			pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 934
 935		/*
 936		 * HighPoint does this for HPT372A.
 937		 * NOTE: This register is only writeable via I/O space.
 938		 */
 939		if (chip_type == HPT372A)
 940			outb(0x0e, io_base + 0x9c);
 941
 942		/*
 943		 * Default to PCI clock. Make sure MA15/16 are set to output
 944		 * to prevent drives having problems with 40-pin cables.
 945		 */
 946		pci_write_config_byte(dev, 0x5b, 0x23);
 947
 948		/*
 949		 * We'll have to read f_CNT value in order to determine
 950		 * the PCI clock frequency according to the following ratio:
 951		 *
 952		 * f_CNT = Fpci * 192 / Fdpll
 953		 *
 954		 * First try reading the register in which the HighPoint BIOS
 955		 * saves f_CNT value before  reprogramming the DPLL from its
 956		 * default setting (which differs for the various chips).
 957		 *
 958		 * NOTE: This register is only accessible via I/O space;
 959		 * HPT374 BIOS only saves it for the function 0, so we have to
 960		 * always read it from there -- no need to check the result of
 961		 * pci_get_slot() for the function 0 as the whole device has
 962		 * been already "pinned" (via function 1) in init_setup_hpt374()
 963		 */
 964		if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
 965			struct pci_dev	*dev1 = pci_get_slot(dev->bus,
 966							     dev->devfn - 1);
 967			unsigned long io_base = pci_resource_start(dev1, 4);
 968
 969			temp =	inl(io_base + 0x90);
 970			pci_dev_put(dev1);
 971		} else
 972			temp =	inl(io_base + 0x90);
 973
 974		/*
 975		 * In case the signature check fails, we'll have to
 976		 * resort to reading the f_CNT register itself in hopes
 977		 * that nobody has touched the DPLL yet...
 978		 */
 979		if ((temp & 0xFFFFF000) != 0xABCDE000) {
 980			int i;
 981
 982			printk(KERN_WARNING "%s %s: no clock data saved by "
 983				"BIOS\n", name, pci_name(dev));
 984
 985			/* Calculate the average value of f_CNT. */
 986			for (temp = i = 0; i < 128; i++) {
 987				pci_read_config_word(dev, 0x78, &f_cnt);
 988				temp += f_cnt & 0x1ff;
 989				mdelay(1);
 990			}
 991			f_cnt = temp / 128;
 992		} else
 993			f_cnt = temp & 0x1ff;
 994
 995		dpll_clk = info->dpll_clk;
 996		pci_clk  = (f_cnt * dpll_clk) / 192;
 997
 998		/* Clamp PCI clock to bands. */
 999		if (pci_clk < 40)
1000			pci_clk = 33;
1001		else if(pci_clk < 45)
1002			pci_clk = 40;
1003		else if(pci_clk < 55)
1004			pci_clk = 50;
1005		else
1006			pci_clk = 66;
1007
1008		printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1009			"assuming %d MHz PCI\n", name, pci_name(dev),
1010			dpll_clk, f_cnt, pci_clk);
1011	} else {
1012		u32 itr1 = 0;
1013
1014		pci_read_config_dword(dev, 0x40, &itr1);
1015
1016		/* Detect PCI clock by looking at cmd_high_time. */
1017		switch ((itr1 >> 8) & 0x0f) {
1018			case 0x09:
1019				pci_clk = 40;
1020				break;
1021			case 0x05:
1022				pci_clk = 25;
1023				break;
1024			case 0x07:
1025			default:
1026				pci_clk = 33;
1027				break;
1028		}
1029	}
1030
1031	/* Let's assume we'll use PCI clock for the ATA clock... */
1032	switch (pci_clk) {
1033		case 25:
1034			clock = ATA_CLOCK_25MHZ;
1035			break;
1036		case 33:
1037		default:
1038			clock = ATA_CLOCK_33MHZ;
1039			break;
1040		case 40:
1041			clock = ATA_CLOCK_40MHZ;
1042			break;
1043		case 50:
1044			clock = ATA_CLOCK_50MHZ;
1045			break;
1046		case 66:
1047			clock = ATA_CLOCK_66MHZ;
1048			break;
1049	}
1050
1051	/*
1052	 * Only try the DPLL if we don't have a table for the PCI clock that
1053	 * we are running at for HPT370/A, always use it  for anything newer...
1054	 *
1055	 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1056	 * We also  don't like using  the DPLL because this causes glitches
1057	 * on PRST-/SRST- when the state engine gets reset...
1058	 */
1059	if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1060		u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1061		int adjust;
1062
1063		 /*
1064		  * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1065		  * supported/enabled, use 50 MHz DPLL clock otherwise...
1066		  */
1067		if (info->udma_mask == ATA_UDMA6) {
1068			dpll_clk = 66;
1069			clock = ATA_CLOCK_66MHZ;
1070		} else if (dpll_clk) {	/* HPT36x chips don't have DPLL */
1071			dpll_clk = 50;
1072			clock = ATA_CLOCK_50MHZ;
1073		}
1074
1075		if (info->timings->clock_table[clock] == NULL) {
1076			printk(KERN_ERR "%s %s: unknown bus timing!\n",
1077				name, pci_name(dev));
1078			return -EIO;
1079		}
1080
1081		/* Select the DPLL clock. */
1082		pci_write_config_byte(dev, 0x5b, 0x21);
1083
1084		/*
1085		 * Adjust the DPLL based upon PCI clock, enable it,
1086		 * and wait for stabilization...
1087		 */
1088		f_low = (pci_clk * 48) / dpll_clk;
1089
1090		for (adjust = 0; adjust < 8; adjust++) {
1091			if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1092				break;
1093
1094			/*
1095			 * See if it'll settle at a fractionally different clock
1096			 */
1097			if (adjust & 1)
1098				f_low -= adjust >> 1;
1099			else
1100				f_low += adjust >> 1;
1101		}
1102		if (adjust == 8) {
1103			printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1104				name, pci_name(dev));
1105			return -EIO;
1106		}
1107
1108		printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1109			name, pci_name(dev), dpll_clk);
1110	} else {
1111		/* Mark the fact that we're not using the DPLL. */
1112		dpll_clk = 0;
1113
1114		printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1115			name, pci_name(dev), pci_clk);
1116	}
1117
1118	/* Store the clock frequencies. */
1119	info->dpll_clk	= dpll_clk;
1120	info->pci_clk	= pci_clk;
1121	info->clock	= clock;
1122
1123	if (chip_type >= HPT370) {
1124		u8  mcr1, mcr4;
1125
1126		/*
1127		 * Reset the state engines.
1128		 * NOTE: Avoid accidentally enabling the disabled channels.
1129		 */
1130		pci_read_config_byte (dev, 0x50, &mcr1);
1131		pci_read_config_byte (dev, 0x54, &mcr4);
1132		pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1133		pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1134		udelay(100);
1135	}
1136
1137	/*
1138	 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1139	 * the MISC. register to stretch the UltraDMA Tss timing.
1140	 * NOTE: This register is only writeable via I/O space.
1141	 */
1142	if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1143		outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1144
1145	hpt3xx_disable_fast_irq(dev, 0x50);
1146	hpt3xx_disable_fast_irq(dev, 0x54);
1147
1148	return 0;
1149}
1150
1151static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
1152{
1153	struct pci_dev	*dev	= to_pci_dev(hwif->dev);
1154	struct hpt_info *info	= hpt3xx_get_info(hwif->dev);
1155	u8 chip_type		= info->chip_type;
1156	u8 scr1 = 0, ata66	= hwif->channel ? 0x01 : 0x02;
1157
1158	/*
1159	 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1160	 * address lines to access an external EEPROM.  To read valid
1161	 * cable detect state the pins must be enabled as inputs.
1162	 */
1163	if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1164		/*
1165		 * HPT374 PCI function 1
1166		 * - set bit 15 of reg 0x52 to enable TCBLID as input
1167		 * - set bit 15 of reg 0x56 to enable FCBLID as input
1168		 */
1169		u8  mcr_addr = hwif->select_data + 2;
1170		u16 mcr;
1171
1172		pci_read_config_word(dev, mcr_addr, &mcr);
1173		pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
1174		/* Debounce, then read cable ID register */
1175		udelay(10);
1176		pci_read_config_byte(dev, 0x5a, &scr1);
1177		pci_write_config_word(dev, mcr_addr, mcr);
1178	} else if (chip_type >= HPT370) {
1179		/*
1180		 * HPT370/372 and 374 pcifn 0
1181		 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1182		 */
1183		u8 scr2 = 0;
1184
1185		pci_read_config_byte(dev, 0x5b, &scr2);
1186		pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1187		/* Debounce, then read cable ID register */
1188		udelay(10);
1189		pci_read_config_byte(dev, 0x5a, &scr1);
1190		pci_write_config_byte(dev, 0x5b, scr2);
1191	} else
1192		pci_read_config_byte(dev, 0x5a, &scr1);
1193
1194	return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1195}
1196
1197static void init_hwif_hpt366(ide_hwif_t *hwif)
1198{
1199	struct hpt_info *info	= hpt3xx_get_info(hwif->dev);
1200	u8  chip_type		= info->chip_type;
1201
1202	/* Cache the channel's MISC. control registers' offset */
1203	hwif->select_data	= hwif->channel ? 0x54 : 0x50;
1204
1205	/*
1206	 * HPT3xxN chips have some complications:
1207	 *
1208	 * - on 33 MHz PCI we must clock switch
1209	 * - on 66 MHz PCI we must NOT use the PCI clock
1210	 */
1211	if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1212		/*
1213		 * Clock is shared between the channels,
1214		 * so we'll have to serialize them... :-(
1215		 */
1216		hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
1217		hwif->rw_disk = &hpt3xxn_rw_disk;
1218	}
1219}
1220
1221static int init_dma_hpt366(ide_hwif_t *hwif,
1222				     const struct ide_port_info *d)
1223{
1224	struct pci_dev *dev = to_pci_dev(hwif->dev);
1225	unsigned long flags, base = ide_pci_dma_base(hwif, d);
1226	u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
1227
1228	if (base == 0)
1229		return -1;
1230
1231	hwif->dma_base = base;
1232
1233	if (ide_pci_check_simplex(hwif, d) < 0)
1234		return -1;
1235
1236	if (ide_pci_set_master(dev, d->name) < 0)
1237		return -1;
1238
1239	dma_old = inb(base + 2);
1240
1241	local_irq_save(flags);
1242
1243	dma_new = dma_old;
1244	pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1245	pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47,  &slavedma);
1246
1247	if (masterdma & 0x30)	dma_new |= 0x20;
1248	if ( slavedma & 0x30)	dma_new |= 0x40;
1249	if (dma_new != dma_old)
1250		outb(dma_new, base + 2);
1251
1252	local_irq_restore(flags);
1253
1254	printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx\n",
1255			 hwif->name, base, base + 7);
1256
1257	hwif->extra_base = base + (hwif->channel ? 8 : 16);
1258
1259	if (ide_allocate_dma_engine(hwif))
1260		return -1;
1261
1262	return 0;
1263}
1264
1265static void hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1266{
1267	if (dev2->irq != dev->irq) {
1268		/* FIXME: we need a core pci_set_interrupt() */
1269		dev2->irq = dev->irq;
1270		printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
1271			"fixed\n", pci_name(dev2));
1272	}
1273}
1274
1275static void hpt371_init(struct pci_dev *dev)
1276{
1277	u8 mcr1 = 0;
1278
1279	/*
1280	 * HPT371 chips physically have only one channel, the secondary one,
1281	 * but the primary channel registers do exist!  Go figure...
1282	 * So,  we manually disable the non-existing channel here
1283	 * (if the BIOS hasn't done this already).
1284	 */
1285	pci_read_config_byte(dev, 0x50, &mcr1);
1286	if (mcr1 & 0x04)
1287		pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1288}
1289
1290static int hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1291{
1292	u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1293
1294	/*
1295	 * Now we'll have to force both channels enabled if
1296	 * at least one of them has been enabled by BIOS...
1297	 */
1298	pci_read_config_byte(dev, 0x50, &mcr1);
1299	if (mcr1 & 0x30)
1300		pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1301
1302	pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1303	pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1304
1305	if (pin1 != pin2 && dev->irq == dev2->irq) {
1306		printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
1307			"pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
1308		return 1;
1309	}
1310
1311	return 0;
1312}
1313
1314#define IDE_HFLAGS_HPT3XX \
1315	(IDE_HFLAG_NO_ATAPI_DMA | \
1316	 IDE_HFLAG_OFF_BOARD)
1317
1318static const struct ide_port_ops hpt3xx_port_ops = {
1319	.set_pio_mode		= hpt3xx_set_pio_mode,
1320	.set_dma_mode		= hpt3xx_set_mode,
1321	.maskproc		= hpt3xx_maskproc,
1322	.mdma_filter		= hpt3xx_mdma_filter,
1323	.udma_filter		= hpt3xx_udma_filter,
1324	.cable_detect		= hpt3xx_cable_detect,
1325};
1326
1327static const struct ide_dma_ops hpt37x_dma_ops = {
1328	.dma_host_set		= ide_dma_host_set,
1329	.dma_setup		= ide_dma_setup,
1330	.dma_start		= ide_dma_start,
1331	.dma_end		= hpt374_dma_end,
1332	.dma_test_irq		= hpt374_dma_test_irq,
1333	.dma_lost_irq		= ide_dma_lost_irq,
1334	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
1335	.dma_sff_read_status	= ide_dma_sff_read_status,
1336};
1337
1338static const struct ide_dma_ops hpt370_dma_ops = {
1339	.dma_host_set		= ide_dma_host_set,
1340	.dma_setup		= ide_dma_setup,
1341	.dma_start		= hpt370_dma_start,
1342	.dma_end		= hpt370_dma_end,
1343	.dma_test_irq		= ide_dma_test_irq,
1344	.dma_lost_irq		= ide_dma_lost_irq,
1345	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
1346	.dma_clear		= hpt370_irq_timeout,
1347	.dma_sff_read_status	= ide_dma_sff_read_status,
1348};
1349
1350static const struct ide_dma_ops hpt36x_dma_ops = {
1351	.dma_host_set		= ide_dma_host_set,
1352	.dma_setup		= ide_dma_setup,
1353	.dma_start		= ide_dma_start,
1354	.dma_end		= ide_dma_end,
1355	.dma_test_irq		= ide_dma_test_irq,
1356	.dma_lost_irq		= hpt366_dma_lost_irq,
1357	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
1358	.dma_sff_read_status	= ide_dma_sff_read_status,
1359};
1360
1361static const struct ide_port_info hpt366_chipsets[] = {
1362	{	/* 0: HPT36x */
1363		.name		= DRV_NAME,
1364		.init_chipset	= init_chipset_hpt366,
1365		.init_hwif	= init_hwif_hpt366,
1366		.init_dma	= init_dma_hpt366,
1367		/*
1368		 * HPT36x chips have one channel per function and have
1369		 * both channel enable bits located differently and visible
1370		 * to both functions -- really stupid design decision... :-(
1371		 * Bit 4 is for the primary channel, bit 5 for the secondary.
1372		 */
1373		.enablebits	= {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1374		.port_ops	= &hpt3xx_port_ops,
1375		.dma_ops	= &hpt36x_dma_ops,
1376		.host_flags	= IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1377		.pio_mask	= ATA_PIO4,
1378		.mwdma_mask	= ATA_MWDMA2,
1379	},
1380	{	/* 1: HPT3xx */
1381		.name		= DRV_NAME,
1382		.init_chipset	= init_chipset_hpt366,
1383		.init_hwif	= init_hwif_hpt366,
1384		.init_dma	= init_dma_hpt366,
1385		.enablebits	= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1386		.port_ops	= &hpt3xx_port_ops,
1387		.dma_ops	= &hpt37x_dma_ops,
1388		.host_flags	= IDE_HFLAGS_HPT3XX,
1389		.pio_mask	= ATA_PIO4,
1390		.mwdma_mask	= ATA_MWDMA2,
1391	}
1392};
1393
1394/**
1395 *	hpt366_init_one	-	called when an HPT366 is found
1396 *	@dev: the hpt366 device
1397 *	@id: the matching pci id
1398 *
1399 *	Called when the PCI registration layer (or the IDE initialization)
1400 *	finds a device matching our IDE device tables.
1401 */
1402static int hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1403{
1404	const struct hpt_info *info = NULL;
1405	struct hpt_info *dyn_info;
1406	struct pci_dev *dev2 = NULL;
1407	struct ide_port_info d;
1408	u8 idx = id->driver_data;
1409	u8 rev = dev->revision;
1410	int ret;
1411
1412	if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1413		return -ENODEV;
1414
1415	switch (idx) {
1416	case 0:
1417		if (rev < 3)
1418			info = &hpt36x;
1419		else {
1420			switch (min_t(u8, rev, 6)) {
1421			case 3: info = &hpt370;  break;
1422			case 4: info = &hpt370a; break;
1423			case 5: info = &hpt372;  break;
1424			case 6: info = &hpt372n; break;
1425			}
1426			idx++;
1427		}
1428		break;
1429	case 1:
1430		info = (rev > 1) ? &hpt372n : &hpt372a;
1431		break;
1432	case 2:
1433		info = (rev > 1) ? &hpt302n : &hpt302;
1434		break;
1435	case 3:
1436		hpt371_init(dev);
1437		info = (rev > 1) ? &hpt371n : &hpt371;
1438		break;
1439	case 4:
1440		info = &hpt374;
1441		break;
1442	case 5:
1443		info = &hpt372n;
1444		break;
1445	}
1446
1447	printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
1448
1449	d = hpt366_chipsets[min_t(u8, idx, 1)];
1450
1451	d.udma_mask = info->udma_mask;
1452
1453	/* fixup ->dma_ops for HPT370/HPT370A */
1454	if (info == &hpt370 || info == &hpt370a)
1455		d.dma_ops = &hpt370_dma_ops;
1456
1457	if (info == &hpt36x || info == &hpt374)
1458		dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1459
1460	dyn_info = kcalloc(dev2 ? 2 : 1, sizeof(*dyn_info), GFP_KERNEL);
1461	if (dyn_info == NULL) {
1462		printk(KERN_ERR "%s %s: out of memory!\n",
1463			d.name, pci_name(dev));
1464		pci_dev_put(dev2);
1465		return -ENOMEM;
1466	}
1467
1468	/*
1469	 * Copy everything from a static "template" structure
1470	 * to just allocated per-chip hpt_info structure.
1471	 */
1472	memcpy(dyn_info, info, sizeof(*dyn_info));
1473
1474	if (dev2) {
1475		memcpy(dyn_info + 1, info, sizeof(*dyn_info));
1476
1477		if (info == &hpt374)
1478			hpt374_init(dev, dev2);
1479		else {
1480			if (hpt36x_init(dev, dev2))
1481				d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
1482		}
1483
1484		ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1485		if (ret < 0) {
1486			pci_dev_put(dev2);
1487			kfree(dyn_info);
1488		}
1489		return ret;
1490	}
1491
1492	ret = ide_pci_init_one(dev, &d, dyn_info);
1493	if (ret < 0)
1494		kfree(dyn_info);
1495
1496	return ret;
1497}
1498
1499static void hpt366_remove(struct pci_dev *dev)
1500{
1501	struct ide_host *host = pci_get_drvdata(dev);
1502	struct ide_info *info = host->host_priv;
1503	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1504
1505	ide_pci_remove(dev);
1506	pci_dev_put(dev2);
1507	kfree(info);
1508}
1509
1510static const struct pci_device_id hpt366_pci_tbl[] = {
1511	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366),  0 },
1512	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372),  1 },
1513	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302),  2 },
1514	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371),  3 },
1515	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374),  4 },
1516	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1517	{ 0, },
1518};
1519MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1520
1521static struct pci_driver hpt366_pci_driver = {
1522	.name		= "HPT366_IDE",
1523	.id_table	= hpt366_pci_tbl,
1524	.probe		= hpt366_init_one,
1525	.remove		= hpt366_remove,
1526	.suspend	= ide_pci_suspend,
1527	.resume		= ide_pci_resume,
1528};
1529
1530static int __init hpt366_ide_init(void)
1531{
1532	return ide_pci_register_driver(&hpt366_pci_driver);
1533}
1534
1535static void __exit hpt366_ide_exit(void)
1536{
1537	pci_unregister_driver(&hpt366_pci_driver);
1538}
1539
1540module_init(hpt366_ide_init);
1541module_exit(hpt366_ide_exit);
1542
1543MODULE_AUTHOR("Andre Hedrick");
1544MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1545MODULE_LICENSE("GPL");