/fishlamp.timer/main.e

http://github.com/gbalage/fishlamptimer · Specman e · 55 lines · 49 code · 6 blank · 0 comment · 0 complexity · 791d0d11ef624a06ce649db9666068d0 MD5 · raw file

  1. namespace main;
  2. import microchip.PIC18F14K50;
  3. import microchip.pic18;
  4. import e.types;
  5. import e.platform;
  6. import RTE;
  7. reg uint8 ANSELH : 0xF7F;
  8. reg uint8 ANSEL : 0xF7E;
  9. main(){
  10. OSCCON = 0x50;
  11. ANSEL = 0;
  12. ANSELH = 0;
  13. TRISC = 0;
  14. PORTC = 0;
  15. LATC = 0;
  16. PORTB = 0;
  17. LATB = 0;
  18. TRISB = 0;
  19. RTE::debug(0x99);
  20. RTE::init();
  21. label start;
  22. RTE::run();
  23. GOTO(@start);
  24. }
  25. binary fishlamp hexfile{
  26. link main {
  27. memwidth = 8;
  28. mem 0x00..0xeff;
  29. } at 0;
  30. include config at 0;
  31. }
  32. binary config{
  33. data {
  34. 0;
  35. CONFIG1H_FCMEN_Disabled+CONFIG1H_IESO_Disabled+CONFIG1H_OSC_INTRCPortonRA6PortonRA7;
  36. CONFIG2L_BODENV__20V+CONFIG2L_BODEN_DisabledinhardwareSBORENdisabled+CONFIG2L_PUT_Disabled;
  37. CONFIG2H_WDTPS__18192+CONFIG2H_WDT_DisabledControlledbySWDTENbit;
  38. 0;
  39. CONFIG3H_CCP2MUX_RB3+CONFIG3H_LPT1OSC_Disabled+CONFIG3H_MCLRE_MCLRDisabledRE3Enabled+CONFIG3H_PBADEN_PORTB40configuredasdigitalIOonRESET;
  40. CONFIG4L_BACKBUG_Disabled+CONFIG4L_ENHCPU_Disabled+CONFIG4L_LVP_Disabled+CONFIG4L_STVR_Disabled;
  41. 0;
  42. CONFIG5L_CP_0_Disabled+CONFIG5L_CP_1_Disabled;
  43. CONFIG5H_CPB_Disabled+CONFIG5H_CPD_Disabled;
  44. CONFIG6L_WRT_0_Disabled+CONFIG6L_WRT_1_Disabled;
  45. 0;
  46. CONFIG7L_EBTR_0_Disabled+CONFIG7L_EBTR_1_Disabled;
  47. CONFIG7H_EBTRB_Disabled;
  48. } at CONFIG_ADDRESS;
  49. }