/fishlamp.timer/main.e

 1namespace main;
 2
 3import microchip.PIC18F14K50;
 4import microchip.pic18;
 5import e.types;
 6import e.platform;
 7import RTE;
 8
 9reg uint8 ANSELH : 0xF7F;
10reg uint8 ANSEL : 0xF7E;
11
12main(){
13	OSCCON = 0x50;
14	ANSEL = 0;
15	ANSELH = 0;
16	TRISC = 0;
17	PORTC = 0;
18	LATC = 0;
19	PORTB = 0;
20	LATB = 0;
21	TRISB = 0;
22	RTE::debug(0x99);
23	
24	RTE::init();
25	label start;
26	RTE::run();
27	GOTO(@start);
28}
29
30binary fishlamp hexfile{
31	link main {
32		memwidth = 8;
33		mem 0x00..0xeff;
34	} at 0;
35	include config at 0;
36}
37
38binary config{
39	data {
40		0;
41		CONFIG1H_FCMEN_Disabled+CONFIG1H_IESO_Disabled+CONFIG1H_OSC_INTRCPortonRA6PortonRA7;
42		CONFIG2L_BODENV__20V+CONFIG2L_BODEN_DisabledinhardwareSBORENdisabled+CONFIG2L_PUT_Disabled;
43		CONFIG2H_WDTPS__18192+CONFIG2H_WDT_DisabledControlledbySWDTENbit;
44		0;
45		CONFIG3H_CCP2MUX_RB3+CONFIG3H_LPT1OSC_Disabled+CONFIG3H_MCLRE_MCLRDisabledRE3Enabled+CONFIG3H_PBADEN_PORTB40configuredasdigitalIOonRESET;
46		CONFIG4L_BACKBUG_Disabled+CONFIG4L_ENHCPU_Disabled+CONFIG4L_LVP_Disabled+CONFIG4L_STVR_Disabled;
47		0;
48		CONFIG5L_CP_0_Disabled+CONFIG5L_CP_1_Disabled;
49		CONFIG5H_CPB_Disabled+CONFIG5H_CPD_Disabled;
50		CONFIG6L_WRT_0_Disabled+CONFIG6L_WRT_1_Disabled;
51		0;
52		CONFIG7L_EBTR_0_Disabled+CONFIG7L_EBTR_1_Disabled;
53		CONFIG7H_EBTRB_Disabled;
54	} at CONFIG_ADDRESS;
55}