/fishlamp.timer/test/test.e
Specman e | 112 lines | 94 code | 18 blank | 0 comment | 2 complexity | 4b3c605286b295046dce0d43ce339551 MD5 | raw file
1namespace test; 2 3import e.types; 4import e.platform; 5import microchip.pic18; 6import microchip.pic18.assisted; 7import microchip.PIC18F14K50; 8import dio; 9import spi; 10import pic18f14k50.eusart; 11 12reg uint8 ANSEL : 0xF7E; 13reg uint8 ANSELH : 0xF7F; 14 15wait(){ 16 uint8 counter; 17 aCLRF(addr(counter)); 18 label countstart; 19 NOP(); 20 NOP(); 21 NOP(); 22 aINCFSZ(addr(counter)); 23 GOTO(@countstart); 24} 25 26wait2(){ 27 uint8 counter; 28 aCLRF(addr(counter)); 29 label countstart; 30 wait(); 31 aINCFSZ(addr(counter)); 32 GOTO(@countstart); 33} 34 35wait3(){ 36 uint8 counter; 37 aCLRF(addr(counter)); 38 label countstart; 39 wait2(); 40 aINCFSZ(addr(counter)); 41 GOTO(@countstart); 42} 43 44main(){ 45 uint8 rcv; 46 uint8 send; 47 uint8 display; 48 49 OSCCON = 0x50; 50 51 ANSEL = 0; 52 ANSELH = 0; 53 TRISC = 0; 54 PORTC = 0; 55 LATC = 0; 56 send = 0; 57 rcv = 0; 58 PORTB = 0; 59 LATB = 0; 60 TRISB = 0; 61 62 display = 0xFF; 63 /* Send data to display */ 64 SPI_Send(RC0, RC1, display); 65 66 RS232_init(); 67 68 label start; 69 70 /* Communicate */ 71 RS232_syncSend(display,rcv); 72 73 if (rcv == display){ 74 75 }else{ 76 /* Display received value */ 77 display = rcv; 78 79 /* Send data to display */ 80 SPI_Send(RC0, RC1, display); 81 } 82 83 wait(); 84 GOTO(@start); 85} 86 87binary config{ 88 data { 89 0; 90 CONFIG1H_FCMEN_Disabled+CONFIG1H_IESO_Disabled+CONFIG1H_OSC_INTRCPortonRA6PortonRA7; 91 CONFIG2L_BODENV__20V+CONFIG2L_BODEN_DisabledinhardwareSBORENdisabled+CONFIG2L_PUT_Disabled; 92 CONFIG2H_WDTPS__18192+CONFIG2H_WDT_DisabledControlledbySWDTENbit; 93 0; 94 CONFIG3H_CCP2MUX_RB3+CONFIG3H_LPT1OSC_Disabled+CONFIG3H_MCLRE_MCLRDisabledRE3Enabled+CONFIG3H_PBADEN_PORTB40configuredasdigitalIOonRESET; 95 CONFIG4L_BACKBUG_Disabled+CONFIG4L_ENHCPU_Disabled+CONFIG4L_LVP_Disabled+CONFIG4L_STVR_Disabled; 96 0; 97 CONFIG5L_CP_0_Disabled+CONFIG5L_CP_1_Disabled; 98 CONFIG5H_CPB_Disabled+CONFIG5H_CPD_Disabled; 99 CONFIG6L_WRT_0_Disabled+CONFIG6L_WRT_1_Disabled; 100 0; 101 CONFIG7L_EBTR_0_Disabled+CONFIG7L_EBTR_1_Disabled; 102 CONFIG7H_EBTRB_Disabled; 103 } at CONFIG_ADDRESS; 104} 105 106binary test hexfile{ 107 link main { 108 memwidth = 8; 109 mem 0x00..0xeff; 110 } at 0; 111 include config at 0; 112}