/compiler/arm/cpubase.pas

https://github.com/slibre/freepascal · Pascal · 686 lines · 431 code · 116 blank · 139 comment · 21 complexity · a07d2b41d5a4b27aed782440fe917bec MD5 · raw file

  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Peter Vreman
  3. Contains the base types for the ARM
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. {# Base unit for processor information. This unit contains
  18. enumerations of registers, opcodes, sizes, and other
  19. such things which are processor specific.
  20. }
  21. unit cpubase;
  22. {$define USEINLINE}
  23. {$i fpcdefs.inc}
  24. interface
  25. uses
  26. globtype,globals,
  27. cpuinfo,
  28. cgbase
  29. ;
  30. {*****************************************************************************
  31. Assembler Opcodes
  32. *****************************************************************************}
  33. type
  34. TAsmOp= {$i armop.inc}
  35. {This is a bit of a hack, because there are more than 256 ARM Assembly Ops
  36. But FPC currently can't handle more than 256 elements in a set.}
  37. TCommonAsmOps = Set of A_None .. A_UQASX;
  38. { This should define the array of instructions as string }
  39. op2strtable=array[tasmop] of string[11];
  40. const
  41. { First value of opcode enumeration }
  42. firstop = low(tasmop);
  43. { Last value of opcode enumeration }
  44. lastop = high(tasmop);
  45. {*****************************************************************************
  46. Registers
  47. *****************************************************************************}
  48. type
  49. { Number of registers used for indexing in tables }
  50. tregisterindex=0..{$i rarmnor.inc}-1;
  51. const
  52. { Available Superregisters }
  53. {$i rarmsup.inc}
  54. RS_PC = RS_R15;
  55. { No Subregisters }
  56. R_SUBWHOLE = R_SUBNONE;
  57. { Available Registers }
  58. {$i rarmcon.inc}
  59. { aliases }
  60. NR_PC = NR_R15;
  61. { Integer Super registers first and last }
  62. first_int_supreg = RS_R0;
  63. first_int_imreg = $10;
  64. { Float Super register first and last }
  65. first_fpu_supreg = RS_F0;
  66. first_fpu_imreg = $08;
  67. { MM Super register first and last }
  68. first_mm_supreg = RS_S0;
  69. first_mm_imreg = $30;
  70. { TODO: Calculate bsstart}
  71. regnumber_count_bsstart = 64;
  72. regnumber_table : array[tregisterindex] of tregister = (
  73. {$i rarmnum.inc}
  74. );
  75. regstabs_table : array[tregisterindex] of shortint = (
  76. {$i rarmsta.inc}
  77. );
  78. regdwarf_table : array[tregisterindex] of shortint = (
  79. {$i rarmdwa.inc}
  80. );
  81. { registers which may be destroyed by calls }
  82. VOLATILE_INTREGISTERS = [RS_R0..RS_R3,RS_R12..RS_R14];
  83. VOLATILE_FPUREGISTERS = [RS_F0..RS_F3];
  84. VOLATILE_MMREGISTERS = [RS_D0..RS_D7,RS_D16..RS_D31,RS_S1..RS_S15];
  85. VOLATILE_INTREGISTERS_DARWIN = [RS_R0..RS_R3,RS_R9,RS_R12..RS_R14];
  86. type
  87. totherregisterset = set of tregisterindex;
  88. {*****************************************************************************
  89. Instruction post fixes
  90. *****************************************************************************}
  91. type
  92. { ARM instructions load/store and arithmetic instructions
  93. can have several instruction post fixes which are collected
  94. in this enumeration
  95. }
  96. TOpPostfix = (PF_None,
  97. { update condition flags
  98. or floating point single }
  99. PF_S,
  100. { floating point size }
  101. PF_D,PF_E,PF_P,PF_EP,
  102. { load/store }
  103. PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T,
  104. { multiple load/store address modes }
  105. PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA,
  106. { multiple load/store vfp address modes }
  107. PF_IAD,PF_DBD,PF_FDD,PF_EAD,
  108. PF_IAS,PF_DBS,PF_FDS,PF_EAS,
  109. PF_IAX,PF_DBX,PF_FDX,PF_EAX,
  110. { FPv4 postfixes }
  111. PF_32,PF_64,PF_F32,PF_F64,
  112. PF_F32S32,PF_F32U32,
  113. PF_S32F32,PF_U32F32
  114. );
  115. TOpPostfixes = set of TOpPostfix;
  116. TRoundingMode = (RM_None,RM_P,RM_M,RM_Z);
  117. const
  118. cgsize2fpuoppostfix : array[OS_NO..OS_F128] of toppostfix = (
  119. PF_None,
  120. PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,
  121. PF_S,PF_D,PF_E,PF_None,PF_None);
  122. oppostfix2str : array[TOpPostfix] of string[8] = ('',
  123. 's',
  124. 'd','e','p','ep',
  125. 'b','sb','bt','h','sh','t',
  126. 'ia','ib','da','db','fd','fa','ed','ea',
  127. 'iad','dbd','fdd','ead',
  128. 'ias','dbs','fds','eas',
  129. 'iax','dbx','fdx','eax',
  130. '.32','.64','.f32','.f64',
  131. '.f32.s32','.f32.u32',
  132. '.s32.f32','.u32.f32');
  133. roundingmode2str : array[TRoundingMode] of string[1] = ('',
  134. 'p','m','z');
  135. {*****************************************************************************
  136. Conditions
  137. *****************************************************************************}
  138. type
  139. TAsmCond=(C_None,
  140. C_EQ,C_NE,C_CS,C_CC,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
  141. C_GE,C_LT,C_GT,C_LE,C_AL,C_NV
  142. );
  143. TAsmConds = set of TAsmCond;
  144. const
  145. cond2str : array[TAsmCond] of string[2]=('',
  146. 'eq','ne','cs','cc','mi','pl','vs','vc','hi','ls',
  147. 'ge','lt','gt','le','al','nv'
  148. );
  149. uppercond2str : array[TAsmCond] of string[2]=('',
  150. 'EQ','NE','CS','CC','MI','PL','VS','VC','HI','LS',
  151. 'GE','LT','GT','LE','AL','NV'
  152. );
  153. {*****************************************************************************
  154. Flags
  155. *****************************************************************************}
  156. type
  157. TResFlags = (F_EQ,F_NE,F_CS,F_CC,F_MI,F_PL,F_VS,F_VC,F_HI,F_LS,
  158. F_GE,F_LT,F_GT,F_LE);
  159. {*****************************************************************************
  160. Operands
  161. *****************************************************************************}
  162. taddressmode = (AM_OFFSET,AM_PREINDEXED,AM_POSTINDEXED);
  163. tshiftmode = (SM_None,SM_LSL,SM_LSR,SM_ASR,SM_ROR,SM_RRX);
  164. tupdatereg = (UR_None,UR_Update);
  165. pshifterop = ^tshifterop;
  166. tshifterop = record
  167. shiftmode : tshiftmode;
  168. rs : tregister;
  169. shiftimm : byte;
  170. end;
  171. tcpumodeflag = (mfA, mfI, mfF);
  172. tcpumodeflags = set of tcpumodeflag;
  173. tspecialregflag = (srC, srX, srS, srF);
  174. tspecialregflags = set of tspecialregflag;
  175. {*****************************************************************************
  176. Constants
  177. *****************************************************************************}
  178. const
  179. max_operands = 6;
  180. maxintregs = 15;
  181. maxfpuregs = 8;
  182. maxaddrregs = 0;
  183. {*****************************************************************************
  184. Operand Sizes
  185. *****************************************************************************}
  186. type
  187. topsize = (S_NO,
  188. S_B,S_W,S_L,S_BW,S_BL,S_WL,
  189. S_IS,S_IL,S_IQ,
  190. S_FS,S_FL,S_FX,S_D,S_Q,S_FV,S_FXX
  191. );
  192. {*****************************************************************************
  193. Constants
  194. *****************************************************************************}
  195. const
  196. maxvarregs = 7;
  197. varregs : Array [1..maxvarregs] of tsuperregister =
  198. (RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,RS_R10);
  199. maxfpuvarregs = 4;
  200. fpuvarregs : Array [1..maxfpuvarregs] of tsuperregister =
  201. (RS_F4,RS_F5,RS_F6,RS_F7);
  202. {*****************************************************************************
  203. Default generic sizes
  204. *****************************************************************************}
  205. { Defines the default address size for a processor, }
  206. OS_ADDR = OS_32;
  207. { the natural int size for a processor,
  208. has to match osuinttype/ossinttype as initialized in psystem }
  209. OS_INT = OS_32;
  210. OS_SINT = OS_S32;
  211. { the maximum float size for a processor, }
  212. OS_FLOAT = OS_F64;
  213. { the size of a vector register for a processor }
  214. OS_VECTOR = OS_M32;
  215. {*****************************************************************************
  216. Generic Register names
  217. *****************************************************************************}
  218. { Stack pointer register }
  219. NR_STACK_POINTER_REG = NR_R13;
  220. RS_STACK_POINTER_REG = RS_R13;
  221. { Frame pointer register (initialized in tarmprocinfo.init_framepointer) }
  222. RS_FRAME_POINTER_REG: tsuperregister = RS_NO;
  223. NR_FRAME_POINTER_REG: tregister = NR_NO;
  224. { Register for addressing absolute data in a position independant way,
  225. such as in PIC code. The exact meaning is ABI specific. For
  226. further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
  227. }
  228. NR_PIC_OFFSET_REG = NR_R9;
  229. { Results are returned in this register (32-bit values) }
  230. NR_FUNCTION_RETURN_REG = NR_R0;
  231. RS_FUNCTION_RETURN_REG = RS_R0;
  232. { The value returned from a function is available in this register }
  233. NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
  234. RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
  235. NR_FPU_RESULT_REG = NR_F0;
  236. NR_MM_RESULT_REG = NR_D0;
  237. NR_RETURN_ADDRESS_REG = NR_FUNCTION_RETURN_REG;
  238. { Offset where the parent framepointer is pushed }
  239. PARENT_FRAMEPOINTER_OFFSET = 0;
  240. NR_DEFAULTFLAGS = NR_CPSR;
  241. RS_DEFAULTFLAGS = RS_CPSR;
  242. { Low part of 64bit return value }
  243. function NR_FUNCTION_RESULT64_LOW_REG: tregister;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  244. function RS_FUNCTION_RESULT64_LOW_REG: shortint;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  245. { High part of 64bit return value }
  246. function NR_FUNCTION_RESULT64_HIGH_REG: tregister;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  247. function RS_FUNCTION_RESULT64_HIGH_REG: shortint;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  248. {*****************************************************************************
  249. GCC /ABI linking information
  250. *****************************************************************************}
  251. const
  252. { Registers which must be saved when calling a routine declared as
  253. cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
  254. saved should be the ones as defined in the target ABI and / or GCC.
  255. This value can be deduced from the CALLED_USED_REGISTERS array in the
  256. GCC source.
  257. }
  258. saved_standard_registers : array[0..6] of tsuperregister =
  259. (RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,RS_R10);
  260. { this is only for the generic code which is not used for this architecture }
  261. saved_mm_registers : array[0..0] of tsuperregister = (RS_INVALID);
  262. { Required parameter alignment when calling a routine declared as
  263. stdcall and cdecl. The alignment value should be the one defined
  264. by GCC or the target ABI.
  265. The value of this constant is equal to the constant
  266. PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
  267. }
  268. std_param_align = 4;
  269. {*****************************************************************************
  270. Helpers
  271. *****************************************************************************}
  272. { Returns the tcgsize corresponding with the size of reg.}
  273. function reg_cgsize(const reg: tregister) : tcgsize;
  274. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  275. function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  276. procedure inverse_flags(var f: TResFlags);
  277. function flags_to_cond(const f: TResFlags) : TAsmCond;
  278. function findreg_by_number(r:Tregister):tregisterindex;
  279. function std_regnum_search(const s:string):Tregister;
  280. function std_regname(r:Tregister):string;
  281. function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  282. function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  283. procedure shifterop_reset(var so : tshifterop); {$ifdef USEINLINE}inline;{$endif USEINLINE}
  284. function is_pc(const r : tregister) : boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  285. function is_shifter_const(d : aint;var imm_shift : byte) : boolean;
  286. function is_thumb_imm(d : aint) : boolean; { Doesn't handle ROR_C detection }
  287. function split_into_shifter_const(value : aint;var imm1: dword; var imm2: dword):boolean;
  288. function dwarf_reg(r:tregister):shortint;
  289. function IsIT(op: TAsmOp) : boolean;
  290. function GetITLevels(op: TAsmOp) : longint;
  291. implementation
  292. uses
  293. systems,rgBase,verbose;
  294. const
  295. std_regname_table : TRegNameTable = (
  296. {$i rarmstd.inc}
  297. );
  298. regnumber_index : array[tregisterindex] of tregisterindex = (
  299. {$i rarmrni.inc}
  300. );
  301. std_regname_index : array[tregisterindex] of tregisterindex = (
  302. {$i rarmsri.inc}
  303. );
  304. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  305. begin
  306. case regtype of
  307. R_MMREGISTER:
  308. begin
  309. case s of
  310. OS_F32:
  311. cgsize2subreg:=R_SUBFS;
  312. OS_F64:
  313. cgsize2subreg:=R_SUBFD;
  314. else
  315. internalerror(2009112701);
  316. end;
  317. end;
  318. else
  319. cgsize2subreg:=R_SUBWHOLE;
  320. end;
  321. end;
  322. function reg_cgsize(const reg: tregister): tcgsize;
  323. begin
  324. case getregtype(reg) of
  325. R_INTREGISTER :
  326. reg_cgsize:=OS_32;
  327. R_FPUREGISTER :
  328. reg_cgsize:=OS_F80;
  329. R_MMREGISTER :
  330. begin
  331. case getsubreg(reg) of
  332. R_SUBFD,
  333. R_SUBWHOLE:
  334. result:=OS_F64;
  335. R_SUBFS:
  336. result:=OS_F32;
  337. else
  338. internalerror(2009112903);
  339. end;
  340. end;
  341. else
  342. internalerror(200303181);
  343. end;
  344. end;
  345. function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  346. begin
  347. { This isn't 100% perfect because the arm allows jumps also by writing to PC=R15.
  348. To overcome this problem we simply forbid that FPC generates jumps by loading R15 }
  349. is_calljmp:= o in [A_B,A_BL,A_BX,A_BLX];
  350. end;
  351. procedure inverse_flags(var f: TResFlags);
  352. const
  353. inv_flags: array[TResFlags] of TResFlags =
  354. (F_NE,F_EQ,F_CC,F_CS,F_PL,F_MI,F_VC,F_VS,F_LS,F_HI,
  355. F_LT,F_GE,F_LE,F_GT);
  356. begin
  357. f:=inv_flags[f];
  358. end;
  359. function flags_to_cond(const f: TResFlags) : TAsmCond;
  360. const
  361. flag_2_cond: array[F_EQ..F_LE] of TAsmCond =
  362. (C_EQ,C_NE,C_CS,C_CC,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
  363. C_GE,C_LT,C_GT,C_LE);
  364. begin
  365. if f>high(flag_2_cond) then
  366. internalerror(200112301);
  367. result:=flag_2_cond[f];
  368. end;
  369. function findreg_by_number(r:Tregister):tregisterindex;
  370. begin
  371. result:=rgBase.findreg_by_number_table(r,regnumber_index);
  372. end;
  373. function std_regnum_search(const s:string):Tregister;
  374. begin
  375. result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
  376. end;
  377. function std_regname(r:Tregister):string;
  378. var
  379. p : tregisterindex;
  380. begin
  381. p:=findreg_by_number_table(r,regnumber_index);
  382. if p<>0 then
  383. result:=std_regname_table[p]
  384. else
  385. result:=generic_regname(r);
  386. end;
  387. procedure shifterop_reset(var so : tshifterop);{$ifdef USEINLINE}inline;{$endif USEINLINE}
  388. begin
  389. FillChar(so,sizeof(so),0);
  390. end;
  391. function is_pc(const r : tregister) : boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  392. begin
  393. is_pc:=(r=NR_R15);
  394. end;
  395. function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  396. const
  397. inverse: array[TAsmCond] of TAsmCond=(C_None,
  398. C_NE,C_EQ,C_CC,C_CS,C_PL,C_MI,C_VC,C_VS,C_LS,C_HI,
  399. C_LT,C_GE,C_LE,C_GT,C_None,C_None
  400. );
  401. begin
  402. result := inverse[c];
  403. end;
  404. function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  405. begin
  406. result := c1 = c2;
  407. end;
  408. function is_shifter_const(d : aint;var imm_shift : byte) : boolean;
  409. var
  410. i : longint;
  411. begin
  412. if current_settings.cputype in cpu_thumb2 then
  413. begin
  414. for i:=0 to 24 do
  415. begin
  416. if (dword(d) and not($ff shl i))=0 then
  417. begin
  418. imm_shift:=i;
  419. result:=true;
  420. exit;
  421. end;
  422. end;
  423. end
  424. else
  425. begin
  426. for i:=0 to 15 do
  427. begin
  428. if (dword(d) and not(roldword($ff,i*2)))=0 then
  429. begin
  430. imm_shift:=i*2;
  431. result:=true;
  432. exit;
  433. end;
  434. end;
  435. end;
  436. result:=false;
  437. end;
  438. function is_thumb_imm(d: aint): boolean;
  439. var
  440. t : aint;
  441. i : longint;
  442. imm : byte;
  443. begin
  444. result:=false;
  445. if (d and $FF) = d then
  446. begin
  447. result:=true;
  448. exit;
  449. end;
  450. if ((d and $FF00FF00) = 0) and
  451. ((d shr 16)=(d and $FFFF)) then
  452. begin
  453. result:=true;
  454. exit;
  455. end;
  456. if ((d and $00FF00FF) = 0) and
  457. ((d shr 16)=(d and $FFFF)) then
  458. begin
  459. result:=true;
  460. exit;
  461. end;
  462. if ((d shr 16)=(d and $FFFF)) and
  463. ((d shr 8)=(d and $FF)) then
  464. begin
  465. result:=true;
  466. exit;
  467. end;
  468. if is_shifter_const(d,imm) then
  469. begin
  470. result:=true;
  471. exit;
  472. end;
  473. end;
  474. function split_into_shifter_const(value : aint;var imm1: dword; var imm2: dword) : boolean;
  475. var
  476. d, i, i2: Dword;
  477. begin
  478. Result:=false;
  479. {Thumb2 is not supported (YET?)}
  480. if current_settings.cputype in cpu_thumb2 then exit;
  481. d:=DWord(value);
  482. for i:=0 to 15 do
  483. begin
  484. imm1:=d and rordword($FF, I*2);
  485. imm2:=d and not (imm1); {remove already found bits}
  486. {is the remainder a shifterconst? YAY! we've done it!}
  487. {Could we start from i instead of 0?}
  488. for i2:=0 to 15 do
  489. begin
  490. if (imm2 and not(rordword($FF,i2*2)))=0 then
  491. begin
  492. result:=true;
  493. exit;
  494. end;
  495. end;
  496. end;
  497. end;
  498. function dwarf_reg(r:tregister):shortint;
  499. begin
  500. result:=regdwarf_table[findreg_by_number(r)];
  501. if result=-1 then
  502. internalerror(200603251);
  503. end;
  504. { Low part of 64bit return value }
  505. function NR_FUNCTION_RESULT64_LOW_REG: tregister; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  506. begin
  507. if target_info.endian=endian_little then
  508. result:=NR_R0
  509. else
  510. result:=NR_R1;
  511. end;
  512. function RS_FUNCTION_RESULT64_LOW_REG: shortint; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  513. begin
  514. if target_info.endian=endian_little then
  515. result:=RS_R0
  516. else
  517. result:=RS_R1;
  518. end;
  519. { High part of 64bit return value }
  520. function NR_FUNCTION_RESULT64_HIGH_REG: tregister; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  521. begin
  522. if target_info.endian=endian_little then
  523. result:=NR_R1
  524. else
  525. result:=NR_R0;
  526. end;
  527. function RS_FUNCTION_RESULT64_HIGH_REG: shortint; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  528. begin
  529. if target_info.endian=endian_little then
  530. result:=RS_R1
  531. else
  532. result:=RS_R0;
  533. end;
  534. function IsIT(op: TAsmOp) : boolean;
  535. begin
  536. case op of
  537. A_IT,
  538. A_ITE, A_ITT,
  539. A_ITEE, A_ITTE, A_ITET, A_ITTT,
  540. A_ITEEE, A_ITTEE, A_ITETE, A_ITTTE,
  541. A_ITEET, A_ITTET, A_ITETT, A_ITTTT:
  542. result:=true;
  543. else
  544. result:=false;
  545. end;
  546. end;
  547. function GetITLevels(op: TAsmOp) : longint;
  548. begin
  549. case op of
  550. A_IT:
  551. result:=1;
  552. A_ITE, A_ITT:
  553. result:=2;
  554. A_ITEE, A_ITTE, A_ITET, A_ITTT:
  555. result:=3;
  556. A_ITEEE, A_ITTEE, A_ITETE, A_ITTTE,
  557. A_ITEET, A_ITTET, A_ITETT, A_ITTTT:
  558. result:=4;
  559. else
  560. result:=0;
  561. end;
  562. end;
  563. end.