/compiler/arm/cgcpu.pas
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- {
- Copyright (c) 2003 by Florian Klaempfl
- Member of the Free Pascal development team
- This unit implements the code generator for the ARM
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- ****************************************************************************
- }
- unit cgcpu;
- {$i fpcdefs.inc}
- interface
- uses
- globtype,symtype,symdef,
- cgbase,cgutils,cgobj,
- aasmbase,aasmcpu,aasmtai,aasmdata,
- parabase,
- cpubase,cpuinfo,cg64f32,rgcpu;
- type
- tcgarm = class(tcg)
- { true, if the next arithmetic operation should modify the flags }
- cgsetflags : boolean;
- procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
- procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
- procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
- procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
- procedure a_call_reg(list : TAsmList;reg: tregister);override;
- procedure a_call_ref(list : TAsmList;ref: treference);override;
- procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
- procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
- procedure a_op_const_reg_reg(list: TAsmList; op: TOpCg;
- size: tcgsize; a: tcgint; src, dst: tregister); override;
- procedure a_op_reg_reg_reg(list: TAsmList; op: TOpCg;
- size: tcgsize; src1, src2, dst: tregister); override;
- procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
- procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
- { move instructions }
- procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
- procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
- function a_internal_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference):treference;
- function a_internal_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister):treference;
- { fpu move instructions }
- procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
- procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
- procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
- procedure a_loadfpu_ref_cgpara(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);override;
- { comparison operations }
- procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
- l : tasmlabel);override;
- procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
- procedure a_jmp_name(list : TAsmList;const s : string); override;
- procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
- procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
- procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
- procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
- procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
- procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
- procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
- procedure g_concatcopy_unaligned(list : TAsmList;const source,dest : treference;len : tcgint);override;
- procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
- procedure g_concatcopy_internal(list : TAsmList;const source,dest : treference;len : tcgint;aligned : boolean);
- procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
- procedure g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;ovloc : tlocation);override;
- procedure g_save_registers(list : TAsmList);override;
- procedure g_restore_registers(list : TAsmList);override;
- procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
- procedure fixref(list : TAsmList;var ref : treference);
- function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference; virtual;
- procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
- procedure g_adjust_self_value(list:TAsmList;procdef: tprocdef;ioffset: tcgint); override;
- procedure g_stackpointer_alloc(list : TAsmList;size : longint);override;
- procedure a_loadmm_reg_reg(list: TAsmList; fromsize, tosize : tcgsize;reg1, reg2: tregister;shuffle : pmmshuffle); override;
- procedure a_loadmm_ref_reg(list: TAsmList; fromsize, tosize : tcgsize;const ref: treference; reg: tregister;shuffle : pmmshuffle); override;
- procedure a_loadmm_reg_ref(list: TAsmList; fromsize, tosize : tcgsize;reg: tregister; const ref: treference;shuffle : pmmshuffle); override;
- procedure a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize : tcgsize;intreg, mmreg: tregister; shuffle: pmmshuffle); override;
- procedure a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize : tcgsize;mmreg, intreg: tregister; shuffle : pmmshuffle); override;
- procedure a_opmm_reg_reg(list: TAsmList; Op: TOpCG; size : tcgsize;src,dst: tregister;shuffle : pmmshuffle); override;
- { Transform unsupported methods into Internal errors }
- procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister); override;
- { try to generate optimized 32 Bit multiplication, returns true if successful generated }
- function try_optimized_mul32_const_reg_reg(list: TAsmList; a: tcgint; src, dst: tregister) : boolean;
- { clear out potential overflow bits from 8 or 16 bit operations }
- { the upper 24/16 bits of a register after an operation }
- procedure maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
- function get_darwin_call_stub(const s: string; weak: boolean): tasmsymbol;
- end;
- tarmcgarm = class(tcgarm)
- procedure init_register_allocators;override;
- procedure done_register_allocators;override;
- procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
- procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
- end;
- tcg64farm = class(tcg64f32)
- procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
- procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
- procedure a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);override;
- procedure a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
- procedure a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
- procedure a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
- procedure a_loadmm_intreg64_reg(list: TAsmList; mmsize: tcgsize; intreg: tregister64; mmreg: tregister);override;
- procedure a_loadmm_reg_intreg64(list: TAsmList; mmsize: tcgsize; mmreg: tregister; intreg: tregister64);override;
- end;
- Tthumb2cgarm = class(tcgarm)
- procedure init_register_allocators;override;
- procedure done_register_allocators;override;
- procedure a_call_reg(list : TAsmList;reg: tregister);override;
- procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
- procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
- procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
- procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
- procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
- procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
- procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
- function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference; override;
- procedure a_loadmm_reg_reg(list: TAsmList; fromsize, tosize : tcgsize;reg1, reg2: tregister;shuffle : pmmshuffle); override;
- procedure a_loadmm_ref_reg(list: TAsmList; fromsize, tosize : tcgsize;const ref: treference; reg: tregister;shuffle : pmmshuffle); override;
- procedure a_loadmm_reg_ref(list: TAsmList; fromsize, tosize : tcgsize;reg: tregister; const ref: treference;shuffle : pmmshuffle); override;
- procedure a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize : tcgsize;intreg, mmreg: tregister; shuffle: pmmshuffle); override;
- procedure a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize : tcgsize;mmreg, intreg: tregister; shuffle : pmmshuffle); override;
- end;
- tthumb2cg64farm = class(tcg64farm)
- procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
- end;
- const
- OpCmp2AsmCond : Array[topcmp] of TAsmCond = (C_NONE,C_EQ,C_GT,
- C_LT,C_GE,C_LE,C_NE,C_LS,C_CC,C_CS,C_HI);
- winstackpagesize = 4096;
- function get_fpu_postfix(def : tdef) : toppostfix;
- procedure create_codegen;
- implementation
- uses
- globals,verbose,systems,cutils,
- aopt,aoptcpu,
- fmodule,
- symconst,symsym,symtable,
- tgobj,
- procinfo,cpupi,
- paramgr;
- function get_fpu_postfix(def : tdef) : toppostfix;
- begin
- if def.typ=floatdef then
- begin
- case tfloatdef(def).floattype of
- s32real:
- result:=PF_S;
- s64real:
- result:=PF_D;
- s80real:
- result:=PF_E;
- else
- internalerror(200401272);
- end;
- end
- else
- internalerror(200401271);
- end;
- procedure tarmcgarm.init_register_allocators;
- begin
- inherited init_register_allocators;
- { currently, we always save R14, so we can use it }
- if (target_info.system<>system_arm_darwin) then
- begin
- if assigned(current_procinfo) and (current_procinfo.framepointer<>NR_R11) then
- rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
- [RS_R0,RS_R1,RS_R2,RS_R3,RS_R12,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
- RS_R9,RS_R10,RS_R11,RS_R14],first_int_imreg,[])
- else
- rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
- [RS_R0,RS_R1,RS_R2,RS_R3,RS_R12,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
- RS_R9,RS_R10,RS_R14],first_int_imreg,[])
- end
- else
- { r7 is not available on Darwin, it's used as frame pointer (always,
- for backtrace support -- also in gcc/clang -> R11 can be used).
- r9 is volatile }
- rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
- [RS_R0,RS_R1,RS_R2,RS_R3,RS_R9,RS_R12,RS_R4,RS_R5,RS_R6,RS_R8,
- RS_R10,RS_R11,RS_R14],first_int_imreg,[]);
- rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
- [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
- { The register allocator currently cannot deal with multiple
- non-overlapping subregs per register, so we can only use
- half the single precision registers for now (as sub registers of the
- double precision ones). }
- if current_settings.fputype=fpu_vfpv3 then
- rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
- [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,
- RS_D16,RS_D17,RS_D18,RS_D19,RS_D20,RS_D21,RS_D22,RS_D23,RS_D24,RS_D25,RS_D26,RS_D27,RS_D28,RS_D29,RS_D30,RS_D31,
- RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15
- ],first_mm_imreg,[])
- else
- rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
- [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15],first_mm_imreg,[]);
- end;
- procedure tarmcgarm.done_register_allocators;
- begin
- rg[R_INTREGISTER].free;
- rg[R_FPUREGISTER].free;
- rg[R_MMREGISTER].free;
- inherited done_register_allocators;
- end;
- procedure tarmcgarm.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
- var
- imm_shift : byte;
- l : tasmlabel;
- hr : treference;
- imm1, imm2: DWord;
- begin
- if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
- internalerror(2002090902);
- if is_shifter_const(a,imm_shift) then
- list.concat(taicpu.op_reg_const(A_MOV,reg,a))
- else if is_shifter_const(not(a),imm_shift) then
- list.concat(taicpu.op_reg_const(A_MVN,reg,not(a)))
- { loading of constants with mov and orr }
- else if (split_into_shifter_const(a,imm1, imm2)) then
- begin
- list.concat(taicpu.op_reg_const(A_MOV,reg, imm1));
- list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg, imm2));
- end
- { loading of constants with mvn and bic }
- else if (split_into_shifter_const(not(a), imm1, imm2)) then
- begin
- list.concat(taicpu.op_reg_const(A_MVN,reg, imm1));
- list.concat(taicpu.op_reg_reg_const(A_BIC,reg,reg, imm2));
- end
- else
- begin
- reference_reset(hr,4);
- current_asmdata.getjumplabel(l);
- cg.a_label(current_procinfo.aktlocaldata,l);
- hr.symboldata:=current_procinfo.aktlocaldata.last;
- current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(longint(a)));
- hr.symbol:=l;
- hr.base:=NR_PC;
- list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
- end;
- end;
- procedure tarmcgarm.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);
- var
- oppostfix:toppostfix;
- usedtmpref: treference;
- tmpreg,tmpreg2 : tregister;
- so : tshifterop;
- dir : integer;
- begin
- if (TCGSize2Size[FromSize] >= TCGSize2Size[ToSize]) then
- FromSize := ToSize;
- case FromSize of
- { signed integer registers }
- OS_8:
- oppostfix:=PF_B;
- OS_S8:
- oppostfix:=PF_SB;
- OS_16:
- oppostfix:=PF_H;
- OS_S16:
- oppostfix:=PF_SH;
- OS_32,
- OS_S32:
- oppostfix:=PF_None;
- else
- InternalError(200308297);
- end;
- if (ref.alignment in [1,2]) and (ref.alignment<tcgsize2size[fromsize]) then
- begin
- if target_info.endian=endian_big then
- dir:=-1
- else
- dir:=1;
- case FromSize of
- OS_16,OS_S16:
- begin
- { only complicated references need an extra loadaddr }
- if assigned(ref.symbol) or
- (ref.index<>NR_NO) or
- (ref.offset<-4095) or
- (ref.offset>4094) or
- { sometimes the compiler reused registers }
- (reg=ref.index) or
- (reg=ref.base) then
- begin
- tmpreg2:=getintregister(list,OS_INT);
- a_loadaddr_ref_reg(list,ref,tmpreg2);
- reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
- end
- else
- usedtmpref:=ref;
- if target_info.endian=endian_big then
- inc(usedtmpref.offset,1);
- shifterop_reset(so);so.shiftmode:=SM_LSL;so.shiftimm:=8;
- tmpreg:=getintregister(list,OS_INT);
- a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
- inc(usedtmpref.offset,dir);
- if FromSize=OS_16 then
- a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg)
- else
- a_internal_load_ref_reg(list,OS_S8,OS_S8,usedtmpref,tmpreg);
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
- end;
- OS_32,OS_S32:
- begin
- tmpreg:=getintregister(list,OS_INT);
- { only complicated references need an extra loadaddr }
- if assigned(ref.symbol) or
- (ref.index<>NR_NO) or
- (ref.offset<-4095) or
- (ref.offset>4092) or
- { sometimes the compiler reused registers }
- (reg=ref.index) or
- (reg=ref.base) then
- begin
- tmpreg2:=getintregister(list,OS_INT);
- a_loadaddr_ref_reg(list,ref,tmpreg2);
- reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
- end
- else
- usedtmpref:=ref;
- shifterop_reset(so);so.shiftmode:=SM_LSL;
- if ref.alignment=2 then
- begin
- if target_info.endian=endian_big then
- inc(usedtmpref.offset,2);
- a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,reg);
- inc(usedtmpref.offset,dir*2);
- a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,tmpreg);
- so.shiftimm:=16;
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
- end
- else
- begin
- tmpreg2:=getintregister(list,OS_INT);
- if target_info.endian=endian_big then
- inc(usedtmpref.offset,3);
- a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
- inc(usedtmpref.offset,dir);
- a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
- inc(usedtmpref.offset,dir);
- a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg2);
- so.shiftimm:=8;
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
- inc(usedtmpref.offset,dir);
- a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
- so.shiftimm:=16;
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg2,so));
- so.shiftimm:=24;
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
- end;
- end
- else
- handle_load_store(list,A_LDR,oppostfix,reg,ref);
- end;
- end
- else
- handle_load_store(list,A_LDR,oppostfix,reg,ref);
- if (fromsize=OS_S8) and (tosize = OS_16) then
- a_load_reg_reg(list,OS_16,OS_32,reg,reg);
- end;
- procedure tcgarm.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
- var
- ref: treference;
- begin
- paraloc.check_simple_location;
- paramanager.allocparaloc(list,paraloc.location);
- case paraloc.location^.loc of
- LOC_REGISTER,LOC_CREGISTER:
- a_load_const_reg(list,size,a,paraloc.location^.register);
- LOC_REFERENCE:
- begin
- reference_reset(ref,paraloc.alignment);
- ref.base:=paraloc.location^.reference.index;
- ref.offset:=paraloc.location^.reference.offset;
- a_load_const_ref(list,size,a,ref);
- end;
- else
- internalerror(2002081101);
- end;
- end;
- procedure tcgarm.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
- var
- tmpref, ref: treference;
- location: pcgparalocation;
- sizeleft: aint;
- begin
- location := paraloc.location;
- tmpref := r;
- sizeleft := paraloc.intsize;
- while assigned(location) do
- begin
- paramanager.allocparaloc(list,location);
- case location^.loc of
- LOC_REGISTER,LOC_CREGISTER:
- a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
- LOC_REFERENCE:
- begin
- reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
- { doubles in softemu mode have a strange order of registers and references }
- if location^.size=OS_32 then
- g_concatcopy(list,tmpref,ref,4)
- else
- begin
- g_concatcopy(list,tmpref,ref,sizeleft);
- if assigned(location^.next) then
- internalerror(2005010710);
- end;
- end;
- LOC_FPUREGISTER,LOC_CFPUREGISTER:
- case location^.size of
- OS_F32, OS_F64:
- a_loadfpu_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
- else
- internalerror(2002072801);
- end;
- LOC_VOID:
- begin
- // nothing to do
- end;
- else
- internalerror(2002081103);
- end;
- inc(tmpref.offset,tcgsize2size[location^.size]);
- dec(sizeleft,tcgsize2size[location^.size]);
- location := location^.next;
- end;
- end;
- procedure tcgarm.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
- var
- ref: treference;
- tmpreg: tregister;
- begin
- paraloc.check_simple_location;
- paramanager.allocparaloc(list,paraloc.location);
- case paraloc.location^.loc of
- LOC_REGISTER,LOC_CREGISTER:
- a_loadaddr_ref_reg(list,r,paraloc.location^.register);
- LOC_REFERENCE:
- begin
- reference_reset(ref,paraloc.alignment);
- ref.base := paraloc.location^.reference.index;
- ref.offset := paraloc.location^.reference.offset;
- tmpreg := getintregister(list,OS_ADDR);
- a_loadaddr_ref_reg(list,r,tmpreg);
- a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
- end;
- else
- internalerror(2002080701);
- end;
- end;
- procedure tcgarm.a_call_name(list : TAsmList;const s : string; weak: boolean);
- var
- branchopcode: tasmop;
- begin
- { check not really correct: should only be used for non-Thumb cpus }
- if CPUARM_HAS_BLX_LABEL in cpu_capabilities[current_settings.cputype] then
- branchopcode:=A_BLX
- else
- branchopcode:=A_BL;
- if target_info.system<>system_arm_darwin then
- if not weak then
- list.concat(taicpu.op_sym(branchopcode,current_asmdata.RefAsmSymbol(s)))
- else
- list.concat(taicpu.op_sym(branchopcode,current_asmdata.WeakRefAsmSymbol(s)))
- else
- list.concat(taicpu.op_sym(branchopcode,get_darwin_call_stub(s,weak)));
- {
- the compiler does not properly set this flag anymore in pass 1, and
- for now we only need it after pass 2 (I hope) (JM)
- if not(pi_do_call in current_procinfo.flags) then
- internalerror(2003060703);
- }
- include(current_procinfo.flags,pi_do_call);
- end;
- procedure tcgarm.a_call_reg(list : TAsmList;reg: tregister);
- begin
- { check not really correct: should only be used for non-Thumb cpus }
- if not(CPUARM_HAS_BLX in cpu_capabilities[current_settings.cputype]) then
- begin
- list.concat(taicpu.op_reg_reg(A_MOV,NR_R14,NR_PC));
- list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,reg));
- end
- else
- list.concat(taicpu.op_reg(A_BLX, reg));
- {
- the compiler does not properly set this flag anymore in pass 1, and
- for now we only need it after pass 2 (I hope) (JM)
- if not(pi_do_call in current_procinfo.flags) then
- internalerror(2003060703);
- }
- include(current_procinfo.flags,pi_do_call);
- end;
- procedure tcgarm.a_call_ref(list : TAsmList;ref: treference);
- begin
- a_reg_alloc(list,NR_R12);
- a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,NR_R12);
- a_call_reg(list,NR_R12);
- a_reg_dealloc(list,NR_R12);
- include(current_procinfo.flags,pi_do_call);
- end;
- procedure tcgarm.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
- begin
- a_op_const_reg_reg(list,op,size,a,reg,reg);
- end;
- procedure tcgarm.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
- var
- so : tshifterop;
- begin
- if op = OP_NEG then
- list.concat(taicpu.op_reg_reg_const(A_RSB,dst,src,0))
- else if op = OP_NOT then
- begin
- if size in [OS_8, OS_16, OS_S8, OS_S16] then
- begin
- shifterop_reset(so);
- so.shiftmode:=SM_LSL;
- if size in [OS_8, OS_S8] then
- so.shiftimm:=24
- else
- so.shiftimm:=16;
- list.concat(taicpu.op_reg_reg_shifterop(A_MVN,dst,src,so));
- {Using a shift here allows this to be folded into another instruction}
- if size in [OS_S8, OS_S16] then
- so.shiftmode:=SM_ASR
- else
- so.shiftmode:=SM_LSR;
- list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,dst,so));
- end
- else
- list.concat(taicpu.op_reg_reg(A_MVN,dst,src));
- end
- else
- a_op_reg_reg_reg(list,op,OS_32,src,dst,dst);
- end;
- const
- op_reg_reg_opcg2asmop: array[TOpCG] of tasmop =
- (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,A_NONE,A_MUL,A_MUL,A_NONE,A_NONE,A_ORR,
- A_NONE,A_NONE,A_NONE,A_SUB,A_EOR,A_NONE,A_NONE);
- procedure tcgarm.a_op_const_reg_reg(list: TAsmList; op: TOpCg;
- size: tcgsize; a: tcgint; src, dst: tregister);
- var
- ovloc : tlocation;
- begin
- a_op_const_reg_reg_checkoverflow(list,op,size,a,src,dst,false,ovloc);
- end;
- procedure tcgarm.a_op_reg_reg_reg(list: TAsmList; op: TOpCg;
- size: tcgsize; src1, src2, dst: tregister);
- var
- ovloc : tlocation;
- begin
- a_op_reg_reg_reg_checkoverflow(list,op,size,src1,src2,dst,false,ovloc);
- end;
- function opshift2shiftmode(op: TOpCg): tshiftmode;
- begin
- case op of
- OP_SHL: Result:=SM_LSL;
- OP_SHR: Result:=SM_LSR;
- OP_ROR: Result:=SM_ROR;
- OP_ROL: Result:=SM_ROR;
- OP_SAR: Result:=SM_ASR;
- else internalerror(2012070501);
- end
- end;
- function tcgarm.try_optimized_mul32_const_reg_reg(list: TAsmList; a: tcgint; src, dst: tregister) : boolean;
- var
- multiplier : dword;
- power : longint;
- shifterop : tshifterop;
- bitsset : byte;
- negative : boolean;
- first : boolean;
- b,
- cycles : byte;
- maxeffort : byte;
- begin
- result:=true;
- cycles:=0;
- negative:=a<0;
- shifterop.rs:=NR_NO;
- shifterop.shiftmode:=SM_LSL;
- if negative then
- inc(cycles);
- multiplier:=dword(abs(a));
- bitsset:=popcnt(multiplier and $fffffffe);
- { heuristics to estimate how much instructions are reasonable to replace the mul,
- this is currently based on XScale timings }
- { in the simplest case, we need a mov to load the constant and a mul to carry out the
- actual multiplication, this requires min. 1+4 cycles
- because the first shift imm. might cause a stall and because we need more instructions
- when replacing the mul we generate max. 3 instructions to replace this mul }
- maxeffort:=3;
- { if the constant is not a shifter op, we need either some mov/mvn/bic/or sequence or
- a ldr, so generating one more operation to replace this is beneficial }
- if not(is_shifter_const(dword(a),b)) and not(is_shifter_const(not(dword(a)),b)) then
- inc(maxeffort);
- { if the upper 5 bits are all set or clear, mul is one cycle faster }
- if ((dword(a) and $f8000000)=0) or ((dword(a) and $f8000000)=$f8000000) then
- dec(maxeffort);
- { if the upper 17 bits are all set or clear, mul is another cycle faster }
- if ((dword(a) and $ffff8000)=0) or ((dword(a) and $ffff8000)=$ffff8000) then
- dec(maxeffort);
- { most simple cases }
- if a=1 then
- a_load_reg_reg(list,OS_32,OS_32,src,dst)
- else if a=0 then
- a_load_const_reg(list,OS_32,0,dst)
- else if a=-1 then
- a_op_reg_reg(list,OP_NEG,OS_32,src,dst)
- { add up ?
- basically, one add is needed for each bit being set in the constant factor
- however, the least significant bit is for free, it can be hidden in the initial
- instruction
- }
- else if (bitsset+cycles<=maxeffort) and
- (bitsset<=popcnt(dword(nextpowerof2(multiplier,power)-multiplier) and $fffffffe)) then
- begin
- first:=true;
- while multiplier<>0 do
- begin
- shifterop.shiftimm:=BsrDWord(multiplier);
- if odd(multiplier) then
- begin
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,src,src,shifterop));
- dec(multiplier);
- end
- else
- if first then
- list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,shifterop))
- else
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,dst,src,shifterop));
- first:=false;
- dec(multiplier,1 shl shifterop.shiftimm);
- end;
- if negative then
- list.concat(taicpu.op_reg_reg_const(A_RSB,dst,dst,0));
- end
- { subtract from the next greater power of two? }
- else if popcnt(dword(nextpowerof2(multiplier,power)-multiplier) and $fffffffe)+cycles+1<=maxeffort then
- begin
- first:=true;
- while multiplier<>0 do
- begin
- if first then
- begin
- multiplier:=(1 shl power)-multiplier;
- shifterop.shiftimm:=power;
- end
- else
- shifterop.shiftimm:=BsrDWord(multiplier);
- if odd(multiplier) then
- begin
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_RSB,dst,src,src,shifterop));
- dec(multiplier);
- end
- else
- if first then
- list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,shifterop))
- else
- begin
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_SUB,dst,dst,src,shifterop));
- dec(multiplier,1 shl shifterop.shiftimm);
- end;
- first:=false;
- end;
- if negative then
- list.concat(taicpu.op_reg_reg_const(A_RSB,dst,dst,0));
- end
- else
- result:=false;
- end;
- procedure tcgarm.a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);
- var
- shift : byte;
- tmpreg : tregister;
- so : tshifterop;
- l1 : longint;
- imm1, imm2: DWord;
- begin
- ovloc.loc:=LOC_VOID;
- if {$ifopt R+}(a<>-2147483648) and{$endif} not setflags and is_shifter_const(-a,shift) then
- case op of
- OP_ADD:
- begin
- op:=OP_SUB;
- a:=aint(dword(-a));
- end;
- OP_SUB:
- begin
- op:=OP_ADD;
- a:=aint(dword(-a));
- end
- end;
- if is_shifter_const(a,shift) and not(op in [OP_IMUL,OP_MUL]) then
- case op of
- OP_NEG,OP_NOT:
- internalerror(200308281);
- OP_SHL,
- OP_SHR,
- OP_ROL,
- OP_ROR,
- OP_SAR:
- begin
- if a>32 then
- internalerror(200308294);
- if a<>0 then
- begin
- shifterop_reset(so);
- so.shiftmode:=opshift2shiftmode(op);
- if op = OP_ROL then
- so.shiftimm:=32-a
- else
- so.shiftimm:=a;
- list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
- end
- else
- list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
- end;
- else
- {if (op in [OP_SUB, OP_ADD]) and
- ((a < 0) or
- (a > 4095)) then
- begin
- tmpreg:=getintregister(list,size);
- list.concat(taicpu.op_reg_const(A_MOVT, tmpreg, (a shr 16) and $FFFF));
- list.concat(taicpu.op_reg_const(A_MOV, tmpreg, a and $FFFF));
- list.concat(setoppostfix(taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src,tmpreg),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))
- ));
- end
- else}
- begin
- if cgsetflags or setflags then
- a_reg_alloc(list,NR_DEFAULTFLAGS);
- list.concat(setoppostfix(
- taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))));
- end;
- if (cgsetflags or setflags) and (size in [OS_8,OS_16,OS_32]) then
- begin
- ovloc.loc:=LOC_FLAGS;
- case op of
- OP_ADD:
- ovloc.resflags:=F_CS;
- OP_SUB:
- ovloc.resflags:=F_CC;
- end;
- end;
- end
- else
- begin
- { there could be added some more sophisticated optimizations }
- if (op in [OP_MUL,OP_IMUL,OP_DIV,OP_IDIV]) and (a=1) then
- a_load_reg_reg(list,size,size,src,dst)
- else if (op in [OP_MUL,OP_IMUL]) and (a=0) then
- a_load_const_reg(list,size,0,dst)
- else if (op in [OP_IMUL,OP_IDIV]) and (a=-1) then
- a_op_reg_reg(list,OP_NEG,size,src,dst)
- { we do this here instead in the peephole optimizer because
- it saves us a register }
- else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a,l1) and not(cgsetflags or setflags) then
- a_op_const_reg_reg(list,OP_SHL,size,l1,src,dst)
- { for example : b=a*5 -> b=a*4+a with add instruction and shl }
- else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
- begin
- if l1>32 then{roozbeh does this ever happen?}
- internalerror(200308296);
- shifterop_reset(so);
- so.shiftmode:=SM_LSL;
- so.shiftimm:=l1;
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,src,src,so));
- end
- { for example : b=a*7 -> b=a*8-a with rsb instruction and shl }
- else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a+1,l1) and not(cgsetflags or setflags) then
- begin
- if l1>32 then{does this ever happen?}
- internalerror(201205181);
- shifterop_reset(so);
- so.shiftmode:=SM_LSL;
- so.shiftimm:=l1;
- list.concat(taicpu.op_reg_reg_reg_shifterop(A_RSB,dst,src,src,so));
- end
- else if (op in [OP_MUL,OP_IMUL]) and not(cgsetflags or setflags) and try_optimized_mul32_const_reg_reg(list,a,src,dst) then
- begin
- { nothing to do on success }
- end
- { x := y and 0; just clears a register, this sometimes gets generated on 64bit ops.
- Just using mov x, #0 might allow some easier optimizations down the line. }
- else if (op = OP_AND) and (dword(a)=0) then
- list.concat(taicpu.op_reg_const(A_MOV,dst,0))
- { x := y AND $FFFFFFFF just copies the register, so use mov for better optimizations }
- else if (op = OP_AND) and (not(dword(a))=0) then
- list.concat(taicpu.op_reg_reg(A_MOV,dst,src))
- { BIC clears the specified bits, while AND keeps them, using BIC allows to use a
- broader range of shifterconstants.}
- else if (op = OP_AND) and is_shifter_const(not(dword(a)),shift) then
- list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a))))
- else if (op = OP_AND) and split_into_shifter_const(not(dword(a)), imm1, imm2) then
- begin
- list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,imm1));
- list.concat(taicpu.op_reg_reg_const(A_BIC,dst,dst,imm2));
- end
- else if (op in [OP_ADD, OP_SUB, OP_OR]) and
- not(cgsetflags or setflags) and
- split_into_shifter_const(a, imm1, imm2) then
- begin
- list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,imm1));
- list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,dst,imm2));
- end
- else
- begin
- tmpreg:=getintregister(list,size);
- a_load_const_reg(list,size,a,tmpreg);
- a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
- end;
- end;
- maybeadjustresult(list,op,size,dst);
- end;
- procedure tcgarm.a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);
- var
- so : tshifterop;
- tmpreg,overflowreg : tregister;
- asmop : tasmop;
- begin
- ovloc.loc:=LOC_VOID;
- case op of
- OP_NEG,OP_NOT,
- OP_DIV,OP_IDIV:
- internalerror(200308281);
- OP_SHL,
- OP_SHR,
- OP_SAR,
- OP_ROR:
- begin
- if (op = OP_ROR) and not(size in [OS_32,OS_S32]) then
- internalerror(2008072801);
- shifterop_reset(so);
- so.rs:=src1;
- so.shiftmode:=opshift2shiftmode(op);
- list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
- end;
- OP_ROL:
- begin
- if not(size in [OS_32,OS_S32]) then
- internalerror(2008072801);
- { simulate ROL by ror'ing 32-value }
- tmpreg:=getintregister(list,OS_32);
- list.concat(taicpu.op_reg_reg_const(A_RSB,tmpreg,src1, 32));
- shifterop_reset(so);
- so.rs:=tmpreg;
- so.shiftmode:=SM_ROR;
- list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
- end;
- OP_IMUL,
- OP_MUL:
- begin
- if cgsetflags or setflags then
- begin
- overflowreg:=getintregister(list,size);
- if op=OP_IMUL then
- asmop:=A_SMULL
- else
- asmop:=A_UMULL;
- { the arm doesn't allow that rd and rm are the same }
- if dst=src2 then
- begin
- if dst<>src1 then
- list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src1,src2))
- else
- begin
- tmpreg:=getintregister(list,size);
- a_load_reg_reg(list,size,size,src2,dst);
- list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,tmpreg,src1));
- end;
- end
- else
- list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src2,src1));
- a_reg_alloc(list,NR_DEFAULTFLAGS);
- if op=OP_IMUL then
- begin
- shifterop_reset(so);
- so.shiftmode:=SM_ASR;
- so.shiftimm:=31;
- list.concat(taicpu.op_reg_reg_shifterop(A_CMP,overflowreg,dst,so));
- end
- else
- list.concat(taicpu.op_reg_const(A_CMP,overflowreg,0));
- ovloc.loc:=LOC_FLAGS;
- ovloc.resflags:=F_NE;
- end
- else
- begin
- { the arm doesn't allow that rd and rm are the same }
- if dst=src2 then
- begin
- if dst<>src1 then
- list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src1,src2))
- else
- begin
- tmpreg:=getintregister(list,size);
- a_load_reg_reg(list,size,size,src2,dst);
- list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,tmpreg,src1));
- end;
- end
- else
- list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src2,src1));
- end;
- end;
- else
- begin
- if cgsetflags or setflags then
- a_reg_alloc(list,NR_DEFAULTFLAGS);
- list.concat(setoppostfix(
- taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))));
- end;
- end;
- maybeadjustresult(list,op,size,dst);
- end;
- function tcgarm.handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference;
- var
- tmpreg : tregister;
- tmpref : treference;
- l : tasmlabel;
- begin
- tmpreg:=NR_NO;
- { Be sure to have a base register }
- if (ref.base=NR_NO) then
- begin
- if ref.shiftmode<>SM_None then
- internalerror(200308294);
- ref.base:=ref.index;
- ref.index:=NR_NO;
- end;
- { absolute symbols can't be handled directly, we've to store the symbol reference
- in the text segment and access it pc relative
- For now, we assume that references where base or index equals to PC are already
- relative, all other references are assumed to be absolute and thus they need
- to be handled extra.
- A proper solution would be to change refoptions to a set and store the information
- if the symbol is absolute or relative there.
- }
- if (assigned(ref.symbol) and
- not(is_pc(ref.base)) and
- not(is_pc(ref.index))
- ) or
- { [#xxx] isn't a valid address operand }
- ((ref.base=NR_NO) and (ref.index=NR_NO)) or
- (ref.offset<-4095) or
- (ref.offset>4095) or
- ((oppostfix in [PF_SB,PF_H,PF_SH]) and
- ((ref.offset<-255) or
- (ref.offset>255)
- )
- ) or
- ((op in [A_LDF,A_STF,A_FLDS,A_FLDD,A_FSTS,A_FSTD]) and
- ((ref.offset<-1020) or
- (ref.offset>1020) or
- ((abs(ref.offset) mod 4)<>0)
- )
- ) then
- begin
- fixref(list,ref);
- end;
- { fold if there is base, index and offset, however, don't fold
- for vfp memory instructions because we later fold the index }
- if not(op in [A_FLDS,A_FLDD,A_FSTS,A_FSTD]) and
- (ref.base<>NR_NO) and (ref.index<>NR_NO) and (ref.offset<>0) then
- begin
- if tmpreg<>NR_NO then
- a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,tmpreg,tmpreg)
- else
- begin
- tmpreg:=getintregister(list,OS_ADDR);
- a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,ref.base,tmpreg);
- ref.base:=tmpreg;
- end;
- ref.offset:=0;
- end;
- { floating point operations have only limited references
- we expect here, that a base is already set }
- if (op in [A_LDF,A_STF,A_FLDS,A_FLDD,A_FSTS,A_FSTD]) and (ref.index<>NR_NO) then
- begin
- if ref.shiftmode<>SM_none then
- internalerror(200309121);
- if tmpreg<>NR_NO then
- begin
- if ref.base=tmpreg then
- begin
- if ref.signindex<0 then
- list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg,tmpreg,ref.index))
- else
- list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,tmpreg,ref.index));
- ref.index:=NR_NO;
- end
- else
- begin
- if ref.index<>tmpreg then
- internalerror(200403161);
- if ref.signindex<0 then
- list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg,ref.base,tmpreg))
- else
- list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
- ref.base:=tmpreg;
- ref.index:=NR_NO;
- end;
- end
- else
- begin
- tmpreg:=getintregister(list,OS_ADDR);
- list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,ref.index));
- ref.base:=tmpreg;
- ref.index:=NR_NO;
- end;
- end;
- list.concat(setoppostfix(taicpu.op_reg_ref(op,reg,ref),oppostfix));
- Result := ref;
- end;
- procedure tcgarm.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
- var
- oppostfix:toppostfix;
- usedtmpref: treference;
- tmpreg : tregister;
- so : tshifterop;
- dir : integer;
- begin
- if (TCGSize2Size[FromSize] >= TCGSize2Size[ToSize]) then
- FromSize := ToSize;
- case ToSize of
- { signed integer registers }
- OS_8,
- OS_S8:
- oppostfix:=PF_B;
- OS_16,
- OS_S16:
- oppostfix:=PF_H;
- OS_32,
- OS_S32,
- { for vfp value stored in integer register }
- OS_F32:
- oppostfix:=PF_None;
- else
- Inter…