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/Ethereal-msm8939-beta9/arch/m68k/include/asm/m5272sim.h

https://bitbucket.org/MilosStamenkovic95/etherealos
C Header | 140 lines | 102 code | 19 blank | 19 comment | 0 complexity | 4bc65d2a82e02045bff5dcaaaaf6a836 MD5 | raw file
  1/****************************************************************************/
  2
  3/*
  4 *	m5272sim.h -- ColdFire 5272 System Integration Module support.
  5 *
  6 *	(C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
  7 * 	(C) Copyright 2000, Lineo Inc. (www.lineo.com) 
  8 */
  9
 10/****************************************************************************/
 11#ifndef	m5272sim_h
 12#define	m5272sim_h
 13/****************************************************************************/
 14
 15#define	CPU_NAME		"COLDFIRE(m5272)"
 16#define	CPU_INSTR_PER_JIFFY	3
 17#define	MCF_BUSCLK		MCF_CLK
 18
 19#include <asm/m52xxacr.h>
 20
 21/*
 22 *	Define the 5272 SIM register set addresses.
 23 */
 24#define	MCFSIM_SCR		(MCF_MBAR + 0x04)	/* SIM Config reg */
 25#define	MCFSIM_SPR		(MCF_MBAR + 0x06)	/* System Protection */
 26#define	MCFSIM_PMR		(MCF_MBAR + 0x08)	/* Power Management */
 27#define	MCFSIM_APMR		(MCF_MBAR + 0x0e)	/* Active Low Power */
 28#define	MCFSIM_DIR		(MCF_MBAR + 0x10)	/* Device Identity */
 29
 30#define	MCFSIM_ICR1		(MCF_MBAR + 0x20)	/* Intr Ctrl reg 1 */
 31#define	MCFSIM_ICR2		(MCF_MBAR + 0x24)	/* Intr Ctrl reg 2 */
 32#define	MCFSIM_ICR3		(MCF_MBAR + 0x28)	/* Intr Ctrl reg 3 */
 33#define	MCFSIM_ICR4		(MCF_MBAR + 0x2c)	/* Intr Ctrl reg 4 */
 34
 35#define	MCFSIM_ISR		(MCF_MBAR + 0x30)	/* Intr Source */
 36#define	MCFSIM_PITR		(MCF_MBAR + 0x34)	/* Intr Transition */
 37#define	MCFSIM_PIWR		(MCF_MBAR + 0x38)	/* Intr Wakeup */
 38#define	MCFSIM_PIVR		(MCF_MBAR + 0x3f)	/* Intr Vector */
 39
 40#define	MCFSIM_WRRR		(MCF_MBAR + 0x280)	/* Watchdog reference */
 41#define	MCFSIM_WIRR		(MCF_MBAR + 0x284)	/* Watchdog interrupt */
 42#define	MCFSIM_WCR		(MCF_MBAR + 0x288)	/* Watchdog counter */
 43#define	MCFSIM_WER		(MCF_MBAR + 0x28c)	/* Watchdog event */
 44
 45#define	MCFSIM_CSBR0		(MCF_MBAR + 0x40)	/* CS0 Base Address */
 46#define	MCFSIM_CSOR0		(MCF_MBAR + 0x44)	/* CS0 Option */
 47#define	MCFSIM_CSBR1		(MCF_MBAR + 0x48)	/* CS1 Base Address */
 48#define	MCFSIM_CSOR1		(MCF_MBAR + 0x4c)	/* CS1 Option */
 49#define	MCFSIM_CSBR2		(MCF_MBAR + 0x50)	/* CS2 Base Address */
 50#define	MCFSIM_CSOR2		(MCF_MBAR + 0x54)	/* CS2 Option */
 51#define	MCFSIM_CSBR3		(MCF_MBAR + 0x58)	/* CS3 Base Address */
 52#define	MCFSIM_CSOR3		(MCF_MBAR + 0x5c)	/* CS3 Option */
 53#define	MCFSIM_CSBR4		(MCF_MBAR + 0x60)	/* CS4 Base Address */
 54#define	MCFSIM_CSOR4		(MCF_MBAR + 0x64)	/* CS4 Option */
 55#define	MCFSIM_CSBR5		(MCF_MBAR + 0x68)	/* CS5 Base Address */
 56#define	MCFSIM_CSOR5		(MCF_MBAR + 0x6c)	/* CS5 Option */
 57#define	MCFSIM_CSBR6		(MCF_MBAR + 0x70)	/* CS6 Base Address */
 58#define	MCFSIM_CSOR6		(MCF_MBAR + 0x74)	/* CS6 Option */
 59#define	MCFSIM_CSBR7		(MCF_MBAR + 0x78)	/* CS7 Base Address */
 60#define	MCFSIM_CSOR7		(MCF_MBAR + 0x7c)	/* CS7 Option */
 61
 62#define	MCFSIM_SDCR		(MCF_MBAR + 0x180)	/* SDRAM Config */
 63#define	MCFSIM_SDTR		(MCF_MBAR + 0x184)	/* SDRAM Timing */
 64#define	MCFSIM_DCAR0		(MCF_MBAR + 0x4c)	/* DRAM 0 Address */
 65#define	MCFSIM_DCMR0		(MCF_MBAR + 0x50)	/* DRAM 0 Mask */
 66#define	MCFSIM_DCCR0		(MCF_MBAR + 0x57)	/* DRAM 0 Control */
 67#define	MCFSIM_DCAR1		(MCF_MBAR + 0x58)	/* DRAM 1 Address */
 68#define	MCFSIM_DCMR1		(MCF_MBAR + 0x5c)	/* DRAM 1 Mask reg */
 69#define	MCFSIM_DCCR1		(MCF_MBAR + 0x63)	/* DRAM 1 Control */
 70
 71#define	MCFUART_BASE0		(MCF_MBAR + 0x100) /* Base address UART0 */
 72#define	MCFUART_BASE1		(MCF_MBAR + 0x140) /* Base address UART1 */
 73
 74#define	MCFSIM_PACNT		(MCF_MBAR + 0x80) /* Port A Control (r/w) */
 75#define	MCFSIM_PADDR		(MCF_MBAR + 0x84) /* Port A Direction (r/w) */
 76#define	MCFSIM_PADAT		(MCF_MBAR + 0x86) /* Port A Data (r/w) */
 77#define	MCFSIM_PBCNT		(MCF_MBAR + 0x88) /* Port B Control (r/w) */
 78#define	MCFSIM_PBDDR		(MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
 79#define	MCFSIM_PBDAT		(MCF_MBAR + 0x8e) /* Port B Data (r/w) */
 80#define	MCFSIM_PCDDR		(MCF_MBAR + 0x94) /* Port C Direction (r/w) */
 81#define	MCFSIM_PCDAT		(MCF_MBAR + 0x96) /* Port C Data (r/w) */
 82#define	MCFSIM_PDCNT		(MCF_MBAR + 0x98) /* Port D Control (r/w) */
 83
 84#define	MCFDMA_BASE0		(MCF_MBAR + 0xe0) /* Base address DMA 0 */
 85
 86#define	MCFTIMER_BASE1		(MCF_MBAR + 0x200) /* Base address TIMER1 */
 87#define	MCFTIMER_BASE2		(MCF_MBAR + 0x220) /* Base address TIMER2 */
 88#define	MCFTIMER_BASE3		(MCF_MBAR + 0x240) /* Base address TIMER4 */
 89#define	MCFTIMER_BASE4		(MCF_MBAR + 0x260) /* Base address TIMER3 */
 90
 91#define	MCFFEC_BASE0		(MCF_MBAR + 0x840) /* Base FEC ethernet */
 92#define	MCFFEC_SIZE0		0x1d0
 93
 94/*
 95 *	Define system peripheral IRQ usage.
 96 */
 97#define	MCFINT_VECBASE		64		/* Base of interrupts */
 98#define	MCF_IRQ_SPURIOUS	64		/* User Spurious */
 99#define	MCF_IRQ_EINT1		65		/* External Interrupt 1 */
100#define	MCF_IRQ_EINT2		66		/* External Interrupt 2 */
101#define	MCF_IRQ_EINT3		67		/* External Interrupt 3 */
102#define	MCF_IRQ_EINT4		68		/* External Interrupt 4 */
103#define	MCF_IRQ_TIMER1		69		/* Timer 1 */
104#define	MCF_IRQ_TIMER2		70		/* Timer 2 */
105#define	MCF_IRQ_TIMER3		71		/* Timer 3 */
106#define	MCF_IRQ_TIMER4		72		/* Timer 4 */
107#define	MCF_IRQ_UART0		73		/* UART 0 */
108#define	MCF_IRQ_UART1		74		/* UART 1 */
109#define	MCF_IRQ_PLIP		75		/* PLIC 2Khz Periodic */
110#define	MCF_IRQ_PLIA		76		/* PLIC Asynchronous */
111#define	MCF_IRQ_USB0		77		/* USB Endpoint 0 */
112#define	MCF_IRQ_USB1		78		/* USB Endpoint 1 */
113#define	MCF_IRQ_USB2		79		/* USB Endpoint 2 */
114#define	MCF_IRQ_USB3		80		/* USB Endpoint 3 */
115#define	MCF_IRQ_USB4		81		/* USB Endpoint 4 */
116#define	MCF_IRQ_USB5		82		/* USB Endpoint 5 */
117#define	MCF_IRQ_USB6		83		/* USB Endpoint 6 */
118#define	MCF_IRQ_USB7		84		/* USB Endpoint 7 */
119#define	MCF_IRQ_DMA		85		/* DMA Controller */
120#define	MCF_IRQ_FECRX0		86		/* Ethernet Receiver */
121#define	MCF_IRQ_FECTX0		87		/* Ethernet Transmitter */
122#define	MCF_IRQ_FECENTC0	88		/* Ethernet Non-Time Critical */
123#define	MCF_IRQ_QSPI		89		/* Queued Serial Interface */
124#define	MCF_IRQ_EINT5		90		/* External Interrupt 5 */
125#define	MCF_IRQ_EINT6		91		/* External Interrupt 6 */
126#define	MCF_IRQ_SWTO		92		/* Software Watchdog */
127#define	MCFINT_VECMAX		95		/* Maxmum interrupt */
128
129#define	MCF_IRQ_TIMER		MCF_IRQ_TIMER1
130#define	MCF_IRQ_PROFILER	MCF_IRQ_TIMER2
131
132/*
133 * Generic GPIO support
134 */
135#define MCFGPIO_PIN_MAX		48
136#define MCFGPIO_IRQ_MAX		-1
137#define MCFGPIO_IRQ_VECBASE	-1
138
139/****************************************************************************/
140#endif	/* m5272sim_h */