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/Ethereal-msm8939-beta9/arch/m68k/platform/coldfire/m5441x.c

https://bitbucket.org/MilosStamenkovic95/etherealos
C | 261 lines | 233 code | 21 blank | 7 comment | 2 complexity | 26713f42b8da75353601db4c0c75b0f5 MD5 | raw file
  1/*
  2 *	m5441x.c -- support for Coldfire m5441x processors
  3 *
  4 *	(C) Copyright Steven King <sfking@fdwdc.com>
  5 */
  6
  7#include <linux/kernel.h>
  8#include <linux/param.h>
  9#include <linux/init.h>
 10#include <linux/io.h>
 11#include <linux/clk.h>
 12#include <asm/machdep.h>
 13#include <asm/coldfire.h>
 14#include <asm/mcfsim.h>
 15#include <asm/mcfuart.h>
 16#include <asm/mcfdma.h>
 17#include <asm/mcfclk.h>
 18
 19DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
 20DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
 21DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
 22DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
 23DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
 24DEFINE_CLK(0, "edma", 17, MCF_CLK);
 25DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
 26DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
 27DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
 28DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
 29DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
 30DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
 31DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
 32DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
 33DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
 34DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
 35DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
 36DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
 37DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
 38DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
 39DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
 40DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
 41DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
 42DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
 43DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
 44DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
 45DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
 46DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
 47DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
 48DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
 49DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
 50DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
 51DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
 52DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
 53DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
 54DEFINE_CLK(0, "mcfsdhc.0", 51, MCF_CLK);
 55DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
 56DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
 57DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
 58DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
 59DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
 60
 61DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
 62DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK);
 63DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK);
 64DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK);
 65DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK);
 66DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
 67DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
 68DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
 69DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
 70DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
 71DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
 72DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
 73DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
 74DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
 75
 76struct clk *mcf_clks[] = {
 77	&__clk_0_2,
 78	&__clk_0_8,
 79	&__clk_0_9,
 80	&__clk_0_14,
 81	&__clk_0_15,
 82	&__clk_0_17,
 83	&__clk_0_18,
 84	&__clk_0_19,
 85	&__clk_0_20,
 86	&__clk_0_22,
 87	&__clk_0_23,
 88	&__clk_0_24,
 89	&__clk_0_25,
 90	&__clk_0_26,
 91	&__clk_0_27,
 92	&__clk_0_28,
 93	&__clk_0_29,
 94	&__clk_0_30,
 95	&__clk_0_31,
 96	&__clk_0_32,
 97	&__clk_0_33,
 98	&__clk_0_34,
 99	&__clk_0_35,
100	&__clk_0_37,
101	&__clk_0_38,
102	&__clk_0_39,
103	&__clk_0_42,
104	&__clk_0_43,
105	&__clk_0_44,
106	&__clk_0_45,
107	&__clk_0_46,
108	&__clk_0_47,
109	&__clk_0_48,
110	&__clk_0_49,
111	&__clk_0_50,
112	&__clk_0_51,
113	&__clk_0_53,
114	&__clk_0_54,
115	&__clk_0_55,
116	&__clk_0_56,
117	&__clk_0_63,
118
119	&__clk_1_2,
120	&__clk_1_4,
121	&__clk_1_5,
122	&__clk_1_6,
123	&__clk_1_7,
124	&__clk_1_24,
125	&__clk_1_25,
126	&__clk_1_26,
127	&__clk_1_27,
128	&__clk_1_28,
129	&__clk_1_29,
130	&__clk_1_34,
131	&__clk_1_36,
132	&__clk_1_37,
133	NULL,
134};
135
136
137static struct clk * const enable_clks[] __initconst = {
138	/* make sure these clocks are enabled */
139	&__clk_0_18, /* intc0 */
140	&__clk_0_19, /* intc0 */
141	&__clk_0_20, /* intc0 */
142	&__clk_0_24, /* uart0 */
143	&__clk_0_25, /* uart1 */
144	&__clk_0_26, /* uart2 */
145	&__clk_0_27, /* uart3 */
146
147	&__clk_0_33, /* pit.1 */
148	&__clk_0_37, /* eport */
149	&__clk_0_48, /* pll */
150
151	&__clk_1_36, /* CCM/reset module/Power management */
152	&__clk_1_37, /* gpio */
153};
154static struct clk * const disable_clks[] __initconst = {
155	&__clk_0_8, /* can.0 */
156	&__clk_0_9, /* can.1 */
157	&__clk_0_14, /* i2c.1 */
158	&__clk_0_15, /* dspi.1 */
159	&__clk_0_17, /* eDMA */
160	&__clk_0_22, /* i2c.0 */
161	&__clk_0_23, /* dspi.0 */
162	&__clk_0_28, /* tmr.1 */
163	&__clk_0_29, /* tmr.2 */
164	&__clk_0_30, /* tmr.2 */
165	&__clk_0_31, /* tmr.3 */
166	&__clk_0_32, /* pit.0 */
167	&__clk_0_34, /* pit.2 */
168	&__clk_0_35, /* pit.3 */
169	&__clk_0_38, /* adc */
170	&__clk_0_39, /* dac */
171	&__clk_0_44, /* usb otg */
172	&__clk_0_45, /* usb host */
173	&__clk_0_47, /* ssi.0 */
174	&__clk_0_49, /* rng */
175	&__clk_0_50, /* ssi.1 */
176	&__clk_0_51, /* eSDHC */
177	&__clk_0_53, /* enet-fec */
178	&__clk_0_54, /* enet-fec */
179	&__clk_0_55, /* switch.0 */
180	&__clk_0_56, /* switch.1 */
181
182	&__clk_1_2, /* 1-wire */
183	&__clk_1_4, /* i2c.2 */
184	&__clk_1_5, /* i2c.3 */
185	&__clk_1_6, /* i2c.4 */
186	&__clk_1_7, /* i2c.5 */
187	&__clk_1_24, /* uart 4 */
188	&__clk_1_25, /* uart 5 */
189	&__clk_1_26, /* uart 6 */
190	&__clk_1_27, /* uart 7 */
191	&__clk_1_28, /* uart 8 */
192	&__clk_1_29, /* uart 9 */
193};
194
195static void __init m5441x_clk_init(void)
196{
197	unsigned i;
198
199	for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
200		__clk_init_enabled(enable_clks[i]);
201	/* make sure these clocks are disabled */
202	for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
203		__clk_init_disabled(disable_clks[i]);
204}
205
206static void __init m5441x_uarts_init(void)
207{
208	__raw_writeb(0x0f, MCFGPIO_PAR_UART0);
209	__raw_writeb(0x00, MCFGPIO_PAR_UART1);
210	__raw_writeb(0x00, MCFGPIO_PAR_UART2);
211}
212
213static void __init m5441x_fec_init(void)
214{
215	__raw_writeb(0x03, MCFGPIO_PAR_FEC);
216}
217
218void __init config_BSP(char *commandp, int size)
219{
220	m5441x_clk_init();
221	mach_sched_init = hw_timer_init;
222	m5441x_uarts_init();
223	m5441x_fec_init();
224}
225
226
227#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
228static struct resource m5441x_rtc_resources[] = {
229	{
230		.start		= MCFRTC_BASE,
231		.end		= MCFRTC_BASE + MCFRTC_SIZE - 1,
232		.flags		= IORESOURCE_MEM,
233	},
234	{
235		.start		= MCF_IRQ_RTC,
236		.end		= MCF_IRQ_RTC,
237		.flags		= IORESOURCE_IRQ,
238	},
239};
240
241static struct platform_device m5441x_rtc = {
242	.name			= "mcfrtc",
243	.id			= 0,
244	.resource		= m5441x_rtc_resources,
245	.num_resources		= ARRAY_SIZE(m5441x_rtc_resources),
246};
247#endif
248
249static struct platform_device *m5441x_devices[] __initdata = {
250#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
251	&m5441x_rtc,
252#endif
253};
254
255static int __init init_BSP(void)
256{
257	platform_add_devices(m5441x_devices, ARRAY_SIZE(m5441x_devices));
258	return 0;
259}
260
261arch_initcall(init_BSP);