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/Ethereal-msm8939-beta9/arch/microblaze/include/asm/pvr.h

https://bitbucket.org/MilosStamenkovic95/etherealos
C Header | 227 lines | 169 code | 29 blank | 29 comment | 0 complexity | 46d3176645dd2f1794d2057fc3bd9e6f MD5 | raw file
  1/*
  2 * Support for the MicroBlaze PVR (Processor Version Register)
  3 *
  4 * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
  5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
  6 * Copyright (C) 2007 - 2011 PetaLogix
  7 *
  8 * This file is subject to the terms and conditions of the GNU General
  9 * Public License. See the file COPYING in the main directory of this
 10 * archive for more details.
 11 */
 12
 13#ifndef _ASM_MICROBLAZE_PVR_H
 14#define _ASM_MICROBLAZE_PVR_H
 15
 16#define PVR_MSR_BIT 0x400
 17
 18struct pvr_s {
 19	unsigned pvr[12];
 20};
 21
 22/* The following taken from Xilinx's standalone BSP pvr.h */
 23
 24/* Basic PVR mask */
 25#define PVR0_PVR_FULL_MASK		0x80000000
 26#define PVR0_USE_BARREL_MASK		0x40000000
 27#define PVR0_USE_DIV_MASK		0x20000000
 28#define PVR0_USE_HW_MUL_MASK		0x10000000
 29#define PVR0_USE_FPU_MASK		0x08000000
 30#define PVR0_USE_EXC_MASK		0x04000000
 31#define PVR0_USE_ICACHE_MASK		0x02000000
 32#define PVR0_USE_DCACHE_MASK		0x01000000
 33#define PVR0_USE_MMU			0x00800000
 34#define PVR0_USE_BTC			0x00400000
 35#define PVR0_ENDI			0x00200000
 36#define PVR0_VERSION_MASK		0x0000FF00
 37#define PVR0_USER1_MASK			0x000000FF
 38
 39/* User 2 PVR mask */
 40#define PVR1_USER2_MASK			0xFFFFFFFF
 41
 42/* Configuration PVR masks */
 43#define PVR2_D_OPB_MASK			0x80000000 /* or AXI */
 44#define PVR2_D_LMB_MASK			0x40000000
 45#define PVR2_I_OPB_MASK			0x20000000 /* or AXI */
 46#define PVR2_I_LMB_MASK			0x10000000
 47#define PVR2_INTERRUPT_IS_EDGE_MASK	0x08000000
 48#define PVR2_EDGE_IS_POSITIVE_MASK	0x04000000
 49#define PVR2_D_PLB_MASK			0x02000000 /* new */
 50#define PVR2_I_PLB_MASK			0x01000000 /* new */
 51#define PVR2_INTERCONNECT		0x00800000 /* new */
 52#define PVR2_USE_EXTEND_FSL		0x00080000 /* new */
 53#define PVR2_USE_FSL_EXC		0x00040000 /* new */
 54#define PVR2_USE_MSR_INSTR		0x00020000
 55#define PVR2_USE_PCMP_INSTR		0x00010000
 56#define PVR2_AREA_OPTIMISED		0x00008000
 57#define PVR2_USE_BARREL_MASK		0x00004000
 58#define PVR2_USE_DIV_MASK		0x00002000
 59#define PVR2_USE_HW_MUL_MASK		0x00001000
 60#define PVR2_USE_FPU_MASK		0x00000800
 61#define PVR2_USE_MUL64_MASK		0x00000400
 62#define PVR2_USE_FPU2_MASK		0x00000200 /* new */
 63#define PVR2_USE_IPLBEXC 		0x00000100
 64#define PVR2_USE_DPLBEXC		0x00000080
 65#define PVR2_OPCODE_0x0_ILL_MASK	0x00000040
 66#define PVR2_UNALIGNED_EXC_MASK		0x00000020
 67#define PVR2_ILL_OPCODE_EXC_MASK	0x00000010
 68#define PVR2_IOPB_BUS_EXC_MASK		0x00000008 /* or AXI */
 69#define PVR2_DOPB_BUS_EXC_MASK		0x00000004 /* or AXI */
 70#define PVR2_DIV_ZERO_EXC_MASK		0x00000002
 71#define PVR2_FPU_EXC_MASK		0x00000001
 72
 73/* Debug and exception PVR masks */
 74#define PVR3_DEBUG_ENABLED_MASK		0x80000000
 75#define PVR3_NUMBER_OF_PC_BRK_MASK	0x1E000000
 76#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK	0x00380000
 77#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK	0x0000E000
 78#define PVR3_FSL_LINKS_MASK		0x00000380
 79
 80/* ICache config PVR masks */
 81#define PVR4_USE_ICACHE_MASK		0x80000000 /* ICU */
 82#define PVR4_ICACHE_ADDR_TAG_BITS_MASK	0x7C000000 /* ICTS */
 83#define PVR4_ICACHE_ALLOW_WR_MASK	0x01000000 /* ICW */
 84#define PVR4_ICACHE_LINE_LEN_MASK	0x00E00000 /* ICLL */
 85#define PVR4_ICACHE_BYTE_SIZE_MASK	0x001F0000 /* ICBS */
 86#define PVR4_ICACHE_ALWAYS_USED		0x00008000 /* IAU */
 87#define PVR4_ICACHE_INTERFACE		0x00002000 /* ICI */
 88
 89/* DCache config PVR masks */
 90#define PVR5_USE_DCACHE_MASK		0x80000000 /* DCU */
 91#define PVR5_DCACHE_ADDR_TAG_BITS_MASK	0x7C000000 /* DCTS */
 92#define PVR5_DCACHE_ALLOW_WR_MASK	0x01000000 /* DCW */
 93#define PVR5_DCACHE_LINE_LEN_MASK	0x00E00000 /* DCLL */
 94#define PVR5_DCACHE_BYTE_SIZE_MASK	0x001F0000 /* DCBS */
 95#define PVR5_DCACHE_ALWAYS_USED		0x00008000 /* DAU */
 96#define PVR5_DCACHE_USE_WRITEBACK	0x00004000 /* DWB */
 97#define PVR5_DCACHE_INTERFACE		0x00002000 /* DCI */
 98
 99/* ICache base address PVR mask */
100#define PVR6_ICACHE_BASEADDR_MASK	0xFFFFFFFF
101
102/* ICache high address PVR mask */
103#define PVR7_ICACHE_HIGHADDR_MASK	0xFFFFFFFF
104
105/* DCache base address PVR mask */
106#define PVR8_DCACHE_BASEADDR_MASK	0xFFFFFFFF
107
108/* DCache high address PVR mask */
109#define PVR9_DCACHE_HIGHADDR_MASK	0xFFFFFFFF
110
111/* Target family PVR mask */
112#define PVR10_TARGET_FAMILY_MASK	0xFF000000
113
114/* MMU description */
115#define PVR11_USE_MMU			0xC0000000
116#define PVR11_MMU_ITLB_SIZE		0x38000000
117#define PVR11_MMU_DTLB_SIZE		0x07000000
118#define PVR11_MMU_TLB_ACCESS		0x00C00000
119#define PVR11_MMU_ZONES			0x003C0000
120#define PVR11_MMU_PRIVINS		0x00010000
121/* MSR Reset value PVR mask */
122#define PVR11_MSR_RESET_VALUE_MASK	0x000007FF
123
124/* PVR access macros */
125#define PVR_IS_FULL(_pvr)	(_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
126#define PVR_USE_BARREL(_pvr)	(_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
127#define PVR_USE_DIV(_pvr)	(_pvr.pvr[0] & PVR0_USE_DIV_MASK)
128#define PVR_USE_HW_MUL(_pvr)	(_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
129#define PVR_USE_FPU(_pvr)	(_pvr.pvr[0] & PVR0_USE_FPU_MASK)
130#define PVR_USE_FPU2(_pvr)	(_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
131#define PVR_USE_ICACHE(_pvr)	(_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
132#define PVR_USE_DCACHE(_pvr)	(_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
133#define PVR_VERSION(_pvr)	((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
134#define PVR_USER1(_pvr)		(_pvr.pvr[0] & PVR0_USER1_MASK)
135#define PVR_USER2(_pvr)		(_pvr.pvr[1] & PVR1_USER2_MASK)
136
137#define PVR_D_OPB(_pvr)		(_pvr.pvr[2] & PVR2_D_OPB_MASK)
138#define PVR_D_LMB(_pvr)		(_pvr.pvr[2] & PVR2_D_LMB_MASK)
139#define PVR_I_OPB(_pvr)		(_pvr.pvr[2] & PVR2_I_OPB_MASK)
140#define PVR_I_LMB(_pvr)		(_pvr.pvr[2] & PVR2_I_LMB_MASK)
141#define PVR_INTERRUPT_IS_EDGE(_pvr) \
142			(_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
143#define PVR_EDGE_IS_POSITIVE(_pvr) \
144			(_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
145#define PVR_USE_MSR_INSTR(_pvr)		(_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
146#define PVR_USE_PCMP_INSTR(_pvr)	(_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
147#define PVR_AREA_OPTIMISED(_pvr)	(_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
148#define PVR_USE_MUL64(_pvr)		(_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
149#define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
150			(_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
151#define PVR_UNALIGNED_EXCEPTION(_pvr) \
152			(_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
153#define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
154			(_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
155#define PVR_IOPB_BUS_EXCEPTION(_pvr) \
156			(_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
157#define PVR_DOPB_BUS_EXCEPTION(_pvr) \
158			(_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
159#define PVR_DIV_ZERO_EXCEPTION(_pvr) \
160			(_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
161#define PVR_FPU_EXCEPTION(_pvr)		(_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
162#define PVR_FSL_EXCEPTION(_pvr)		(_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
163
164#define PVR_DEBUG_ENABLED(_pvr)		(_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
165#define PVR_NUMBER_OF_PC_BRK(_pvr) \
166			((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
167#define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
168			((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
169#define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
170			((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
171#define PVR_FSL_LINKS(_pvr)	((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
172
173#define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
174		((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
175#define PVR_ICACHE_USE_FSL(_pvr) \
176		(_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
177#define PVR_ICACHE_ALLOW_WR(_pvr) \
178		(_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
179#define PVR_ICACHE_LINE_LEN(_pvr) \
180		(1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
181#define PVR_ICACHE_BYTE_SIZE(_pvr) \
182		(1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
183
184#define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
185			((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
186#define PVR_DCACHE_USE_FSL(_pvr)	(_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
187#define PVR_DCACHE_ALLOW_WR(_pvr) \
188			(_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
189/* FIXME two shifts on one line needs any comment */
190#define PVR_DCACHE_LINE_LEN(_pvr) \
191		(1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
192#define PVR_DCACHE_BYTE_SIZE(_pvr) \
193		(1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
194
195#define PVR_DCACHE_USE_WRITEBACK(_pvr) \
196			((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
197
198#define PVR_ICACHE_BASEADDR(_pvr) \
199			(_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
200#define PVR_ICACHE_HIGHADDR(_pvr) \
201			(_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
202#define PVR_DCACHE_BASEADDR(_pvr) \
203			(_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
204#define PVR_DCACHE_HIGHADDR(_pvr) \
205			(_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
206
207#define PVR_TARGET_FAMILY(_pvr) \
208			((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
209
210#define PVR_MSR_RESET_VALUE(_pvr) \
211			(_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
212
213/* mmu */
214#define PVR_USE_MMU(_pvr)		((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
215#define PVR_MMU_ITLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
216#define PVR_MMU_DTLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
217#define PVR_MMU_TLB_ACCESS(_pvr)	(_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
218#define PVR_MMU_ZONES(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ZONES)
219#define PVR_MMU_PRIVINS(pvr)		(pvr.pvr[11] & PVR11_MMU_PRIVINS)
220
221/* endian */
222#define PVR_ENDIAN(_pvr)	(_pvr.pvr[0] & PVR0_ENDI)
223
224int cpu_has_pvr(void);
225void get_pvr(struct pvr_s *pvr);
226
227#endif /* _ASM_MICROBLAZE_PVR_H */