PageRenderTime 27ms CodeModel.GetById 17ms app.highlight 4ms RepoModel.GetById 1ms app.codeStats 1ms

/Ethereal-msm8939-beta9/arch/microblaze/platform/generic/system.dts

https://bitbucket.org/MilosStamenkovic95/etherealos
Device Tree | 367 lines | 333 code | 6 blank | 28 comment | 0 complexity | 74776f588ba8f37b1469215b3f9b7af1 MD5 | raw file
  1/*
  2 * Device Tree Generator version: 1.1
  3 *
  4 * (C) Copyright 2007-2008 Xilinx, Inc.
  5 * (C) Copyright 2007-2009 Michal Simek
  6 *
  7 * Michal SIMEK <monstr@monstr.eu>
  8 *
  9 * This program is free software; you can redistribute it and/or
 10 * modify it under the terms of the GNU General Public License as
 11 * published by the Free Software Foundation; either version 2 of
 12 * the License, or (at your option) any later version.
 13 *
 14 * This program is distributed in the hope that it will be useful,
 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 17 * GNU General Public License for more details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this program; if not, write to the Free Software
 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 22 * MA 02111-1307 USA
 23 *
 24 * CAUTION: This file is automatically generated by libgen.
 25 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
 26 *
 27 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
 28 */
 29
 30/dts-v1/;
 31/ {
 32	#address-cells = <1>;
 33	#size-cells = <1>;
 34	compatible = "xlnx,microblaze";
 35	hard-reset-gpios = <&LEDs_8Bit 2 1>;
 36	model = "testing";
 37	DDR2_SDRAM: memory@90000000 {
 38		device_type = "memory";
 39		reg = < 0x90000000 0x10000000 >;
 40	} ;
 41	aliases {
 42		ethernet0 = &Hard_Ethernet_MAC;
 43		serial0 = &RS232_Uart_1;
 44	} ;
 45	chosen {
 46		bootargs = "console=ttyUL0,115200 highres=on";
 47		linux,stdout-path = "/plb@0/serial@84000000";
 48	} ;
 49	cpus {
 50		#address-cells = <1>;
 51		#cpus = <0x1>;
 52		#size-cells = <0>;
 53		microblaze_0: cpu@0 {
 54			clock-frequency = <125000000>;
 55			compatible = "xlnx,microblaze-7.10.d";
 56			d-cache-baseaddr = <0x90000000>;
 57			d-cache-highaddr = <0x9fffffff>;
 58			d-cache-line-size = <0x10>;
 59			d-cache-size = <0x2000>;
 60			device_type = "cpu";
 61			i-cache-baseaddr = <0x90000000>;
 62			i-cache-highaddr = <0x9fffffff>;
 63			i-cache-line-size = <0x10>;
 64			i-cache-size = <0x2000>;
 65			model = "microblaze,7.10.d";
 66			reg = <0>;
 67			timebase-frequency = <125000000>;
 68			xlnx,addr-tag-bits = <0xf>;
 69			xlnx,allow-dcache-wr = <0x1>;
 70			xlnx,allow-icache-wr = <0x1>;
 71			xlnx,area-optimized = <0x0>;
 72			xlnx,cache-byte-size = <0x2000>;
 73			xlnx,d-lmb = <0x1>;
 74			xlnx,d-opb = <0x0>;
 75			xlnx,d-plb = <0x1>;
 76			xlnx,data-size = <0x20>;
 77			xlnx,dcache-addr-tag = <0xf>;
 78			xlnx,dcache-always-used = <0x1>;
 79			xlnx,dcache-byte-size = <0x2000>;
 80			xlnx,dcache-line-len = <0x4>;
 81			xlnx,dcache-use-fsl = <0x1>;
 82			xlnx,debug-enabled = <0x1>;
 83			xlnx,div-zero-exception = <0x1>;
 84			xlnx,dopb-bus-exception = <0x0>;
 85			xlnx,dynamic-bus-sizing = <0x1>;
 86			xlnx,edge-is-positive = <0x1>;
 87			xlnx,family = "virtex5";
 88			xlnx,endianness = <0x1>;
 89			xlnx,fpu-exception = <0x1>;
 90			xlnx,fsl-data-size = <0x20>;
 91			xlnx,fsl-exception = <0x0>;
 92			xlnx,fsl-links = <0x0>;
 93			xlnx,i-lmb = <0x1>;
 94			xlnx,i-opb = <0x0>;
 95			xlnx,i-plb = <0x1>;
 96			xlnx,icache-always-used = <0x1>;
 97			xlnx,icache-line-len = <0x4>;
 98			xlnx,icache-use-fsl = <0x1>;
 99			xlnx,ill-opcode-exception = <0x1>;
100			xlnx,instance = "microblaze_0";
101			xlnx,interconnect = <0x1>;
102			xlnx,interrupt-is-edge = <0x0>;
103			xlnx,iopb-bus-exception = <0x0>;
104			xlnx,mmu-dtlb-size = <0x4>;
105			xlnx,mmu-itlb-size = <0x2>;
106			xlnx,mmu-tlb-access = <0x3>;
107			xlnx,mmu-zones = <0x10>;
108			xlnx,number-of-pc-brk = <0x1>;
109			xlnx,number-of-rd-addr-brk = <0x0>;
110			xlnx,number-of-wr-addr-brk = <0x0>;
111			xlnx,opcode-0x0-illegal = <0x1>;
112			xlnx,pvr = <0x2>;
113			xlnx,pvr-user1 = <0x0>;
114			xlnx,pvr-user2 = <0x0>;
115			xlnx,reset-msr = <0x0>;
116			xlnx,sco = <0x0>;
117			xlnx,unaligned-exceptions = <0x1>;
118			xlnx,use-barrel = <0x1>;
119			xlnx,use-dcache = <0x1>;
120			xlnx,use-div = <0x1>;
121			xlnx,use-ext-brk = <0x1>;
122			xlnx,use-ext-nm-brk = <0x1>;
123			xlnx,use-extended-fsl-instr = <0x0>;
124			xlnx,use-fpu = <0x2>;
125			xlnx,use-hw-mul = <0x2>;
126			xlnx,use-icache = <0x1>;
127			xlnx,use-interrupt = <0x1>;
128			xlnx,use-mmu = <0x3>;
129			xlnx,use-msr-instr = <0x1>;
130			xlnx,use-pcmp-instr = <0x1>;
131		} ;
132	} ;
133	mb_plb: plb@0 {
134		#address-cells = <1>;
135		#size-cells = <1>;
136		compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
137		ranges ;
138		FLASH: flash@a0000000 {
139			bank-width = <2>;
140			compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
141			reg = < 0xa0000000 0x2000000 >;
142			xlnx,family = "virtex5";
143			xlnx,include-datawidth-matching-0 = <0x1>;
144			xlnx,include-datawidth-matching-1 = <0x0>;
145			xlnx,include-datawidth-matching-2 = <0x0>;
146			xlnx,include-datawidth-matching-3 = <0x0>;
147			xlnx,include-negedge-ioregs = <0x0>;
148			xlnx,include-plb-ipif = <0x1>;
149			xlnx,include-wrbuf = <0x1>;
150			xlnx,max-mem-width = <0x10>;
151			xlnx,mch-native-dwidth = <0x20>;
152			xlnx,mch-plb-clk-period-ps = <0x1f40>;
153			xlnx,mch-splb-awidth = <0x20>;
154			xlnx,mch0-accessbuf-depth = <0x10>;
155			xlnx,mch0-protocol = <0x0>;
156			xlnx,mch0-rddatabuf-depth = <0x10>;
157			xlnx,mch1-accessbuf-depth = <0x10>;
158			xlnx,mch1-protocol = <0x0>;
159			xlnx,mch1-rddatabuf-depth = <0x10>;
160			xlnx,mch2-accessbuf-depth = <0x10>;
161			xlnx,mch2-protocol = <0x0>;
162			xlnx,mch2-rddatabuf-depth = <0x10>;
163			xlnx,mch3-accessbuf-depth = <0x10>;
164			xlnx,mch3-protocol = <0x0>;
165			xlnx,mch3-rddatabuf-depth = <0x10>;
166			xlnx,mem0-width = <0x10>;
167			xlnx,mem1-width = <0x20>;
168			xlnx,mem2-width = <0x20>;
169			xlnx,mem3-width = <0x20>;
170			xlnx,num-banks-mem = <0x1>;
171			xlnx,num-channels = <0x0>;
172			xlnx,priority-mode = <0x0>;
173			xlnx,synch-mem-0 = <0x0>;
174			xlnx,synch-mem-1 = <0x0>;
175			xlnx,synch-mem-2 = <0x0>;
176			xlnx,synch-mem-3 = <0x0>;
177			xlnx,synch-pipedelay-0 = <0x2>;
178			xlnx,synch-pipedelay-1 = <0x2>;
179			xlnx,synch-pipedelay-2 = <0x2>;
180			xlnx,synch-pipedelay-3 = <0x2>;
181			xlnx,tavdv-ps-mem-0 = <0x1adb0>;
182			xlnx,tavdv-ps-mem-1 = <0x3a98>;
183			xlnx,tavdv-ps-mem-2 = <0x3a98>;
184			xlnx,tavdv-ps-mem-3 = <0x3a98>;
185			xlnx,tcedv-ps-mem-0 = <0x1adb0>;
186			xlnx,tcedv-ps-mem-1 = <0x3a98>;
187			xlnx,tcedv-ps-mem-2 = <0x3a98>;
188			xlnx,tcedv-ps-mem-3 = <0x3a98>;
189			xlnx,thzce-ps-mem-0 = <0x88b8>;
190			xlnx,thzce-ps-mem-1 = <0x1b58>;
191			xlnx,thzce-ps-mem-2 = <0x1b58>;
192			xlnx,thzce-ps-mem-3 = <0x1b58>;
193			xlnx,thzoe-ps-mem-0 = <0x1b58>;
194			xlnx,thzoe-ps-mem-1 = <0x1b58>;
195			xlnx,thzoe-ps-mem-2 = <0x1b58>;
196			xlnx,thzoe-ps-mem-3 = <0x1b58>;
197			xlnx,tlzwe-ps-mem-0 = <0x88b8>;
198			xlnx,tlzwe-ps-mem-1 = <0x0>;
199			xlnx,tlzwe-ps-mem-2 = <0x0>;
200			xlnx,tlzwe-ps-mem-3 = <0x0>;
201			xlnx,twc-ps-mem-0 = <0x2af8>;
202			xlnx,twc-ps-mem-1 = <0x3a98>;
203			xlnx,twc-ps-mem-2 = <0x3a98>;
204			xlnx,twc-ps-mem-3 = <0x3a98>;
205			xlnx,twp-ps-mem-0 = <0x11170>;
206			xlnx,twp-ps-mem-1 = <0x2ee0>;
207			xlnx,twp-ps-mem-2 = <0x2ee0>;
208			xlnx,twp-ps-mem-3 = <0x2ee0>;
209			xlnx,xcl0-linesize = <0x4>;
210			xlnx,xcl0-writexfer = <0x1>;
211			xlnx,xcl1-linesize = <0x4>;
212			xlnx,xcl1-writexfer = <0x1>;
213			xlnx,xcl2-linesize = <0x4>;
214			xlnx,xcl2-writexfer = <0x1>;
215			xlnx,xcl3-linesize = <0x4>;
216			xlnx,xcl3-writexfer = <0x1>;
217		} ;
218		Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
219			#address-cells = <1>;
220			#size-cells = <1>;
221			compatible = "xlnx,compound";
222			ranges ;
223			ethernet@81c00000 {
224				compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
225				device_type = "network";
226				interrupt-parent = <&xps_intc_0>;
227				interrupts = < 5 2 >;
228				llink-connected = <&PIM3>;
229				local-mac-address = [ 00 0a 35 00 00 00 ];
230				reg = < 0x81c00000 0x40 >;
231				xlnx,bus2core-clk-ratio = <0x1>;
232				xlnx,phy-type = <0x1>;
233				xlnx,phyaddr = <0x1>;
234				xlnx,rxcsum = <0x0>;
235				xlnx,rxfifo = <0x1000>;
236				xlnx,temac-type = <0x0>;
237				xlnx,txcsum = <0x0>;
238				xlnx,txfifo = <0x1000>;
239			} ;
240		} ;
241		IIC_EEPROM: i2c@81600000 {
242			compatible = "xlnx,xps-iic-2.00.a";
243			interrupt-parent = <&xps_intc_0>;
244			interrupts = < 6 2 >;
245			reg = < 0x81600000 0x10000 >;
246			xlnx,clk-freq = <0x7735940>;
247			xlnx,family = "virtex5";
248			xlnx,gpo-width = <0x1>;
249			xlnx,iic-freq = <0x186a0>;
250			xlnx,scl-inertial-delay = <0x0>;
251			xlnx,sda-inertial-delay = <0x0>;
252			xlnx,ten-bit-adr = <0x0>;
253		} ;
254		LEDs_8Bit: gpio@81400000 {
255			compatible = "xlnx,xps-gpio-1.00.a";
256			interrupt-parent = <&xps_intc_0>;
257			interrupts = < 7 2 >;
258			reg = < 0x81400000 0x10000 >;
259			xlnx,all-inputs = <0x0>;
260			xlnx,all-inputs-2 = <0x0>;
261			xlnx,dout-default = <0x0>;
262			xlnx,dout-default-2 = <0x0>;
263			xlnx,family = "virtex5";
264			xlnx,gpio-width = <0x8>;
265			xlnx,interrupt-present = <0x1>;
266			xlnx,is-bidir = <0x1>;
267			xlnx,is-bidir-2 = <0x1>;
268			xlnx,is-dual = <0x0>;
269			xlnx,tri-default = <0xffffffff>;
270			xlnx,tri-default-2 = <0xffffffff>;
271			#gpio-cells = <2>;
272			gpio-controller;
273		} ;
274
275		gpio-leds {
276			compatible = "gpio-leds";
277
278			heartbeat {
279				label = "Heartbeat";
280				gpios = <&LEDs_8Bit 4 1>;
281				linux,default-trigger = "heartbeat";
282			};
283
284			yellow {
285				label = "Yellow";
286				gpios = <&LEDs_8Bit 5 1>;
287			};
288
289			red {
290				label = "Red";
291				gpios = <&LEDs_8Bit 6 1>;
292			};
293
294			green {
295				label = "Green";
296				gpios = <&LEDs_8Bit 7 1>;
297			};
298		} ;
299		RS232_Uart_1: serial@84000000 {
300			clock-frequency = <125000000>;
301			compatible = "xlnx,xps-uartlite-1.00.a";
302			current-speed = <115200>;
303			device_type = "serial";
304			interrupt-parent = <&xps_intc_0>;
305			interrupts = < 8 0 >;
306			port-number = <0>;
307			reg = < 0x84000000 0x10000 >;
308			xlnx,baudrate = <0x1c200>;
309			xlnx,data-bits = <0x8>;
310			xlnx,family = "virtex5";
311			xlnx,odd-parity = <0x0>;
312			xlnx,use-parity = <0x0>;
313		} ;
314		SysACE_CompactFlash: sysace@83600000 {
315			compatible = "xlnx,xps-sysace-1.00.a";
316			interrupt-parent = <&xps_intc_0>;
317			interrupts = < 4 2 >;
318			reg = < 0x83600000 0x10000 >;
319			xlnx,family = "virtex5";
320			xlnx,mem-width = <0x10>;
321		} ;
322		debug_module: debug@84400000 {
323			compatible = "xlnx,mdm-1.00.d";
324			reg = < 0x84400000 0x10000 >;
325			xlnx,family = "virtex5";
326			xlnx,interconnect = <0x1>;
327			xlnx,jtag-chain = <0x2>;
328			xlnx,mb-dbg-ports = <0x1>;
329			xlnx,uart-width = <0x8>;
330			xlnx,use-uart = <0x1>;
331			xlnx,write-fsl-ports = <0x0>;
332		} ;
333		mpmc@90000000 {
334			#address-cells = <1>;
335			#size-cells = <1>;
336			compatible = "xlnx,mpmc-4.02.a";
337			ranges ;
338			PIM3: sdma@84600180 {
339				compatible = "xlnx,ll-dma-1.00.a";
340				interrupt-parent = <&xps_intc_0>;
341				interrupts = < 2 2 1 2 >;
342				reg = < 0x84600180 0x80 >;
343			} ;
344		} ;
345		xps_intc_0: interrupt-controller@81800000 {
346			#interrupt-cells = <0x2>;
347			compatible = "xlnx,xps-intc-1.00.a";
348			interrupt-controller ;
349			reg = < 0x81800000 0x10000 >;
350			xlnx,kind-of-intr = <0x100>;
351			xlnx,num-intr-inputs = <0x9>;
352		} ;
353		xps_timer_1: timer@83c00000 {
354			compatible = "xlnx,xps-timer-1.00.a";
355			interrupt-parent = <&xps_intc_0>;
356			interrupts = < 3 2 >;
357			reg = < 0x83c00000 0x10000 >;
358			xlnx,count-width = <0x20>;
359			xlnx,family = "virtex5";
360			xlnx,gen0-assert = <0x1>;
361			xlnx,gen1-assert = <0x1>;
362			xlnx,one-timer-only = <0x0>;
363			xlnx,trig0-assert = <0x1>;
364			xlnx,trig1-assert = <0x1>;
365		} ;
366	} ;
367}  ;