/Ethereal-msm8939-beta9/arch/mips/alchemy/common/time.c

https://bitbucket.org/MilosStamenkovic95/etherealos · C · 179 lines · 108 code · 26 blank · 45 comment · 14 complexity · 71db77edbc5bfca081eb6de638dce996 MD5 · raw file

  1. /*
  2. * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
  3. *
  4. * Previous incarnations were:
  5. * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
  6. * Copied and modified Carsten Langgaard's time.c
  7. *
  8. * Carsten Langgaard, carstenl@mips.com
  9. * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
  10. *
  11. * ########################################################################
  12. *
  13. * This program is free software; you can distribute it and/or modify it
  14. * under the terms of the GNU General Public License (Version 2) as
  15. * published by the Free Software Foundation.
  16. *
  17. * This program is distributed in the hope it will be useful, but WITHOUT
  18. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  20. * for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License along
  23. * with this program; if not, write to the Free Software Foundation, Inc.,
  24. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  25. *
  26. * ########################################################################
  27. *
  28. * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
  29. * databooks). Firmware/Board init code must enable the counters in the
  30. * counter control register, otherwise the CP0 counter clocksource/event
  31. * will be installed instead (and use of 'wait' instruction is prohibited).
  32. */
  33. #include <linux/clockchips.h>
  34. #include <linux/clocksource.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/spinlock.h>
  37. #include <asm/idle.h>
  38. #include <asm/processor.h>
  39. #include <asm/time.h>
  40. #include <asm/mach-au1x00/au1000.h>
  41. /* 32kHz clock enabled and detected */
  42. #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
  43. static cycle_t au1x_counter1_read(struct clocksource *cs)
  44. {
  45. return au_readl(SYS_RTCREAD);
  46. }
  47. static struct clocksource au1x_counter1_clocksource = {
  48. .name = "alchemy-counter1",
  49. .read = au1x_counter1_read,
  50. .mask = CLOCKSOURCE_MASK(32),
  51. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  52. .rating = 1500,
  53. };
  54. static int au1x_rtcmatch2_set_next_event(unsigned long delta,
  55. struct clock_event_device *cd)
  56. {
  57. delta += au_readl(SYS_RTCREAD);
  58. /* wait for register access */
  59. while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
  60. ;
  61. au_writel(delta, SYS_RTCMATCH2);
  62. au_sync();
  63. return 0;
  64. }
  65. static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
  66. struct clock_event_device *cd)
  67. {
  68. }
  69. static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
  70. {
  71. struct clock_event_device *cd = dev_id;
  72. cd->event_handler(cd);
  73. return IRQ_HANDLED;
  74. }
  75. static struct clock_event_device au1x_rtcmatch2_clockdev = {
  76. .name = "rtcmatch2",
  77. .features = CLOCK_EVT_FEAT_ONESHOT,
  78. .rating = 1500,
  79. .set_next_event = au1x_rtcmatch2_set_next_event,
  80. .set_mode = au1x_rtcmatch2_set_mode,
  81. .cpumask = cpu_all_mask,
  82. };
  83. static struct irqaction au1x_rtcmatch2_irqaction = {
  84. .handler = au1x_rtcmatch2_irq,
  85. .flags = IRQF_TIMER,
  86. .name = "timer",
  87. .dev_id = &au1x_rtcmatch2_clockdev,
  88. };
  89. static int __init alchemy_time_init(unsigned int m2int)
  90. {
  91. struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
  92. unsigned long t;
  93. au1x_rtcmatch2_clockdev.irq = m2int;
  94. /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
  95. * has been detected. If so install the rtcmatch2 clocksource,
  96. * otherwise don't bother. Note that both bits being set is by
  97. * no means a definite guarantee that the counters actually work
  98. * (the 32S bit seems to be stuck set to 1 once a single clock-
  99. * edge is detected, hence the timeouts).
  100. */
  101. if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
  102. goto cntr_err;
  103. /*
  104. * setup counter 1 (RTC) to tick at full speed
  105. */
  106. t = 0xffffff;
  107. while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
  108. asm volatile ("nop");
  109. if (!t)
  110. goto cntr_err;
  111. au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */
  112. au_sync();
  113. t = 0xffffff;
  114. while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
  115. asm volatile ("nop");
  116. if (!t)
  117. goto cntr_err;
  118. au_writel(0, SYS_RTCWRITE);
  119. au_sync();
  120. t = 0xffffff;
  121. while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
  122. asm volatile ("nop");
  123. if (!t)
  124. goto cntr_err;
  125. /* register counter1 clocksource and event device */
  126. clocksource_register_hz(&au1x_counter1_clocksource, 32768);
  127. cd->shift = 32;
  128. cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
  129. cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
  130. cd->min_delta_ns = clockevent_delta2ns(9, cd); /* ~0.28ms */
  131. clockevents_register_device(cd);
  132. setup_irq(m2int, &au1x_rtcmatch2_irqaction);
  133. printk(KERN_INFO "Alchemy clocksource installed\n");
  134. return 0;
  135. cntr_err:
  136. return -1;
  137. }
  138. static int alchemy_m2inttab[] __initdata = {
  139. AU1000_RTC_MATCH2_INT,
  140. AU1500_RTC_MATCH2_INT,
  141. AU1100_RTC_MATCH2_INT,
  142. AU1550_RTC_MATCH2_INT,
  143. AU1200_RTC_MATCH2_INT,
  144. AU1300_RTC_MATCH2_INT,
  145. };
  146. void __init plat_time_init(void)
  147. {
  148. int t;
  149. t = alchemy_get_cputype();
  150. if (t == ALCHEMY_CPU_UNKNOWN ||
  151. alchemy_time_init(alchemy_m2inttab[t]))
  152. cpu_wait = NULL; /* wait doesn't work with r4k timer */
  153. }