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/arch/hc/src/m9s12/m9s12_emac.h

https://bitbucket.org/hg42/nuttx
C Header | 248 lines | 125 code | 45 blank | 78 comment | 0 complexity | 9b01621025f010063a79c2b2231c5792 MD5 | raw file
Possible License(s): 0BSD 
    

  1. /************************************************************************************
    2. 

  2.  * arch/hc/src/m9s12/m9s12_emac.h
    3. 

  3.  *
    4. 

  4.  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
    5. 

  5.  *   Author: Gregory Nutt <gnutt@nuttx.org>
    6. 

  6.  *
    7. 

  7.  * Redistribution and use in source and binary forms, with or without
    8. 

  8.  * modification, are permitted provided that the following conditions
    9. 

  9.  * are met:
    10. 

  10.  *
    11. 

  11.  * 1. Redistributions of source code must retain the above copyright
    12. 

  12.  *    notice, this list of conditions and the following disclaimer.
    13. 

  13.  * 2. Redistributions in binary form must reproduce the above copyright
    14. 

  14.  *    notice, this list of conditions and the following disclaimer in
    15. 

  15.  *    the documentation and/or other materials provided with the
    16. 

  16.  *    distribution.
    17. 

  17.  * 3. Neither the name NuttX nor the names of its contributors may be
    18. 

  18.  *    used to endorse or promote products derived from this software
    19. 

  19.  *    without specific prior written permission.
    20. 

  20.  *
    21. 

  21.  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    22. 

  22.  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    23. 

  23.  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
    24. 

  24.  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
    25. 

  25.  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
    26. 

  26.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    27. 

  27.  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
    28. 

  28.  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
    29. 

  29.  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
    30. 

  30.  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
    31. 

  31.  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    32. 

  32.  * POSSIBILITY OF SUCH DAMAGE.
    33. 

  33.  *
    34. 

  34.  ************************************************************************************/
    35. 

  35. 

  36. #ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_EMAC_H
    37. 

  37. #define __ARCH_ARM_HC_SRC_M9S12_M9S12_EMAC_H
    38. 

  38. 

  39. /************************************************************************************
    40. 

  40.  * Included Files
    41. 

  41.  ************************************************************************************/
    42. 

  42. 

  43. #include <nuttx/config.h>
    44. 

  44. #include "chip.h"
    45. 

  45. 

  46. /************************************************************************************
    47. 

  47.  * Pre-processor Definitions
    48. 

  48.  ************************************************************************************/
    49. 

  49. 

  50. /* Register Offsets *****************************************************************/
    51. 

  51. 

  52. #define HCS12_EMAC_NETCTL_OFFSET       0x0000 /* Network Control (8-bit) */
    53. 

  53. #define HCS12_EMAC_RXCTS_OFFSET        0x0003 /* Receive Control and Status (8-bit) */
    54. 

  54. #define HCS12_EMAC_TXCTS_OFFSET        0x0004 /* Transmit Control and Status (8-bit) */
    55. 

  55. #define HCS12_EMAC_ETCTL_OFFSET        0x0005 /* Ethertype Control (8-bit) */
    56. 

  56. #define HCS12_EMAC_ETYPE_OFFSET        0x0006 /* Programmable Ethertype (16-bit) */
    57. 

  57. #define HCS12_EMAC_PTIME_OFFSET        0x0008 /* PAUSE Timer Value and Counter (16-bit) */
    58. 

  58. #define HCS12_EMAC_IEVENT_OFFSET       0x000a /* Interrupt Event (16-bit) */
    59. 

  59. #define HCS12_EMAC_IMASK_OFFSET        0x000c /* Interrupt Mask (16-bit) */
    60. 

  60. #define HCS12_EMAC_SWRST_OFFSET        0x000e /* Software Reset (8-bit) */
    61. 

  61. #define HCS12_EMAC_MPADR_OFFSET        0x0010 /* MII Management PHY Address (8-bit) */
    62. 

  62. #define HCS12_EMAC_MRADR_OFFSET        0x0011 /* MII Management Register Address (8-bit) */
    63. 

  63. #define HCS12_EMAC_MWDATA_OFFSET       0x0012 /* MII Management Write Data (16-bit) */
    64. 

  64. #define HCS12_EMAC_MRDATA_OFFSET       0x0014 /* MII Management Read Data (16-bit) */
    65. 

  65. #define HCS12_EMAC_MCMST_OFFSET        0x0016 /* MII Management Command and Status (8-bit) */
    66. 

  66. #define HCS12_EMAC_BUFCFG_OFFSET       0x0018 /* Ethernet Buffer Configuration (16-bit) */
    67. 

  67. #define HCS12_EMAC_RXAEFP_OFFSET       0x001a /* Receive A End-of-Frame Pointer (16-bit) */
    68. 

  68. #define HCS12_EMAC_RXBEFP_OFFSET       0x001c /* Receive B End-of-Frame Pointer (16-bit) */
    69. 

  69. #define HCS12_EMAC_TXEFP_OFFSET        0x001e /* Transmit End-of-Frame Pointer (16-bit) */
    70. 

  70. #define HCS12_EMAC_MCHASH48_OFFSET     0x0020 /* Multicast Hash Table 48-63 (16-bit) */
    71. 

  71. #define HCS12_EMAC_MCHASH32_OFFSET     0x0022 /* Multicast Hash Table 32-47 (16-bit) */
    72. 

  72. #define HCS12_EMAC_MCHASH16_OFFSET     0x0024 /* Multicast Hash Table 16-31 (16-bit) */
    73. 

  73. #define HCS12_EMAC_MCHASH0_OFFSET      0x0026 /* Multicast Hash Table 0:15 (16-bit) */
    74. 

  74. #define HCS12_EMAC_MACAD32_OFFSET      0x0028 /* MAC Unicast AAddress 32-47 (16-bit) */
    75. 

  75. #define HCS12_EMAC_MACAD16_OFFSET      0x002a /* MAC Unicast AAddress 16-31 (16-bit) */
    76. 

  76. #define HCS12_EMAC_MACAD0_OFFSET       0x002c /* MAC Unicast AAddress 0-15 (16-bit) */
    77. 

  77. #define HCS12_EMAC_EMISC _OFFSET       0x002e /* Miscellaneous (16-bit) */
    78. 

  78. 

  79. /* Register Addresses ***************************************************************/
    80. 

  80. 

  81. #define HCS12_EMAC_NETCTL              (HCS12_EMAC_BASE+HCS12_EMAC_NETCTL_OFFSET)
    82. 

  82. #define HCS12_EMAC_RXCTS               (HCS12_EMAC_BASE+HCS12_EMAC_RXCTS_OFFSET)
    83. 

  83. #define HCS12_EMAC_TXCTS               (HCS12_EMAC_BASE+HCS12_EMAC_TXCTS_OFFSET)
    84. 

  84. #define HCS12_EMAC_ETCTL               (HCS12_EMAC_BASE+HCS12_EMAC_ETCTL_OFFSET)
    85. 

  85. #define HCS12_EMAC_ETYPE               (HCS12_EMAC_BASE+HCS12_EMAC_ETYPE_OFFSET)
    86. 

  86. #define HCS12_EMAC_PTIME               (HCS12_EMAC_BASE+HCS12_EMAC_PTIME_OFFSET)
    87. 

  87. #define HCS12_EMAC_IEVENT              (HCS12_EMAC_BASE+HCS12_EMAC_IEVENT_OFFSET)
    88. 

  88. #define HCS12_EMAC_IMASK               (HCS12_EMAC_BASE+HCS12_EMAC_IMASK_OFFSET)
    89. 

  89. #define HCS12_EMAC_SWRST               (HCS12_EMAC_BASE+HCS12_EMAC_SWRST_OFFSET)
    90. 

  90. #define HCS12_EMAC_MPADR               (HCS12_EMAC_BASE+HCS12_EMAC_MPADR_OFFSET)
    91. 

  91. #define HCS12_EMAC_MRADR               (HCS12_EMAC_BASE+HCS12_EMAC_MRADR_OFFSET)
    92. 

  92. #define HCS12_EMAC_MWDATA              (HCS12_EMAC_BASE+HCS12_EMAC_MWDATA_OFFSET)
    93. 

  93. #define HCS12_EMAC_MRDATA              (HCS12_EMAC_BASE+HCS12_EMAC_MRDATA_OFFSET)
    94. 

  94. #define HCS12_EMAC_MCMST               (HCS12_EMAC_BASE+HCS12_EMAC_MCMST_OFFSET)
    95. 

  95. #define HCS12_EMAC_BUFCFG              (HCS12_EMAC_BASE+HCS12_EMAC_BUFCFG_OFFSET)
    96. 

  96. #define HCS12_EMAC_RXAEFP              (HCS12_EMAC_BASE+HCS12_EMAC_RXAEFP_OFFSET)
    97. 

  97. #define HCS12_EMAC_RXBEFP              (HCS12_EMAC_BASE+HCS12_EMAC_RXBEFP_OFFSET)
    98. 

  98. #define HCS12_EMAC_TXEFP               (HCS12_EMAC_BASE+HCS12_EMAC_TXEFP_OFFSET)
    99. 

  99. #define HCS12_EMAC_MCHASH48            (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH48_OFFSET)
    100. 

  100. #define HCS12_EMAC_MCHASH32            (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH32_OFFSET)
    101. 

  101. #define HCS12_EMAC_MCHASH16            (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH16_OFFSET)
    102. 

  102. #define HCS12_EMAC_MCHASH0             (HCS12_EMAC_BASE+HCS12_EMAC_MCHASH0_OFFSET)
    103. 

  103. #define HCS12_EMAC_MACAD32             (HCS12_EMAC_BASE+HCS12_EMAC_MACAD32_OFFSET)
    104. 

  104. #define HCS12_EMAC_MACAD16             (HCS12_EMAC_BASE+HCS12_EMAC_MACAD16_OFFSET)
    105. 

  105. #define HCS12_EMAC_MACAD0              (HCS12_EMAC_BASE+HCS12_EMAC_MACAD0_OFFSET)
    106. 

  106. #define HCS12_EMAC_EMISC               (HCS12_EMAC_BASE+HCS12_EMAC_EMISC_OFFSET)
    107. 

  107. 

  108. /* Register Bit-Field Definitions ***************************************************/
    109. 

  109. 

  110. /* Network Control (8-bit) */
    111. 

  111. 

  112. #define EMAC_NETCTL_FDX                (1 << 1)  /* Bit 1: Full Duplex */
    113. 

  113. #define EMAC_NETCTL_MLB                (1 << 2)  /* Bit 2: MAC Loopback */
    114. 

  114. #define EMAC_NETCTL_EXTPHY             (1 << 3)  /* Bit 3: External PHY */
    115. 

  115. #define EMAC_NETCTL_ESWAI              (1 << 4)  /* Bit 4: EMAC Disabled during Wait Mode */
    116. 

  116. #define EMAC_NETCTL_EMACE              (1 << 7)  /* Bit 7: EMAC Enable */
    117. 

  117. 

  118. /* Receive Control and Status (8-bit) */
    119. 

  119. 

  120. #define EMAC_RXCTS_BCREJ               (1 << 0)  /* Bit 0: Broadcast Reject */
    121. 

  121. #define EMAC_RXCTS_CONMC               (1 << 1)  /* Bit 1: Conditional Multicast */
    122. 

  122. #define EMAC_RXCTS_PROM                (1 << 2)  /* Bit 2: Promiscuous Mode */
    123. 

  123. #define EMAC_RXCTS_RFCE                (1 << 4)  /* Bit 4: Reception Flow Control Enable */
    124. 

  124. #define EMAC_RXCTS_RXACT               (1 << 7)  /* Bit 7: Receiver Active Status */
    125. 

  125. 

  126. /* Transmit Control and Status (8-bit) */
    127. 

  127. 

  128. #define EMAC_TXCTS_TCMD_SHIFT          (0)       /* Bits 0-1: Transmit Command */
    129. 

  129. #define EMAC_TXCTS_TCMD_MASK           (3)
    130. 

  130. #  define EMAC_TXCTS_TCMD_START        (1)       /* Transmit buffer frame */
    131. 

  131. #  define EMAC_TXCTS_TCMD_PAUSE        (2)       /* Transmit PAUSE frame (full-duplex mode only) */
    132. 

  132. #  define EMAC_TXCTS_TCMD_ABORT        (3)       /* Abort transmission */
    133. 

  133. #define EMAC_TXCTS_SSB                 (1 << 3)  /* Bit 3: Single Slot Backoff */
    134. 

  134. #define EMAC_TXCTS_PTRC                (1 << 4)  /* Bit 4: PAUSE Timer Register Control */
    135. 

  135. #define EMAC_TXCTS_CSLF                (1 << 5)  /* Bit 5: Carrier Sense Lost Flag */
    136. 

  136. #define EMAC_TXCTS_TXACT               (1 << 7)  /* Bit 7: Transmitter Active Status */
    137. 

  137. 

  138. /* Ethertype Control (8-bit) */
    139. 

  139. 

  140. #define EMAC_ETCTL_FIEEE               (1 << 0)  /* Bit 0: IEEE802.3 Length Field Ethertype */
    141. 

  141. #define EMAC_ETCTL_FIPV4               (1 << 1)  /* Bit 1: Internet Protocol Version 4 (IPv4) Ethertype */
    142. 

  142. #define EMAC_ETCTL_FARP                (1 << 2)  /* Bit 2: Address Resolution Protocol (ARP) Ethertype */
    143. 

  143. #define EMAC_ETCTL_FIPV6               (1 << 3)  /* Bit 3: Internet Protocol Version 6 (IPv6) Ethertype */
    144. 

  144. #define EMAC_ETCTL_FEMW                (1 << 4)  /* Bit 4: Emware Ethertype */
    145. 

  145. #define EMAC_ETCTL_FPET                (1 << 7)  /* Bit 7: Programmable Ethertype */
    146. 

  146. 

  147. /* Programmable Ethertype (16-bit) -- 16-bit Ethernet type data */
    148. 

  148. /* PAUSE Timer Value and Counter (16-bit) -- 16-bit PAUSER timer value */
    149. 

  149. 

  150. /* Interrupt Event (16-bit) */
    151. 

  151. /* Interrupt Mask (16-bit) */
    152. 

  152. 

  153. #define EMAC_INT_TXCI                  (1 << 1)  /* Bit 1:  Frame Transmission Complete Interrupt */
    154. 

  154. #define EMAC_INT_ECI                   (1 << 4)  /* Bit 4:  Excessive Collision Interrupt */
    155. 

  155. #define EMAC_INT_LCI                   (1 << 5)  /* Bit 5:  Late Collision Interrupt */
    156. 

  156. #define EMAC_INT_MMCI                  (1 << 7)  /* Bit 7:  MII Management Transfer Complete Interrupt */
    157. 

  157. #define EMAC_INT_RXBCI                 (1 << 8)  /* Bit 8:  Valid Frame Reception to Receive Buffer B Complete Interrupt */
    158. 

  158. #define EMAC_INT_RXACI                 (1 << 9)  /* Bit 9:  Valid Frame Reception to Receive Buffer A Complete Interrupt */
    159. 

  159. #define EMAC_INT_RXBOI                 (1 << 10) /* Bit 10: Receive Buffer B Overrun Interrupt */
    160. 

  160. #define EMAC_INT_RXAOI                 (1 << 11) /* Bit 11: Receive Buffer A Overrun Interrupt */
    161. 

  161. #define EMAC_INT_RXEI                  (1 << 12) /* Bit 12: Receive Error Interrupt */
    162. 

  162. #define EMAC_INT_BREI                  (1 << 13) /* Bit 13: Babbling Receive Error Interrupt */
    163. 

  163. #define EMAC_INT_RFCI                  (1 << 15) /* Bit 15: Receive Flow Control Interrupt */
    164. 

  164. 

  165. /* Software Reset (8-bit) */
    166. 

  166. 

  167. #define EMAC_SWRST_MACRST              (1 << 7)  /* Bit 7: EMAC is reset */
    168. 

  168. 

  169. /* MII Management PHY Address (8-bit) */
    170. 

  170. 

  171. #define EMAC_MPADR_MASK                (0x1f)
    172. 

  172. 

  173. /* MII Management Register Address (8-bit) */
    174. 

  174. 

  175. #define EMAC_MRADR_MASK                (0x1f)
    176. 

  176. 

  177. /* MII Management Write Data (16-bit) -- 16-bit write data */
    178. 

  178. /* MII Management Read Data (16-bit) -- 16-bit read data */
    179. 

  179. 

  180. /* MII Management Command and Status (8-bit) */
    181. 

  181. 

  182. #define EMAC_MCMST_MDCSEL_SHIFT        (0)       /* Bits 0-3: Management Clock Rate Sel */
    183. 

  183. #define EMAC_MCMST_MDCSEL_MASK         (15)      /*           MDC frequency = Bus clock frequency / (2 * MDCSEL) */
    184. 

  184. #define EMAC_MCMST_NOPRE               (1 << 4)  /* Bit 4:  No Preamble */
    185. 

  185. #define EMAC_MCMST_BUSY                (1 << 5)  /* Bit 5:  Operation in Progress */
    186. 

  186. #define EMAC_MCMST_OP_SHIFT            (6)       /* Bits 6-7: Operation Code */
    187. 

  187. #define EMAC_MCMST_OP_MASK             (3 << EMAC_MCMST_OP_SHIFT)
    188. 

  188. #  define EMAC_MCMST_OP_IGNORE         (0 << EMAC_MCMST_OP_SHIFT)
    189. 

  189. #  define EMAC_MCMST_OP_WRITE          (1 << EMAC_MCMST_OP_SHIFT)
    190. 

  190. #  define EMAC_MCMST_OP_READ           (2 << EMAC_MCMST_OP_SHIFT)
    191. 

  191. 

  192. /* Ethernet Buffer Configuration (16-bit) */
    193. 

  193. 

  194. #define EMAC_BUFCFG_MAXFL_SHIFT        (0)       /* Bits 0-10 Receive Maximum Frame Length */
    195. 

  195. #define EMAC_BUFCFG_MAXFL_MASK         (0x07ff)
    196. 

  196. #define EMAC_BUFCFG_BUFMAP_SHIFT       (12)      /* Bits 12-14: Buffer Size and Starting Address Mapping */
    197. 

  197. #define EMAC_BUFCFG_BUFMAP_SHIFT       (7 << EMAC_BUFCFG_BUFMAP_SHIFT)
    198. 

  198. #  define EMAC_BUFCFG_BUFMAP_128       (0 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 128 bytes */
    199. 

  199. #  define EMAC_BUFCFG_BUFMAP_256       (1 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 256 bytes */
    200. 

  200. #  define EMAC_BUFCFG_BUFMAP_512       (2 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 512 bytes */
    201. 

  201. #  define EMAC_BUFCFG_BUFMAP_1024      (3 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 1Kb */
    202. 

  202. #  define EMAC_BUFCFG_BUFMAP_1536      (4 << EMAC_BUFCFG_BUFMAP_SHIFT) /* Rx/Tx = 1.5Kb */
    203. 

  203. 

  204. /* Receive A End-of-Frame Pointer (16-bit) */
    205. 

  205. 

  206. #define EMAC_RXAEFP_MASK               (0x07ff)
    207. 

  207. 

  208. /* Receive B End-of-Frame Pointer (16-bit) */
    209. 

  209. 

  210. #define EMAC_RXBEFP_MASK               (0x07ff)
    211. 

  211. 

  212. /* Transmit End-of-Frame Pointer (16-bit) */
    213. 

  213. 

  214. #define EMAC_TXEFP_MASK                (0x07ff)
    215. 

  215. 

  216. /* Multicast Hash Table 48-63 (16-bit) -- 16-bits of MAC address */
    217. 

  217. /* Multicast Hash Table 32-47 (16-bit) -- 16-bits of MAC address */
    218. 

  218. /* Multicast Hash Table 16-31 (16-bit) -- 16-bits of MAC address */
    219. 

  219. /* Multicast Hash Table  0:15 (16-bit) -- 16-bits of MAC address */
    220. 

  220. 

  221. /* MAC Unicast Address 32-47 (16-bit) -- 16-bits of address */
    222. 

  222. /* MAC Unicast AAddress 16-31 (16-bit) -- 16-bits of address */
    223. 

  223. /* MAC Unicast AAddress 0-15 (16-bit) -- 16-bits of address */
    224. 

  224. 

  225. /* Miscellaneous (16-bit) */
    226. 

  226. 

  227. #define EMAC_EMISC_SHIFT               (0)       /* Bits 0-10: Misc data */
    228. 

  228. #define EMAC_EMISC_MASK                (0x07ff)
    229. 

  229. #define EMAC_EMISC_INDEX_SHIFT         (13)      /* Bits 13-15: Miscellaneous Index */
    230. 

  230. #define EMAC_EMISC_INDEX_MASK          (7 << EMAC_EMISC_INDEX_SHIFT)
    231. 

  231. #  define EMAC_EMISC_INDEX_TXBYT       (3 << EMAC_EMISC_INDEX_SHIFT) /* Transmit Frame Byte Counter */
    232. 

  232. #  define EMAC_EMISC_INDEX_BSLOT       (4 << EMAC_EMISC_INDEX_SHIFT) /* Backoff Slot Time Counter */
    233. 

  233. #  define EMAC_EMISC_INDEX_RETX        (5 << EMAC_EMISC_INDEX_SHIFT) /* Retransmission Counter */
    234. 

  234. #  define EMAC_EMISC_INDEX_RANDOM      (6 << EMAC_EMISC_INDEX_SHIFT) /* Backoff Random Number */
    235. 

  235. 

  236. /************************************************************************************
    237. 

  237.  * Public Types
    238. 

  238.  ************************************************************************************/
    239. 

  239. 

  240. /************************************************************************************
    241. 

  241.  * Public Data
    242. 

  242.  ************************************************************************************/
    243. 

  243. 

  244. /************************************************************************************
    245. 

  245.  * Public Functions
    246. 

  246.  ************************************************************************************/
    247. 

  247. 

  248. #endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_EMAC_H */
    249. 

  249.