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/arch/arm/include/stm32l4/stm32l4x6xx_irq.h

https://bitbucket.org/benchmark-electronics/nuttx
C Header | 200 lines | 121 code | 18 blank | 61 comment | 1 complexity | 982531eeddf566939bf5291cc07d7009 MD5 | raw file
Possible License(s): 0BSD 
    

  1. /****************************************************************************************************
    2. 

  2.  * arch/arm/include/stm32l4/stm32l4x6xx_irq.h
    3. 

  3.  *
    4. 

  4.  *   Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
    5. 

  5.  *   Author: Sebastien Lorquet <sebastien@lorquet.fr>
    6. 

  6.  *
    7. 

  7.  * Redistribution and use in source and binary forms, with or without
    8. 

  8.  * modification, are permitted provided that the following conditions
    9. 

  9.  * are met:
    10. 

  10.  *
    11. 

  11.  * 1. Redistributions of source code must retain the above copyright
    12. 

  12.  *    notice, this list of conditions and the following disclaimer.
    13. 

  13.  *
    14. 

  14.  * 2. Redistributions in binary form must reproduce the above copyright
    15. 

  15.  *    notice, this list of conditions and the following disclaimer in
    16. 

  16.  *    the documentation and/or other materials provided with the
    17. 

  17.  *    distribution.
    18. 

  18.  * 3. Neither the name NuttX nor the names of its contributors may be
    19. 

  19.  *    used to endorse or promote products derived from this software
    20. 

  20.  *    without specific prior written permission.
    21. 

  21.  *
    22. 

  22.  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    23. 

  23.  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    24. 

  24.  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
    25. 

  25.  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
    26. 

  26.  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
    27. 

  27.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    28. 

  28.  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
    29. 

  29.  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
    30. 

  30.  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
    31. 

  31.  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
    32. 

  32.  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    33. 

  33.  * POSSIBILITY OF SUCH DAMAGE.
    34. 

  34.  *
    35. 

  35.  ****************************************************************************************************/
    36. 

  36. 

  37. /* This file should never be included directed but, rather, only indirectly through arch/irq.h */
    38. 

  38. 

  39. #ifndef __ARCH_ARM_INCLUDE_STM32L4_STM32L4X6XX_IRQ_H
    40. 

  40. #define __ARCH_ARM_INCLUDE_STM32L4_STM32L4X6XX_IRQ_H
    41. 

  41. 

  42. /****************************************************************************************************
    43. 

  43.  * Included Files
    44. 

  44.  ****************************************************************************************************/
    45. 

  45. 

  46. #include <nuttx/config.h>
    47. 

  47. 

  48. /****************************************************************************************************
    49. 

  49.  * Pre-processor Definitions
    50. 

  50.  ****************************************************************************************************/
    51. 

  51. 

  52. /* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to bits in the
    53. 

  53.  * NVIC.  This does, however, waste several words of memory in the IRQ to handle mapping tables.
    54. 

  54.  *
    55. 

  55.  * Processor Exceptions (vectors 0-15).  These common definitions can be found in the file
    56. 

  56.  * nuttx/arch/arm/include/stm32l4/irq.h which includes this file.
    57. 

  57.  *
    58. 

  58.  * External interrupts (vectors >= 16)
    59. 

  59.  */
    60. 

  60. 

  61. #define STM32L4_IRQ_WWDG        (STM32L4_IRQ_FIRST + 0)  /* 0:  Window Watchdog interrupt */
    62. 

  62. #define STM32L4_IRQ_PVD         (STM32L4_IRQ_FIRST + 1)  /* 1:  PVD through EXTI Line detection interrupt */
    63. 

  63. #define STM32L4_IRQ_TAMPER      (STM32L4_IRQ_FIRST + 2)  /* 2:  Tamper and time stamp interrupts */
    64. 

  64. #define STM32L4_IRQ_TIMESTAMP   (STM32L4_IRQ_FIRST + 2)  /* 2:  Tamper and time stamp interrupts */
    65. 

  65. #define STM32L4_IRQ_RTC_WKUP    (STM32L4_IRQ_FIRST + 3)  /* 3:  RTC global interrupt */
    66. 

  66. #define STM32L4_IRQ_FLASH       (STM32L4_IRQ_FIRST + 4)  /* 4:  Flash global interrupt */
    67. 

  67. #define STM32L4_IRQ_RCC         (STM32L4_IRQ_FIRST + 5)  /* 5:  RCC global interrupt */
    68. 

  68. #define STM32L4_IRQ_EXTI0       (STM32L4_IRQ_FIRST + 6)  /* 6:  EXTI Line 0 interrupt */
    69. 

  69. #define STM32L4_IRQ_EXTI1       (STM32L4_IRQ_FIRST + 7)  /* 7:  EXTI Line 1 interrupt */
    70. 

  70. #define STM32L4_IRQ_EXTI2       (STM32L4_IRQ_FIRST + 8)  /* 8:  EXTI Line 2 interrupt */
    71. 

  71. #define STM32L4_IRQ_EXTI3       (STM32L4_IRQ_FIRST + 9)  /* 9:  EXTI Line 3 interrupt */
    72. 

  72. #define STM32L4_IRQ_EXTI4       (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
    73. 

  73. #define STM32L4_IRQ_DMA1CH1     (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
    74. 

  74. #define STM32L4_IRQ_DMA1CH2     (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
    75. 

  75. #define STM32L4_IRQ_DMA1CH3     (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
    76. 

  76. #define STM32L4_IRQ_DMA1CH4     (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
    77. 

  77. #define STM32L4_IRQ_DMA1CH5     (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
    78. 

  78. #define STM32L4_IRQ_DMA1CH6     (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
    79. 

  79. #define STM32L4_IRQ_DMA1CH7     (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
    80. 

  80. #define STM32L4_IRQ_ADC12       (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
    81. 

  81. #define STM32L4_IRQ_CAN1TX      (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
    82. 

  82. #define STM32L4_IRQ_CAN1RX0     (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
    83. 

  83. #define STM32L4_IRQ_CAN1RX1     (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
    84. 

  84. #define STM32L4_IRQ_CAN1SCE     (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
    85. 

  85. #define STM32L4_IRQ_EXTI95      (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
    86. 

  86. #define STM32L4_IRQ_TIM1BRK     (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
    87. 

  87. #define STM32L4_IRQ_TIM15       (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
    88. 

  88. #define STM32L4_IRQ_TIM1UP      (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
    89. 

  89. #define STM32L4_IRQ_TIM16       (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
    90. 

  90. #define STM32L4_IRQ_TIM1TRGCOM  (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
    91. 

  91. #define STM32L4_IRQ_TIM17       (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
    92. 

  92. #define STM32L4_IRQ_TIM1CC      (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
    93. 

  93. #define STM32L4_IRQ_TIM2        (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
    94. 

  94. #define STM32L4_IRQ_TIM3        (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
    95. 

  95. #define STM32L4_IRQ_TIM4        (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
    96. 

  96. #define STM32L4_IRQ_I2C1EV      (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
    97. 

  97. #define STM32L4_IRQ_I2C1ER      (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
    98. 

  98. #define STM32L4_IRQ_I2C2EV      (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
    99. 

  99. #define STM32L4_IRQ_I2C2ER      (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
    100. 

  100. #define STM32L4_IRQ_SPI1        (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
    101. 

  101. #define STM32L4_IRQ_SPI2        (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
    102. 

  102. #define STM32L4_IRQ_USART1      (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
    103. 

  103. #define STM32L4_IRQ_USART2      (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
    104. 

  104. #define STM32L4_IRQ_USART3      (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
    105. 

  105. #define STM32L4_IRQ_EXTI1510    (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
    106. 

  106. #define STM32L4_IRQ_RTCALRM     (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
    107. 

  107. #define STM32L4_IRQ_DFSDM3      (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
    108. 

  108. #define STM32L4_IRQ_TIM8BRK     (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
    109. 

  109. #define STM32L4_IRQ_TIM8UP      (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
    110. 

  110. #define STM32L4_IRQ_TIM8TRGCOM  (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
    111. 

  111. #define STM32L4_IRQ_TIM8CC      (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
    112. 

  112. #define STM32L4_IRQ_ADC3        (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
    113. 

  113. #define STM32L4_IRQ_FSMC        (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
    114. 

  114. #define STM32L4_IRQ_SDMMC1      (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
    115. 

  115. #define STM32L4_IRQ_TIM5        (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
    116. 

  116. #define STM32L4_IRQ_SPI3        (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
    117. 

  117. #define STM32L4_IRQ_UART4       (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
    118. 

  118. #define STM32L4_IRQ_UART5       (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
    119. 

  119. #define STM32L4_IRQ_TIM6        (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
    120. 

  120. #define STM32L4_IRQ_DAC         (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
    121. 

  121. #define STM32L4_IRQ_TIM7        (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
    122. 

  122. #define STM32L4_IRQ_DMA2CH1     (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
    123. 

  123. #define STM32L4_IRQ_DMA2CH2     (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
    124. 

  124. #define STM32L4_IRQ_DMA2CH3     (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
    125. 

  125. #define STM32L4_IRQ_DMA2CH4     (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
    126. 

  126. #define STM32L4_IRQ_DMA2CH5     (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
    127. 

  127. #define STM32L4_IRQ_DFSDM0      (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
    128. 

  128. #define STM32L4_IRQ_DFSDM1      (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
    129. 

  129. #define STM32L4_IRQ_DFSDM2      (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
    130. 

  130. #define STM32L4_IRQ_COMP        (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
    131. 

  131. #define STM32L4_IRQ_LPTIM1      (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
    132. 

  132. #define STM32L4_IRQ_LPTIM2      (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
    133. 

  133. #define STM32L4_IRQ_OTGFS       (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
    134. 

  134. #define STM32L4_IRQ_DMA2CH6     (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
    135. 

  135. #define STM32L4_IRQ_DMA2CH7     (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
    136. 

  136. #define STM32L4_IRQ_LPUART1     (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
    137. 

  137. #define STM32L4_IRQ_QUADSPI     (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
    138. 

  138. #define STM32L4_IRQ_I2C3EV      (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
    139. 

  139. #define STM32L4_IRQ_I2C3ER      (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
    140. 

  140. #define STM32L4_IRQ_SAI1        (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
    141. 

  141. #define STM32L4_IRQ_SAI2        (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
    142. 

  142. #define STM32L4_IRQ_SWPMI1      (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
    143. 

  143. #define STM32L4_IRQ_TSC         (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
    144. 

  144. #define STM32L4_IRQ_LCD         (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */
    145. 

  145. #define STM32L4_IRQ_AES         (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
    146. 

  146. #define STM32L4_IRQ_RNG         (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
    147. 

  147. #define STM32L4_IRQ_FPU         (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
    148. 

  148. 

  149. /* STM32L496xx/4A6xx only: */
    150. 

  150. 

  151. #define STM32L4_IRQ_HASH_CRS    (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
    152. 

  152. #define STM32L4_IRQ_I2C4EV      (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
    153. 

  153. #define STM32L4_IRQ_I2C4ER      (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
    154. 

  154. #define STM32L4_IRQ_DCMI        (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
    155. 

  155. #define STM32L4_IRQ_CAN2TX      (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */
    156. 

  156. #define STM32L4_IRQ_CAN2RX0     (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */
    157. 

  157. #define STM32L4_IRQ_CAN2RX1     (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */
    158. 

  158. #define STM32L4_IRQ_CAN2SCE     (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */
    159. 

  159. #define STM32L4_IRQ_DMA2D       (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
    160. 

  160. 

  161. #if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
    162. 

  162. #  define STM32L4_IRQ_NEXTINTS  82
    163. 

  163. #elif defined(CONFIG_STM32L4_STM32L496XX)
    164. 

  164. #  define STM32L4_IRQ_NEXTINTS  91
    165. 

  165. #else
    166. 

  166. #  error "Unsupported STM32L4 chip"
    167. 

  167. #endif
    168. 

  168. 

  169. /* EXTI interrupts (Do not use IRQ numbers) */
    170. 

  170. 

  171. #define NR_IRQS                 (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
    172. 

  172. 

  173. /****************************************************************************************************
    174. 

  174.  * Public Types
    175. 

  175.  ****************************************************************************************************/
    176. 

  176. 

  177. /****************************************************************************************************
    178. 

  178.  * Public Data
    179. 

  179.  ****************************************************************************************************/
    180. 

  180. 

  181. #ifndef __ASSEMBLY__
    182. 

  182. #ifdef __cplusplus
    183. 

  183. #define EXTERN extern "C"
    184. 

  184. extern "C"
    185. 

  185. {
    186. 

  186. #else
    187. 

  187. #define EXTERN extern
    188. 

  188. #endif
    189. 

  189. 

  190. /****************************************************************************************************
    191. 

  191.  * Public Functions
    192. 

  192.  ****************************************************************************************************/
    193. 

  193. 

  194. #undef EXTERN
    195. 

  195. #ifdef __cplusplus
    196. 

  196. }
    197. 

  197. #endif
    198. 

  198. #endif
    199. 

  199. 

  200. #endif /* __ARCH_ARM_INCLUDE_STM32L4_STM32L4X6XX_IRQ_H */
    201. 

  201.