/Src/stm32f7xx_it.c

/**

  ******************************************************************************

  * @file    stm32f7xx_it.c

  * @brief   Interrupt Service Routines.

  ******************************************************************************

  *

  * COPYRIGHT(c) 2018 STMicroelectronics

  *

  * Redistribution and use in source and binary forms, with or without modification,

  * are permitted provided that the following conditions are met:

  *   1. Redistributions of source code must retain the above copyright notice,

  *      this list of conditions and the following disclaimer.

  *   2. Redistributions in binary form must reproduce the above copyright notice,

  *      this list of conditions and the following disclaimer in the documentation

  *      and/or other materials provided with the distribution.

  *   3. Neither the name of STMicroelectronics nor the names of its contributors

  *      may be used to endorse or promote products derived from this software

  *      without specific prior written permission.

  *

  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  *

  ******************************************************************************

  */

/* Includes ------------------------------------------------------------------*/

#include "stm32f7xx_hal.h"

#include "stm32f7xx.h"

#include "stm32f7xx_it.h"

#include "cmsis_os.h"



/* USER CODE BEGIN 0 */



/* USER CODE END 0 */



/* External variables --------------------------------------------------------*/

extern DMA_HandleTypeDef hdma_adc1;

extern ADC_HandleTypeDef hadc1;

extern DMA_HandleTypeDef hdma_dac1;

extern DMA_HandleTypeDef hdma_dac2;

extern DAC_HandleTypeDef hdac;

extern DMA_HandleTypeDef hdma_sai1_a;

extern DMA_HandleTypeDef hdma_sai1_b;

extern DMA_HandleTypeDef hdma_sai2_a;

extern DMA_HandleTypeDef hdma_sai2_b;

extern TIM_HandleTypeDef htim2;

extern TIM_HandleTypeDef htim6;

extern DMA_HandleTypeDef hdma_uart5_rx;

extern DMA_HandleTypeDef hdma_uart5_tx;

extern UART_HandleTypeDef huart1;



extern TIM_HandleTypeDef htim1;



/******************************************************************************/

/*            Cortex-M7 Processor Interruption and Exception Handlers         */ 

/******************************************************************************/



/**

* @brief This function handles Non maskable interrupt.

*/

void NMI_Handler(void)

{

  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */



  /* USER CODE END NonMaskableInt_IRQn 0 */

  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */



  /* USER CODE END NonMaskableInt_IRQn 1 */

}



/**

* @brief This function handles Hard fault interrupt.

*/

void HardFault_Handler(void)

{

  /* USER CODE BEGIN HardFault_IRQn 0 */



  /* USER CODE END HardFault_IRQn 0 */

  while (1)

  {

    /* USER CODE BEGIN W1_HardFault_IRQn 0 */

    /* USER CODE END W1_HardFault_IRQn 0 */

  }

  /* USER CODE BEGIN HardFault_IRQn 1 */



  /* USER CODE END HardFault_IRQn 1 */

}



/**

* @brief This function handles Memory management fault.

*/

void MemManage_Handler(void)

{

  /* USER CODE BEGIN MemoryManagement_IRQn 0 */



  /* USER CODE END MemoryManagement_IRQn 0 */

  while (1)

  {

    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */

    /* USER CODE END W1_MemoryManagement_IRQn 0 */

  }

  /* USER CODE BEGIN MemoryManagement_IRQn 1 */



  /* USER CODE END MemoryManagement_IRQn 1 */

}



/**

* @brief This function handles Pre-fetch fault, memory access fault.

*/

void BusFault_Handler(void)

{

  /* USER CODE BEGIN BusFault_IRQn 0 */



  /* USER CODE END BusFault_IRQn 0 */

  while (1)

  {

    /* USER CODE BEGIN W1_BusFault_IRQn 0 */

    /* USER CODE END W1_BusFault_IRQn 0 */

  }

  /* USER CODE BEGIN BusFault_IRQn 1 */



  /* USER CODE END BusFault_IRQn 1 */

}



/**

* @brief This function handles Undefined instruction or illegal state.

*/

void UsageFault_Handler(void)

{

  /* USER CODE BEGIN UsageFault_IRQn 0 */



  /* USER CODE END UsageFault_IRQn 0 */

  while (1)

  {

    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */

    /* USER CODE END W1_UsageFault_IRQn 0 */

  }

  /* USER CODE BEGIN UsageFault_IRQn 1 */



  /* USER CODE END UsageFault_IRQn 1 */

}



/**

* @brief This function handles Debug monitor.

*/

void DebugMon_Handler(void)

{

  /* USER CODE BEGIN DebugMonitor_IRQn 0 */



  /* USER CODE END DebugMonitor_IRQn 0 */

  /* USER CODE BEGIN DebugMonitor_IRQn 1 */



  /* USER CODE END DebugMonitor_IRQn 1 */

}



/**

* @brief This function handles System tick timer.

*/

void SysTick_Handler(void)

{

  /* USER CODE BEGIN SysTick_IRQn 0 */



  /* USER CODE END SysTick_IRQn 0 */

  osSystickHandler();

  /* USER CODE BEGIN SysTick_IRQn 1 */



  /* USER CODE END SysTick_IRQn 1 */

}



/******************************************************************************/

/* STM32F7xx Peripheral Interrupt Handlers                                    */

/* Add here the Interrupt Handlers for the used peripherals.                  */

/* For the available peripheral interrupt handler names,                      */

/* please refer to the startup file (startup_stm32f7xx.s).                    */

/******************************************************************************/



/**

* @brief This function handles DMA1 stream0 global interrupt.

*/

void DMA1_Stream0_IRQHandler(void)

{

  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */



  /* USER CODE END DMA1_Stream0_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_uart5_rx);

  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */



  /* USER CODE END DMA1_Stream0_IRQn 1 */

}



/**

* @brief This function handles DMA1 stream5 global interrupt.

*/

void DMA1_Stream5_IRQHandler(void)

{

  /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */



  /* USER CODE END DMA1_Stream5_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_dac1);

  /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */



  /* USER CODE END DMA1_Stream5_IRQn 1 */

}



/**

* @brief This function handles DMA1 stream6 global interrupt.

*/

void DMA1_Stream6_IRQHandler(void)

{

  /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */



  /* USER CODE END DMA1_Stream6_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_dac2);

  /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */



  /* USER CODE END DMA1_Stream6_IRQn 1 */

}



/**

* @brief This function handles ADC1, ADC2 and ADC3 global interrupts.

*/

void ADC_IRQHandler(void)

{

  /* USER CODE BEGIN ADC_IRQn 0 */



  /* USER CODE END ADC_IRQn 0 */

  HAL_ADC_IRQHandler(&hadc1);

  /* USER CODE BEGIN ADC_IRQn 1 */



  /* USER CODE END ADC_IRQn 1 */

}



/**

* @brief This function handles TIM1 update interrupt and TIM10 global interrupt.

*/

void TIM1_UP_TIM10_IRQHandler(void)

{

  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */



  /* USER CODE END TIM1_UP_TIM10_IRQn 0 */

  HAL_TIM_IRQHandler(&htim1);

  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */



  /* USER CODE END TIM1_UP_TIM10_IRQn 1 */

}



/**

* @brief This function handles TIM2 global interrupt.

*/

void TIM2_IRQHandler(void)

{

  /* USER CODE BEGIN TIM2_IRQn 0 */



  /* USER CODE END TIM2_IRQn 0 */

  HAL_TIM_IRQHandler(&htim2);

  /* USER CODE BEGIN TIM2_IRQn 1 */



  /* USER CODE END TIM2_IRQn 1 */

}



/**

* @brief This function handles USART1 global interrupt.

*/

void USART1_IRQHandler(void)

{

  /* USER CODE BEGIN USART1_IRQn 0 */



  /* USER CODE END USART1_IRQn 0 */

  HAL_UART_IRQHandler(&huart1);

  /* USER CODE BEGIN USART1_IRQn 1 */



  /* USER CODE END USART1_IRQn 1 */

}



/**

* @brief This function handles EXTI line[15:10] interrupts.

*/

void EXTI15_10_IRQHandler(void)

{

  /* USER CODE BEGIN EXTI15_10_IRQn 0 */



  /* USER CODE END EXTI15_10_IRQn 0 */

  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);

  /* USER CODE BEGIN EXTI15_10_IRQn 1 */



  /* USER CODE END EXTI15_10_IRQn 1 */

}



/**

* @brief This function handles DMA1 stream7 global interrupt.

*/

void DMA1_Stream7_IRQHandler(void)

{

  /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */



  /* USER CODE END DMA1_Stream7_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_uart5_tx);

  /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */



  /* USER CODE END DMA1_Stream7_IRQn 1 */

}



/**

* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.

*/

void TIM6_DAC_IRQHandler(void)

{

  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */



  /* USER CODE END TIM6_DAC_IRQn 0 */

  HAL_DAC_IRQHandler(&hdac);

  HAL_TIM_IRQHandler(&htim6);

  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */



  /* USER CODE END TIM6_DAC_IRQn 1 */

}



/**

* @brief This function handles DMA2 stream0 global interrupt.

*/

void DMA2_Stream0_IRQHandler(void)

{

  /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */



  /* USER CODE END DMA2_Stream0_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_adc1);

  /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */



  /* USER CODE END DMA2_Stream0_IRQn 1 */

}



/**

* @brief This function handles DMA2 stream3 global interrupt.

*/

void DMA2_Stream3_IRQHandler(void)

{

  /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */



  /* USER CODE END DMA2_Stream3_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_sai1_a);

  /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */



  /* USER CODE END DMA2_Stream3_IRQn 1 */

}



/**

* @brief This function handles DMA2 stream4 global interrupt.

*/

void DMA2_Stream4_IRQHandler(void)

{

  /* USER CODE BEGIN DMA2_Stream4_IRQn 0 */



  /* USER CODE END DMA2_Stream4_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_sai2_a);

  /* USER CODE BEGIN DMA2_Stream4_IRQn 1 */



  /* USER CODE END DMA2_Stream4_IRQn 1 */

}



/**

* @brief This function handles DMA2 stream5 global interrupt.

*/

void DMA2_Stream5_IRQHandler(void)

{

  /* USER CODE BEGIN DMA2_Stream5_IRQn 0 */



  /* USER CODE END DMA2_Stream5_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_sai1_b);

  /* USER CODE BEGIN DMA2_Stream5_IRQn 1 */



  /* USER CODE END DMA2_Stream5_IRQn 1 */

}



/**

* @brief This function handles DMA2 stream6 global interrupt.

*/

void DMA2_Stream6_IRQHandler(void)

{

  /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */



  /* USER CODE END DMA2_Stream6_IRQn 0 */

  HAL_DMA_IRQHandler(&hdma_sai2_b);

  /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */



  /* USER CODE END DMA2_Stream6_IRQn 1 */

}



/* USER CODE BEGIN 1 */



/* USER CODE END 1 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/