/drivers/net/wireless/tiwlan1251/common/src/hal/FirmwareApi/public_host_int.h

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#ifndef PUBLIC_HOST_INT_H
#define PUBLIC_HOST_INT_H

#include "public_types.h"

                
/*************************************************************************

    Host Interrupt Register (WiLink -> Host)
 
**************************************************************************/

#define ACX_INTR_RX0_DATA			BIT_0   /* RX packet is ready in Xfer buffer #0*/
#define ACX_INTR_TX_RESULT			BIT_1   /* TX result(s) are in the TX complete buffer  */
#define ACX_INTR_TX_XFR				BIT_2   /* OBSOLETE*/
#define ACX_INTR_RX1_DATA			BIT_3   /* RX packet is ready in Xfer buffer #1*/
#define ACX_INTR_EVENT_A			BIT_4   /* Event was entered to Event MBOX #A*/
#define ACX_INTR_EVENT_B	        BIT_5   /* Event was entered to Event MBOX #B */
#define ACX_INTR_WAKE_ON_HOST       BIT_6   /* OBSOLETE */
#define ACX_INTR_TRACE_A	        BIT_7   /* Trace meassge on MBOX #A*/
#define ACX_INTR_TRACE_B            BIT_8   /* Trace meassge on MBOX #B*/
#define ACX_INTR_CMD_COMPLETE       BIT_9   /* Command processing completion*/
#define ACX_INTR_INIT_COMPLETE		BIT_14	/* Init sequence is done*/

#define ACX_INTR_ALL                0xFFFFFFFF


/*************************************************************************

    Interrupt Trigger Register (Host -> WiLink)              
  
**************************************************************************/

/******** Hardware to Embedded CPU Interrupts - first 32-bit register set ********/ 
   
#define INTR_TRIG_CMD       BIT_0   /* Host Command Interrupt. Setting this bit masks*/
                                    /* the interrupt that the host issues to inform*/
                                    /* the FW that it has sent a command*/
                                    /* to the Wlan hardware Command Mailbox.*/
    
#define INTR_TRIG_EVENT_ACK BIT_1   /* Host Event Acknowlegde Interrupt. The host */
                                    /* sets this bit to acknowledge that it received*/
                                    /* the unsolicited information from the event*/
                                    /* mailbox.*/
                                       
#define INTR_TRIG_TX_PROC0 BIT_2    /* The host sets this bit to inform the Wlan */
                                    /* FW that a TX packet is in the XFER */
                                    /* Buffer #0.*/
                                       
#define INTR_TRIG_RX_PROC0 BIT_3    /* The host sets this bit to inform the FW */
                                    /* that it read a packet from RX XFER */
                                    /* Buffer #0.*/

#define INTR_TRIG_DEBUG_ACK BIT_4 
    
#define INTR_TRIG_STATE_CHANGED BIT_5
        

/******** Hardware to Embedded CPU Interrupts - second 32-bit register set ********/

#define INTR_TRIG_RX_PROC1 BIT_17     /* The host sets this bit to inform the FW */
                                     /* that it read a packet from RX XFER */
                                     /* Buffer #1.  */

#define INTR_TRIG_TX_PROC1 BIT_18    /* The host sets this bit to inform the Wlan */
                                     /* hardware that a TX packet is in the XFER */
                                     /* Buffer #1.*/

#endif