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/drivers/net/wireless/tiwlan1251/common/src/hal/TnetwServices/TNETW1251/TnetwRegisters.h

http://github.com/CyanogenMod/cm-kernel
C Header | 971 lines | 775 code | 80 blank | 116 comment | 0 complexity | e2390807841852e1ee35ca4e45808f00 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0 
    

  1. /****************************************************************************
    2. 

  2. **+-----------------------------------------------------------------------+**
    3. 

  3. **|                                                                       |**
    4. 

  4. **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved.      |**
    5. 

  5. **| All rights reserved.                                                  |**
    6. 

  6. **|                                                                       |**
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  7. **| Redistribution and use in source and binary forms, with or without    |**
    8. 

  8. **| modification, are permitted provided that the following conditions    |**
    9. 

  9. **| are met:                                                              |**
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  10. **|                                                                       |**
    11. 

  11. **|  * Redistributions of source code must retain the above copyright     |**
    12. 

  12. **|    notice, this list of conditions and the following disclaimer.      |**
    13. 

  13. **|  * Redistributions in binary form must reproduce the above copyright  |**
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  14. **|    notice, this list of conditions and the following disclaimer in    |**
    15. 

  15. **|    the documentation and/or other materials provided with the         |**
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  16. **|    distribution.                                                      |**
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  17. **|  * Neither the name Texas Instruments nor the names of its            |**
    18. 

  18. **|    contributors may be used to endorse or promote products derived    |**
    19. 

  19. **|    from this software without specific prior written permission.      |**
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  20. **|                                                                       |**
    21. 

  21. **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS   |**
    22. 

  22. **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT     |**
    23. 

  23. **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |**
    24. 

  24. **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT  |**
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  25. **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |**
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  26. **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      |**
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  27. **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |**
    28. 

  28. **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |**
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  29. **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT   |**
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  30. **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |**
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  31. **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  |**
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  32. **|                                                                       |**
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  33. **+-----------------------------------------------------------------------+**
    34. 

  34. ****************************************************************************/
    35. 

  35. 

  36. #ifndef RGM_TNETW1150_H
    37. 

  37. #define RGM_TNETW1150_H
    38. 

  38. 

  39. #include "public_types.h"
    40. 

  40. 

  41. 

  42. /* Base addresses*/
    43. 

  43. /* They are not used inside registers definition in purpose to allow this header file*/
    44. 

  44. /* to be used as an easy reference to register -> address date base. Keep this as it*/
    45. 

  45. /* is very powerful for debugging purpose.*/
    46. 

  46. #define HOST_SLAVE_BASE	0x00300000
    47. 

  47. #define INT_BASE		0x00300400
    48. 

  48. #define REG_CONFIG_BASE	0x00300800
    49. 

  49. #define CLK_BASE		0x00300C00
    50. 

  50. #define SDMA_BASE		0x00301000
    51. 

  51. #define AES_BASE		0x00301400
    52. 

  52. #define WEP_BASE		0x00301800
    53. 

  53. #define TKIP_BASE		0x00301C00
    54. 

  54. #define SEEPROM_BASE	0x00302000
    55. 

  55. #define PAR_HOST_BASE	0x00302400
    56. 

  56. #define SDIO_BASE		0x00302800
    57. 

  57. #define UART_BASE		0x00302C00
    58. 

  58. #define USB11_BASE		0x00304000
    59. 

  59. #define LDMA_BASE		0x00304400
    60. 

  60. #define RX_BASE			0x00304800
    61. 

  61. #define ACCESS_BASE		0x00304c00
    62. 

  62. #define TX_BASE			0x00305000
    63. 

  63. #define RMAC_CSR_BASE	0x00305400
    64. 

  64. #define AFE_PM			0x00305800
    65. 

  65. #define VLYNQ_BASE		0x00308000
    66. 

  66. #define PCI_BASE		0x00308400
    67. 

  67. #define USB20_BASE		0x0030A000
    68. 

  68. #define PHY_BASE		0x003C0000
    69. 

  69. 

  70. 

  71. /* System DMA registers*/
    72. 

  72. /* Order of registers was changed*/
    73. 

  73. #define DMA_GLB_CFG                    (0x1000)
    74. 

  74. #define DMA_HDESC_OFFSET               (0x1004)
    75. 

  75. #define DMA_HDATA_OFFSET               (0x1008)
    76. 

  76. #define DMA_CFG0                       (0x100C) /* SDMA_HOST_CFG0 changed*/
    77. 

  77. #define DMA_CTL0                       (0x1010) /* SDMA_CTRL0 changed*/
    78. 

  78. #define DMA_LENGTH0                    (0x1014)
    79. 

  79. #define DMA_L_ADDR0                    (0x1018) /* SDMA_RD_ADDR ?*/
    80. 

  80. #define DMA_L_PTR0                     (0x101C) /* SDMA_RD_OFFSET ?*/
    81. 

  81. #define DMA_H_ADDR0                    (0x1020) /* SDMA_WR_ADDR ?*/
    82. 

  82. #define DMA_H_PTR0                     (0x1024) /* SDMA_WR_OFFSET ?*/
    83. 

  83. #define DMA_STS0                       (0x1028) /* Changed*/
    84. 

  84. #define DMA_CFG1                       (0x1030) /* SDMA_HOST_CFG1 changed*/
    85. 

  85. #define DMA_CTL1                       (0x1034) /* SDMA_CTRL1 changed*/
    86. 

  86. #define DMA_LENGTH1                    (0x1038)
    87. 

  87. #define DMA_L_ADDR1                    (0x103C)
    88. 

  88. #define DMA_L_PTR1                     (0x1040)
    89. 

  89. #define DMA_H_ADDR1                    (0x1044)
    90. 

  90. #define DMA_H_PTR1                     (0x1048)
    91. 

  91. #define DMA_STS1                       (0x104C)
    92. 

  92. #define DMA_HFRM_PTR                   (0x1050) /* New ?*/
    93. 

  93. #define DMA_DEBUG                      (0x1054) /* Changed*/
    94. 

  94. 

  95. /* Local DMA registers*/
    96. 

  96. /* number changed from 4 to 2*/
    97. 

  97. #define LDMA_DEBUG                     (0x4400)
    98. 

  98. #define LDMA_CTL0                      (0x4404) /* Add 2 bits to support fix address (FIFO)*/
    99. 

  99. #define LDMA_STATUS0                   (0x4408)
    100. 

  100. #define LDMA_LENGTH0                   (0x440c)
    101. 

  101. #define LDMA_RD_ADDR0                  (0x4410)
    102. 

  102. #define LDMA_RD_OFFSET0                (0x4414)
    103. 

  103. #define LDMA_WR_ADDR0                  (0x4418)
    104. 

  104. #define LDMA_WR_OFFSET0                (0x441c)
    105. 

  105. #define LDMA_CTL1                      (0x4428) /* Add 2 bits to support fix address (FIFO)*/
    106. 

  106. #define LDMA_STATUS1                   (0x442c)
    107. 

  107. #define LDMA_LENGTH1                   (0x4430)
    108. 

  108. #define LDMA_RD_ADDR1                  (0x4434)
    109. 

  109. #define LDMA_RD_OFFSET1                (0x4438)
    110. 

  110. #define LDMA_WR_ADDR1                  (0x443c)
    111. 

  111. #define LDMA_WR_OFFSET1                (0x4440)
    112. 

  112. /* For TNETW compatability (if willbe )*/
    113. 

  113. #define LDMA_CUR_RD_PTR0               LDMA_RD_ADDR0
    114. 

  114. #define LDMA_CUR_WR_PTR0               LDMA_WR_ADDR0
    115. 

  115. #define LDMA_CUR_RD_PTR1               LDMA_RD_ADDR1
    116. 

  116. #define LDMA_CUR_WR_PTR1               LDMA_WR_ADDR1
    117. 

  117. 

  118. /* Host Slave registers*/
    119. 

  119. #define SLV_SOFT_RESET                 (0x0000) /* self clearing*/
    120. 

  120. #define SLV_REG_ADDR                   (0x0004)
    121. 

  121. #define SLV_REG_DATA                   (0x0008)
    122. 

  122. #define SLV_REG_ADATA                  (0x000c)
    123. 

  123. #define SLV_MEM_CP                     (0x0010)
    124. 

  124. #define SLV_MEM_ADDR                   (0x0014)
    125. 

  125. #define SLV_MEM_DATA                   (0x0018)
    126. 

  126. #define SLV_MEM_CTL                    (0x001c) /* bit 19 moved to PCMCIA_CTL*/
    127. 

  127. #define SLV_END_CTL                    (0x0020) /* 2 bits moved to ENDIAN_CTL*/
    128. 

  128. 

  129. /* Timer registers*/
    130. 

  130. /* Timer1/2 count MAC clocks*/
    131. 

  131. /* Timer3/4/5 count usec*/
    132. 

  132. #define TIM1_CTRL                      (0x0918)
    133. 

  133. #define TIM1_LOAD                      (0x091C)
    134. 

  134. #define TIM1_CNT                       (0x0920)
    135. 

  135. #define TIM2_CTRL                      (0x0924)
    136. 

  136. #define TIM2_LOAD                      (0x0928)
    137. 

  137. #define TIM2_CNT                       (0x092C)
    138. 

  138. #define TIM3_CTRL                      (0x0930)
    139. 

  139. #define TIM3_LOAD                      (0x0934)
    140. 

  140. #define TIM3_CNT                       (0x0938)
    141. 

  141. #define TIM4_CTRL                      (0x093C)
    142. 

  142. #define TIM4_LOAD                      (0x0940)
    143. 

  143. #define TIM4_CNT                       (0x0944)
    144. 

  144. #define TIM5_CTRL                      (0x0948)
    145. 

  145. #define TIM5_LOAD                      (0x094C)
    146. 

  146. #define TIM5_CNT                       (0x0950)
    147. 

  147. 

  148. /* Watchdog registers*/
    149. 

  149. #define WDOG_CTRL                      (0x0954)
    150. 

  150. #define WDOG_LOAD                      (0x0958)
    151. 

  151. #define WDOG_CNT                       (0x095C)
    152. 

  152. #define WDOG_STS                       (0x0960)
    153. 

  153. #define WDOG_FEED                      (0x0964)
    154. 

  154. 

  155. /* Interrupt registers*/
    156. 

  156. /* 64 bit interrupt sources registers ws ced. sme interupts were removed and new ones were added*/
    157. 

  157. /* Order was changed*/
    158. 

  158. #define FIQ_MASK                       (0x0400)
    159. 

  159. #define FIQ_MASK_L                     (0x0400)
    160. 

  160. #define FIQ_MASK_H                     (0x0404)
    161. 

  161. #define FIQ_MASK_SET                   (0x0408)
    162. 

  162. #define FIQ_MASK_SET_L                 (0x0408)
    163. 

  163. #define FIQ_MASK_SET_H                 (0x040C)
    164. 

  164. #define FIQ_MASK_CLR                   (0x0410)
    165. 

  165. #define FIQ_MASK_CLR_L                 (0x0410)
    166. 

  166. #define FIQ_MASK_CLR_H                 (0x0414)
    167. 

  167. #define IRQ_MASK                       (0x0418)
    168. 

  168. #define IRQ_MASK_L                     (0x0418)
    169. 

  169. #define IRQ_MASK_H                     (0x041C)
    170. 

  170. #define IRQ_MASK_SET                   (0x0420)
    171. 

  171. #define IRQ_MASK_SET_L                 (0x0420)
    172. 

  172. #define IRQ_MASK_SET_H                 (0x0424)
    173. 

  173. #define IRQ_MASK_CLR                   (0x0428)
    174. 

  174. #define IRQ_MASK_CLR_L                 (0x0428)
    175. 

  175. #define IRQ_MASK_CLR_H                 (0x042C)
    176. 

  176. #define ECPU_MASK                      (0x0448)
    177. 

  177. #define FIQ_STS_L                      (0x044C)
    178. 

  178. #define FIQ_STS_H                      (0x0450)
    179. 

  179. #define IRQ_STS_L                      (0x0454)
    180. 

  180. #define IRQ_STS_H                      (0x0458)
    181. 

  181. #define INT_STS_ND                     (0x0464)
    182. 

  182. #define INT_STS_RAW_L                  (0x0464)
    183. 

  183. #define INT_STS_RAW_H                  (0x0468)
    184. 

  184. #define INT_STS_CLR                    (0x04B4)
    185. 

  185. #define INT_STS_CLR_L                  (0x04B4)
    186. 

  186. #define INT_STS_CLR_H                  (0x04B8)
    187. 

  187. #define INT_ACK                        (0x046C)
    188. 

  188. #define INT_ACK_L                      (0x046C)
    189. 

  189. #define INT_ACK_H                      (0x0470)
    190. 

  190. #define INT_TRIG                       (0x0474)
    191. 

  191. #define INT_TRIG_L                     (0x0474)
    192. 

  192. #define INT_TRIG_H                     (0x0478)
    193. 

  193. #define HOST_STS_L                     (0x045C)
    194. 

  194. #define HOST_STS_H                     (0x0460)
    195. 

  195. #define HOST_MASK                      (0x0430)
    196. 

  196. #define HOST_MASK_L                    (0x0430)
    197. 

  197. #define HOST_MASK_H                    (0x0434)
    198. 

  198. #define HOST_MASK_SET                  (0x0438)
    199. 

  199. #define HOST_MASK_SET_L                (0x0438)
    200. 

  200. #define HOST_MASK_SET_H                (0x043C)
    201. 

  201. #define HOST_MASK_CLR                  (0x0440)
    202. 

  202. #define HOST_MASK_CLR_L                (0x0440)
    203. 

  203. #define HOST_MASK_CLR_H                (0x0444)
    204. 

  204. 

  205. /* GPIO Interrupts*/
    206. 

  206. #define GPIO_INT_STS                   (0x0484) /* 22 GPIOs*/
    207. 

  207. #define GPIO_INT_ACK                   (0x047C)
    208. 

  208. #define GPIO_INT_MASK                  (0x0480)
    209. 

  209. #define GPIO_POS_MASK                  (0x04BC) /* New*/
    210. 

  210. #define GPIO_NEG_MASK                  (0x04C0) /* New*/
    211. 

  211. 

  212. /* Protocol Interrupts*/
    213. 

  213. #define PROTO_INT_STS                  (0x0490) /* Add 2 PHY->MAC source interrupts*/
    214. 

  214. #define PROTO_INT_ACK                  (0x0488)
    215. 

  215. #define PROTO_INT_MASK                 (0x048C)
    216. 

  216. 

  217. /* Host Interrupts*/
    218. 

  218. #define HINT_MASK                      (0x0494)
    219. 

  219. #define HINT_MASK_SET                  (0x0498)
    220. 

  220. #define HINT_MASK_CLR                  (0x049C)
    221. 

  221. #define HINT_STS_ND_MASKED             (0x04A0)
    222. 

  222. #define HINT_STS_ND  		           (0x04B0) /*1150 spec calls this HINT_STS_RAW*/
    223. 

  223. #define HINT_STS_CLR                   (0x04A4)
    224. 

  224. #define HINT_ACK                       (0x04A8)
    225. 

  225. #define HINT_TRIG                      (0x04AC)
    226. 

  226. 

  227. /* Clock registers*/
    228. 

  228. #define CLK_CFG                        (0x0C00) /* new ARM clock bit */
    229. 

  229. #define CLK_CTRL                       (0x0C04) /* changed*/
    230. 

  230. #define BLK_RST                        (0x0C08) /* changed*/
    231. 

  231. #define CFG_USEC_STB                   (0x0C0C)
    232. 

  232. #define ARM_GATE_CLK_REG               (0x0C10) /* new*/
    233. 

  233. #define BUSY_STAT_REG                  (0x0C14) /* new*/
    234. 

  234. #define CFG_PHY_CLK88                  (0x0C18)
    235. 

  235. #define DYNAMIC_CLKGATE                (0x0C1C) /* new*/
    236. 

  236. 

  237. /* AES registers*/
    238. 

  238. /* Major changes to this module*/
    239. 

  239. #define AES_START                      (0x1400)
    240. 

  240. #define AES_CFG                        (0x1404)
    241. 

  241. #define AES_CTL                        (0x1408)
    242. 

  242. #define AES_STATUS                     (0x140C)
    243. 

  243. #define AES_LENGTH                     (0x1410)
    244. 

  244. #define AES_RD_ADDR                    (0x1414)
    245. 

  245. #define AES_RD_OFFSET                  (0x1418)
    246. 

  246. #define AES_WR_ADDR                    (0x141C)
    247. 

  247. #define AES_WR_OFFSET                  (0x1420)
    248. 

  248. #define AES_CUR_RD_PTR                 (0x1424)
    249. 

  249. #define AES_CUR_WR_PTR                 (0x1428)
    250. 

  250. #define AES_KEY_0                      (0x142C)
    251. 

  251. #define AES_KEY_1                      (0x1430)
    252. 

  252. #define AES_KEY_2                      (0x1434)
    253. 

  253. #define AES_KEY_3                      (0x1438)
    254. 

  254. #define AES_NONCE_0                    (0x143C)
    255. 

  255. #define AES_NONCE_1                    (0x1440)
    256. 

  256. #define AES_NONCE_2                    (0x1444)
    257. 

  257. #define AES_NONCE_3                    (0x1448)
    258. 

  258. #define AES_MIC_0                      (0x144C)
    259. 

  259. #define AES_MIC_1                      (0x1450)
    260. 

  260. #define AES_MIC_2                      (0x1454)
    261. 

  261. #define AES_MIC_3                      (0x1458)
    262. 

  262. #define AES_ASSO_DATA_0                (0x145C)
    263. 

  263. #define AES_ASSO_DATA_1                (0x1460)
    264. 

  264. #define AES_ASSO_DATA_2                (0x1464)
    265. 

  265. #define AES_ASSO_DATA_3                (0x1468)
    266. 

  266. #define AES_NUM_OF_ROUNDS              (0x146C)
    267. 

  267. #define AES_TX_QUEUE_PTR               (0x1470)
    268. 

  268. #define AES_RX_QUEUE_PTR               (0x1474)
    269. 

  269. #define AES_STACK                      (0x1478)
    270. 

  270. #define AES_INT_RAW                    (0x147C)
    271. 

  271. #define AES_INT_MASK                   (0x1480)
    272. 

  272. #define AES_INT_STS                    (0x1484)
    273. 

  273. 

  274. /* WEP registers*/
    275. 

  275. /* Order was changed*/
    276. 

  276. #define DEC_CTL                        (0x1800)
    277. 

  277. #define DEC_STATUS                     (0x1804)
    278. 

  278. #define DEC_MBLK                       (0x1808)
    279. 

  279. #define DEC_KEY_ADDR                   (0x180C)
    280. 

  280. #define DEC_KEY_LEN                    (0x1810)
    281. 

  281. #define DEC_ADDR_UPPER_BYTE            (0x1814) /* new*/
    282. 

  282. #define DEC_LEN                        (0x1818)
    283. 

  283. #define DEC_OFFSET                     (0x181C)
    284. 

  284. #define DEC_WR_MBLK                    (0x1820)
    285. 

  285. #define DEC_WR_OFFSET                  (0x1824)
    286. 

  286. 

  287. /* TKIP MICHAEL reisters*/
    288. 

  288. /* order changed*/
    289. 

  289. #define MCHL_START0                    (0x1C00)
    290. 

  290. #define MCHL_DMV_START_MBLK0           (0x1C04) /* Changed to 23:5 format*/
    291. 

  291. #define MCHL_DMV_CUR_MBLK0             (0x1C10)
    292. 

  292. #define MCHL_DMV_OFFSET0               (0x1C08)
    293. 

  293. #define MCHL_DMV_LENGTH0               (0x1C0C)
    294. 

  294. #define MCHL_DMV_CFG0                  (0x1C14)
    295. 

  295. #define MCHL_KEY_L0                    (0x1C18)
    296. 

  296. #define MCHL_KEY_H0                    (0x1C1C)
    297. 

  297. #define MCHL_MIC_L0                    (0x1C20)
    298. 

  298. #define MCHL_MIC_H0                    (0x1C24)
    299. 

  299. #define MCHL_START1                    (0x1C28)
    300. 

  300. #define MCHL_DMV_START_MBLK1           (0x1C2C) /* Changed to 23:5 format*/
    301. 

  301. #define MCHL_DMV_CUR_MBLK1             (0x1C38)
    302. 

  302. #define MCHL_DMV_OFFSET1               (0x1C30)
    303. 

  303. #define MCHL_DMV_LENGTH1               (0x1C34)
    304. 

  304. #define MCHL_DMV_CFG1                  (0x1C3C)
    305. 

  305. #define MCHL_KEY_L1                    (0x1C40)
    306. 

  306. #define MCHL_KEY_H1                    (0x1C44)
    307. 

  307. #define MCHL_MIC_L1                    (0x1C48)
    308. 

  308. #define MCHL_MIC_H1                    (0x1C4C)
    309. 

  309. #define MCHL_CTL0                      (0x1C50) /* new name MCHL_CTRL0*/
    310. 

  310. #define MCHL_CTL1                      (0x1C54) /* new name MCHL_CTRL1*/
    311. 

  311. #define MCHL_UPPER_BYTE_ADDR0          (0x1C58) /* new*/
    312. 

  312. #define MCHL_UPPER_BYTE_ADDR1          (0x1C5C) /* new*/
    313. 

  313. 

  314. /* SEEPROM registers*/
    315. 

  315. #define EE_CFG                         (0x0820)
    316. 

  316. #define EE_CTL                         (0x2000)
    317. 

  317. #define EE_DATA                        (0x2004)
    318. 

  318. #define EE_ADDR                        (0x2008)
    319. 

  319. 

  320. /* Parallel Host (PCI/CARDBUS/PCMCIA/GS*/
    321. 

  321. #define CIS_LADDR                      (0x2400)
    322. 

  322. #define HI_CTL                         (0x2404)
    323. 

  323. #define LPWR_MGT                       (0x2408)
    324. 

  324. /*#define PDR0                         (0x04ec)*/
    325. 

  325. /*#define PDR1                         (0x04f0)*/
    326. 

  326. /*#define PDR2                         (0x04f4)*/
    327. 

  327. /*#define PDR3                         (0x04f8)*/
    328. 

  328. /*#define BAR2_ENABLE                  (0x04fc)*/
    329. 

  329. /*#define BAR2_TRANS                   (0x0500)*/
    330. 

  330. /*#define BAR2_MASK                    (0x0504)*/
    331. 

  331. #define PCI_MEM_SIZE1                  (0x2428)
    332. 

  332. #define PCI_MEM_OFFSET1                (0x242C)
    333. 

  333. #define PCI_MEM_OFFSET2                (0x2430)
    334. 

  334. /*#define PCI_IO_SIZE1                 (0x0514)*/
    335. 

  335. /*#define PCI_IO_OFFSET1               (0x0518)*/
    336. 

  336. /*#define PCI_IO_OFFSET2               (0x051c)*/
    337. 

  337. /*#define PCI_CFG_OFFSET               (0x0520)*/
    338. 

  338. #define PCMCIA_CFG                     (0x2444)
    339. 

  339. #define PCMCIA_CTL                     (0x2448)
    340. 

  340. #define PCMCIA_CFG2                    (0x244C) /* new*/
    341. 

  341. #define SRAM_PAGE                      (0x2450)
    342. 

  342. #define CFG_PULLUPDN                   (0x2454)
    343. 

  343. #define CIS_MAP                        (0x2458) /* new*/
    344. 

  344. #define ENDIAN_CTRL                    (0x245C) /* new*/
    345. 

  345. #define GS_SLEEP_ACCESS                (0x2480) /* new*/
    346. 

  346. #define PCMCIA_PWR_DN                  (0x04C4) 
    347. 

  347. #define PCI_OUTPUT_DLY_CFG             (0x2464) /* new*/
    348. 

  348. 

  349. /* VLYNQ registers*/
    350. 

  350. /* VLYNQ2 was removed from hardware*/
    351. 

  351. #define VL1_REV_ID                     (0x8000) /* VLYNQ_REVISION*/
    352. 

  352. #define VL1_CTL                        (0x8004) /* VLYNQ_ CONTROL*/
    353. 

  353. #define VL1_STS                        (0x8008) /* VLYNQ_STATUS*/
    354. 

  354. #define VLYNQ_INTVEC                   (0x800C)
    355. 

  355. #define VL1_INT_STS                    (0x8010) /* VLYNQ_INTCR*/
    356. 

  356. #define VL1_INT_PEND                   (0x8014) /* VLYNQ_INTSR*/
    357. 

  357. #define VL1_INT_PTR                    (0x8018) /* VLYNQ_INTPTR*/
    358. 

  358. #define VL1_TX_ADDR                    (0x801C) /* VLYNQ_TX_MAP_ADDR*/
    359. 

  359. #define VL1_RX_SIZE1                   (0x8020) /* VLYNQ_RX_MAP_SIZE1*/
    360. 

  360. #define VL1_RX_OFF1                    (0x8024) /* VLYNQ_RX_MAP_OFFSET1*/
    361. 

  361. #define VL1_RX_SIZE2                   (0x8028) /* VLYNQ_RX_MAP_SIZE2*/
    362. 

  362. #define VL1_RX_OFF2                    (0x802C) /* VLYNQ_RX_MAP_OFFSET2*/
    363. 

  363. #define VL1_RX_SIZE3                   (0x8030) /* VLYNQ_RX_MAP_SIZE3*/
    364. 

  364. #define VL1_RX_OFF3                    (0x8034) /* VLYNQ_RX_MAP_OFFSET3*/
    365. 

  365. #define VL1_RX_SIZE4                   (0x8038) /* VLYNQ_RX_MAP_SIZE4*/
    366. 

  366. #define VL1_RX_OFF4                    (0x803C) /* VLYNQ_RX_MAP_OFFSET4*/
    367. 

  367. #define VL1_CHIP_VER                   (0x8040) /* VLYNQ_CHIP_VER*/
    368. 

  368. #define VLYNQ_AUTONEG                  (0x8044)
    369. 

  369. #define VLYNQ_MANNEG                   (0x8048)
    370. 

  370. #define VLYNQ_NEGSTAT                  (0x804C)
    371. 

  371. #define VLYNQ_ENDIAN                   (0x805C)
    372. 

  372. #define VL1_INT_VEC3_0                 (0x8060) /* VLYNQ_HW_INT3TO0_CFG*/
    373. 

  373. #define VL1_INT_VEC7_4                 (0x8064) /* VLYNQ_HW_INT7TO4_CFG*/
    374. 

  374. /* VLYNQ Remote configuration registers*/
    375. 

  375. #define VL1_REM_REV_ID                 (0x8080) /* VLYNQ_REM_REVISION*/
    376. 

  376. #define VL1_REM_CTL                    (0x8084) /* VLYNQ_REM_ CONTROL*/
    377. 

  377. #define VL1_REM_STS                    (0x8088) /* VLYNQ_REM_STATUS*/
    378. 

  378. #define VLYNQ_REM_INTVEC               (0x808C)
    379. 

  379. #define VL1_REM_INT_STS                (0x8090) /* VLYNQ_REM_INTCR*/
    380. 

  380. #define VL1_REM_INT_PEND               (0x8094) /* VLYNQ_REM_INTSR*/
    381. 

  381. #define VL1_REM_INT_PTR                (0x8098) /* VLYNQ_REM_INTPTR*/
    382. 

  382. #define VL1_REM_TX_ADDR                (0x809C) /* VLYNQ_REM_TX_MAP_ADDR*/
    383. 

  383. #define VL1_REM_RX_SIZE1               (0x80A0) /* VLYNQ_REM_RX_MAP_SIZE1*/
    384. 

  384. #define VL1_REM_RX_OFF1                (0x80A4) /* VLYNQ_REM_RX_MAP_OFFSET1*/
    385. 

  385. #define VL1_REM_RX_SIZE2               (0x80A8) /* VLYNQ_REM_RX_MAP_SIZE2*/
    386. 

  386. #define VL1_REM_RX_OFF2                (0x80AC) /* VLYNQ_REM_RX_MAP_OFFSET2*/
    387. 

  387. #define VL1_REM_RX_SIZE3               (0x80B0) /* VLYNQ_REM_RX_MAP_SIZE3*/
    388. 

  388. #define VL1_REM_RX_OFF3                (0x80B4) /* VLYNQ_REM_RX_MAP_OFFSET3*/
    389. 

  389. #define VL1_REM_RX_SIZE4               (0x80B8) /* VLYNQ_REM_RX_MAP_SIZE4*/
    390. 

  390. #define VL1_REM_RX_OFF4                (0x80BC) /* VLYNQ_REM_RX_MAP_OFFSET4*/
    391. 

  391. #define VL1_REM_CHIP_VER               (0x80C0) /* VLYNQ_REM_CHIP_VER*/
    392. 

  392. #define VLYNQ_REM_AUTONEG              (0x80C4)
    393. 

  393. #define VLYNQ_REM_MANNEG               (0x80C8)
    394. 

  394. #define VLYNQ_REM_NEGSTAT              (0x80CC)
    395. 

  395. #define VLYNQ_REM_ENDIAN               (0x80DC)
    396. 

  396. #define VL1_REM_INT_VEC3_0             (0x80E0) /* VLYNQ_REM_HW_INT3TO0_CFG*/
    397. 

  397. #define VL1_REM_INT_VEC7_4             (0x80E4) /* VLYNQ_REM_HW_INT7TO4_CFG*/
    398. 

  398. 

  399. /* PCIIF*/
    400. 

  400. /**/
    401. 

  401. #define PCI_ID_REG                     (0x8400)
    402. 

  402. #define PCI_STATUS_SET_REG             (0x8410)
    403. 

  403. #define PCI_STATUS_CLR_REG             (0x8414)
    404. 

  404. #define PCI_HIMASK_SET_REG             (0x8420)
    405. 

  405. #define PCI_HIMASK_CLR_REG             (0x8424)
    406. 

  406. #define PCI_AMASK_SET_REG              (0x8430)
    407. 

  407. #define PCI_AMASK_CLR_REG              (0x8434)
    408. 

  408. #define PCI_CLKRUN_REG                 (0x8438)
    409. 

  409. #define PCI_BE_VENDOR_ID_REG           (0x8500)
    410. 

  410. #define PCI_BE_COMMAND_REG             (0x8504)
    411. 

  411. #define PCI_BE_REVISION_REG            (0x8508)
    412. 

  412. #define PCI_BE_CL_SIZE_REG             (0x850C)
    413. 

  413. #define PCI_BE_BAR0_MASK_REG           (0x8510)
    414. 

  414. #define PCI_BE_BAR1_MASK_REG           (0x8514)
    415. 

  415. #define PCI_BE_BAR2_MASK_REG           (0x8518)
    416. 

  416. #define PCI_BE_BAR3_MASK_REG           (0x851C)
    417. 

  417. #define PCI_BE_CIS_PTR_REG             (0x8528)
    418. 

  418. #define PCI_BE_SUBSYS_ID_REG           (0x852C)
    419. 

  419. #define PCI_BE_CAP_PTR_REG             (0x8534)
    420. 

  420. #define PCI_BE_INTR_LINE_REG           (0x853C)
    421. 

  421. #define PCI_BE_PM_CAP_REG              (0x8540)
    422. 

  422. #define PCI_BE_PM_CTRL_REG             (0x8544)
    423. 

  423. #define PCI_BE_PM_D0_CTRL_REG          (0x8560)
    424. 

  424. #define PCI_BE_PM_D1_CTRL_REG          (0x8564)
    425. 

  425. #define PCI_BE_PM_D2_CTRL_REG          (0x8568)
    426. 

  426. #define PCI_BE_PM_D3_CTRL_REG          (0x856C)
    427. 

  427. #define PCI_BE_SLV_CFG_REG             (0x8580)
    428. 

  428. #define PCI_BE_ARB_CTRL_REG            (0x8584)
    429. 

  429.                                        
    430. 

  430. #define FER                            (0x85A0) /* PCI_BE_STSCHG_FE_REG*/
    431. 

  431. #define FEMR                           (0x85A4) /* PCI_BE_STSCHG_FEM_REG*/
    432. 

  432. #define FPSR                           (0x85A8) /* PCI_BE_STSCHG_FPS_REG*/
    433. 

  433. #define FFER                           (0x85AC) /* PCI_BE_STSCHG_FFE_REG*/
    434. 

  434. 

  435. #define PCI_BE_BAR0_TRANS_REG          (0x85C0)
    436. 

  436. #define PCI_BE_BAR1_TRANS_REG          (0x85C4)
    437. 

  437. #define PCI_BE_BAR2_TRANS_REG          (0x85C8)
    438. 

  438. #define PCI_BE_BAR3_TRANS_REG          (0x85CC)
    439. 

  439. #define PCI_BE_BAR4_TRANS_REG          (0x85D0)
    440. 

  440. #define PCI_BE_BAR5_TRANS_REG          (0x85D4)
    441. 

  441. #define PCI_BE_BAR0_REG                (0x85E0)
    442. 

  442. #define PCI_BE_BAR1_REG                (0x85E4)
    443. 

  443. #define PCI_BE_BAR2_REG                (0x85E8)
    444. 

  444. #define PCI_BE_BAR3_REG                (0x85EC)
    445. 

  445. 

  446. #define PCI_PROXY_DATA                 (0x8700)
    447. 

  447. #define PCI_PROXY_ADDR                 (0x8704)
    448. 

  448. #define PCI_PROXY_CMD                  (0x8708)
    449. 

  449. #define PCI_CONTROL                    (0x8710)
    450. 

  450. 

  451. /*#define CPC_REGION                   (f0100)*/
    452. 

  452. /*#define VLYNQ1_BASE                  (f00a0)*/
    453. 

  453. /*#define VLYNQ2_BASE                  (f00b0)*/
    454. 

  454. /*#define SCR_IADDR1                   (f00c0)*/
    455. 

  455. /*#define SCR_IDATA1                   (f00c0)*/
    456. 

  456. /*#define SCR_IADDR2                   (f00c0)*/
    457. 

  457. /*#define SCR_IDATA2                   (f00c0)*/
    458. 

  458. 

  459. /* SDIO/WSPI*/
    460. 

  460. #define	CCCR_1                         (002800)
    461. 

  461. #define	CCCR_2                         (002804)
    462. 

  462. #define	CCCR_3                         (002808)
    463. 

  463. #define	FUN_BASE_REG_1                 (00280C)
    464. 

  464. #define	FUN_BASE_REG_2                 (002810)
    465. 

  465. #define	FUN_BASE_REG_3                 (002814)
    466. 

  466. #define	ADDR_MAP_SIZE_1                (002818)
    467. 

  467. #define	ADDR_MAP_SIZE_2                (002820)
    468. 

  468. #define	ADDR_MAP_SIZE_3                (002828)
    469. 

  469. #define	ADDR_MAP_OFFSET_1              (00281C)
    470. 

  470. #define	ADDR_MAP_OFFSET_2              (002824)
    471. 

  471. #define	ADDR_MAP_OFFSET_3              (00282C)
    472. 

  472. #define	ADDR_MAP_OFFSET_4              (002830)
    473. 

  473. #define	CIS_OFFSET                     (002834)
    474. 

  474. #define	CSA_OFFSET                     (002838)
    475. 

  475. #define	DEBUG_REG_1                    (002840)
    476. 

  476. #define	DEBUG_REG_2                    (00283C)
    477. 

  477. #define	INTR_MASK                      (002844)
    478. 

  478. #define	STATUS_REG                     (002848)
    479. 

  479. #define	WR_ERR_LENGTH                  (00284C)
    480. 

  480. #define	WR_ERR_ADDR                    (002850)
    481. 

  481. #define	OCR                            (002858)
    482. 

  482. 

  483. /* UART*/
    484. 

  484. /* TODO - fill in registers*/
    485. 

  485. 

  486. /* USB1.1 registers*/
    487. 

  487. /**/
    488. 

  488. #define USB_STS_CLR                    (0x4000)
    489. 

  489. #define USB_STS_ND                     (0x4004)
    490. 

  490. #define USB_INT_ACK                    (0x4008)
    491. 

  491. #define USB_MASK                       (0x400c)
    492. 

  492. #define USB_MASK_SET                   (0x4010)
    493. 

  493. #define USB_MASK_CLR                   (0x4014)
    494. 

  494. #define USB_WU                         (0x4018)
    495. 

  495. #define USB_EP0_OUT_PTR                (0x401c)
    496. 

  496. #define USB_EP0_OUT_VLD                (0x4020)
    497. 

  497. #define USB_EP0_OUT_LEN                (0x4024)
    498. 

  498. #define USB_EP0_IN_PTR                 (0x4028)
    499. 

  499. #define USB_EP0_IN_VLD                 (0x402c)
    500. 

  500. #define USB_EP0_IN_LEN                 (0x4030)
    501. 

  501. #define USB_EP1_CFG                    (0x4034)
    502. 

  502. #define USB_EP1_OUT_INT_CFG            (0x4038)
    503. 

  503. #define USB_EP1_OUT_PTR                (0x403c)
    504. 

  504. #define USB_EP1_OUT_VLD                (0x4040)
    505. 

  505. #define USB_EP1_OUT_CUR_MBLK           (0x4044)
    506. 

  506. #define USB_EP1_OUT_LEN                (0x4048)
    507. 

  507. #define USB_EP1_IN_START_MBLK          (0x404c)
    508. 

  508. #define USB_EP1_IN_LAST_MBLK           (0x4050)
    509. 

  509. #define USB_EP1_IN_VLD                 (0x4054)
    510. 

  510. 

  511. #define USB_EP2_PTR                    (0x405c)
    512. 

  512. #define USB_EP2_VLD                    (0x4060)
    513. 

  513. #define USB_EP2_LEN                    (0x4064)
    514. 

  514. #define USB_EP3_OUT_PTR0               (0x4068)
    515. 

  515. #define USB_EP3_OUT_VLD0               (0x406c)
    516. 

  516. #define USB_EP3_OUT_LEN0               (0x4070)
    517. 

  517. #define USB_EP3_OUT_PTR1               (0x4074)
    518. 

  518. #define USB_EP3_OUT_VLD1               (0x4078)
    519. 

  519. #define USB_EP3_OUT_LEN1               (0x407c)
    520. 

  520. #define USB_EP3_IN_PTR0                (0x4080)
    521. 

  521. #define USB_EP3_IN_VLD0                (0x4084)
    522. 

  522. #define USB_EP3_IN_LEN0                (0x4088)
    523. 

  523. #define USB_EP3_IN_PTR1                (0x408c)
    524. 

  524. #define USB_EP3_IN_VLD1                (0x4090)
    525. 

  525. #define USB_EP3_IN_LEN1                (0x4094)
    526. 

  526. #define USB_EP1_OUT_END_MBLK           (0x4098)
    527. 

  527. #define USB_EP0_OUT_SETUP              (0x409c)
    528. 

  528. #define USB_EP0_STALL                  (0x40a0)
    529. 

  529. #define USB_EP1_IN_OFFSET              (0x40a4)
    530. 

  530. 

  531. /* Device Configuration registers*/
    532. 

  532. #define SOR_CFG                        (0x0800)
    533. 

  533. #define ECPU_CTRL                      (0x0804)
    534. 

  534. #define HI_CFG                         (0x0808)
    535. 

  535. #define EE_START                       (0x080C)
    536. 

  536. 

  537. /* IO Control registers*/
    538. 

  538. #define SERIAL_HOST_IOCFG0             (0x0894) /* new*/
    539. 

  539. #define SERIAL_HOST_IOCFG1             (0x0898) /* new*/
    540. 

  540. #define SERIAL_HOST_IOCFG2             (0x089C) /* new*/
    541. 

  541. #define SERIAL_HOST_IOCFG3             (0x08A0) /* new*/
    542. 

  542. #define GPIO_IOCFG0                    (0x08F4) /* new*/
    543. 

  543. #define GPIO_IOCFG1                    (0x08F8) /* new*/
    544. 

  544. #define GPIO_IOCFG2                    (0x08FC) /* new*/
    545. 

  545. #define GPIO_IOCFG3                    (0x0900) /* new*/
    546. 

  546. #define CHIP_ID_B                      (0x5674) /* new*/
    547. 

  547. #define CHIP_ID                        CHIP_ID_B/* Leave for TNETW compatability*/
    548. 

  548. #define CHIP_ID_1251_PG10	           (0x7010101)
    549. 

  549. #define CHIP_ID_1251_PG11	           (0x7020101)
    550. 

  550. #define CHIP_ID_1251_PG12	           (0x7030101)
    551. 

  551. 

  552. #define SYSTEM                         (0x0810)
    553. 

  553. #define PCI_ARB_CFG                    (0x0814)
    554. 

  554. #define BOOT_IRAM_CFG                  (0x0818)
    555. 

  555. #define ENABLE                         (0x5450)
    556. 

  556. #define MBLK_CFG                       (0x5460)
    557. 

  557. #define RS232_BITINTERVAL              (0x0824)
    558. 

  558. #define TEST_PORT                      (0x096C)
    559. 

  559. #define DEBUG_PORT                     (0x0970)
    560. 

  560. 

  561. /* GPIO registers*/
    562. 

  562. #define GPIO_OE                        (0x082C) /* 22 GPIOs*/
    563. 

  563. #define GPIO_OUT                       (0x0834)
    564. 

  564. #define GPIO_IN                        (0x0830)
    565. 

  565. #define GPO_CFG                        (0x083C)
    566. 

  566. #define PWRDN_BUS_L                    (0x0844)
    567. 

  567. #define PWRDN_BUS_H                    (0x0848)
    568. 

  568. #define DIE_ID_L                       (0x088C)
    569. 

  569. #define DIE_ID_H                       (0x0890)
    570. 

  570. 

  571. /* Power Management registers*/
    572. 

  572. /* */
    573. 

  573. #define ELP_START                      (0x5800)
    574. 

  574. #define ELP_CFG_MODE                   (0x5804)
    575. 

  575. #define ELP_CMD                        (0x5808)
    576. 

  576. #define PLL_CAL_TIME                   (0x5810)
    577. 

  577. #define CLK_REQ_TIME                   (0x5814)
    578. 

  578. #define CLK_BUF_TIME                   (0x5818)
    579. 

  579. 

  580. #define CFG_PLL_SYNC_CNT               (0x5820) /* Points to the CFG_PLL_SYNC_CNT_xx registers set*/
    581. 

  581. #define CFG_PLL_SYNC_CNT_I             (0x5820)
    582. 

  582. #define CFG_PLL_SYNC_CNT_II            (0x5824)
    583. 

  583. #define CFG_PLL_SYNC_CNT_III           (0x5828)
    584. 

  584. 

  585. #define CFG_ELP_SLEEP_CNT              (0x5830) /* Points to the CFG_ELP_SLEEP_CNT_xx registers set*/
    586. 

  586. #define CFG_ELP_SLEEP_CNT_I            (0x5830)
    587. 

  587. #define CFG_ELP_SLEEP_CNT_II           (0x5834)
    588. 

  588. #define CFG_ELP_SLEEP_CNT_III          (0x5838)
    589. 

  589. #define CFG_ELP_SLEEP_CNT_IV           (0x583c)
    590. 

  590. 

  591. #define ELP_SLEEP_CNT                  (0x5840) /* Points to the ELP_SLEEP_CNT_xx registers set*/
    592. 

  592. #define ELP_SLEEP_CNT_I                (0x5840)
    593. 

  593. #define ELP_SLEEP_CNT_II               (0x5844)
    594. 

  594. #define ELP_SLEEP_CNT_III              (0x5848)
    595. 

  595. #define ELP_SLEEP_CNT_IV               (0x584c)
    596. 

  596. 

  597. #define ELP_WAKE_UP_STS                (0x5850)
    598. 

  598. #define CFG_SLP_CLK_SEL                (0x5860)
    599. 

  599. #define CFG_SLP_CLK_EN                 (0x5870)
    600. 

  600. 

  601. #define CFG_WAKE_UP_EN_I               (0x5880)
    602. 

  602. #define CFG_WAKE_UP_EN_II              (0x5884)
    603. 

  603. #define CFG_WAKE_UP_EN_III             (0x5888)
    604. 

  604. 

  605. #define CFG_ELP_PWRDN_I                (0x5890)
    606. 

  606. #define CFG_ELP_PWRDN_II               (0x5894)
    607. 

  607. #define CFG_ELP_PWRDN_III              (0x5898)
    608. 

  608. 

  609. #define CFG_POWER_DOWN_I               (0x58a0)
    610. 

  610. #define CFG_POWER_DOWN_II              (0x58a4)
    611. 

  611. #define CFG_POWER_DOWN_III             (0x58a8)
    612. 

  612. 

  613. #define CFG_BUCK_TESTMODE_I            (0x58b0)
    614. 

  614. #define CFG_BUCK_TESTMODE_II           (0x58b4)
    615. 

  615. 

  616. #define POWER_STATUS_I                 (0x58C0)
    617. 

  617. #define POWER_STATUS_II                (0x58C4)
    618. 

  618. 

  619. #define DIGLDO_BIAS_PROG_I             (0x58d0)
    620. 

  620. #define DIGLDO_BIAS_PROG_II            (0x58d4)
    621. 

  621. 

  622. #define LDO2P8_BIAS_PROG_I             (0x58e0)
    623. 

  623. #define LDO2P8_BIAS_PROG_II            (0x58e4)
    624. 

  624. 

  625. #define ADCLDO_BIAS_PROG               (0x58f0)
    626. 

  626. 

  627. #define REFSYS_PROG_I                  (0x5910)
    628. 

  628. #define REFSYS_PROG_II                 (0x5914)
    629. 

  629. 

  630. #define PM_TEST_I                      (0x5920)
    631. 

  631. #define PM_TEST_II                     (0x5924)
    632. 

  632. 

  633. #define POR_PROG                       (0x5930)
    634. 

  634. 

  635. #define TEST_PIN_DIR_I                 (0x5940)
    636. 

  636. #define TEST_PIN_DIR_II                (0x5944)
    637. 

  637. 

  638. #define PROC_CTL                       (0x5950)
    639. 

  639. 

  640. #define ADC_REF_WAKEUP_I               (0x5960)
    641. 

  641. #define ADC_REF_WAKEUP_II              (0x5964)
    642. 

  642. #define ADC_REF_WAKEUP_III             (0x5968)
    643. 

  643. #define ADC_REF_WAKEUP_IV              (0x596C)
    644. 

  644. 

  645. #define VREG_WAKEUP_I                  (0x5970)
    646. 

  646. #define VREG_WAKEUP_II                 (0x5974)
    647. 

  647. #define VREG_WAKEUP_III                (0x5978)
    648. 

  648. #define VREG_WAKEUP_IV                 (0x597C)
    649. 

  649. 

  650. #define PLL_WAKEUP_I                   (0x5980)
    651. 

  651. #define PLL_WAKEUP_II                  (0x5984)
    652. 

  652. #define PLL_WAKEUP_III                 (0x5988)
    653. 

  653. #define PLL_WAKEUP_IV                  (0x598C)
    654. 

  654. 

  655. #define XTALOSC_WAKEUP_I               (0x5990)
    656. 

  656. #define XTALOSC_WAKEUP_II              (0x5994)
    657. 

  657. #define XTALOSC_WAKEUP_III             (0x5998)
    658. 

  658. #define XTALOSC_WAKEUP_IV              (0x599C)
    659. 

  659. 

  660. /* ----------*/
    661. 

  661. 

  662. #define POWER_MGMT2                    (0x0840)
    663. 

  663. #define POWER_MGMT                     (0x5098)
    664. 

  664. #define MAC_HW_DOZE                    (0x090c)
    665. 

  665. #define ECPU_SLEEP                     (0x0840)
    666. 

  666. #define DOZE_CFG                       (0x54bc)
    667. 

  667. #define DOZE2_CFG                      (0x081c)
    668. 

  668. #define WAKEUP_CFG                     (0x54c0)
    669. 

  669. #define WAKEUP_TIME_L                  (0x54c8)
    670. 

  670. #define WAKEUP_TIME_H                  (0x54c4)
    671. 

  671. 

  672. /**/
    673. 

  673. 

  674. /*#define CPU_WAIT_CFG                 (f0020)*/
    675. 

  675. /*#define CFG_QOS_ACM                  (f0046)*/
    676. 

  676. 

  677. /* Scratch Pad registers*/
    678. 

  678. #define SCR_PAD0                       (0x5608)
    679. 

  679. #define SCR_PAD1                       (0x560C)
    680. 

  680. #define SCR_PAD2                       (0x5610)
    681. 

  681. #define SCR_PAD3                       (0x5614)
    682. 

  682. #define SCR_PAD4                       (0x5618)
    683. 

  683. #define SCR_PAD4_SET                   (0x561C)
    684. 

  684. #define SCR_PAD4_CLR                   (0x5620)
    685. 

  685. #define SCR_PAD5                       (0x5624)
    686. 

  686. #define SCR_PAD5_SET                   (0x5628)
    687. 

  687. #define SCR_PAD5_CLR                   (0x562C)
    688. 

  688. #define SCR_PAD6                       (0x5630)
    689. 

  689. #define SCR_PAD7                       (0x5634)
    690. 

  690. #define SCR_PAD8                       (0x5638)
    691. 

  691. #define SCR_PAD9                       (0x563C)
    692. 

  692. 

  693. /* Spare registers*/
    694. 

  694. #define SPARE_A1                       (0x0994)
    695. 

  695. #define SPARE_A2                       (0x0998)
    696. 

  696. #define SPARE_A3                       (0x099C)
    697. 

  697. #define SPARE_A4                       (0x09A0)
    698. 

  698. #define SPARE_A5                       (0x09A4)
    699. 

  699. #define SPARE_A6                       (0x09A8)
    700. 

  700. #define SPARE_A7                       (0x09AC)
    701. 

  701. #define SPARE_A8                       (0x09B0)
    702. 

  702. #define SPARE_B1                       (0x5420)
    703. 

  703. #define SPARE_B2                       (0x5424)
    704. 

  704. #define SPARE_B3                       (0x5428)
    705. 

  705. #define SPARE_B4                       (0x542C)
    706. 

  706. #define SPARE_B5                       (0x5430)
    707. 

  707. #define SPARE_B6                       (0x5434)
    708. 

  708. #define SPARE_B7                       (0x5438)
    709. 

  709. #define SPARE_B8                       (0x543C)
    710. 

  710. 

  711. /* RMAC registers (Raleigh MAC)*/
    712. 

  712. 

  713. /* Station registers*/
    714. 

  714. #define DEV_MODE                       (0x5464)
    715. 

  715. #define STA_ADDR_L                     (0x546C)
    716. 

  716. #define STA_ADDR_H                     (0x5470)
    717. 

  717. #define BSSID_L                        (0x5474)
    718. 

  718. #define BSSID_H                        (0x5478)
    719. 

  719. #define AID_CFG                        (0x547C)
    720. 

  720. #define BASIC_RATE_CFG                 (0x4C6C)
    721. 

  721. #define BASIC_RATE_TX_CFG              (0x55F0)
    722. 

  722. 

  723. /* Protocol timers registers*/
    724. 

  724. #define IFS_CFG0                       (0x5494)
    725. 

  725. #define IFS_CFG1                       (0x5498)
    726. 

  726. #define TIMEOUT_CFG                    (0x549C)
    727. 

  727. #define CONT_WIND_CFG                  (0x54A0)
    728. 

  728. #define BCN_INT_CFG                    (0x54A4)
    729. 

  729. #define RETRY_CFG                      (0x54A8)
    730. 

  730. #define DELAY_CFG                      (0x54B0)
    731. 

  731. 

  732. /* Hardware Override registers*/
    733. 

  733. #define CCA_CFG                        (0x54CC)
    734. 

  734. #define CCA_FILTER_CFG                 (0x5480)
    735. 

  735. #define RADIO_PLL_CFG                  (0x555C)
    736. 

  736. #define CCA_MON                        (0x54D0)
    737. 

  737. #define TX_FRM_CTL                     (0x54D4)
    738. 

  738. #define CONT_TX_EN                     (0x50EC)
    739. 

  739. #define PHY_STANDBY_EN                 (0x5668)
    740. 

  740. 

  741. /* Transmit Setup registers*/
    742. 

  742. #define TX_PING_PONG                   (0x5090)
    743. 

  743. #define TX_CFG0                        (0x5000)
    744. 

  744. #define TX_CFG1                        (0x5004)
    745. 

  745. #define TX_CFG2                        (0x5008)
    746. 

  746. #define MAX_LIFETIME                   (0x50FC)
    747. 

  747. #define TX_PANG_SEL                    (0x50E0)
    748. 

  748. #define TX_PANG0                       (0x50A0)
    749. 

  749. #define TX_PING0                       (0x5010)
    750. 

  750. #define TX_PONG0                       (0x5050)
    751. 

  751. #define TX_PANG1                       (0x50A4)
    752. 

  752. #define TX_PING1                       (0x5014)
    753. 

  753. #define TX_PONG1                       (0x5054)
    754. 

  754. #define TX_PANG2                       (0x50A8)
    755. 

  755. #define TX_PING2                       (0x5018)
    756. 

  756. #define TX_PONG2                       (0x5058)
    757. 

  757. #define TX_PANG3                       (0x50AC)
    758. 

  758. #define TX_PING3                       (0x501C)
    759. 

  759. #define TX_PONG3                       (0x505C)
    760. 

  760. #define TX_PANG4                       (0x50B0)
    761. 

  761. #define TX_PING4                       (0x5020)
    762. 

  762. #define TX_PONG4                       (0x5060)
    763. 

  763. #define TX_PANG5                       (0x50B4)
    764. 

  764. #define TX_PING5                       (0x5024)
    765. 

  765. #define TX_PONG5                       (0x5064)
    766. 

  766. #define TX_PANG6                       (0x50B8)
    767. 

  767. #define TX_PING6                       (0x5028)
    768. 

  768. #define TX_PONG6                       (0x5068)
    769. 

  769. #define TX_PANG7                       (0x50BC)
    770. 

  770. #define TX_PING7                       (0x502C)
    771. 

  771. #define TX_PONG7                       (0x506C)
    772. 

  772. #define TX_PANG8                       (0x50C0)
    773. 

  773. #define TX_PING8                       (0x5030)
    774. 

  774. #define TX_PONG8                       (0x5070)
    775. 

  775. #define TX_PANG9                       (0x50C4)
    776. 

  776. #define TX_PING9                       (0x5034)
    777. 

  777. #define TX_PONG9                       (0x5074)
    778. 

  778. #define TX_PANG10                      (0x50C8)
    779. 

  779. #define TX_PING10                      (0x5038)
    780. 

  780. #define TX_PONG10                      (0x5078)
    781. 

  781. #define TX_PANG11                      (0x50CC)
    782. 

  782. #define TX_PING11                      (0x503C)
    783. 

  783. #define TX_PONG11                      (0x507C)
    784. 

  784. 

  785. /* Transmit Status registers*/
    786. 

  786. #define TX_STATUS                      (0x509C)
    787. 

  787. #define TX_PANG_EXCH                   (0x50D0)
    788. 

  788. #define TX_PING_EXCH                   (0x5040)
    789. 

  789. #define TX_PONG_EXCH                   (0x5080)
    790. 

  790. #define TX_PANG_ATT                    (0x50D4)
    791. 

  791. #define TX_PING_ATT                    (0x5044)
    792. 

  792. #define TX_PONG_ATT                    (0x5084)
    793. 

  793. #define TX_PANG_TIMESTAMP              (0x50DC)
    794. 

  794. #define TX_PING_TIMESTAMP              (0x504C)
    795. 

  795. #define TX_PONG_TIMESTAMP              (0x508C)
    796. 

  796. 

  797. /* Transmit State registers*/
    798. 

  798. #define TX_STATE                       (0x5094)
    799. 

  799. #define TX_PANG_OVRD_CFG               (0x50D8)
    800. 

  800. #define TX_PING_OVRD_CFG               (0x5048)
    801. 

  801. #define TX_PONG_OVRD_CFG               (0x5088)
    802. 

  802. #define TX_HOLD_CFG                    (0x54D8)
    803. 

  803. #define TSF_ADJ_CFG1                   (0x54DC)
    804. 

  804. #define TSF_ADJ_CFG2                   (0x54E0)
    805. 

  805. #define TSF_ADJ_CFG3                   (0x54E4)
    806. 

  806. #define TSF_ADJ_CFG4                   (0x54E8)
    807. 

  807. #define CFG_OFDM_TIMES0                (0x5648)
    808. 

  808. #define CFG_OFDM_TIMES1                (0x564C)
    809. 

  809. 

  810. /* Beacon/Probe Response registers*/
    811. 

  811. #define PRB_ADDR                       (0x54EC)
    812. 

  812. #define PRB_LENGTH                     (0x54F0)
    813. 

  813. #define BCN_ADDR                       (0x54F4)
    814. 

  814. #define BCN_LENGTH                     (0x54F8)
    815. 

  815. #define TIM_VALID0                     (0x54FC)
    816. 

  816. #define TIM_ADDR0                      (0x5500)
    817. 

  817. #define TIM_LENGTH0                    (0x5504)
    818. 

  818. #define TIM_VALID1                     (0x5654)
    819. 

  819. #define TIM_ADDR1                      (0x5658)
    820. 

  820. #define TIM_LENGTH1                    (0x565C)
    821. 

  821. #define TIM_SELECT                     (0x5660)
    822. 

  822. #define TSF_CFG                        (0x5508)
    823. 

  823. 

  824. /* Other Hardware Generated Frames regi*/
    825. 

  825. #define CTL_FRM_CFG                    (0x550C)
    826. 

  826. #define MGMT_FRM_CFG                   (0x5510)
    827. 

  827. #define CFG_ANT_SEL                    (0x5664)
    828. 

  828. #define RMAC_ADDR_BASE                 (0x5680) /* new*/
    829. 

  829. 

  830. /* Protocol Interface Read Write Interf*/
    831. 

  831. #define TXSIFS_TIMER                   (0x4C00)
    832. 

  832. #define TXPIFS_TIMER                   (0x4C04)
    833. 

  833. #define TXDIFS_TIMER                   (0x4C08)
    834. 

  834. #define SLOT_TIMER                     (0x4C0C)
    835. 

  835. #define BACKOFF_TIMER                  (0x4C10)
    836. 

  836. #define BCN_PSP_TIMER                  (0x4C14)
    837. 

  837. #define NAV                            (0x4C18)
    838. 

  838. #define TSF_L                          (0x4C1C)
    839. 

  839. #define TSF_H                          (0x4C20)
    840. 

  840. #define TSF_PREV_L                     (0x4CC4) /* new */
    841. 

  841. #define TSF_PREV_H                     (0x4CC8) /* new */
    842. 

  842. #define TOUT_TIMER                     (0x4C2C)
    843. 

  843. #define NEXT_TBTT_L                    (0x4C30)
    844. 

  844. #define NEXT_TBTT_H                    (0x4C34)
    845. 

  845. #define DTIM_CNT                       (0x4C38)
    846. 

  846. #define CONT_WIND                      (0x4C3C)
    847. 

  847. #define PRSP_REQ                       (0x4C40)
    848. 

  848. #define PRSP_DA_L                      (0x4C44)
    849. 

  849. #define PRSP_DA_H                      (0x4C48)
    850. 

  850. #define PRSP_RETRY                     (0x4C4C)
    851. 

  851. #define PSPOLL_REQ                     (0x4C50)
    852. 

  852. #define NEXT_SEQ_NUM                   (0x4C54)
    853. 

  853. #define PRSP_SEQ_NUM                   (0x4C58)
    854. 

  854. #define BCN_SEQ_NUM                    (0x4C5C)
    855. 

  855. #define MED_USAGE                      (0x4C24)
    856. 

  856. #define MED_USAGE_TM                   (0x4C28)
    857. 

  857. #define PRB_DLY                        (0x4C60)
    858. 

  858. #define STA_SRC                        (0x4C64)
    859. 

  859. #define STA_LRC                        (0x4C68)
    860. 

  860. #define CFG_ACM                        (0x4C70)
    861. 

  861. #define RAND_NUMB                      (0x4C6C)
    862. 

  862. #define CFG_ACK_CTS_DOT11A             (0x4C74)
    863. 

  863. #define CFG_ACK_CTS_DOT11B             (0x4C78)
    864. 

  864. #define ACM_IFS_CFG0                   (0x4C7C)
    865. 

  865. #define ACM_IFS_CFG1                   (0x4C80)
    866. 

  866. #define ACM_IFS_CFG2                   (0x4C84)
    867. 

  867. #define ACM_IFS_CFG3                   (0x4C88)
    868. 

  868. #define ACK_CTS_FRM_CFG                (0x4C8C)
    869. 

  869. #define CFG_RX_TSTMP_DLY0              (0x4C90)
    870. 

  870. #define CFG_RX_TSTMP_DLY1              (0x4C94)
    871. 

  871. #define CFG_RX_TSTMP_DLY2              (0x4C98)
    872. 

  872. #define CFG_RX_TSTMP_DLY3              (0x4C9C)
    873. 

  873. #define CCA_BUSY                       (0x4CA0)
    874. 

  874. #define CCA_BUSY_CLR                   (0x4CA4)
    875. 

  875. #define CCA_IDLE                       (0x4CA8)
    876. 

  876. #define CCA_IDLE_CLR                   (0x4CAC)
    877. 

  877. 

  878. /* Receive Manager registers*/
    879. 

  879. #define RX_HEAD_PTR                    (0x567C) /* new*/
    880. 

  880. #define RX_TAIL_PTR                    (0x4898) /* new*/
    881. 

  881. #define RX_CURR_PTR                    (0x5678) /* new*/
    882. 

  882. #define RX_RESET                       (0x4800)
    883. 

  883. #define RX_MODMODE                     (0x4838) /* new*/
    884. 

  884. #define MAC_HEADER_BYTECNT             (0x4890)
    885. 

  885. #define RX_MAC_BYTECNT_INT             (0x489C)
    886. 

  886. #define MAC_HEADER_WORD0               (0x4868)
    887. 

  887. #define MAC_HEADER_WORD1               (0x486C)
    888. 

  888. #define MAC_HEADER_WORD2               (0x4870)
    889. 

  889. #define MAC_HEADER_WORD3               (0x4874)
    890. 

  890. #define MAC_HEADER_WORD4               (0x4878)
    891. 

  891. #define MAC_HEADER_WORD5               (0x487C)
    892. 

  892. #define MAC_HEADER_WORD6               (0x4880)
    893. 

  893. #define MAC_HEADER_WORD7               (0x4884)
    894. 

  894. #define MAC_HEADER_WORD8               (0x4888)
    895. 

  895. #define MAC_HEADER_WORD9               (0x488C)
    896. 

  896. #define RX_CFG                         (0x5514)
    897. 

  897. #define RX_FILTER_CFG                  (0x55B4)
    898. 

  898. #define RX_MC0_L                       (0x5518)
    899. 

  899. #define RX_MC0_H                       (0x551C)
    900. 

  900. #define RX_MC1_L                       (0x5520)
    901. 

  901. #define RX_MC1_H                       (0x5524)
    902. 

  902. #define STA_SSID0                      (0x4804)
    903. 

  903. #define STA_SSID1                      (0x4808)
    904. 

  904. #define STA_SSID2                      (0x480C)
    905. 

  905. #define STA_SSID3                      (0x4810)
    906. 

  906. #define STA_SSID4                      (0x4814)
    907. 

  907. #define STA_SSID5                      (0x4818)
    908. 

  908. #define STA_SSID6                      (0x481C)
    909. 

  909. #define STA_SSID7                      (0x4820)
    910. 

  910. #define SSID_LEN                       (0x4824)
    911. 

  911. #define RX_FREE_MEM                    (0x5528)
    912. 

  912. #define RX_CURR_MEM                    (0x552C)
    913. 

  913. #define MAC_TIMESTAMP                  (0x5560) /* Check place*/
    914. 

  914. #define RX_TIMESTAMP                   (0x5564)
    915. 

  915. #define RX_FRM_PTR                     (0x5568)
    916. 

  916. #define RX_FRM_LEN                     (0x556C)
    917. 

  917. #define RX_PLCP_HDR                    (0x5570)
    918. 

  918. #define RX_PLCP_SIGNAL                 (0x5574)
    919. 

  919. #define RX_PLCP_SERVICE                (0x5578) /* 16 bits ?*/
    920. 

  920. #define RX_PLCP_LENGTH                 (0x557C)
    921. 

  921. #define RX_FRM_CTL                     (0x5580)
    922. 

  922. #define RX_DUR_ID                      (0x5584)
    923. 

  923. #define RX_ADDR1_L                     (0x5588)
    924. 

  924. #define RX_ADDR1_H                     (0x558C)
    925. 

  925. #define RX_ADDR2_L                     (0x5590)
    926. 

  926. #define RX_ADDR2_H                     (0x5594)
    927. 

  927. #define RX_ADDR3_L                     (0x5598)
    928. 

  928. #define RX_ADDR3_H                     (0x559C)
    929. 

  929. #define RX_SEQ_CTL                     (0x55A0)
    930. 

  930. #define RX_WEP_IV                      (0x55A4)
    931. 

  931. #define RX_TIME_L                      (0x55A8)
    932. 

  932. #define RX_TIME_H                      (0x55AC)
    933. 

  933. #define RX_STATUS                      (0x55B0)
    934. 

  934. #define PLCP_ERR_CNT                   (0x4828)
    935. 

  935. #define FCS_ERR_CNT                    (0x482C)
    936. 

  936. #define RX_OVERFLOW_CNT                (0x4830)
    937. 

  937. #define RX_DEBUG1                      (0x4858)
    938. 

  938. #define RX_DEBUG2                      (0x485C)
    939. 

  939. #define RX_QOS_CFG                     (0x4848)
    940. 

  940. #define RX_QOS_CTL                     (0x4844)
    941. 

  941. #define RX_QOS_STATUS                  (0x4854) /* new name RX_QOS_STS*/
    942. 

  942. #define RX_TXOP_HOLDER_L               (0x484C)
    943. 

  943. #define RX_TXOP_HOLDER_H               (0x4850)
    944. 

  944. #define RX_FRM_CNT                     (0x4834) /* what is RX_FRM_CTR*/
    945. 

  945. #define CONS_FCS_ERR_CNT               (0x483C)
    946. 

  946. #define CONS_FCS_ERR_CFG               (0x4840)
    947. 

  947. #define RX_QOS_CTL_MASK                (0x48A0) /* new*/
    948. 

  948. #define RX_QOS_ACK_EN                  (0x48A4) /* new*/
    949. 

  949. #define RX_QOS_NOACK_EN                (0x48A8) /* new*/
    950. 

  950. #define RX_QOS_ACK_BITMAP              (0x48AC) /* new*/
    951. 

  951. 

  952. /* Baseband Processor registers*/
    953. 

  953. #define SBB_CFG                        (0x55C8)
    954. 

  954. #define SBB_ADDR                       (0x55D0)
    955. 

  955. #define SBB_DATA                       (0x55D4)
    956. 

  956. #define SBB_CTL                        (0x55D8)
    957. 

  957. 

  958. /* Radio Control Interface registers*/
    959. 

  959. #define RCI_CTL                        (0x55DC)
    960. 

  960. #define RCI_DATA                       (0x55E0)
    961. 

  961. #define RCI_CFG1                       (0x55E4)
    962. 

  962. #define RCI_CFG2                       (0x55E8)
    963. 

  963. #define RCI_CFG3                       (0x55EC)
    964. 

  964. 

  965. #define TNET1150_LAST_REG_ADDR			PCI_CONTROL
    966. 

  966. 

  967. 

  968. /* Missing registers*/
    969. 

  969. 

  970. 

  971. #endif
    972. 

  972.