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/arch/powerpc/platforms/fsl_uli1575.c

https://bitbucket.org/abioy/linux
C | 362 lines | 218 code | 69 blank | 75 comment | 29 complexity | 2e426e5d4d4d27a5f9e924e9a59bfc07 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * ULI M1575 setup code - specific to Freescale boards
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/stddef.h>
  12. #include <linux/kernel.h>
  13. #include <linux/pci.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mc146818rtc.h>
  16. #include <asm/system.h>
  17. #include <asm/pci-bridge.h>
  18. #define ULI_PIRQA 0x08
  19. #define ULI_PIRQB 0x09
  20. #define ULI_PIRQC 0x0a
  21. #define ULI_PIRQD 0x0b
  22. #define ULI_PIRQE 0x0c
  23. #define ULI_PIRQF 0x0d
  24. #define ULI_PIRQG 0x0e
  25. #define ULI_8259_NONE 0x00
  26. #define ULI_8259_IRQ1 0x08
  27. #define ULI_8259_IRQ3 0x02
  28. #define ULI_8259_IRQ4 0x04
  29. #define ULI_8259_IRQ5 0x05
  30. #define ULI_8259_IRQ6 0x07
  31. #define ULI_8259_IRQ7 0x06
  32. #define ULI_8259_IRQ9 0x01
  33. #define ULI_8259_IRQ10 0x03
  34. #define ULI_8259_IRQ11 0x09
  35. #define ULI_8259_IRQ12 0x0b
  36. #define ULI_8259_IRQ14 0x0d
  37. #define ULI_8259_IRQ15 0x0f
  38. u8 uli_pirq_to_irq[8] = {
  39. ULI_8259_IRQ9, /* PIRQA */
  40. ULI_8259_IRQ10, /* PIRQB */
  41. ULI_8259_IRQ11, /* PIRQC */
  42. ULI_8259_IRQ12, /* PIRQD */
  43. ULI_8259_IRQ5, /* PIRQE */
  44. ULI_8259_IRQ6, /* PIRQF */
  45. ULI_8259_IRQ7, /* PIRQG */
  46. ULI_8259_NONE, /* PIRQH */
  47. };
  48. static inline bool is_quirk_valid(void)
  49. {
  50. return (machine_is(mpc86xx_hpcn) ||
  51. machine_is(mpc8544_ds) ||
  52. machine_is(p2020_ds) ||
  53. machine_is(mpc8572_ds));
  54. }
  55. /* Bridge */
  56. static void __devinit early_uli5249(struct pci_dev *dev)
  57. {
  58. unsigned char temp;
  59. if (!is_quirk_valid())
  60. return;
  61. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
  62. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  63. /* read/write lock */
  64. pci_read_config_byte(dev, 0x7c, &temp);
  65. pci_write_config_byte(dev, 0x7c, 0x80);
  66. /* set as P2P bridge */
  67. pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
  68. dev->class |= 0x1;
  69. /* restore lock */
  70. pci_write_config_byte(dev, 0x7c, temp);
  71. }
  72. static void __devinit quirk_uli1575(struct pci_dev *dev)
  73. {
  74. int i;
  75. if (!is_quirk_valid())
  76. return;
  77. /*
  78. * ULI1575 interrupts route setup
  79. */
  80. /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */
  81. for (i = 0; i < 4; i++) {
  82. u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4);
  83. pci_write_config_byte(dev, 0x48 + i, val);
  84. }
  85. /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */
  86. pci_write_config_byte(dev, 0x86, ULI_PIRQD);
  87. /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */
  88. pci_write_config_byte(dev, 0x87, ULI_PIRQA);
  89. /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */
  90. pci_write_config_byte(dev, 0x88, ULI_PIRQB);
  91. /* Lan controller: dev 27, func 0 - IRQ6 */
  92. pci_write_config_byte(dev, 0x89, ULI_PIRQF);
  93. /* AC97 Audio controller: dev 29, func 0 - IRQ6 */
  94. pci_write_config_byte(dev, 0x8a, ULI_PIRQF);
  95. /* Modem controller: dev 29, func 1 - IRQ6 */
  96. pci_write_config_byte(dev, 0x8b, ULI_PIRQF);
  97. /* HD Audio controller: dev 29, func 2 - IRQ6 */
  98. pci_write_config_byte(dev, 0x8c, ULI_PIRQF);
  99. /* SATA controller: dev 31, func 1 - IRQ5 */
  100. pci_write_config_byte(dev, 0x8d, ULI_PIRQE);
  101. /* SMB interrupt: dev 30, func 1 - IRQ7 */
  102. pci_write_config_byte(dev, 0x8e, ULI_PIRQG);
  103. /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */
  104. pci_write_config_byte(dev, 0x8f, ULI_PIRQG);
  105. /* USB 2.0 controller: dev 28, func 3 */
  106. pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11);
  107. /* Primary PATA IDE IRQ: 14
  108. * Secondary PATA IDE IRQ: 15
  109. */
  110. pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14);
  111. pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15);
  112. }
  113. static void __devinit quirk_final_uli1575(struct pci_dev *dev)
  114. {
  115. /* Set i8259 interrupt trigger
  116. * IRQ 3: Level
  117. * IRQ 4: Level
  118. * IRQ 5: Level
  119. * IRQ 6: Level
  120. * IRQ 7: Level
  121. * IRQ 9: Level
  122. * IRQ 10: Level
  123. * IRQ 11: Level
  124. * IRQ 12: Level
  125. * IRQ 14: Edge
  126. * IRQ 15: Edge
  127. */
  128. if (!is_quirk_valid())
  129. return;
  130. outb(0xfa, 0x4d0);
  131. outb(0x1e, 0x4d1);
  132. /* setup RTC */
  133. CMOS_WRITE(RTC_SET, RTC_CONTROL);
  134. CMOS_WRITE(RTC_24H, RTC_CONTROL);
  135. /* ensure month, date, and week alarm fields are ignored */
  136. CMOS_WRITE(0, RTC_VALID);
  137. outb_p(0x7c, 0x72);
  138. outb_p(RTC_ALARM_DONT_CARE, 0x73);
  139. outb_p(0x7d, 0x72);
  140. outb_p(RTC_ALARM_DONT_CARE, 0x73);
  141. }
  142. /* SATA */
  143. static void __devinit quirk_uli5288(struct pci_dev *dev)
  144. {
  145. unsigned char c;
  146. unsigned int d;
  147. if (!is_quirk_valid())
  148. return;
  149. /* read/write lock */
  150. pci_read_config_byte(dev, 0x83, &c);
  151. pci_write_config_byte(dev, 0x83, c|0x80);
  152. pci_read_config_dword(dev, PCI_CLASS_REVISION, &d);
  153. d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8);
  154. pci_write_config_dword(dev, PCI_CLASS_REVISION, d);
  155. /* restore lock */
  156. pci_write_config_byte(dev, 0x83, c);
  157. /* disable emulated PATA mode enabled */
  158. pci_read_config_byte(dev, 0x84, &c);
  159. pci_write_config_byte(dev, 0x84, c & ~0x01);
  160. }
  161. /* PATA */
  162. static void __devinit quirk_uli5229(struct pci_dev *dev)
  163. {
  164. unsigned short temp;
  165. if (!is_quirk_valid())
  166. return;
  167. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
  168. PCI_COMMAND_MASTER | PCI_COMMAND_IO);
  169. /* Enable Native IRQ 14/15 */
  170. pci_read_config_word(dev, 0x4a, &temp);
  171. pci_write_config_word(dev, 0x4a, temp | 0x1000);
  172. }
  173. /* We have to do a dummy read on the P2P for the RTC to work, WTF */
  174. static void __devinit quirk_final_uli5249(struct pci_dev *dev)
  175. {
  176. int i;
  177. u8 *dummy;
  178. struct pci_bus *bus = dev->bus;
  179. struct resource *res;
  180. resource_size_t end = 0;
  181. for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) {
  182. unsigned long flags = pci_resource_flags(dev, i);
  183. if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM)
  184. end = pci_resource_end(dev, i);
  185. }
  186. pci_bus_for_each_resource(bus, res, i) {
  187. if (res && res->flags & IORESOURCE_MEM) {
  188. if (res->end == end)
  189. dummy = ioremap(res->start, 0x4);
  190. else
  191. dummy = ioremap(res->end - 3, 0x4);
  192. if (dummy) {
  193. in_8(dummy);
  194. iounmap(dummy);
  195. }
  196. break;
  197. }
  198. }
  199. }
  200. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
  201. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
  202. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
  203. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
  204. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
  205. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
  206. DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
  207. static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev)
  208. {
  209. u32 temp32;
  210. if (!machine_is(mpc86xx_hpcd))
  211. return;
  212. /* Disable INTx */
  213. pci_read_config_dword(dev, 0x48, &temp32);
  214. pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
  215. /* Enable sideband interrupt */
  216. pci_read_config_dword(dev, 0x90, &temp32);
  217. pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
  218. }
  219. static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev)
  220. {
  221. unsigned char c;
  222. if (!machine_is(mpc86xx_hpcd))
  223. return;
  224. pci_read_config_byte(dev, 0x83, &c);
  225. c |= 0x80;
  226. pci_write_config_byte(dev, 0x83, c);
  227. pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
  228. pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
  229. pci_read_config_byte(dev, 0x83, &c);
  230. c &= 0x7f;
  231. pci_write_config_byte(dev, 0x83, c);
  232. }
  233. /*
  234. * Since 8259PIC was disabled on the board, the IDE device can not
  235. * use the legacy IRQ, we need to let the IDE device work under
  236. * native mode and use the interrupt line like other PCI devices.
  237. * IRQ14 is a sideband interrupt from IDE device to CPU and we use this
  238. * as the interrupt for IDE device.
  239. */
  240. static void __devinit hpcd_quirk_uli5229(struct pci_dev *dev)
  241. {
  242. unsigned char c;
  243. if (!machine_is(mpc86xx_hpcd))
  244. return;
  245. pci_read_config_byte(dev, 0x4b, &c);
  246. c |= 0x10;
  247. pci_write_config_byte(dev, 0x4b, c);
  248. }
  249. /*
  250. * SATA interrupt pin bug fix
  251. * There's a chip bug for 5288, The interrupt pin should be 2,
  252. * not the read only value 1, So it use INTB#, not INTA# which
  253. * actually used by the IDE device 5229.
  254. * As of this bug, during the PCI initialization, 5288 read the
  255. * irq of IDE device from the device tree, this function fix this
  256. * bug by re-assigning a correct irq to 5288.
  257. *
  258. */
  259. static void __devinit hpcd_final_uli5288(struct pci_dev *dev)
  260. {
  261. struct pci_controller *hose = pci_bus_to_host(dev->bus);
  262. struct device_node *hosenode = hose ? hose->dn : NULL;
  263. struct of_irq oirq;
  264. int virq, pin = 2;
  265. u32 laddr[3];
  266. if (!machine_is(mpc86xx_hpcd))
  267. return;
  268. if (!hosenode)
  269. return;
  270. laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
  271. laddr[1] = laddr[2] = 0;
  272. of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
  273. virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
  274. oirq.size);
  275. dev->irq = virq;
  276. }
  277. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575);
  278. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288);
  279. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229);
  280. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288);
  281. int uli_exclude_device(struct pci_controller *hose,
  282. u_char bus, u_char devfn)
  283. {
  284. if (bus == (hose->first_busno + 2)) {
  285. /* exclude Modem controller */
  286. if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1))
  287. return PCIBIOS_DEVICE_NOT_FOUND;
  288. /* exclude HD Audio controller */
  289. if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2))
  290. return PCIBIOS_DEVICE_NOT_FOUND;
  291. }
  292. return PCIBIOS_SUCCESSFUL;
  293. }