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/arch/powerpc/platforms/52xx/mpc52xx_pic.c

https://bitbucket.org/abioy/linux
C | 568 lines | 318 code | 81 blank | 169 comment | 30 complexity | bb7fcc2c12028487e8bc8ec1d5096a69 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. *
  3. * Programmable Interrupt Controller functions for the Freescale MPC52xx.
  4. *
  5. * Copyright (C) 2008 Secret Lab Technologies Ltd.
  6. * Copyright (C) 2006 bplan GmbH
  7. * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
  8. * Copyright (C) 2003 Montavista Software, Inc
  9. *
  10. * Based on the code from the 2.4 kernel by
  11. * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
  12. *
  13. * This file is licensed under the terms of the GNU General Public License
  14. * version 2. This program is licensed "as is" without any warranty of any
  15. * kind, whether express or implied.
  16. *
  17. */
  18. /*
  19. * This is the device driver for the MPC5200 interrupt controller.
  20. *
  21. * hardware overview
  22. * -----------------
  23. * The MPC5200 interrupt controller groups the all interrupt sources into
  24. * three groups called 'critical', 'main', and 'peripheral'. The critical
  25. * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
  26. * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
  27. * gpios, and the general purpose timers. Peripheral group contains the
  28. * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
  29. * USB, DMA, etc).
  30. *
  31. * virqs
  32. * -----
  33. * The Linux IRQ subsystem requires that each irq source be assigned a
  34. * system wide unique IRQ number starting at 1 (0 means no irq). Since
  35. * systems can have multiple interrupt controllers, the virtual IRQ (virq)
  36. * infrastructure lets each interrupt controller to define a local set
  37. * of IRQ numbers and the virq infrastructure maps those numbers into
  38. * a unique range of the global IRQ# space.
  39. *
  40. * To define a range of virq numbers for this controller, this driver first
  41. * assigns a number to each of the irq groups (called the level 1 or L1
  42. * value). Within each group individual irq sources are also assigned a
  43. * number, as defined by the MPC5200 user guide, and refers to it as the
  44. * level 2 or L2 value. The virq number is determined by shifting up the
  45. * L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
  46. *
  47. * For example, the TMR0 interrupt is irq 9 in the main group. The
  48. * virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
  49. *
  50. * The observant reader will also notice that this driver defines a 4th
  51. * interrupt group called 'bestcomm'. The bestcomm group isn't physically
  52. * part of the MPC5200 interrupt controller, but it is used here to assign
  53. * a separate virq number for each bestcomm task (since any of the 16
  54. * bestcomm tasks can cause the bestcomm interrupt to be raised). When a
  55. * bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
  56. * which task needs servicing and returns the irq number for that task. This
  57. * allows drivers which use bestcomm to define their own interrupt handlers.
  58. *
  59. * irq_chip structures
  60. * -------------------
  61. * For actually manipulating IRQs (masking, enabling, clearing, etc) this
  62. * driver defines four separate 'irq_chip' structures, one for the main
  63. * group, one for the peripherals group, one for the bestcomm group and one
  64. * for external interrupts. The irq_chip structures provide the hooks needed
  65. * to manipulate each IRQ source, and since each group is has a separate set
  66. * of registers for controlling the irq, it makes sense to divide up the
  67. * hooks along those lines.
  68. *
  69. * You'll notice that there is not an irq_chip for the critical group and
  70. * you'll also notice that there is an irq_chip defined for external
  71. * interrupts even though there is no external interrupt group. The reason
  72. * for this is that the four external interrupts are all managed with the same
  73. * register even though one of the external IRQs is in the critical group and
  74. * the other three are in the main group. For this reason it makes sense for
  75. * the 4 external irqs to be managed using a separate set of hooks. The
  76. * reason there is no crit irq_chip is that of the 3 irqs in the critical
  77. * group, only external interrupt is actually support at this time by this
  78. * driver and since external interrupt is the only one used, it can just
  79. * be directed to make use of the external irq irq_chip.
  80. *
  81. * device tree bindings
  82. * --------------------
  83. * The device tree bindings for this controller reflect the two level
  84. * organization of irqs in the device. #interrupt-cells = <3> where the
  85. * first cell is the group number [0..3], the second cell is the irq
  86. * number in the group, and the third cell is the sense type (level/edge).
  87. * For reference, the following is a list of the interrupt property values
  88. * associated with external interrupt sources on the MPC5200 (just because
  89. * it is non-obvious to determine what the interrupts property should be
  90. * when reading the mpc5200 manual and it is a frequently asked question).
  91. *
  92. * External interrupts:
  93. * <0 0 n> external irq0, n is sense (n=0: level high,
  94. * <1 1 n> external irq1, n is sense n=1: edge rising,
  95. * <1 2 n> external irq2, n is sense n=2: edge falling,
  96. * <1 3 n> external irq3, n is sense n=3: level low)
  97. */
  98. #undef DEBUG
  99. #include <linux/interrupt.h>
  100. #include <linux/irq.h>
  101. #include <linux/of.h>
  102. #include <asm/io.h>
  103. #include <asm/prom.h>
  104. #include <asm/mpc52xx.h>
  105. /* HW IRQ mapping */
  106. #define MPC52xx_IRQ_L1_CRIT (0)
  107. #define MPC52xx_IRQ_L1_MAIN (1)
  108. #define MPC52xx_IRQ_L1_PERP (2)
  109. #define MPC52xx_IRQ_L1_SDMA (3)
  110. #define MPC52xx_IRQ_L1_OFFSET (6)
  111. #define MPC52xx_IRQ_L1_MASK (0x00c0)
  112. #define MPC52xx_IRQ_L2_MASK (0x003f)
  113. #define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
  114. /* MPC5200 device tree match tables */
  115. static struct of_device_id mpc52xx_pic_ids[] __initdata = {
  116. { .compatible = "fsl,mpc5200-pic", },
  117. { .compatible = "mpc5200-pic", },
  118. {}
  119. };
  120. static struct of_device_id mpc52xx_sdma_ids[] __initdata = {
  121. { .compatible = "fsl,mpc5200-bestcomm", },
  122. { .compatible = "mpc5200-bestcomm", },
  123. {}
  124. };
  125. static struct mpc52xx_intr __iomem *intr;
  126. static struct mpc52xx_sdma __iomem *sdma;
  127. static struct irq_host *mpc52xx_irqhost = NULL;
  128. static unsigned char mpc52xx_map_senses[4] = {
  129. IRQ_TYPE_LEVEL_HIGH,
  130. IRQ_TYPE_EDGE_RISING,
  131. IRQ_TYPE_EDGE_FALLING,
  132. IRQ_TYPE_LEVEL_LOW,
  133. };
  134. /* Utility functions */
  135. static inline void io_be_setbit(u32 __iomem *addr, int bitno)
  136. {
  137. out_be32(addr, in_be32(addr) | (1 << bitno));
  138. }
  139. static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
  140. {
  141. out_be32(addr, in_be32(addr) & ~(1 << bitno));
  142. }
  143. /*
  144. * IRQ[0-3] interrupt irq_chip
  145. */
  146. static void mpc52xx_extirq_mask(unsigned int virq)
  147. {
  148. int irq;
  149. int l2irq;
  150. irq = irq_map[virq].hwirq;
  151. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  152. io_be_clrbit(&intr->ctrl, 11 - l2irq);
  153. }
  154. static void mpc52xx_extirq_unmask(unsigned int virq)
  155. {
  156. int irq;
  157. int l2irq;
  158. irq = irq_map[virq].hwirq;
  159. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  160. io_be_setbit(&intr->ctrl, 11 - l2irq);
  161. }
  162. static void mpc52xx_extirq_ack(unsigned int virq)
  163. {
  164. int irq;
  165. int l2irq;
  166. irq = irq_map[virq].hwirq;
  167. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  168. io_be_setbit(&intr->ctrl, 27-l2irq);
  169. }
  170. static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
  171. {
  172. u32 ctrl_reg, type;
  173. int irq;
  174. int l2irq;
  175. void *handler = handle_level_irq;
  176. irq = irq_map[virq].hwirq;
  177. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  178. pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
  179. switch (flow_type) {
  180. case IRQF_TRIGGER_HIGH: type = 0; break;
  181. case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
  182. case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
  183. case IRQF_TRIGGER_LOW: type = 3; break;
  184. default:
  185. type = 0;
  186. }
  187. ctrl_reg = in_be32(&intr->ctrl);
  188. ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
  189. ctrl_reg |= (type << (22 - (l2irq * 2)));
  190. out_be32(&intr->ctrl, ctrl_reg);
  191. __set_irq_handler_unlocked(virq, handler);
  192. return 0;
  193. }
  194. static struct irq_chip mpc52xx_extirq_irqchip = {
  195. .name = "MPC52xx External",
  196. .mask = mpc52xx_extirq_mask,
  197. .unmask = mpc52xx_extirq_unmask,
  198. .ack = mpc52xx_extirq_ack,
  199. .set_type = mpc52xx_extirq_set_type,
  200. };
  201. /*
  202. * Main interrupt irq_chip
  203. */
  204. static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type)
  205. {
  206. return 0; /* Do nothing so that the sense mask will get updated */
  207. }
  208. static void mpc52xx_main_mask(unsigned int virq)
  209. {
  210. int irq;
  211. int l2irq;
  212. irq = irq_map[virq].hwirq;
  213. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  214. io_be_setbit(&intr->main_mask, 16 - l2irq);
  215. }
  216. static void mpc52xx_main_unmask(unsigned int virq)
  217. {
  218. int irq;
  219. int l2irq;
  220. irq = irq_map[virq].hwirq;
  221. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  222. io_be_clrbit(&intr->main_mask, 16 - l2irq);
  223. }
  224. static struct irq_chip mpc52xx_main_irqchip = {
  225. .name = "MPC52xx Main",
  226. .mask = mpc52xx_main_mask,
  227. .mask_ack = mpc52xx_main_mask,
  228. .unmask = mpc52xx_main_unmask,
  229. .set_type = mpc52xx_null_set_type,
  230. };
  231. /*
  232. * Peripherals interrupt irq_chip
  233. */
  234. static void mpc52xx_periph_mask(unsigned int virq)
  235. {
  236. int irq;
  237. int l2irq;
  238. irq = irq_map[virq].hwirq;
  239. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  240. io_be_setbit(&intr->per_mask, 31 - l2irq);
  241. }
  242. static void mpc52xx_periph_unmask(unsigned int virq)
  243. {
  244. int irq;
  245. int l2irq;
  246. irq = irq_map[virq].hwirq;
  247. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  248. io_be_clrbit(&intr->per_mask, 31 - l2irq);
  249. }
  250. static struct irq_chip mpc52xx_periph_irqchip = {
  251. .name = "MPC52xx Peripherals",
  252. .mask = mpc52xx_periph_mask,
  253. .mask_ack = mpc52xx_periph_mask,
  254. .unmask = mpc52xx_periph_unmask,
  255. .set_type = mpc52xx_null_set_type,
  256. };
  257. /*
  258. * SDMA interrupt irq_chip
  259. */
  260. static void mpc52xx_sdma_mask(unsigned int virq)
  261. {
  262. int irq;
  263. int l2irq;
  264. irq = irq_map[virq].hwirq;
  265. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  266. io_be_setbit(&sdma->IntMask, l2irq);
  267. }
  268. static void mpc52xx_sdma_unmask(unsigned int virq)
  269. {
  270. int irq;
  271. int l2irq;
  272. irq = irq_map[virq].hwirq;
  273. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  274. io_be_clrbit(&sdma->IntMask, l2irq);
  275. }
  276. static void mpc52xx_sdma_ack(unsigned int virq)
  277. {
  278. int irq;
  279. int l2irq;
  280. irq = irq_map[virq].hwirq;
  281. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  282. out_be32(&sdma->IntPend, 1 << l2irq);
  283. }
  284. static struct irq_chip mpc52xx_sdma_irqchip = {
  285. .name = "MPC52xx SDMA",
  286. .mask = mpc52xx_sdma_mask,
  287. .unmask = mpc52xx_sdma_unmask,
  288. .ack = mpc52xx_sdma_ack,
  289. .set_type = mpc52xx_null_set_type,
  290. };
  291. /**
  292. * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
  293. */
  294. static int mpc52xx_is_extirq(int l1, int l2)
  295. {
  296. return ((l1 == 0) && (l2 == 0)) ||
  297. ((l1 == 1) && (l2 >= 1) && (l2 <= 3));
  298. }
  299. /**
  300. * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
  301. */
  302. static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
  303. const u32 *intspec, unsigned int intsize,
  304. irq_hw_number_t *out_hwirq,
  305. unsigned int *out_flags)
  306. {
  307. int intrvect_l1;
  308. int intrvect_l2;
  309. int intrvect_type;
  310. int intrvect_linux;
  311. if (intsize != 3)
  312. return -1;
  313. intrvect_l1 = (int)intspec[0];
  314. intrvect_l2 = (int)intspec[1];
  315. intrvect_type = (int)intspec[2] & 0x3;
  316. intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
  317. MPC52xx_IRQ_L1_MASK;
  318. intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
  319. *out_hwirq = intrvect_linux;
  320. *out_flags = IRQ_TYPE_LEVEL_LOW;
  321. if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
  322. *out_flags = mpc52xx_map_senses[intrvect_type];
  323. pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
  324. intrvect_l2);
  325. return 0;
  326. }
  327. /**
  328. * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
  329. */
  330. static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
  331. irq_hw_number_t irq)
  332. {
  333. int l1irq;
  334. int l2irq;
  335. struct irq_chip *irqchip;
  336. void *hndlr;
  337. int type;
  338. u32 reg;
  339. l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
  340. l2irq = irq & MPC52xx_IRQ_L2_MASK;
  341. /*
  342. * External IRQs are handled differently by the hardware so they are
  343. * handled by a dedicated irq_chip structure.
  344. */
  345. if (mpc52xx_is_extirq(l1irq, l2irq)) {
  346. reg = in_be32(&intr->ctrl);
  347. type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
  348. if ((type == IRQ_TYPE_EDGE_FALLING) ||
  349. (type == IRQ_TYPE_EDGE_RISING))
  350. hndlr = handle_edge_irq;
  351. else
  352. hndlr = handle_level_irq;
  353. set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
  354. pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
  355. __func__, l2irq, virq, (int)irq, type);
  356. return 0;
  357. }
  358. /* It is an internal SOC irq. Choose the correct irq_chip */
  359. switch (l1irq) {
  360. case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
  361. case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
  362. case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
  363. default:
  364. pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n",
  365. __func__, virq, l1irq, l2irq);
  366. return -EINVAL;
  367. }
  368. set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
  369. pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
  370. return 0;
  371. }
  372. static struct irq_host_ops mpc52xx_irqhost_ops = {
  373. .xlate = mpc52xx_irqhost_xlate,
  374. .map = mpc52xx_irqhost_map,
  375. };
  376. /**
  377. * mpc52xx_init_irq - Initialize and register with the virq subsystem
  378. *
  379. * Hook for setting up IRQs on an mpc5200 system. A pointer to this function
  380. * is to be put into the machine definition structure.
  381. *
  382. * This function searches the device tree for an MPC5200 interrupt controller,
  383. * initializes it, and registers it with the virq subsystem.
  384. */
  385. void __init mpc52xx_init_irq(void)
  386. {
  387. u32 intr_ctrl;
  388. struct device_node *picnode;
  389. struct device_node *np;
  390. /* Remap the necessary zones */
  391. picnode = of_find_matching_node(NULL, mpc52xx_pic_ids);
  392. intr = of_iomap(picnode, 0);
  393. if (!intr)
  394. panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. "
  395. "Check node !");
  396. np = of_find_matching_node(NULL, mpc52xx_sdma_ids);
  397. sdma = of_iomap(np, 0);
  398. of_node_put(np);
  399. if (!sdma)
  400. panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
  401. "Check node !");
  402. pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
  403. /* Disable all interrupt sources. */
  404. out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
  405. out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
  406. out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
  407. out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
  408. intr_ctrl = in_be32(&intr->ctrl);
  409. intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
  410. intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
  411. 0x00001000 | /* MEE master external enable */
  412. 0x00000000 | /* 0 means disable IRQ 0-3 */
  413. 0x00000001; /* CEb route critical normally */
  414. out_be32(&intr->ctrl, intr_ctrl);
  415. /* Zero a bunch of the priority settings. */
  416. out_be32(&intr->per_pri1, 0);
  417. out_be32(&intr->per_pri2, 0);
  418. out_be32(&intr->per_pri3, 0);
  419. out_be32(&intr->main_pri1, 0);
  420. out_be32(&intr->main_pri2, 0);
  421. /*
  422. * As last step, add an irq host to translate the real
  423. * hw irq information provided by the ofw to linux virq
  424. */
  425. mpc52xx_irqhost = irq_alloc_host(picnode, IRQ_HOST_MAP_LINEAR,
  426. MPC52xx_IRQ_HIGHTESTHWIRQ,
  427. &mpc52xx_irqhost_ops, -1);
  428. if (!mpc52xx_irqhost)
  429. panic(__FILE__ ": Cannot allocate the IRQ host\n");
  430. irq_set_default_host(mpc52xx_irqhost);
  431. pr_info("MPC52xx PIC is up and running!\n");
  432. }
  433. /**
  434. * mpc52xx_get_irq - Get pending interrupt number hook function
  435. *
  436. * Called by the interupt handler to determine what IRQ handler needs to be
  437. * executed.
  438. *
  439. * Status of pending interrupts is determined by reading the encoded status
  440. * register. The encoded status register has three fields; one for each of the
  441. * types of interrupts defined by the controller - 'critical', 'main' and
  442. * 'peripheral'. This function reads the status register and returns the IRQ
  443. * number associated with the highest priority pending interrupt. 'Critical'
  444. * interrupts have the highest priority, followed by 'main' interrupts, and
  445. * then 'peripheral'.
  446. *
  447. * The mpc5200 interrupt controller can be configured to boost the priority
  448. * of individual 'peripheral' interrupts. If this is the case then a special
  449. * value will appear in either the crit or main fields indicating a high
  450. * or medium priority peripheral irq has occurred.
  451. *
  452. * This function checks each of the 3 irq request fields and returns the
  453. * first pending interrupt that it finds.
  454. *
  455. * This function also identifies a 4th type of interrupt; 'bestcomm'. Each
  456. * bestcomm DMA task can raise the bestcomm peripheral interrupt. When this
  457. * occurs at task-specific IRQ# is decoded so that each task can have its
  458. * own IRQ handler.
  459. */
  460. unsigned int mpc52xx_get_irq(void)
  461. {
  462. u32 status;
  463. int irq = NO_IRQ_IGNORE;
  464. status = in_be32(&intr->enc_status);
  465. if (status & 0x00000400) { /* critical */
  466. irq = (status >> 8) & 0x3;
  467. if (irq == 2) /* high priority peripheral */
  468. goto peripheral;
  469. irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET);
  470. } else if (status & 0x00200000) { /* main */
  471. irq = (status >> 16) & 0x1f;
  472. if (irq == 4) /* low priority peripheral */
  473. goto peripheral;
  474. irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET);
  475. } else if (status & 0x20000000) { /* peripheral */
  476. peripheral:
  477. irq = (status >> 24) & 0x1f;
  478. if (irq == 0) { /* bestcomm */
  479. status = in_be32(&sdma->IntPend);
  480. irq = ffs(status) - 1;
  481. irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET);
  482. } else {
  483. irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET);
  484. }
  485. }
  486. return irq_linear_revmap(mpc52xx_irqhost, irq);
  487. }