/arch/powerpc/boot/dts/mpc8572ds_36b.dts
Device Tree | 808 lines | 686 code | 90 blank | 32 comment | 0 complexity | f819e652dc729b3f42a330361dabe273 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
61
62 memory {
63 device_type = "memory";
64 };
65
66 localbus@fffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0xf 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73
74 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
75 0x1 0x0 0xf 0xe0000000 0x08000000
76 0x2 0x0 0xf 0xffa00000 0x00040000
77 0x3 0x0 0xf 0xffdf0000 0x00008000
78 0x4 0x0 0xf 0xffa40000 0x00040000
79 0x5 0x0 0xf 0xffa80000 0x00040000
80 0x6 0x0 0xf 0xffac0000 0x00040000>;
81
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
89
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
94
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
99
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
104
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
109
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
113
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
118
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
124
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
131
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
136
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
140
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
145
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
149
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
154
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
159
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
165
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
171
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 };
178
179 soc8572@fffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0xf 0xffe00000 0x100000>;
185 bus-frequency = <0>; // Filled out by uboot.
186
187 ecm-law@0 {
188 compatible = "fsl,ecm-law";
189 reg = <0x0 0x1000>;
190 fsl,num-laws = <12>;
191 };
192
193 ecm@1000 {
194 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
195 reg = <0x1000 0x1000>;
196 interrupts = <17 2>;
197 interrupt-parent = <&mpic>;
198 };
199
200 memory-controller@2000 {
201 compatible = "fsl,mpc8572-memory-controller";
202 reg = <0x2000 0x1000>;
203 interrupt-parent = <&mpic>;
204 interrupts = <18 2>;
205 };
206
207 memory-controller@6000 {
208 compatible = "fsl,mpc8572-memory-controller";
209 reg = <0x6000 0x1000>;
210 interrupt-parent = <&mpic>;
211 interrupts = <18 2>;
212 };
213
214 L2: l2-cache-controller@20000 {
215 compatible = "fsl,mpc8572-l2-cache-controller";
216 reg = <0x20000 0x1000>;
217 cache-line-size = <32>; // 32 bytes
218 cache-size = <0x100000>; // L2, 1M
219 interrupt-parent = <&mpic>;
220 interrupts = <16 2>;
221 };
222
223 i2c@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 cell-index = <0>;
227 compatible = "fsl-i2c";
228 reg = <0x3000 0x100>;
229 interrupts = <43 2>;
230 interrupt-parent = <&mpic>;
231 dfsrr;
232 };
233
234 i2c@3100 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl-i2c";
239 reg = <0x3100 0x100>;
240 interrupts = <43 2>;
241 interrupt-parent = <&mpic>;
242 dfsrr;
243 };
244
245 dma@c300 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
249 reg = <0xc300 0x4>;
250 ranges = <0x0 0xc100 0x200>;
251 cell-index = <1>;
252 dma-channel@0 {
253 compatible = "fsl,mpc8572-dma-channel",
254 "fsl,eloplus-dma-channel";
255 reg = <0x0 0x80>;
256 cell-index = <0>;
257 interrupt-parent = <&mpic>;
258 interrupts = <76 2>;
259 };
260 dma-channel@80 {
261 compatible = "fsl,mpc8572-dma-channel",
262 "fsl,eloplus-dma-channel";
263 reg = <0x80 0x80>;
264 cell-index = <1>;
265 interrupt-parent = <&mpic>;
266 interrupts = <77 2>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,mpc8572-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupt-parent = <&mpic>;
274 interrupts = <78 2>;
275 };
276 dma-channel@180 {
277 compatible = "fsl,mpc8572-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x180 0x80>;
280 cell-index = <3>;
281 interrupt-parent = <&mpic>;
282 interrupts = <79 2>;
283 };
284 };
285
286 dma@21300 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
290 reg = <0x21300 0x4>;
291 ranges = <0x0 0x21100 0x200>;
292 cell-index = <0>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
296 reg = <0x0 0x80>;
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
299 interrupts = <20 2>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
307 interrupts = <21 2>;
308 };
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
312 reg = <0x100 0x80>;
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
315 interrupts = <22 2>;
316 };
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
320 reg = <0x180 0x80>;
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
323 interrupts = <23 2>;
324 };
325 };
326
327 enet0: ethernet@24000 {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 cell-index = <0>;
331 device_type = "network";
332 model = "eTSEC";
333 compatible = "gianfar";
334 reg = <0x24000 0x1000>;
335 ranges = <0x0 0x24000 0x1000>;
336 local-mac-address = [ 00 00 00 00 00 00 ];
337 interrupts = <29 2 30 2 34 2>;
338 interrupt-parent = <&mpic>;
339 tbi-handle = <&tbi0>;
340 phy-handle = <&phy0>;
341 phy-connection-type = "rgmii-id";
342
343 mdio@520 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,gianfar-mdio";
347 reg = <0x520 0x20>;
348
349 phy0: ethernet-phy@0 {
350 interrupt-parent = <&mpic>;
351 interrupts = <10 1>;
352 reg = <0x0>;
353 };
354 phy1: ethernet-phy@1 {
355 interrupt-parent = <&mpic>;
356 interrupts = <10 1>;
357 reg = <0x1>;
358 };
359 phy2: ethernet-phy@2 {
360 interrupt-parent = <&mpic>;
361 interrupts = <10 1>;
362 reg = <0x2>;
363 };
364 phy3: ethernet-phy@3 {
365 interrupt-parent = <&mpic>;
366 interrupts = <10 1>;
367 reg = <0x3>;
368 };
369
370 tbi0: tbi-phy@11 {
371 reg = <0x11>;
372 device_type = "tbi-phy";
373 };
374 };
375 };
376
377 enet1: ethernet@25000 {
378 #address-cells = <1>;
379 #size-cells = <1>;
380 cell-index = <1>;
381 device_type = "network";
382 model = "eTSEC";
383 compatible = "gianfar";
384 reg = <0x25000 0x1000>;
385 ranges = <0x0 0x25000 0x1000>;
386 local-mac-address = [ 00 00 00 00 00 00 ];
387 interrupts = <35 2 36 2 40 2>;
388 interrupt-parent = <&mpic>;
389 tbi-handle = <&tbi1>;
390 phy-handle = <&phy1>;
391 phy-connection-type = "rgmii-id";
392
393 mdio@520 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 compatible = "fsl,gianfar-tbi";
397 reg = <0x520 0x20>;
398
399 tbi1: tbi-phy@11 {
400 reg = <0x11>;
401 device_type = "tbi-phy";
402 };
403 };
404 };
405
406 enet2: ethernet@26000 {
407 #address-cells = <1>;
408 #size-cells = <1>;
409 cell-index = <2>;
410 device_type = "network";
411 model = "eTSEC";
412 compatible = "gianfar";
413 reg = <0x26000 0x1000>;
414 ranges = <0x0 0x26000 0x1000>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
416 interrupts = <31 2 32 2 33 2>;
417 interrupt-parent = <&mpic>;
418 tbi-handle = <&tbi2>;
419 phy-handle = <&phy2>;
420 phy-connection-type = "rgmii-id";
421
422 mdio@520 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,gianfar-tbi";
426 reg = <0x520 0x20>;
427
428 tbi2: tbi-phy@11 {
429 reg = <0x11>;
430 device_type = "tbi-phy";
431 };
432 };
433 };
434
435 enet3: ethernet@27000 {
436 #address-cells = <1>;
437 #size-cells = <1>;
438 cell-index = <3>;
439 device_type = "network";
440 model = "eTSEC";
441 compatible = "gianfar";
442 reg = <0x27000 0x1000>;
443 ranges = <0x0 0x27000 0x1000>;
444 local-mac-address = [ 00 00 00 00 00 00 ];
445 interrupts = <37 2 38 2 39 2>;
446 interrupt-parent = <&mpic>;
447 tbi-handle = <&tbi3>;
448 phy-handle = <&phy3>;
449 phy-connection-type = "rgmii-id";
450
451 mdio@520 {
452 #address-cells = <1>;
453 #size-cells = <0>;
454 compatible = "fsl,gianfar-tbi";
455 reg = <0x520 0x20>;
456
457 tbi3: tbi-phy@11 {
458 reg = <0x11>;
459 device_type = "tbi-phy";
460 };
461 };
462 };
463
464 serial0: serial@4500 {
465 cell-index = <0>;
466 device_type = "serial";
467 compatible = "ns16550";
468 reg = <0x4500 0x100>;
469 clock-frequency = <0>;
470 interrupts = <42 2>;
471 interrupt-parent = <&mpic>;
472 };
473
474 serial1: serial@4600 {
475 cell-index = <1>;
476 device_type = "serial";
477 compatible = "ns16550";
478 reg = <0x4600 0x100>;
479 clock-frequency = <0>;
480 interrupts = <42 2>;
481 interrupt-parent = <&mpic>;
482 };
483
484 global-utilities@e0000 { //global utilities block
485 compatible = "fsl,mpc8572-guts";
486 reg = <0xe0000 0x1000>;
487 fsl,has-rstcr;
488 };
489
490 msi@41600 {
491 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
492 reg = <0x41600 0x80>;
493 msi-available-ranges = <0 0x100>;
494 interrupts = <
495 0xe0 0
496 0xe1 0
497 0xe2 0
498 0xe3 0
499 0xe4 0
500 0xe5 0
501 0xe6 0
502 0xe7 0>;
503 interrupt-parent = <&mpic>;
504 };
505
506 crypto@30000 {
507 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
508 "fsl,sec2.1", "fsl,sec2.0";
509 reg = <0x30000 0x10000>;
510 interrupts = <45 2 58 2>;
511 interrupt-parent = <&mpic>;
512 fsl,num-channels = <4>;
513 fsl,channel-fifo-len = <24>;
514 fsl,exec-units-mask = <0x9fe>;
515 fsl,descriptor-types-mask = <0x3ab0ebf>;
516 };
517
518 mpic: pic@40000 {
519 interrupt-controller;
520 #address-cells = <0>;
521 #interrupt-cells = <2>;
522 reg = <0x40000 0x40000>;
523 compatible = "chrp,open-pic";
524 device_type = "open-pic";
525 };
526 };
527
528 pci0: pcie@fffe08000 {
529 compatible = "fsl,mpc8548-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xffe08000 0 0x1000>;
535 bus-range = <0 255>;
536 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
537 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
538 clock-frequency = <33333333>;
539 interrupt-parent = <&mpic>;
540 interrupts = <24 2>;
541 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
542 interrupt-map = <
543 /* IDSEL 0x11 func 0 - PCI slot 1 */
544 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
545 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
546 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
547 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
548
549 /* IDSEL 0x11 func 1 - PCI slot 1 */
550 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
551 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
552 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
553 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
554
555 /* IDSEL 0x11 func 2 - PCI slot 1 */
556 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
557 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
558 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
559 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
560
561 /* IDSEL 0x11 func 3 - PCI slot 1 */
562 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
563 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
564 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
565 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
566
567 /* IDSEL 0x11 func 4 - PCI slot 1 */
568 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
569 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
570 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
571 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
572
573 /* IDSEL 0x11 func 5 - PCI slot 1 */
574 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
575 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
576 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
577 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
578
579 /* IDSEL 0x11 func 6 - PCI slot 1 */
580 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
581 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
582 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
583 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
584
585 /* IDSEL 0x11 func 7 - PCI slot 1 */
586 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
587 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
588 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
589 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
590
591 /* IDSEL 0x12 func 0 - PCI slot 2 */
592 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
593 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
594 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
595 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
596
597 /* IDSEL 0x12 func 1 - PCI slot 2 */
598 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
599 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
600 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
601 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
602
603 /* IDSEL 0x12 func 2 - PCI slot 2 */
604 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
605 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
606 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
607 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
608
609 /* IDSEL 0x12 func 3 - PCI slot 2 */
610 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
611 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
612 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
613 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
614
615 /* IDSEL 0x12 func 4 - PCI slot 2 */
616 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
617 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
618 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
619 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
620
621 /* IDSEL 0x12 func 5 - PCI slot 2 */
622 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
623 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
624 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
625 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
626
627 /* IDSEL 0x12 func 6 - PCI slot 2 */
628 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
629 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
630 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
631 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
632
633 /* IDSEL 0x12 func 7 - PCI slot 2 */
634 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
635 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
636 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
637 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
638
639 // IDSEL 0x1c USB
640 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
641 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
642 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
643 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
644
645 // IDSEL 0x1d Audio
646 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
647
648 // IDSEL 0x1e Legacy
649 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
650 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
651
652 // IDSEL 0x1f IDE/SATA
653 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
654 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
655
656 >;
657
658 pcie@0 {
659 reg = <0x0 0x0 0x0 0x0 0x0>;
660 #size-cells = <2>;
661 #address-cells = <3>;
662 device_type = "pci";
663 ranges = <0x2000000 0x0 0xe0000000
664 0x2000000 0x0 0xe0000000
665 0x0 0x20000000
666
667 0x1000000 0x0 0x0
668 0x1000000 0x0 0x0
669 0x0 0x10000>;
670 uli1575@0 {
671 reg = <0x0 0x0 0x0 0x0 0x0>;
672 #size-cells = <2>;
673 #address-cells = <3>;
674 ranges = <0x2000000 0x0 0xe0000000
675 0x2000000 0x0 0xe0000000
676 0x0 0x20000000
677
678 0x1000000 0x0 0x0
679 0x1000000 0x0 0x0
680 0x0 0x10000>;
681 isa@1e {
682 device_type = "isa";
683 #interrupt-cells = <2>;
684 #size-cells = <1>;
685 #address-cells = <2>;
686 reg = <0xf000 0x0 0x0 0x0 0x0>;
687 ranges = <0x1 0x0 0x1000000 0x0 0x0
688 0x1000>;
689 interrupt-parent = <&i8259>;
690
691 i8259: interrupt-controller@20 {
692 reg = <0x1 0x20 0x2
693 0x1 0xa0 0x2
694 0x1 0x4d0 0x2>;
695 interrupt-controller;
696 device_type = "interrupt-controller";
697 #address-cells = <0>;
698 #interrupt-cells = <2>;
699 compatible = "chrp,iic";
700 interrupts = <9 2>;
701 interrupt-parent = <&mpic>;
702 };
703
704 i8042@60 {
705 #size-cells = <0>;
706 #address-cells = <1>;
707 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
708 interrupts = <1 3 12 3>;
709 interrupt-parent =
710 <&i8259>;
711
712 keyboard@0 {
713 reg = <0x0>;
714 compatible = "pnpPNP,303";
715 };
716
717 mouse@1 {
718 reg = <0x1>;
719 compatible = "pnpPNP,f03";
720 };
721 };
722
723 rtc@70 {
724 compatible = "pnpPNP,b00";
725 reg = <0x1 0x70 0x2>;
726 };
727
728 gpio@400 {
729 reg = <0x1 0x400 0x80>;
730 };
731 };
732 };
733 };
734
735 };
736
737 pci1: pcie@fffe09000 {
738 compatible = "fsl,mpc8548-pcie";
739 device_type = "pci";
740 #interrupt-cells = <1>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 reg = <0xf 0xffe09000 0 0x1000>;
744 bus-range = <0 255>;
745 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
746 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
747 clock-frequency = <33333333>;
748 interrupt-parent = <&mpic>;
749 interrupts = <25 2>;
750 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
751 interrupt-map = <
752 /* IDSEL 0x0 */
753 0000 0x0 0x0 0x1 &mpic 0x4 0x1
754 0000 0x0 0x0 0x2 &mpic 0x5 0x1
755 0000 0x0 0x0 0x3 &mpic 0x6 0x1
756 0000 0x0 0x0 0x4 &mpic 0x7 0x1
757 >;
758 pcie@0 {
759 reg = <0x0 0x0 0x0 0x0 0x0>;
760 #size-cells = <2>;
761 #address-cells = <3>;
762 device_type = "pci";
763 ranges = <0x2000000 0x0 0xe0000000
764 0x2000000 0x0 0xe0000000
765 0x0 0x20000000
766
767 0x1000000 0x0 0x0
768 0x1000000 0x0 0x0
769 0x0 0x10000>;
770 };
771 };
772
773 pci2: pcie@fffe0a000 {
774 compatible = "fsl,mpc8548-pcie";
775 device_type = "pci";
776 #interrupt-cells = <1>;
777 #size-cells = <2>;
778 #address-cells = <3>;
779 reg = <0xf 0xffe0a000 0 0x1000>;
780 bus-range = <0 255>;
781 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
782 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
783 clock-frequency = <33333333>;
784 interrupt-parent = <&mpic>;
785 interrupts = <26 2>;
786 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
787 interrupt-map = <
788 /* IDSEL 0x0 */
789 0000 0x0 0x0 0x1 &mpic 0x0 0x1
790 0000 0x0 0x0 0x2 &mpic 0x1 0x1
791 0000 0x0 0x0 0x3 &mpic 0x2 0x1
792 0000 0x0 0x0 0x4 &mpic 0x3 0x1
793 >;
794 pcie@0 {
795 reg = <0x0 0x0 0x0 0x0 0x0>;
796 #size-cells = <2>;
797 #address-cells = <3>;
798 device_type = "pci";
799 ranges = <0x2000000 0x0 0xe0000000
800 0x2000000 0x0 0xe0000000
801 0x0 0x20000000
802
803 0x1000000 0x0 0x0
804 0x1000000 0x0 0x0
805 0x0 0x10000>;
806 };
807 };
808};