/sound/soc/soc-cache.c

https://bitbucket.org/abioy/linux · C · 465 lines · 351 code · 78 blank · 36 comment · 52 complexity · a07b6c0025c54463fb2c648f118820e3 MD5 · raw file

  1. /*
  2. * soc-cache.c -- ASoC register cache helpers
  3. *
  4. * Copyright 2009 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/i2c.h>
  14. #include <linux/spi/spi.h>
  15. #include <sound/soc.h>
  16. static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
  17. unsigned int reg)
  18. {
  19. u16 *cache = codec->reg_cache;
  20. if (reg >= codec->reg_cache_size)
  21. return -1;
  22. return cache[reg];
  23. }
  24. static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
  25. unsigned int value)
  26. {
  27. u16 *cache = codec->reg_cache;
  28. u8 data[2];
  29. int ret;
  30. BUG_ON(codec->volatile_register);
  31. data[0] = (reg << 4) | ((value >> 8) & 0x000f);
  32. data[1] = value & 0x00ff;
  33. if (reg < codec->reg_cache_size)
  34. cache[reg] = value;
  35. if (codec->cache_only) {
  36. codec->cache_sync = 1;
  37. return 0;
  38. }
  39. ret = codec->hw_write(codec->control_data, data, 2);
  40. if (ret == 2)
  41. return 0;
  42. if (ret < 0)
  43. return ret;
  44. else
  45. return -EIO;
  46. }
  47. #if defined(CONFIG_SPI_MASTER)
  48. static int snd_soc_4_12_spi_write(void *control_data, const char *data,
  49. int len)
  50. {
  51. struct spi_device *spi = control_data;
  52. struct spi_transfer t;
  53. struct spi_message m;
  54. u8 msg[2];
  55. if (len <= 0)
  56. return 0;
  57. msg[0] = data[1];
  58. msg[1] = data[0];
  59. spi_message_init(&m);
  60. memset(&t, 0, (sizeof t));
  61. t.tx_buf = &msg[0];
  62. t.len = len;
  63. spi_message_add_tail(&t, &m);
  64. spi_sync(spi, &m);
  65. return len;
  66. }
  67. #else
  68. #define snd_soc_4_12_spi_write NULL
  69. #endif
  70. static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
  71. unsigned int reg)
  72. {
  73. u16 *cache = codec->reg_cache;
  74. if (reg >= codec->reg_cache_size)
  75. return -1;
  76. return cache[reg];
  77. }
  78. static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
  79. unsigned int value)
  80. {
  81. u16 *cache = codec->reg_cache;
  82. u8 data[2];
  83. int ret;
  84. BUG_ON(codec->volatile_register);
  85. data[0] = (reg << 1) | ((value >> 8) & 0x0001);
  86. data[1] = value & 0x00ff;
  87. if (reg < codec->reg_cache_size)
  88. cache[reg] = value;
  89. if (codec->cache_only) {
  90. codec->cache_sync = 1;
  91. return 0;
  92. }
  93. ret = codec->hw_write(codec->control_data, data, 2);
  94. if (ret == 2)
  95. return 0;
  96. if (ret < 0)
  97. return ret;
  98. else
  99. return -EIO;
  100. }
  101. #if defined(CONFIG_SPI_MASTER)
  102. static int snd_soc_7_9_spi_write(void *control_data, const char *data,
  103. int len)
  104. {
  105. struct spi_device *spi = control_data;
  106. struct spi_transfer t;
  107. struct spi_message m;
  108. u8 msg[2];
  109. if (len <= 0)
  110. return 0;
  111. msg[0] = data[0];
  112. msg[1] = data[1];
  113. spi_message_init(&m);
  114. memset(&t, 0, (sizeof t));
  115. t.tx_buf = &msg[0];
  116. t.len = len;
  117. spi_message_add_tail(&t, &m);
  118. spi_sync(spi, &m);
  119. return len;
  120. }
  121. #else
  122. #define snd_soc_7_9_spi_write NULL
  123. #endif
  124. static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
  125. unsigned int value)
  126. {
  127. u8 *cache = codec->reg_cache;
  128. u8 data[2];
  129. BUG_ON(codec->volatile_register);
  130. data[0] = reg & 0xff;
  131. data[1] = value & 0xff;
  132. if (reg < codec->reg_cache_size)
  133. cache[reg] = value;
  134. if (codec->cache_only) {
  135. codec->cache_sync = 1;
  136. return 0;
  137. }
  138. if (codec->hw_write(codec->control_data, data, 2) == 2)
  139. return 0;
  140. else
  141. return -EIO;
  142. }
  143. static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
  144. unsigned int reg)
  145. {
  146. u8 *cache = codec->reg_cache;
  147. if (reg >= codec->reg_cache_size)
  148. return -1;
  149. return cache[reg];
  150. }
  151. static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
  152. unsigned int value)
  153. {
  154. u16 *reg_cache = codec->reg_cache;
  155. u8 data[3];
  156. data[0] = reg;
  157. data[1] = (value >> 8) & 0xff;
  158. data[2] = value & 0xff;
  159. if (!snd_soc_codec_volatile_register(codec, reg))
  160. reg_cache[reg] = value;
  161. if (codec->cache_only) {
  162. codec->cache_sync = 1;
  163. return 0;
  164. }
  165. if (codec->hw_write(codec->control_data, data, 3) == 3)
  166. return 0;
  167. else
  168. return -EIO;
  169. }
  170. static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
  171. unsigned int reg)
  172. {
  173. u16 *cache = codec->reg_cache;
  174. if (reg >= codec->reg_cache_size ||
  175. snd_soc_codec_volatile_register(codec, reg)) {
  176. if (codec->cache_only)
  177. return -EINVAL;
  178. return codec->hw_read(codec, reg);
  179. } else {
  180. return cache[reg];
  181. }
  182. }
  183. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  184. static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
  185. unsigned int r)
  186. {
  187. struct i2c_msg xfer[2];
  188. u8 reg = r;
  189. u16 data;
  190. int ret;
  191. struct i2c_client *client = codec->control_data;
  192. /* Write register */
  193. xfer[0].addr = client->addr;
  194. xfer[0].flags = 0;
  195. xfer[0].len = 1;
  196. xfer[0].buf = &reg;
  197. /* Read data */
  198. xfer[1].addr = client->addr;
  199. xfer[1].flags = I2C_M_RD;
  200. xfer[1].len = 2;
  201. xfer[1].buf = (u8 *)&data;
  202. ret = i2c_transfer(client->adapter, xfer, 2);
  203. if (ret != 2) {
  204. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  205. return 0;
  206. }
  207. return (data >> 8) | ((data & 0xff) << 8);
  208. }
  209. #else
  210. #define snd_soc_8_16_read_i2c NULL
  211. #endif
  212. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  213. static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
  214. unsigned int r)
  215. {
  216. struct i2c_msg xfer[2];
  217. u16 reg = r;
  218. u8 data;
  219. int ret;
  220. struct i2c_client *client = codec->control_data;
  221. /* Write register */
  222. xfer[0].addr = client->addr;
  223. xfer[0].flags = 0;
  224. xfer[0].len = 2;
  225. xfer[0].buf = (u8 *)&reg;
  226. /* Read data */
  227. xfer[1].addr = client->addr;
  228. xfer[1].flags = I2C_M_RD;
  229. xfer[1].len = 1;
  230. xfer[1].buf = &data;
  231. ret = i2c_transfer(client->adapter, xfer, 2);
  232. if (ret != 2) {
  233. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  234. return 0;
  235. }
  236. return data;
  237. }
  238. #else
  239. #define snd_soc_16_8_read_i2c NULL
  240. #endif
  241. static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
  242. unsigned int reg)
  243. {
  244. u16 *cache = codec->reg_cache;
  245. reg &= 0xff;
  246. if (reg >= codec->reg_cache_size)
  247. return -1;
  248. return cache[reg];
  249. }
  250. static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
  251. unsigned int value)
  252. {
  253. u16 *cache = codec->reg_cache;
  254. u8 data[3];
  255. int ret;
  256. BUG_ON(codec->volatile_register);
  257. data[0] = (reg >> 8) & 0xff;
  258. data[1] = reg & 0xff;
  259. data[2] = value;
  260. reg &= 0xff;
  261. if (reg < codec->reg_cache_size)
  262. cache[reg] = value;
  263. if (codec->cache_only) {
  264. codec->cache_sync = 1;
  265. return 0;
  266. }
  267. ret = codec->hw_write(codec->control_data, data, 3);
  268. if (ret == 3)
  269. return 0;
  270. if (ret < 0)
  271. return ret;
  272. else
  273. return -EIO;
  274. }
  275. #if defined(CONFIG_SPI_MASTER)
  276. static int snd_soc_16_8_spi_write(void *control_data, const char *data,
  277. int len)
  278. {
  279. struct spi_device *spi = control_data;
  280. struct spi_transfer t;
  281. struct spi_message m;
  282. u8 msg[3];
  283. if (len <= 0)
  284. return 0;
  285. msg[0] = data[0];
  286. msg[1] = data[1];
  287. msg[2] = data[2];
  288. spi_message_init(&m);
  289. memset(&t, 0, (sizeof t));
  290. t.tx_buf = &msg[0];
  291. t.len = len;
  292. spi_message_add_tail(&t, &m);
  293. spi_sync(spi, &m);
  294. return len;
  295. }
  296. #else
  297. #define snd_soc_16_8_spi_write NULL
  298. #endif
  299. static struct {
  300. int addr_bits;
  301. int data_bits;
  302. int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
  303. int (*spi_write)(void *, const char *, int);
  304. unsigned int (*read)(struct snd_soc_codec *, unsigned int);
  305. unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
  306. } io_types[] = {
  307. {
  308. .addr_bits = 4, .data_bits = 12,
  309. .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
  310. .spi_write = snd_soc_4_12_spi_write,
  311. },
  312. {
  313. .addr_bits = 7, .data_bits = 9,
  314. .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
  315. .spi_write = snd_soc_7_9_spi_write,
  316. },
  317. {
  318. .addr_bits = 8, .data_bits = 8,
  319. .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
  320. },
  321. {
  322. .addr_bits = 8, .data_bits = 16,
  323. .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
  324. .i2c_read = snd_soc_8_16_read_i2c,
  325. },
  326. {
  327. .addr_bits = 16, .data_bits = 8,
  328. .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
  329. .i2c_read = snd_soc_16_8_read_i2c,
  330. .spi_write = snd_soc_16_8_spi_write,
  331. },
  332. };
  333. /**
  334. * snd_soc_codec_set_cache_io: Set up standard I/O functions.
  335. *
  336. * @codec: CODEC to configure.
  337. * @type: Type of cache.
  338. * @addr_bits: Number of bits of register address data.
  339. * @data_bits: Number of bits of data per register.
  340. * @control: Control bus used.
  341. *
  342. * Register formats are frequently shared between many I2C and SPI
  343. * devices. In order to promote code reuse the ASoC core provides
  344. * some standard implementations of CODEC read and write operations
  345. * which can be set up using this function.
  346. *
  347. * The caller is responsible for allocating and initialising the
  348. * actual cache.
  349. *
  350. * Note that at present this code cannot be used by CODECs with
  351. * volatile registers.
  352. */
  353. int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
  354. int addr_bits, int data_bits,
  355. enum snd_soc_control_type control)
  356. {
  357. int i;
  358. for (i = 0; i < ARRAY_SIZE(io_types); i++)
  359. if (io_types[i].addr_bits == addr_bits &&
  360. io_types[i].data_bits == data_bits)
  361. break;
  362. if (i == ARRAY_SIZE(io_types)) {
  363. printk(KERN_ERR
  364. "No I/O functions for %d bit address %d bit data\n",
  365. addr_bits, data_bits);
  366. return -EINVAL;
  367. }
  368. codec->write = io_types[i].write;
  369. codec->read = io_types[i].read;
  370. switch (control) {
  371. case SND_SOC_CUSTOM:
  372. break;
  373. case SND_SOC_I2C:
  374. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  375. codec->hw_write = (hw_write_t)i2c_master_send;
  376. #endif
  377. if (io_types[i].i2c_read)
  378. codec->hw_read = io_types[i].i2c_read;
  379. break;
  380. case SND_SOC_SPI:
  381. if (io_types[i].spi_write)
  382. codec->hw_write = io_types[i].spi_write;
  383. break;
  384. }
  385. return 0;
  386. }
  387. EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);