/sound/soc/codecs/wm8978.c

https://bitbucket.org/abioy/linux · C · 1150 lines · 809 code · 198 blank · 143 comment · 75 complexity · 5c6b3b465b501224e29cd91f4ac97331 MD5 · raw file

  1. /*
  2. * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
  3. *
  4. * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
  6. * Copyright 2006-2009 Wolfson Microelectronics PLC.
  7. * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/pm.h>
  19. #include <linux/i2c.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/slab.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <asm/div64.h>
  30. #include "wm8978.h"
  31. static struct snd_soc_codec *wm8978_codec;
  32. /* wm8978 register cache. Note that register 0 is not included in the cache. */
  33. static const u16 wm8978_reg[WM8978_CACHEREGNUM] = {
  34. 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */
  35. 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */
  36. 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */
  37. 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */
  38. 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */
  39. 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */
  40. 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */
  41. 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */
  42. 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */
  43. 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */
  44. 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */
  45. 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */
  46. 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */
  47. 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */
  48. 0x0001, 0x0001, /* 0x38...0x3b */
  49. };
  50. /* codec private data */
  51. struct wm8978_priv {
  52. struct snd_soc_codec codec;
  53. unsigned int f_pllout;
  54. unsigned int f_mclk;
  55. unsigned int f_256fs;
  56. unsigned int f_opclk;
  57. int mclk_idx;
  58. enum wm8978_sysclk_src sysclk;
  59. u16 reg_cache[WM8978_CACHEREGNUM];
  60. };
  61. static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
  62. static const char *wm8978_eqmode[] = {"Capture", "Playback"};
  63. static const char *wm8978_bw[] = {"Narrow", "Wide"};
  64. static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
  65. static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
  66. static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
  67. static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
  68. static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
  69. static const char *wm8978_alc3[] = {"ALC", "Limiter"};
  70. static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
  71. static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
  72. wm8978_companding);
  73. static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
  74. wm8978_companding);
  75. static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
  76. static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
  77. static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
  78. static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
  79. static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
  80. static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
  81. static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
  82. static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
  83. static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
  84. static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
  85. static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
  86. static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
  87. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  88. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
  89. static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
  90. static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
  91. static const struct snd_kcontrol_new wm8978_snd_controls[] = {
  92. SOC_SINGLE("Digital Loopback Switch",
  93. WM8978_COMPANDING_CONTROL, 0, 1, 0),
  94. SOC_ENUM("ADC Companding", adc_compand),
  95. SOC_ENUM("DAC Companding", dac_compand),
  96. SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
  97. SOC_DOUBLE_R_TLV("PCM Volume",
  98. WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
  99. 0, 255, 0, digital_tlv),
  100. SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
  101. SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
  102. SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
  103. SOC_DOUBLE_R_TLV("ADC Volume",
  104. WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
  105. 0, 255, 0, digital_tlv),
  106. SOC_ENUM("Equaliser Function", eqmode),
  107. SOC_ENUM("EQ1 Cut Off", eq1),
  108. SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv),
  109. SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw),
  110. SOC_ENUM("EQ2 Cut Off", eq2),
  111. SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv),
  112. SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw),
  113. SOC_ENUM("EQ3 Cut Off", eq3),
  114. SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv),
  115. SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw),
  116. SOC_ENUM("EQ4 Cut Off", eq4),
  117. SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv),
  118. SOC_ENUM("EQ5 Cut Off", eq5),
  119. SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
  120. SOC_SINGLE("DAC Playback Limiter Switch",
  121. WM8978_DAC_LIMITER_1, 8, 1, 0),
  122. SOC_SINGLE("DAC Playback Limiter Decay",
  123. WM8978_DAC_LIMITER_1, 4, 15, 0),
  124. SOC_SINGLE("DAC Playback Limiter Attack",
  125. WM8978_DAC_LIMITER_1, 0, 15, 0),
  126. SOC_SINGLE("DAC Playback Limiter Threshold",
  127. WM8978_DAC_LIMITER_2, 4, 7, 0),
  128. SOC_SINGLE("DAC Playback Limiter Boost",
  129. WM8978_DAC_LIMITER_2, 0, 15, 0),
  130. SOC_ENUM("ALC Enable Switch", alc1),
  131. SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
  132. SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
  133. SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 7, 0),
  134. SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
  135. SOC_ENUM("ALC Capture Mode", alc3),
  136. SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 15, 0),
  137. SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 15, 0),
  138. SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
  139. SOC_SINGLE("ALC Capture Noise Gate Threshold",
  140. WM8978_NOISE_GATE, 0, 7, 0),
  141. SOC_DOUBLE_R("Capture PGA ZC Switch",
  142. WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
  143. 7, 1, 0),
  144. /* OUT1 - Headphones */
  145. SOC_DOUBLE_R("Headphone Playback ZC Switch",
  146. WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
  147. SOC_DOUBLE_R_TLV("Headphone Playback Volume",
  148. WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
  149. 0, 63, 0, spk_tlv),
  150. /* OUT2 - Speakers */
  151. SOC_DOUBLE_R("Speaker Playback ZC Switch",
  152. WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
  153. SOC_DOUBLE_R_TLV("Speaker Playback Volume",
  154. WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
  155. 0, 63, 0, spk_tlv),
  156. /* OUT3/4 - Line Output */
  157. SOC_DOUBLE_R("Line Playback Switch",
  158. WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
  159. /* Mixer #3: Boost (Input) mixer */
  160. SOC_DOUBLE_R("PGA Boost (+20dB)",
  161. WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
  162. 8, 1, 0),
  163. SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
  164. WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
  165. 4, 7, 0, boost_tlv),
  166. SOC_DOUBLE_R_TLV("Aux Boost Volume",
  167. WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
  168. 0, 7, 0, boost_tlv),
  169. /* Input PGA volume */
  170. SOC_DOUBLE_R_TLV("Input PGA Volume",
  171. WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
  172. 0, 63, 0, inpga_tlv),
  173. /* Headphone */
  174. SOC_DOUBLE_R("Headphone Switch",
  175. WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
  176. /* Speaker */
  177. SOC_DOUBLE_R("Speaker Switch",
  178. WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
  179. /* DAC / ADC oversampling */
  180. SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL, 8, 1, 0),
  181. SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL, 8, 1, 0),
  182. };
  183. /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
  184. static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
  185. SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
  186. SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
  187. SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
  188. };
  189. static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
  190. SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
  191. SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
  192. SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
  193. };
  194. /* OUT3/OUT4 Mixer not implemented */
  195. /* Mixer #2: Input PGA Mute */
  196. static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
  197. SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
  198. SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
  199. SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
  200. };
  201. static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
  202. SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
  203. SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
  204. SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
  205. };
  206. static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
  207. SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
  208. WM8978_POWER_MANAGEMENT_3, 0, 0),
  209. SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
  210. WM8978_POWER_MANAGEMENT_3, 1, 0),
  211. SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
  212. WM8978_POWER_MANAGEMENT_2, 0, 0),
  213. SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
  214. WM8978_POWER_MANAGEMENT_2, 1, 0),
  215. /* Mixer #1: OUT1,2 */
  216. SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
  217. 2, 0, wm8978_left_out_mixer),
  218. SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
  219. 3, 0, wm8978_right_out_mixer),
  220. SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
  221. 2, 0, wm8978_left_input_mixer),
  222. SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
  223. 3, 0, wm8978_right_input_mixer),
  224. SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
  225. 4, 0, NULL, 0),
  226. SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
  227. 5, 0, NULL, 0),
  228. SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
  229. 6, 1, NULL, 0),
  230. SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
  231. 6, 1, NULL, 0),
  232. SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
  233. 7, 0, NULL, 0),
  234. SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
  235. 8, 0, NULL, 0),
  236. SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
  237. 6, 0, NULL, 0),
  238. SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
  239. 5, 0, NULL, 0),
  240. SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
  241. 8, 0, NULL, 0),
  242. SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
  243. SND_SOC_DAPM_INPUT("LMICN"),
  244. SND_SOC_DAPM_INPUT("LMICP"),
  245. SND_SOC_DAPM_INPUT("RMICN"),
  246. SND_SOC_DAPM_INPUT("RMICP"),
  247. SND_SOC_DAPM_INPUT("LAUX"),
  248. SND_SOC_DAPM_INPUT("RAUX"),
  249. SND_SOC_DAPM_INPUT("L2"),
  250. SND_SOC_DAPM_INPUT("R2"),
  251. SND_SOC_DAPM_OUTPUT("LHP"),
  252. SND_SOC_DAPM_OUTPUT("RHP"),
  253. SND_SOC_DAPM_OUTPUT("LSPK"),
  254. SND_SOC_DAPM_OUTPUT("RSPK"),
  255. };
  256. static const struct snd_soc_dapm_route audio_map[] = {
  257. /* Output mixer */
  258. {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
  259. {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
  260. {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
  261. {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
  262. {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
  263. {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
  264. /* Outputs */
  265. {"Right Headphone Out", NULL, "Right Output Mixer"},
  266. {"RHP", NULL, "Right Headphone Out"},
  267. {"Left Headphone Out", NULL, "Left Output Mixer"},
  268. {"LHP", NULL, "Left Headphone Out"},
  269. {"Right Speaker Out", NULL, "Right Output Mixer"},
  270. {"RSPK", NULL, "Right Speaker Out"},
  271. {"Left Speaker Out", NULL, "Left Output Mixer"},
  272. {"LSPK", NULL, "Left Speaker Out"},
  273. /* Boost Mixer */
  274. {"Right ADC", NULL, "Right Boost Mixer"},
  275. {"Right Boost Mixer", NULL, "RAUX"},
  276. {"Right Boost Mixer", NULL, "Right Capture PGA"},
  277. {"Right Boost Mixer", NULL, "R2"},
  278. {"Left ADC", NULL, "Left Boost Mixer"},
  279. {"Left Boost Mixer", NULL, "LAUX"},
  280. {"Left Boost Mixer", NULL, "Left Capture PGA"},
  281. {"Left Boost Mixer", NULL, "L2"},
  282. /* Input PGA */
  283. {"Right Capture PGA", NULL, "Right Input Mixer"},
  284. {"Left Capture PGA", NULL, "Left Input Mixer"},
  285. {"Right Input Mixer", "R2 Switch", "R2"},
  286. {"Right Input Mixer", "MicN Switch", "RMICN"},
  287. {"Right Input Mixer", "MicP Switch", "RMICP"},
  288. {"Left Input Mixer", "L2 Switch", "L2"},
  289. {"Left Input Mixer", "MicN Switch", "LMICN"},
  290. {"Left Input Mixer", "MicP Switch", "LMICP"},
  291. };
  292. static int wm8978_add_widgets(struct snd_soc_codec *codec)
  293. {
  294. snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets,
  295. ARRAY_SIZE(wm8978_dapm_widgets));
  296. /* set up the WM8978 audio map */
  297. snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
  298. return 0;
  299. }
  300. /* PLL divisors */
  301. struct wm8978_pll_div {
  302. u32 k;
  303. u8 n;
  304. u8 div2;
  305. };
  306. #define FIXED_PLL_SIZE (1 << 24)
  307. static void pll_factors(struct wm8978_pll_div *pll_div, unsigned int target,
  308. unsigned int source)
  309. {
  310. u64 k_part;
  311. unsigned int k, n_div, n_mod;
  312. n_div = target / source;
  313. if (n_div < 6) {
  314. source >>= 1;
  315. pll_div->div2 = 1;
  316. n_div = target / source;
  317. } else {
  318. pll_div->div2 = 0;
  319. }
  320. if (n_div < 6 || n_div > 12)
  321. dev_warn(wm8978_codec->dev,
  322. "WM8978 N value exceeds recommended range! N = %u\n",
  323. n_div);
  324. pll_div->n = n_div;
  325. n_mod = target - source * n_div;
  326. k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
  327. do_div(k_part, source);
  328. k = k_part & 0xFFFFFFFF;
  329. pll_div->k = k;
  330. }
  331. /* MCLK dividers */
  332. static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12};
  333. static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1};
  334. /*
  335. * find index >= idx, such that, for a given f_out,
  336. * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
  337. * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
  338. * generalised for f_opclk with suitable coefficient arrays, but currently
  339. * the OPCLK divisor is calculated directly, not iteratively.
  340. */
  341. static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
  342. unsigned int *f_pllout)
  343. {
  344. int i;
  345. for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
  346. unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
  347. mclk_denominator[i];
  348. if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
  349. *f_pllout = f_pllout_x4 / 4;
  350. return i;
  351. }
  352. }
  353. return -EINVAL;
  354. }
  355. /*
  356. * Calculate internal frequencies and dividers, according to Figure 40
  357. * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
  358. */
  359. static int wm8978_configure_pll(struct snd_soc_codec *codec)
  360. {
  361. struct wm8978_priv *wm8978 = codec->private_data;
  362. struct wm8978_pll_div pll_div;
  363. unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
  364. f_256fs = wm8978->f_256fs;
  365. unsigned int f2;
  366. if (!f_mclk)
  367. return -EINVAL;
  368. if (f_opclk) {
  369. unsigned int opclk_div;
  370. /* Cannot set up MCLK divider now, do later */
  371. wm8978->mclk_idx = -1;
  372. /*
  373. * The user needs OPCLK. Choose OPCLKDIV to put
  374. * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
  375. * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
  376. * prescale = 1, or prescale = 2. Prescale is calculated inside
  377. * pll_factors(). We have to select f_PLLOUT, such that
  378. * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
  379. * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
  380. */
  381. if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
  382. return -EINVAL;
  383. if (4 * f_opclk < 3 * f_mclk)
  384. /* Have to use OPCLKDIV */
  385. opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
  386. else
  387. opclk_div = 1;
  388. dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
  389. snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
  390. (opclk_div - 1) << 4);
  391. wm8978->f_pllout = f_opclk * opclk_div;
  392. } else if (f_256fs) {
  393. /*
  394. * Not using OPCLK, but PLL is used for the codec, choose R:
  395. * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
  396. * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
  397. * prescale = 1, or prescale = 2. Prescale is calculated inside
  398. * pll_factors(). We have to select f_PLLOUT, such that
  399. * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
  400. * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
  401. * must be 3.781MHz <= f_MCLK <= 32.768MHz
  402. */
  403. int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
  404. if (idx < 0)
  405. return idx;
  406. wm8978->mclk_idx = idx;
  407. /* GPIO1 into default mode as input - before configuring PLL */
  408. snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
  409. } else {
  410. return -EINVAL;
  411. }
  412. f2 = wm8978->f_pllout * 4;
  413. dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
  414. wm8978->f_mclk, wm8978->f_pllout);
  415. pll_factors(&pll_div, f2, wm8978->f_mclk);
  416. dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
  417. __func__, pll_div.n, pll_div.k, pll_div.div2);
  418. /* Turn PLL off for configuration... */
  419. snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
  420. snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
  421. snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18);
  422. snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
  423. snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff);
  424. /* ...and on again */
  425. snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
  426. if (f_opclk)
  427. /* Output PLL (OPCLK) to GPIO1 */
  428. snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4);
  429. return 0;
  430. }
  431. /*
  432. * Configure WM8978 clock dividers.
  433. */
  434. static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
  435. int div_id, int div)
  436. {
  437. struct snd_soc_codec *codec = codec_dai->codec;
  438. struct wm8978_priv *wm8978 = codec->private_data;
  439. int ret = 0;
  440. switch (div_id) {
  441. case WM8978_OPCLKRATE:
  442. wm8978->f_opclk = div;
  443. if (wm8978->f_mclk)
  444. /*
  445. * We know the MCLK frequency, the user has requested
  446. * OPCLK, configure the PLL based on that and start it
  447. * and OPCLK immediately. We will configure PLL to match
  448. * user-requested OPCLK frquency as good as possible.
  449. * In fact, it is likely, that matching the sampling
  450. * rate, when it becomes known, is more important, and
  451. * we will not be reconfiguring PLL then, because we
  452. * must not interrupt OPCLK. But it should be fine,
  453. * because typically the user will request OPCLK to run
  454. * at 256fs or 512fs, and for these cases we will also
  455. * find an exact MCLK divider configuration - it will
  456. * be equal to or double the OPCLK divisor.
  457. */
  458. ret = wm8978_configure_pll(codec);
  459. break;
  460. case WM8978_BCLKDIV:
  461. if (div & ~0x1c)
  462. return -EINVAL;
  463. snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div);
  464. break;
  465. default:
  466. return -EINVAL;
  467. }
  468. dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
  469. return ret;
  470. }
  471. /*
  472. * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
  473. */
  474. static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
  475. unsigned int freq, int dir)
  476. {
  477. struct snd_soc_codec *codec = codec_dai->codec;
  478. struct wm8978_priv *wm8978 = codec->private_data;
  479. int ret = 0;
  480. dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
  481. if (freq) {
  482. wm8978->f_mclk = freq;
  483. /* Even if MCLK is used for system clock, might have to drive OPCLK */
  484. if (wm8978->f_opclk)
  485. ret = wm8978_configure_pll(codec);
  486. /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
  487. if (!ret)
  488. wm8978->sysclk = clk_id;
  489. }
  490. if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
  491. /* Clock CODEC directly from MCLK */
  492. snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
  493. /* GPIO1 into default mode as input - before configuring PLL */
  494. snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
  495. /* Turn off PLL */
  496. snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
  497. wm8978->sysclk = WM8978_MCLK;
  498. wm8978->f_pllout = 0;
  499. wm8978->f_opclk = 0;
  500. }
  501. return ret;
  502. }
  503. /*
  504. * Set ADC and Voice DAC format.
  505. */
  506. static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  507. {
  508. struct snd_soc_codec *codec = codec_dai->codec;
  509. /*
  510. * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
  511. * Data Format mask = 0x18: all will be calculated anew
  512. */
  513. u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198;
  514. u16 clk = snd_soc_read(codec, WM8978_CLOCKING);
  515. dev_dbg(codec->dev, "%s\n", __func__);
  516. /* set master/slave audio interface */
  517. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  518. case SND_SOC_DAIFMT_CBM_CFM:
  519. clk |= 1;
  520. break;
  521. case SND_SOC_DAIFMT_CBS_CFS:
  522. clk &= ~1;
  523. break;
  524. default:
  525. return -EINVAL;
  526. }
  527. /* interface format */
  528. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  529. case SND_SOC_DAIFMT_I2S:
  530. iface |= 0x10;
  531. break;
  532. case SND_SOC_DAIFMT_RIGHT_J:
  533. break;
  534. case SND_SOC_DAIFMT_LEFT_J:
  535. iface |= 0x8;
  536. break;
  537. case SND_SOC_DAIFMT_DSP_A:
  538. iface |= 0x18;
  539. break;
  540. default:
  541. return -EINVAL;
  542. }
  543. /* clock inversion */
  544. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  545. case SND_SOC_DAIFMT_NB_NF:
  546. break;
  547. case SND_SOC_DAIFMT_IB_IF:
  548. iface |= 0x180;
  549. break;
  550. case SND_SOC_DAIFMT_IB_NF:
  551. iface |= 0x100;
  552. break;
  553. case SND_SOC_DAIFMT_NB_IF:
  554. iface |= 0x80;
  555. break;
  556. default:
  557. return -EINVAL;
  558. }
  559. snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface);
  560. snd_soc_write(codec, WM8978_CLOCKING, clk);
  561. return 0;
  562. }
  563. /*
  564. * Set PCM DAI bit size and sample rate.
  565. */
  566. static int wm8978_hw_params(struct snd_pcm_substream *substream,
  567. struct snd_pcm_hw_params *params,
  568. struct snd_soc_dai *dai)
  569. {
  570. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  571. struct snd_soc_device *socdev = rtd->socdev;
  572. struct snd_soc_codec *codec = socdev->card->codec;
  573. struct wm8978_priv *wm8978 = codec->private_data;
  574. /* Word length mask = 0x60 */
  575. u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
  576. /* Sampling rate mask = 0xe (for filters) */
  577. u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe;
  578. u16 clking = snd_soc_read(codec, WM8978_CLOCKING);
  579. enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
  580. WM8978_PLL : WM8978_MCLK;
  581. unsigned int f_sel, diff, diff_best = INT_MAX;
  582. int i, best = 0;
  583. if (!wm8978->f_mclk)
  584. return -EINVAL;
  585. /* bit size */
  586. switch (params_format(params)) {
  587. case SNDRV_PCM_FORMAT_S16_LE:
  588. break;
  589. case SNDRV_PCM_FORMAT_S20_3LE:
  590. iface_ctl |= 0x20;
  591. break;
  592. case SNDRV_PCM_FORMAT_S24_LE:
  593. iface_ctl |= 0x40;
  594. break;
  595. case SNDRV_PCM_FORMAT_S32_LE:
  596. iface_ctl |= 0x60;
  597. break;
  598. }
  599. /* filter coefficient */
  600. switch (params_rate(params)) {
  601. case 8000:
  602. add_ctl |= 0x5 << 1;
  603. break;
  604. case 11025:
  605. add_ctl |= 0x4 << 1;
  606. break;
  607. case 16000:
  608. add_ctl |= 0x3 << 1;
  609. break;
  610. case 22050:
  611. add_ctl |= 0x2 << 1;
  612. break;
  613. case 32000:
  614. add_ctl |= 0x1 << 1;
  615. break;
  616. case 44100:
  617. case 48000:
  618. break;
  619. }
  620. /* Sampling rate is known now, can configure the MCLK divider */
  621. wm8978->f_256fs = params_rate(params) * 256;
  622. if (wm8978->sysclk == WM8978_MCLK) {
  623. wm8978->mclk_idx = -1;
  624. f_sel = wm8978->f_mclk;
  625. } else {
  626. if (!wm8978->f_pllout) {
  627. /* We only enter here, if OPCLK is not used */
  628. int ret = wm8978_configure_pll(codec);
  629. if (ret < 0)
  630. return ret;
  631. }
  632. f_sel = wm8978->f_pllout;
  633. }
  634. if (wm8978->mclk_idx < 0) {
  635. /* Either MCLK is used directly, or OPCLK is used */
  636. if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
  637. return -EINVAL;
  638. for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
  639. diff = abs(wm8978->f_256fs * 3 -
  640. f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
  641. if (diff < diff_best) {
  642. diff_best = diff;
  643. best = i;
  644. }
  645. if (!diff)
  646. break;
  647. }
  648. } else {
  649. /* OPCLK not used, codec driven by PLL */
  650. best = wm8978->mclk_idx;
  651. diff = 0;
  652. }
  653. if (diff)
  654. dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n",
  655. f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
  656. wm8978->sysclk == WM8978_MCLK ?
  657. ", consider using PLL" : "");
  658. dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__,
  659. params_format(params), params_rate(params), best);
  660. /* MCLK divisor mask = 0xe0 */
  661. snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5);
  662. snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl);
  663. snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl);
  664. if (wm8978->sysclk != current_clk_id) {
  665. if (wm8978->sysclk == WM8978_PLL)
  666. /* Run CODEC from PLL instead of MCLK */
  667. snd_soc_update_bits(codec, WM8978_CLOCKING,
  668. 0x100, 0x100);
  669. else
  670. /* Clock CODEC directly from MCLK */
  671. snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
  672. }
  673. return 0;
  674. }
  675. static int wm8978_mute(struct snd_soc_dai *dai, int mute)
  676. {
  677. struct snd_soc_codec *codec = dai->codec;
  678. dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
  679. if (mute)
  680. snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40);
  681. else
  682. snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0);
  683. return 0;
  684. }
  685. static int wm8978_set_bias_level(struct snd_soc_codec *codec,
  686. enum snd_soc_bias_level level)
  687. {
  688. u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3;
  689. switch (level) {
  690. case SND_SOC_BIAS_ON:
  691. case SND_SOC_BIAS_PREPARE:
  692. power1 |= 1; /* VMID 75k */
  693. snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
  694. break;
  695. case SND_SOC_BIAS_STANDBY:
  696. /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
  697. power1 |= 0xc;
  698. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  699. /* Initial cap charge at VMID 5k */
  700. snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
  701. power1 | 0x3);
  702. mdelay(100);
  703. }
  704. power1 |= 0x2; /* VMID 500k */
  705. snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
  706. break;
  707. case SND_SOC_BIAS_OFF:
  708. /* Preserve PLL - OPCLK may be used by someone */
  709. snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
  710. snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0);
  711. snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0);
  712. break;
  713. }
  714. dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
  715. codec->bias_level = level;
  716. return 0;
  717. }
  718. #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  719. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  720. static struct snd_soc_dai_ops wm8978_dai_ops = {
  721. .hw_params = wm8978_hw_params,
  722. .digital_mute = wm8978_mute,
  723. .set_fmt = wm8978_set_dai_fmt,
  724. .set_clkdiv = wm8978_set_dai_clkdiv,
  725. .set_sysclk = wm8978_set_dai_sysclk,
  726. };
  727. /* Also supports 12kHz */
  728. struct snd_soc_dai wm8978_dai = {
  729. .name = "WM8978 HiFi",
  730. .id = 1,
  731. .playback = {
  732. .stream_name = "Playback",
  733. .channels_min = 1,
  734. .channels_max = 2,
  735. .rates = SNDRV_PCM_RATE_8000_48000,
  736. .formats = WM8978_FORMATS,
  737. },
  738. .capture = {
  739. .stream_name = "Capture",
  740. .channels_min = 1,
  741. .channels_max = 2,
  742. .rates = SNDRV_PCM_RATE_8000_48000,
  743. .formats = WM8978_FORMATS,
  744. },
  745. .ops = &wm8978_dai_ops,
  746. };
  747. EXPORT_SYMBOL_GPL(wm8978_dai);
  748. static int wm8978_suspend(struct platform_device *pdev, pm_message_t state)
  749. {
  750. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  751. struct snd_soc_codec *codec = socdev->card->codec;
  752. wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
  753. /* Also switch PLL off */
  754. snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
  755. return 0;
  756. }
  757. static int wm8978_resume(struct platform_device *pdev)
  758. {
  759. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  760. struct snd_soc_codec *codec = socdev->card->codec;
  761. struct wm8978_priv *wm8978 = codec->private_data;
  762. int i;
  763. u16 *cache = codec->reg_cache;
  764. /* Sync reg_cache with the hardware */
  765. for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) {
  766. if (i == WM8978_RESET)
  767. continue;
  768. if (cache[i] != wm8978_reg[i])
  769. snd_soc_write(codec, i, cache[i]);
  770. }
  771. wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  772. if (wm8978->f_pllout)
  773. /* Switch PLL on */
  774. snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
  775. return 0;
  776. }
  777. static int wm8978_probe(struct platform_device *pdev)
  778. {
  779. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  780. struct snd_soc_codec *codec;
  781. int ret = 0;
  782. if (wm8978_codec == NULL) {
  783. dev_err(&pdev->dev, "Codec device not registered\n");
  784. return -ENODEV;
  785. }
  786. socdev->card->codec = wm8978_codec;
  787. codec = wm8978_codec;
  788. /* register pcms */
  789. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  790. if (ret < 0) {
  791. dev_err(codec->dev, "failed to create pcms: %d\n", ret);
  792. goto pcm_err;
  793. }
  794. snd_soc_add_controls(codec, wm8978_snd_controls,
  795. ARRAY_SIZE(wm8978_snd_controls));
  796. wm8978_add_widgets(codec);
  797. pcm_err:
  798. return ret;
  799. }
  800. /* power down chip */
  801. static int wm8978_remove(struct platform_device *pdev)
  802. {
  803. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  804. snd_soc_free_pcms(socdev);
  805. snd_soc_dapm_free(socdev);
  806. return 0;
  807. }
  808. struct snd_soc_codec_device soc_codec_dev_wm8978 = {
  809. .probe = wm8978_probe,
  810. .remove = wm8978_remove,
  811. .suspend = wm8978_suspend,
  812. .resume = wm8978_resume,
  813. };
  814. EXPORT_SYMBOL_GPL(soc_codec_dev_wm8978);
  815. /*
  816. * These registers contain an "update" bit - bit 8. This means, for example,
  817. * that one can write new DAC digital volume for both channels, but only when
  818. * the update bit is set, will also the volume be updated - simultaneously for
  819. * both channels.
  820. */
  821. static const int update_reg[] = {
  822. WM8978_LEFT_DAC_DIGITAL_VOLUME,
  823. WM8978_RIGHT_DAC_DIGITAL_VOLUME,
  824. WM8978_LEFT_ADC_DIGITAL_VOLUME,
  825. WM8978_RIGHT_ADC_DIGITAL_VOLUME,
  826. WM8978_LEFT_INP_PGA_CONTROL,
  827. WM8978_RIGHT_INP_PGA_CONTROL,
  828. WM8978_LOUT1_HP_CONTROL,
  829. WM8978_ROUT1_HP_CONTROL,
  830. WM8978_LOUT2_SPK_CONTROL,
  831. WM8978_ROUT2_SPK_CONTROL,
  832. };
  833. static __devinit int wm8978_register(struct wm8978_priv *wm8978)
  834. {
  835. int ret, i;
  836. struct snd_soc_codec *codec = &wm8978->codec;
  837. if (wm8978_codec) {
  838. dev_err(codec->dev, "Another WM8978 is registered\n");
  839. return -EINVAL;
  840. }
  841. /*
  842. * Set default system clock to PLL, it is more precise, this is also the
  843. * default hardware setting
  844. */
  845. wm8978->sysclk = WM8978_PLL;
  846. mutex_init(&codec->mutex);
  847. INIT_LIST_HEAD(&codec->dapm_widgets);
  848. INIT_LIST_HEAD(&codec->dapm_paths);
  849. codec->private_data = wm8978;
  850. codec->name = "WM8978";
  851. codec->owner = THIS_MODULE;
  852. codec->bias_level = SND_SOC_BIAS_OFF;
  853. codec->set_bias_level = wm8978_set_bias_level;
  854. codec->dai = &wm8978_dai;
  855. codec->num_dai = 1;
  856. codec->reg_cache_size = WM8978_CACHEREGNUM;
  857. codec->reg_cache = &wm8978->reg_cache;
  858. ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
  859. if (ret < 0) {
  860. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  861. goto err;
  862. }
  863. memcpy(codec->reg_cache, wm8978_reg, sizeof(wm8978_reg));
  864. /*
  865. * Set the update bit in all registers, that have one. This way all
  866. * writes to those registers will also cause the update bit to be
  867. * written.
  868. */
  869. for (i = 0; i < ARRAY_SIZE(update_reg); i++)
  870. ((u16 *)codec->reg_cache)[update_reg[i]] |= 0x100;
  871. /* Reset the codec */
  872. ret = snd_soc_write(codec, WM8978_RESET, 0);
  873. if (ret < 0) {
  874. dev_err(codec->dev, "Failed to issue reset\n");
  875. goto err;
  876. }
  877. wm8978_dai.dev = codec->dev;
  878. wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  879. wm8978_codec = codec;
  880. ret = snd_soc_register_codec(codec);
  881. if (ret != 0) {
  882. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  883. goto err;
  884. }
  885. ret = snd_soc_register_dai(&wm8978_dai);
  886. if (ret != 0) {
  887. dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
  888. goto err_codec;
  889. }
  890. return 0;
  891. err_codec:
  892. snd_soc_unregister_codec(codec);
  893. err:
  894. kfree(wm8978);
  895. return ret;
  896. }
  897. static __devexit void wm8978_unregister(struct wm8978_priv *wm8978)
  898. {
  899. wm8978_set_bias_level(&wm8978->codec, SND_SOC_BIAS_OFF);
  900. snd_soc_unregister_dai(&wm8978_dai);
  901. snd_soc_unregister_codec(&wm8978->codec);
  902. kfree(wm8978);
  903. wm8978_codec = NULL;
  904. }
  905. static __devinit int wm8978_i2c_probe(struct i2c_client *i2c,
  906. const struct i2c_device_id *id)
  907. {
  908. struct wm8978_priv *wm8978;
  909. struct snd_soc_codec *codec;
  910. wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL);
  911. if (wm8978 == NULL)
  912. return -ENOMEM;
  913. codec = &wm8978->codec;
  914. codec->hw_write = (hw_write_t)i2c_master_send;
  915. i2c_set_clientdata(i2c, wm8978);
  916. codec->control_data = i2c;
  917. codec->dev = &i2c->dev;
  918. return wm8978_register(wm8978);
  919. }
  920. static __devexit int wm8978_i2c_remove(struct i2c_client *client)
  921. {
  922. struct wm8978_priv *wm8978 = i2c_get_clientdata(client);
  923. wm8978_unregister(wm8978);
  924. return 0;
  925. }
  926. static const struct i2c_device_id wm8978_i2c_id[] = {
  927. { "wm8978", 0 },
  928. { }
  929. };
  930. MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
  931. static struct i2c_driver wm8978_i2c_driver = {
  932. .driver = {
  933. .name = "WM8978",
  934. .owner = THIS_MODULE,
  935. },
  936. .probe = wm8978_i2c_probe,
  937. .remove = __devexit_p(wm8978_i2c_remove),
  938. .id_table = wm8978_i2c_id,
  939. };
  940. static int __init wm8978_modinit(void)
  941. {
  942. return i2c_add_driver(&wm8978_i2c_driver);
  943. }
  944. module_init(wm8978_modinit);
  945. static void __exit wm8978_exit(void)
  946. {
  947. i2c_del_driver(&wm8978_i2c_driver);
  948. }
  949. module_exit(wm8978_exit);
  950. MODULE_DESCRIPTION("ASoC WM8978 codec driver");
  951. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  952. MODULE_LICENSE("GPL");