/sound/oss/ad1848.c
C | 3069 lines | 2251 code | 480 blank | 338 comment | 558 complexity | cdf106b686bfe9ed8abdf5f0479692eb MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0
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1/*
2 * sound/oss/ad1848.c
3 *
4 * The low level driver for the AD1848/CS4248 codec chip which
5 * is used for example in the MS Sound System.
6 *
7 * The CS4231 which is used in the GUS MAX and some other cards is
8 * upwards compatible with AD1848 and this driver is able to drive it.
9 *
10 * CS4231A and AD1845 are upward compatible with CS4231. However
11 * the new features of these chips are different.
12 *
13 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
14 * CS4232A is an improved version of CS4232.
15 *
16 *
17 *
18 * Copyright (C) by Hannu Savolainen 1993-1997
19 *
20 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
21 * Version 2 (June 1991). See the "COPYING" file distributed with this software
22 * for more info.
23 *
24 *
25 * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
26 * general sleep/wakeup clean up.
27 * Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
28 * of irqs. Use dev_id.
29 * Christoph Hellwig : adapted to module_init/module_exit
30 * Aki Laukkanen : added power management support
31 * Arnaldo C. de Melo : added missing restore_flags in ad1848_resume
32 * Miguel Freitas : added ISA PnP support
33 * Alan Cox : Added CS4236->4239 identification
34 * Daniel T. Cobra : Alernate config/mixer for later chips
35 * Alan Cox : Merged chip idents and config code
36 *
37 * TODO
38 * APM save restore assist code on IBM thinkpad
39 *
40 * Status:
41 * Tested. Believed fully functional.
42 */
43
44#include <linux/init.h>
45#include <linux/interrupt.h>
46#include <linux/module.h>
47#include <linux/stddef.h>
48#include <linux/slab.h>
49#include <linux/isapnp.h>
50#include <linux/pnp.h>
51#include <linux/spinlock.h>
52
53#define DEB(x)
54#define DEB1(x)
55#include "sound_config.h"
56
57#include "ad1848.h"
58#include "ad1848_mixer.h"
59
60typedef struct
61{
62 spinlock_t lock;
63 int base;
64 int irq;
65 int dma1, dma2;
66 int dual_dma; /* 1, when two DMA channels allocated */
67 int subtype;
68 unsigned char MCE_bit;
69 unsigned char saved_regs[64]; /* Includes extended register space */
70 int debug_flag;
71
72 int audio_flags;
73 int record_dev, playback_dev;
74
75 int xfer_count;
76 int audio_mode;
77 int open_mode;
78 int intr_active;
79 char *chip_name, *name;
80 int model;
81#define MD_1848 1
82#define MD_4231 2
83#define MD_4231A 3
84#define MD_1845 4
85#define MD_4232 5
86#define MD_C930 6
87#define MD_IWAVE 7
88#define MD_4235 8 /* Crystal Audio CS4235 */
89#define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
90#define MD_4236 10 /* 4236 and higher */
91#define MD_42xB 11 /* CS 42xB */
92#define MD_4239 12 /* CS4239 */
93
94 /* Mixer parameters */
95 int recmask;
96 int supported_devices, orig_devices;
97 int supported_rec_devices, orig_rec_devices;
98 int *levels;
99 short mixer_reroute[32];
100 int dev_no;
101 volatile unsigned long timer_ticks;
102 int timer_running;
103 int irq_ok;
104 mixer_ents *mix_devices;
105 int mixer_output_port;
106} ad1848_info;
107
108typedef struct ad1848_port_info
109{
110 int open_mode;
111 int speed;
112 unsigned char speed_bits;
113 int channels;
114 int audio_format;
115 unsigned char format_bits;
116}
117ad1848_port_info;
118
119static struct address_info cfg;
120static int nr_ad1848_devs;
121
122static int deskpro_xl;
123static int deskpro_m;
124static int soundpro;
125
126static volatile signed char irq2dev[17] = {
127 -1, -1, -1, -1, -1, -1, -1, -1,
128 -1, -1, -1, -1, -1, -1, -1, -1, -1
129};
130
131#ifndef EXCLUDE_TIMERS
132static int timer_installed = -1;
133#endif
134
135static int loaded;
136
137static int ad_format_mask[13 /*devc->model */ ] =
138{
139 0,
140 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
141 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
142 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
143 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
144 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
145 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
146 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
147 AFMT_U8 | AFMT_S16_LE /* CS4235 */,
148 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/,
149 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
150 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
151 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
152};
153
154static ad1848_info adev_info[MAX_AUDIO_DEV];
155
156#define io_Index_Addr(d) ((d)->base)
157#define io_Indexed_Data(d) ((d)->base+1)
158#define io_Status(d) ((d)->base+2)
159#define io_Polled_IO(d) ((d)->base+3)
160
161static struct {
162 unsigned char flags;
163#define CAP_F_TIMER 0x01
164} capabilities [10 /*devc->model */ ] = {
165 {0}
166 ,{0} /* MD_1848 */
167 ,{CAP_F_TIMER} /* MD_4231 */
168 ,{CAP_F_TIMER} /* MD_4231A */
169 ,{CAP_F_TIMER} /* MD_1845 */
170 ,{CAP_F_TIMER} /* MD_4232 */
171 ,{0} /* MD_C930 */
172 ,{CAP_F_TIMER} /* MD_IWAVE */
173 ,{0} /* MD_4235 */
174 ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
175};
176
177#ifdef CONFIG_PNP
178static int isapnp = 1;
179static int isapnpjump;
180static int reverse;
181
182static int audio_activated;
183#else
184static int isapnp;
185#endif
186
187
188
189static int ad1848_open(int dev, int mode);
190static void ad1848_close(int dev);
191static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
192static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
193static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
194static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
195static void ad1848_halt(int dev);
196static void ad1848_halt_input(int dev);
197static void ad1848_halt_output(int dev);
198static void ad1848_trigger(int dev, int bits);
199static irqreturn_t adintr(int irq, void *dev_id);
200
201#ifndef EXCLUDE_TIMERS
202static int ad1848_tmr_install(int dev);
203static void ad1848_tmr_reprogram(int dev);
204#endif
205
206static int ad_read(ad1848_info * devc, int reg)
207{
208 int x;
209 int timeout = 900000;
210
211 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
212 timeout--;
213
214 if(reg < 32)
215 {
216 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
217 x = inb(io_Indexed_Data(devc));
218 }
219 else
220 {
221 int xreg, xra;
222
223 xreg = (reg & 0xff) - 32;
224 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
225 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
226 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
227 x = inb(io_Indexed_Data(devc));
228 }
229
230 return x;
231}
232
233static void ad_write(ad1848_info * devc, int reg, int data)
234{
235 int timeout = 900000;
236
237 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
238 timeout--;
239
240 if(reg < 32)
241 {
242 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
243 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
244 }
245 else
246 {
247 int xreg, xra;
248
249 xreg = (reg & 0xff) - 32;
250 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
251 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
252 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
253 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
254 }
255}
256
257static void wait_for_calibration(ad1848_info * devc)
258{
259 int timeout = 0;
260
261 /*
262 * Wait until the auto calibration process has finished.
263 *
264 * 1) Wait until the chip becomes ready (reads don't return 0x80).
265 * 2) Wait until the ACI bit of I11 gets on and then off.
266 */
267
268 timeout = 100000;
269 while (timeout > 0 && inb(devc->base) == 0x80)
270 timeout--;
271 if (inb(devc->base) & 0x80)
272 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
273
274 timeout = 100;
275 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
276 timeout--;
277 if (!(ad_read(devc, 11) & 0x20))
278 return;
279
280 timeout = 80000;
281 while (timeout > 0 && (ad_read(devc, 11) & 0x20))
282 timeout--;
283 if (ad_read(devc, 11) & 0x20)
284 if ((devc->model != MD_1845) && (devc->model != MD_1845_SSCAPE))
285 printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
286}
287
288static void ad_mute(ad1848_info * devc)
289{
290 int i;
291 unsigned char prev;
292
293 /*
294 * Save old register settings and mute output channels
295 */
296
297 for (i = 6; i < 8; i++)
298 {
299 prev = devc->saved_regs[i] = ad_read(devc, i);
300 }
301
302}
303
304static void ad_unmute(ad1848_info * devc)
305{
306}
307
308static void ad_enter_MCE(ad1848_info * devc)
309{
310 int timeout = 1000;
311 unsigned short prev;
312
313 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
314 timeout--;
315
316 devc->MCE_bit = 0x40;
317 prev = inb(io_Index_Addr(devc));
318 if (prev & 0x40)
319 {
320 return;
321 }
322 outb((devc->MCE_bit), io_Index_Addr(devc));
323}
324
325static void ad_leave_MCE(ad1848_info * devc)
326{
327 unsigned char prev, acal;
328 int timeout = 1000;
329
330 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
331 timeout--;
332
333 acal = ad_read(devc, 9);
334
335 devc->MCE_bit = 0x00;
336 prev = inb(io_Index_Addr(devc));
337 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
338
339 if ((prev & 0x40) == 0) /* Not in MCE mode */
340 {
341 return;
342 }
343 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
344 if (acal & 0x08) /* Auto calibration is enabled */
345 wait_for_calibration(devc);
346}
347
348static int ad1848_set_recmask(ad1848_info * devc, int mask)
349{
350 unsigned char recdev;
351 int i, n;
352 unsigned long flags;
353
354 mask &= devc->supported_rec_devices;
355
356 /* Rename the mixer bits if necessary */
357 for (i = 0; i < 32; i++)
358 {
359 if (devc->mixer_reroute[i] != i)
360 {
361 if (mask & (1 << i))
362 {
363 mask &= ~(1 << i);
364 mask |= (1 << devc->mixer_reroute[i]);
365 }
366 }
367 }
368
369 n = 0;
370 for (i = 0; i < 32; i++) /* Count selected device bits */
371 if (mask & (1 << i))
372 n++;
373
374 spin_lock_irqsave(&devc->lock,flags);
375 if (!soundpro) {
376 if (n == 0)
377 mask = SOUND_MASK_MIC;
378 else if (n != 1) { /* Too many devices selected */
379 mask &= ~devc->recmask; /* Filter out active settings */
380
381 n = 0;
382 for (i = 0; i < 32; i++) /* Count selected device bits */
383 if (mask & (1 << i))
384 n++;
385
386 if (n != 1)
387 mask = SOUND_MASK_MIC;
388 }
389 switch (mask) {
390 case SOUND_MASK_MIC:
391 recdev = 2;
392 break;
393
394 case SOUND_MASK_LINE:
395 case SOUND_MASK_LINE3:
396 recdev = 0;
397 break;
398
399 case SOUND_MASK_CD:
400 case SOUND_MASK_LINE1:
401 recdev = 1;
402 break;
403
404 case SOUND_MASK_IMIX:
405 recdev = 3;
406 break;
407
408 default:
409 mask = SOUND_MASK_MIC;
410 recdev = 2;
411 }
412
413 recdev <<= 6;
414 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
415 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
416 } else { /* soundpro */
417 unsigned char val;
418 int set_rec_bit;
419 int j;
420
421 for (i = 0; i < 32; i++) { /* For each bit */
422 if ((devc->supported_rec_devices & (1 << i)) == 0)
423 continue; /* Device not supported */
424
425 for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
426 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
427 continue;
428
429 /*
430 * This is tricky:
431 * set_rec_bit becomes 1 if the corresponding bit in mask is set
432 * then it gets flipped if the polarity is inverse
433 */
434 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
435
436 val = ad_read(devc, devc->mix_devices[i][j].recreg);
437 val &= ~(1 << devc->mix_devices[i][j].recpos);
438 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
439 ad_write(devc, devc->mix_devices[i][j].recreg, val);
440 }
441 }
442 }
443 spin_unlock_irqrestore(&devc->lock,flags);
444
445 /* Rename the mixer bits back if necessary */
446 for (i = 0; i < 32; i++)
447 {
448 if (devc->mixer_reroute[i] != i)
449 {
450 if (mask & (1 << devc->mixer_reroute[i]))
451 {
452 mask &= ~(1 << devc->mixer_reroute[i]);
453 mask |= (1 << i);
454 }
455 }
456 }
457 devc->recmask = mask;
458 return mask;
459}
460
461static void change_bits(ad1848_info * devc, unsigned char *regval,
462 unsigned char *muteval, int dev, int chn, int newval)
463{
464 unsigned char mask;
465 int shift;
466 int mute;
467 int mutemask;
468 int set_mute_bit;
469
470 set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
471
472 if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
473 newval = 100 - newval;
474
475 mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
476 shift = devc->mix_devices[dev][chn].bitpos;
477
478 if (devc->mix_devices[dev][chn].mutepos == 8)
479 { /* if there is no mute bit */
480 mute = 0; /* No mute bit; do nothing special */
481 mutemask = ~0; /* No mute bit; do nothing special */
482 }
483 else
484 {
485 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
486 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
487 }
488
489 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
490 *regval &= ~(mask << shift); /* Clear bits */
491 *regval |= (newval & mask) << shift; /* Set new value */
492
493 *muteval &= mutemask;
494 *muteval |= mute;
495}
496
497static int ad1848_mixer_get(ad1848_info * devc, int dev)
498{
499 if (!((1 << dev) & devc->supported_devices))
500 return -EINVAL;
501
502 dev = devc->mixer_reroute[dev];
503
504 return devc->levels[dev];
505}
506
507static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
508{
509 int regoffs, muteregoffs;
510 unsigned char val, muteval;
511 unsigned long flags;
512
513 regoffs = devc->mix_devices[dev][channel].regno;
514 muteregoffs = devc->mix_devices[dev][channel].mutereg;
515 val = ad_read(devc, regoffs);
516
517 if (muteregoffs != regoffs) {
518 muteval = ad_read(devc, muteregoffs);
519 change_bits(devc, &val, &muteval, dev, channel, value);
520 }
521 else
522 change_bits(devc, &val, &val, dev, channel, value);
523
524 spin_lock_irqsave(&devc->lock,flags);
525 ad_write(devc, regoffs, val);
526 devc->saved_regs[regoffs] = val;
527 if (muteregoffs != regoffs) {
528 ad_write(devc, muteregoffs, muteval);
529 devc->saved_regs[muteregoffs] = muteval;
530 }
531 spin_unlock_irqrestore(&devc->lock,flags);
532}
533
534static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
535{
536 int left = value & 0x000000ff;
537 int right = (value & 0x0000ff00) >> 8;
538 int retvol;
539
540 if (dev > 31)
541 return -EINVAL;
542
543 if (!(devc->supported_devices & (1 << dev)))
544 return -EINVAL;
545
546 dev = devc->mixer_reroute[dev];
547
548 if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
549 return -EINVAL;
550
551 if (left > 100)
552 left = 100;
553 if (right > 100)
554 right = 100;
555
556 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
557 right = left;
558
559 retvol = left | (right << 8);
560
561 /* Scale volumes */
562 left = mix_cvt[left];
563 right = mix_cvt[right];
564
565 devc->levels[dev] = retvol;
566
567 /*
568 * Set the left channel
569 */
570 ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
571
572 /*
573 * Set the right channel
574 */
575 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
576 goto out;
577 ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
578
579 out:
580 return retvol;
581}
582
583static void ad1848_mixer_reset(ad1848_info * devc)
584{
585 int i;
586 char name[32];
587 unsigned long flags;
588
589 devc->mix_devices = &(ad1848_mix_devices[0]);
590
591 sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
592
593 for (i = 0; i < 32; i++)
594 devc->mixer_reroute[i] = i;
595
596 devc->supported_rec_devices = MODE1_REC_DEVICES;
597
598 switch (devc->model)
599 {
600 case MD_4231:
601 case MD_4231A:
602 case MD_1845:
603 case MD_1845_SSCAPE:
604 devc->supported_devices = MODE2_MIXER_DEVICES;
605 break;
606
607 case MD_C930:
608 devc->supported_devices = C930_MIXER_DEVICES;
609 devc->mix_devices = &(c930_mix_devices[0]);
610 break;
611
612 case MD_IWAVE:
613 devc->supported_devices = MODE3_MIXER_DEVICES;
614 devc->mix_devices = &(iwave_mix_devices[0]);
615 break;
616
617 case MD_42xB:
618 case MD_4239:
619 devc->mix_devices = &(cs42xb_mix_devices[0]);
620 devc->supported_devices = MODE3_MIXER_DEVICES;
621 break;
622 case MD_4232:
623 case MD_4235:
624 case MD_4236:
625 devc->supported_devices = MODE3_MIXER_DEVICES;
626 break;
627
628 case MD_1848:
629 if (soundpro) {
630 devc->supported_devices = SPRO_MIXER_DEVICES;
631 devc->supported_rec_devices = SPRO_REC_DEVICES;
632 devc->mix_devices = &(spro_mix_devices[0]);
633 break;
634 }
635
636 default:
637 devc->supported_devices = MODE1_MIXER_DEVICES;
638 }
639
640 devc->orig_devices = devc->supported_devices;
641 devc->orig_rec_devices = devc->supported_rec_devices;
642
643 devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
644
645 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
646 {
647 if (devc->supported_devices & (1 << i))
648 ad1848_mixer_set(devc, i, devc->levels[i]);
649 }
650
651 ad1848_set_recmask(devc, SOUND_MASK_MIC);
652
653 devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
654
655 spin_lock_irqsave(&devc->lock,flags);
656 if (!soundpro) {
657 if (devc->mixer_output_port & AUDIO_SPEAKER)
658 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
659 else
660 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
661 } else {
662 /*
663 * From the "wouldn't it be nice if the mixer API had (better)
664 * support for custom stuff" category
665 */
666 /* Enable surround mode and SB16 mixer */
667 ad_write(devc, 16, 0x60);
668 }
669 spin_unlock_irqrestore(&devc->lock,flags);
670}
671
672static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
673{
674 ad1848_info *devc = mixer_devs[dev]->devc;
675 int val;
676
677 if (cmd == SOUND_MIXER_PRIVATE1)
678 {
679 if (get_user(val, (int __user *)arg))
680 return -EFAULT;
681
682 if (val != 0xffff)
683 {
684 unsigned long flags;
685 val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
686 devc->mixer_output_port = val;
687 val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
688 devc->mixer_output_port = val;
689 spin_lock_irqsave(&devc->lock,flags);
690 if (val & AUDIO_SPEAKER)
691 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
692 else
693 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
694 spin_unlock_irqrestore(&devc->lock,flags);
695 }
696 val = devc->mixer_output_port;
697 return put_user(val, (int __user *)arg);
698 }
699 if (cmd == SOUND_MIXER_PRIVATE2)
700 {
701 if (get_user(val, (int __user *)arg))
702 return -EFAULT;
703 return(ad1848_control(AD1848_MIXER_REROUTE, val));
704 }
705 if (((cmd >> 8) & 0xff) == 'M')
706 {
707 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
708 {
709 switch (cmd & 0xff)
710 {
711 case SOUND_MIXER_RECSRC:
712 if (get_user(val, (int __user *)arg))
713 return -EFAULT;
714 val = ad1848_set_recmask(devc, val);
715 break;
716
717 default:
718 if (get_user(val, (int __user *)arg))
719 return -EFAULT;
720 val = ad1848_mixer_set(devc, cmd & 0xff, val);
721 break;
722 }
723 return put_user(val, (int __user *)arg);
724 }
725 else
726 {
727 switch (cmd & 0xff)
728 {
729 /*
730 * Return parameters
731 */
732
733 case SOUND_MIXER_RECSRC:
734 val = devc->recmask;
735 break;
736
737 case SOUND_MIXER_DEVMASK:
738 val = devc->supported_devices;
739 break;
740
741 case SOUND_MIXER_STEREODEVS:
742 val = devc->supported_devices;
743 if (devc->model != MD_C930)
744 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
745 break;
746
747 case SOUND_MIXER_RECMASK:
748 val = devc->supported_rec_devices;
749 break;
750
751 case SOUND_MIXER_CAPS:
752 val=SOUND_CAP_EXCL_INPUT;
753 break;
754
755 default:
756 val = ad1848_mixer_get(devc, cmd & 0xff);
757 break;
758 }
759 return put_user(val, (int __user *)arg);
760 }
761 }
762 else
763 return -EINVAL;
764}
765
766static int ad1848_set_speed(int dev, int arg)
767{
768 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
769 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
770
771 /*
772 * The sampling speed is encoded in the least significant nibble of I8. The
773 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
774 * three bits select the divisor (indirectly):
775 *
776 * The available speeds are in the following table. Keep the speeds in
777 * the increasing order.
778 */
779 typedef struct
780 {
781 int speed;
782 unsigned char bits;
783 }
784 speed_struct;
785
786 static speed_struct speed_table[] =
787 {
788 {5510, (0 << 1) | 1},
789 {5510, (0 << 1) | 1},
790 {6620, (7 << 1) | 1},
791 {8000, (0 << 1) | 0},
792 {9600, (7 << 1) | 0},
793 {11025, (1 << 1) | 1},
794 {16000, (1 << 1) | 0},
795 {18900, (2 << 1) | 1},
796 {22050, (3 << 1) | 1},
797 {27420, (2 << 1) | 0},
798 {32000, (3 << 1) | 0},
799 {33075, (6 << 1) | 1},
800 {37800, (4 << 1) | 1},
801 {44100, (5 << 1) | 1},
802 {48000, (6 << 1) | 0}
803 };
804
805 int i, n, selected = -1;
806
807 n = sizeof(speed_table) / sizeof(speed_struct);
808
809 if (arg <= 0)
810 return portc->speed;
811
812 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
813 {
814 if (arg < 4000)
815 arg = 4000;
816 if (arg > 50000)
817 arg = 50000;
818
819 portc->speed = arg;
820 portc->speed_bits = speed_table[3].bits;
821 return portc->speed;
822 }
823 if (arg < speed_table[0].speed)
824 selected = 0;
825 if (arg > speed_table[n - 1].speed)
826 selected = n - 1;
827
828 for (i = 1 /*really */ ; selected == -1 && i < n; i++)
829 {
830 if (speed_table[i].speed == arg)
831 selected = i;
832 else if (speed_table[i].speed > arg)
833 {
834 int diff1, diff2;
835
836 diff1 = arg - speed_table[i - 1].speed;
837 diff2 = speed_table[i].speed - arg;
838
839 if (diff1 < diff2)
840 selected = i - 1;
841 else
842 selected = i;
843 }
844 }
845 if (selected == -1)
846 {
847 printk(KERN_WARNING "ad1848: Can't find speed???\n");
848 selected = 3;
849 }
850 portc->speed = speed_table[selected].speed;
851 portc->speed_bits = speed_table[selected].bits;
852 return portc->speed;
853}
854
855static short ad1848_set_channels(int dev, short arg)
856{
857 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
858
859 if (arg != 1 && arg != 2)
860 return portc->channels;
861
862 portc->channels = arg;
863 return arg;
864}
865
866static unsigned int ad1848_set_bits(int dev, unsigned int arg)
867{
868 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
869 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
870
871 static struct format_tbl
872 {
873 int format;
874 unsigned char bits;
875 }
876 format2bits[] =
877 {
878 {
879 0, 0
880 }
881 ,
882 {
883 AFMT_MU_LAW, 1
884 }
885 ,
886 {
887 AFMT_A_LAW, 3
888 }
889 ,
890 {
891 AFMT_IMA_ADPCM, 5
892 }
893 ,
894 {
895 AFMT_U8, 0
896 }
897 ,
898 {
899 AFMT_S16_LE, 2
900 }
901 ,
902 {
903 AFMT_S16_BE, 6
904 }
905 ,
906 {
907 AFMT_S8, 0
908 }
909 ,
910 {
911 AFMT_U16_LE, 0
912 }
913 ,
914 {
915 AFMT_U16_BE, 0
916 }
917 };
918 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
919
920 if (arg == 0)
921 return portc->audio_format;
922
923 if (!(arg & ad_format_mask[devc->model]))
924 arg = AFMT_U8;
925
926 portc->audio_format = arg;
927
928 for (i = 0; i < n; i++)
929 if (format2bits[i].format == arg)
930 {
931 if ((portc->format_bits = format2bits[i].bits) == 0)
932 return portc->audio_format = AFMT_U8; /* Was not supported */
933
934 return arg;
935 }
936 /* Still hanging here. Something must be terribly wrong */
937 portc->format_bits = 0;
938 return portc->audio_format = AFMT_U8;
939}
940
941static struct audio_driver ad1848_audio_driver =
942{
943 .owner = THIS_MODULE,
944 .open = ad1848_open,
945 .close = ad1848_close,
946 .output_block = ad1848_output_block,
947 .start_input = ad1848_start_input,
948 .prepare_for_input = ad1848_prepare_for_input,
949 .prepare_for_output = ad1848_prepare_for_output,
950 .halt_io = ad1848_halt,
951 .halt_input = ad1848_halt_input,
952 .halt_output = ad1848_halt_output,
953 .trigger = ad1848_trigger,
954 .set_speed = ad1848_set_speed,
955 .set_bits = ad1848_set_bits,
956 .set_channels = ad1848_set_channels
957};
958
959static struct mixer_operations ad1848_mixer_operations =
960{
961 .owner = THIS_MODULE,
962 .id = "SOUNDPORT",
963 .name = "AD1848/CS4248/CS4231",
964 .ioctl = ad1848_mixer_ioctl
965};
966
967static int ad1848_open(int dev, int mode)
968{
969 ad1848_info *devc;
970 ad1848_port_info *portc;
971 unsigned long flags;
972
973 if (dev < 0 || dev >= num_audiodevs)
974 return -ENXIO;
975
976 devc = (ad1848_info *) audio_devs[dev]->devc;
977 portc = (ad1848_port_info *) audio_devs[dev]->portc;
978
979 /* here we don't have to protect against intr */
980 spin_lock(&devc->lock);
981 if (portc->open_mode || (devc->open_mode & mode))
982 {
983 spin_unlock(&devc->lock);
984 return -EBUSY;
985 }
986 devc->dual_dma = 0;
987
988 if (audio_devs[dev]->flags & DMA_DUPLEX)
989 {
990 devc->dual_dma = 1;
991 }
992 devc->intr_active = 0;
993 devc->audio_mode = 0;
994 devc->open_mode |= mode;
995 portc->open_mode = mode;
996 spin_unlock(&devc->lock);
997 ad1848_trigger(dev, 0);
998
999 if (mode & OPEN_READ)
1000 devc->record_dev = dev;
1001 if (mode & OPEN_WRITE)
1002 devc->playback_dev = dev;
1003/*
1004 * Mute output until the playback really starts. This decreases clicking (hope so).
1005 */
1006 spin_lock_irqsave(&devc->lock,flags);
1007 ad_mute(devc);
1008 spin_unlock_irqrestore(&devc->lock,flags);
1009
1010 return 0;
1011}
1012
1013static void ad1848_close(int dev)
1014{
1015 unsigned long flags;
1016 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1017 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1018
1019 DEB(printk("ad1848_close(void)\n"));
1020
1021 devc->intr_active = 0;
1022 ad1848_halt(dev);
1023
1024 spin_lock_irqsave(&devc->lock,flags);
1025
1026 devc->audio_mode = 0;
1027 devc->open_mode &= ~portc->open_mode;
1028 portc->open_mode = 0;
1029
1030 ad_unmute(devc);
1031 spin_unlock_irqrestore(&devc->lock,flags);
1032}
1033
1034static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1035{
1036 unsigned long flags, cnt;
1037 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1038 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1039
1040 cnt = count;
1041
1042 if (portc->audio_format == AFMT_IMA_ADPCM)
1043 {
1044 cnt /= 4;
1045 }
1046 else
1047 {
1048 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1049 cnt >>= 1;
1050 }
1051 if (portc->channels > 1)
1052 cnt >>= 1;
1053 cnt--;
1054
1055 if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1056 intrflag &&
1057 cnt == devc->xfer_count)
1058 {
1059 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1060 devc->intr_active = 1;
1061 return; /*
1062 * Auto DMA mode on. No need to react
1063 */
1064 }
1065 spin_lock_irqsave(&devc->lock,flags);
1066
1067 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1068 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1069
1070 devc->xfer_count = cnt;
1071 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1072 devc->intr_active = 1;
1073 spin_unlock_irqrestore(&devc->lock,flags);
1074}
1075
1076static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1077{
1078 unsigned long flags, cnt;
1079 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1080 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1081
1082 cnt = count;
1083 if (portc->audio_format == AFMT_IMA_ADPCM)
1084 {
1085 cnt /= 4;
1086 }
1087 else
1088 {
1089 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1090 cnt >>= 1;
1091 }
1092 if (portc->channels > 1)
1093 cnt >>= 1;
1094 cnt--;
1095
1096 if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1097 intrflag &&
1098 cnt == devc->xfer_count)
1099 {
1100 devc->audio_mode |= PCM_ENABLE_INPUT;
1101 devc->intr_active = 1;
1102 return; /*
1103 * Auto DMA mode on. No need to react
1104 */
1105 }
1106 spin_lock_irqsave(&devc->lock,flags);
1107
1108 if (devc->model == MD_1848)
1109 {
1110 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1111 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1112 }
1113 else
1114 {
1115 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1116 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1117 }
1118
1119 ad_unmute(devc);
1120
1121 devc->xfer_count = cnt;
1122 devc->audio_mode |= PCM_ENABLE_INPUT;
1123 devc->intr_active = 1;
1124 spin_unlock_irqrestore(&devc->lock,flags);
1125}
1126
1127static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1128{
1129 int timeout;
1130 unsigned char fs, old_fs, tmp = 0;
1131 unsigned long flags;
1132 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1133 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1134
1135 ad_mute(devc);
1136
1137 spin_lock_irqsave(&devc->lock,flags);
1138 fs = portc->speed_bits | (portc->format_bits << 5);
1139
1140 if (portc->channels > 1)
1141 fs |= 0x10;
1142
1143 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1144
1145 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1146 {
1147 fs &= 0xf0; /* Mask off the rate select bits */
1148
1149 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1150 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1151 }
1152 old_fs = ad_read(devc, 8);
1153
1154 if (devc->model == MD_4232 || devc->model >= MD_4236)
1155 {
1156 tmp = ad_read(devc, 16);
1157 ad_write(devc, 16, tmp | 0x30);
1158 }
1159 if (devc->model == MD_IWAVE)
1160 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1161
1162 ad_write(devc, 8, fs);
1163
1164 /*
1165 * Write to I8 starts resynchronization. Wait until it completes.
1166 */
1167
1168 timeout = 0;
1169 while (timeout < 100 && inb(devc->base) != 0x80)
1170 timeout++;
1171 timeout = 0;
1172 while (timeout < 10000 && inb(devc->base) == 0x80)
1173 timeout++;
1174
1175 if (devc->model >= MD_4232)
1176 ad_write(devc, 16, tmp & ~0x30);
1177
1178 ad_leave_MCE(devc); /*
1179 * Starts the calibration process.
1180 */
1181 spin_unlock_irqrestore(&devc->lock,flags);
1182 devc->xfer_count = 0;
1183
1184#ifndef EXCLUDE_TIMERS
1185 if (dev == timer_installed && devc->timer_running)
1186 if ((fs & 0x01) != (old_fs & 0x01))
1187 {
1188 ad1848_tmr_reprogram(dev);
1189 }
1190#endif
1191 ad1848_halt_output(dev);
1192 return 0;
1193}
1194
1195static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1196{
1197 int timeout;
1198 unsigned char fs, old_fs, tmp = 0;
1199 unsigned long flags;
1200 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1201 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1202
1203 if (devc->audio_mode)
1204 return 0;
1205
1206 spin_lock_irqsave(&devc->lock,flags);
1207 fs = portc->speed_bits | (portc->format_bits << 5);
1208
1209 if (portc->channels > 1)
1210 fs |= 0x10;
1211
1212 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1213
1214 if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
1215 {
1216 fs &= 0xf0; /* Mask off the rate select bits */
1217
1218 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1219 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1220 }
1221 if (devc->model == MD_4232)
1222 {
1223 tmp = ad_read(devc, 16);
1224 ad_write(devc, 16, tmp | 0x30);
1225 }
1226 if (devc->model == MD_IWAVE)
1227 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1228
1229 /*
1230 * If mode >= 2 (CS4231), set I28. It's the capture format register.
1231 */
1232
1233 if (devc->model != MD_1848)
1234 {
1235 old_fs = ad_read(devc, 28);
1236 ad_write(devc, 28, fs);
1237
1238 /*
1239 * Write to I28 starts resynchronization. Wait until it completes.
1240 */
1241
1242 timeout = 0;
1243 while (timeout < 100 && inb(devc->base) != 0x80)
1244 timeout++;
1245
1246 timeout = 0;
1247 while (timeout < 10000 && inb(devc->base) == 0x80)
1248 timeout++;
1249
1250 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1251 {
1252 /*
1253 * CS4231 compatible devices don't have separate sampling rate selection
1254 * register for recording an playback. The I8 register is shared so we have to
1255 * set the speed encoding bits of it too.
1256 */
1257 unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1258
1259 ad_write(devc, 8, tmp);
1260 /*
1261 * Write to I8 starts resynchronization. Wait until it completes.
1262 */
1263 timeout = 0;
1264 while (timeout < 100 && inb(devc->base) != 0x80)
1265 timeout++;
1266
1267 timeout = 0;
1268 while (timeout < 10000 && inb(devc->base) == 0x80)
1269 timeout++;
1270 }
1271 }
1272 else
1273 { /* For AD1848 set I8. */
1274
1275 old_fs = ad_read(devc, 8);
1276 ad_write(devc, 8, fs);
1277 /*
1278 * Write to I8 starts resynchronization. Wait until it completes.
1279 */
1280 timeout = 0;
1281 while (timeout < 100 && inb(devc->base) != 0x80)
1282 timeout++;
1283 timeout = 0;
1284 while (timeout < 10000 && inb(devc->base) == 0x80)
1285 timeout++;
1286 }
1287
1288 if (devc->model == MD_4232)
1289 ad_write(devc, 16, tmp & ~0x30);
1290
1291 ad_leave_MCE(devc); /*
1292 * Starts the calibration process.
1293 */
1294 spin_unlock_irqrestore(&devc->lock,flags);
1295 devc->xfer_count = 0;
1296
1297#ifndef EXCLUDE_TIMERS
1298 if (dev == timer_installed && devc->timer_running)
1299 {
1300 if ((fs & 0x01) != (old_fs & 0x01))
1301 {
1302 ad1848_tmr_reprogram(dev);
1303 }
1304 }
1305#endif
1306 ad1848_halt_input(dev);
1307 return 0;
1308}
1309
1310static void ad1848_halt(int dev)
1311{
1312 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1313 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1314
1315 unsigned char bits = ad_read(devc, 9);
1316
1317 if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1318 ad1848_halt_output(dev);
1319
1320 if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1321 ad1848_halt_input(dev);
1322 devc->audio_mode = 0;
1323}
1324
1325static void ad1848_halt_input(int dev)
1326{
1327 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1328 unsigned long flags;
1329
1330 if (!(ad_read(devc, 9) & 0x02))
1331 return; /* Capture not enabled */
1332
1333 spin_lock_irqsave(&devc->lock,flags);
1334
1335 ad_mute(devc);
1336
1337 {
1338 int tmout;
1339
1340 if(!isa_dma_bridge_buggy)
1341 disable_dma(audio_devs[dev]->dmap_in->dma);
1342
1343 for (tmout = 0; tmout < 100000; tmout++)
1344 if (ad_read(devc, 11) & 0x10)
1345 break;
1346 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1347
1348 if(!isa_dma_bridge_buggy)
1349 enable_dma(audio_devs[dev]->dmap_in->dma);
1350 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1351 }
1352
1353 outb(0, io_Status(devc)); /* Clear interrupt status */
1354 outb(0, io_Status(devc)); /* Clear interrupt status */
1355
1356 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1357
1358 spin_unlock_irqrestore(&devc->lock,flags);
1359}
1360
1361static void ad1848_halt_output(int dev)
1362{
1363 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1364 unsigned long flags;
1365
1366 if (!(ad_read(devc, 9) & 0x01))
1367 return; /* Playback not enabled */
1368
1369 spin_lock_irqsave(&devc->lock,flags);
1370
1371 ad_mute(devc);
1372 {
1373 int tmout;
1374
1375 if(!isa_dma_bridge_buggy)
1376 disable_dma(audio_devs[dev]->dmap_out->dma);
1377
1378 for (tmout = 0; tmout < 100000; tmout++)
1379 if (ad_read(devc, 11) & 0x10)
1380 break;
1381 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1382
1383 if(!isa_dma_bridge_buggy)
1384 enable_dma(audio_devs[dev]->dmap_out->dma);
1385
1386 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1387 }
1388
1389 outb((0), io_Status(devc)); /* Clear interrupt status */
1390 outb((0), io_Status(devc)); /* Clear interrupt status */
1391
1392 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1393
1394 spin_unlock_irqrestore(&devc->lock,flags);
1395}
1396
1397static void ad1848_trigger(int dev, int state)
1398{
1399 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1400 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1401 unsigned long flags;
1402 unsigned char tmp, old;
1403
1404 spin_lock_irqsave(&devc->lock,flags);
1405 state &= devc->audio_mode;
1406
1407 tmp = old = ad_read(devc, 9);
1408
1409 if (portc->open_mode & OPEN_READ)
1410 {
1411 if (state & PCM_ENABLE_INPUT)
1412 tmp |= 0x02;
1413 else
1414 tmp &= ~0x02;
1415 }
1416 if (portc->open_mode & OPEN_WRITE)
1417 {
1418 if (state & PCM_ENABLE_OUTPUT)
1419 tmp |= 0x01;
1420 else
1421 tmp &= ~0x01;
1422 }
1423 /* ad_mute(devc); */
1424 if (tmp != old)
1425 {
1426 ad_write(devc, 9, tmp);
1427 ad_unmute(devc);
1428 }
1429 spin_unlock_irqrestore(&devc->lock,flags);
1430}
1431
1432static void ad1848_init_hw(ad1848_info * devc)
1433{
1434 int i;
1435 int *init_values;
1436
1437 /*
1438 * Initial values for the indirect registers of CS4248/AD1848.
1439 */
1440 static int init_values_a[] =
1441 {
1442 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1443 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1444
1445 /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1446 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1447 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1448 };
1449
1450 static int init_values_b[] =
1451 {
1452 /*
1453 Values for the newer chips
1454 Some of the register initialization values were changed. In
1455 order to get rid of the click that preceded PCM playback,
1456 calibration was disabled on the 10th byte. On that same byte,
1457 dual DMA was enabled; on the 11th byte, ADC dithering was
1458 enabled, since that is theoretically desirable; on the 13th
1459 byte, Mode 3 was selected, to enable access to extended
1460 registers.
1461 */
1462 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1463 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1464 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1466 };
1467
1468 /*
1469 * Select initialisation data
1470 */
1471
1472 init_values = init_values_a;
1473 if(devc->model >= MD_4236)
1474 init_values = init_values_b;
1475
1476 for (i = 0; i < 16; i++)
1477 ad_write(devc, i, init_values[i]);
1478
1479
1480 ad_mute(devc); /* Initialize some variables */
1481 ad_unmute(devc); /* Leave it unmuted now */
1482
1483 if (devc->model > MD_1848)
1484 {
1485 if (devc->model == MD_1845_SSCAPE)
1486 ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1487 else
1488 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1489
1490 if (devc->model == MD_IWAVE)
1491 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1492
1493 if (devc->model != MD_1845_SSCAPE)
1494 for (i = 16; i < 32; i++)
1495 ad_write(devc, i, init_values[i]);
1496
1497 if (devc->model == MD_IWAVE)
1498 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1499 }
1500 if (devc->model > MD_1848)
1501 {
1502 if (devc->audio_flags & DMA_DUPLEX)
1503 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1504 else
1505 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1506
1507 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1508 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1509
1510 if (devc->model == MD_IWAVE)
1511 { /* Some magic Interwave specific initialization */
1512 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1513 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1514 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1515 }
1516 }
1517 else
1518 {
1519 devc->audio_flags &= ~DMA_DUPLEX;
1520 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1521 if (soundpro)
1522 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1523 }
1524
1525 outb((0), io_Status(devc)); /* Clear pending interrupts */
1526
1527 /*
1528 * Toggle the MCE bit. It completes the initialization phase.
1529 */
1530
1531 ad_enter_MCE(devc); /* In case the bit was off */
1532 ad_leave_MCE(devc);
1533
1534 ad1848_mixer_reset(devc);
1535}
1536
1537int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
1538{
1539 unsigned char tmp;
1540 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1541 unsigned char tmp1 = 0xff, tmp2 = 0xff;
1542 int optiC930 = 0; /* OPTi 82C930 flag */
1543 int interwave = 0;
1544 int ad1847_flag = 0;
1545 int cs4248_flag = 0;
1546 int sscape_flag = 0;
1547 int io_base = ports->start;
1548
1549 int i;
1550
1551 DDB(printk("ad1848_detect(%x)\n", io_base));
1552
1553 if (ad_flags)
1554 {
1555 if (*ad_flags == 0x12345678)
1556 {
1557 interwave = 1;
1558 *ad_flags = 0;
1559 }
1560
1561 if (*ad_flags == 0x87654321)
1562 {
1563 sscape_flag = 1;
1564 *ad_flags = 0;
1565 }
1566
1567 if (*ad_flags == 0x12345677)
1568 {
1569 cs4248_flag = 1;
1570 *ad_flags = 0;
1571 }
1572 }
1573 if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1574 {
1575 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1576 return 0;
1577 }
1578 spin_lock_init(&devc->lock);
1579 devc->base = io_base;
1580 devc->irq_ok = 0;
1581 devc->timer_running = 0;
1582 devc->MCE_bit = 0x40;
1583 devc->irq = 0;
1584 devc->open_mode = 0;
1585 devc->chip_name = devc->name = "AD1848";
1586 devc->model = MD_1848; /* AD1848 or CS4248 */
1587 devc->levels = NULL;
1588 devc->debug_flag = 0;
1589
1590 /*
1591 * Check that the I/O address is in use.
1592 *
1593 * The bit 0x80 of the base I/O port is known to be 0 after the
1594 * chip has performed its power on initialization. Just assume
1595 * this has happened before the OS is starting.
1596 *
1597 * If the I/O address is unused, it typically returns 0xff.
1598 */
1599
1600 if (inb(devc->base) == 0xff)
1601 {
1602 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1603 }
1604
1605 /*
1606 * Wait for the device to stop initialization
1607 */
1608
1609 DDB(printk("ad1848_detect() - step 0\n"));
1610
1611 for (i = 0; i < 10000000; i++)
1612 {
1613 unsigned char x = inb(devc->base);
1614
1615 if (x == 0xff || !(x & 0x80))
1616 break;
1617 }
1618
1619 DDB(printk("ad1848_detect() - step A\n"));
1620
1621 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
1622 ad_leave_MCE(devc);
1623
1624 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
1625 {
1626 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1627 return 0;
1628 }
1629
1630 /*
1631 * Test if it's possible to change contents of the indirect registers.
1632 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1633 * so try to avoid using it.
1634 */
1635
1636 DDB(printk("ad1848_detect() - step B\n"));
1637 ad_write(devc, 0, 0xaa);
1638 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1639
1640 if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1641 {
1642 if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
1643 ad1847_flag = 1;
1644 else
1645 {
1646 DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1647 return 0;
1648 }
1649 }
1650 DDB(printk("ad1848_detect() - step C\n"));
1651 ad_write(devc, 0, 0x45);
1652 ad_write(devc, 1, 0xaa);
1653
1654 if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1655 {
1656 if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
1657 ad1847_flag = 1;
1658 else
1659 {
1660 DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1661 return 0;
1662 }
1663 }
1664
1665 /*
1666 * The indirect register I12 has some read only bits. Let's
1667 * try to change them.
1668 */
1669
1670 DDB(printk("ad1848_detect() - step D\n"));
1671 tmp = ad_read(devc, 12);
1672 ad_write(devc, 12, (~tmp) & 0x0f);
1673
1674 if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1675 {
1676 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1677 return 0;
1678 }
1679
1680 /*
1681 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1682 * 0x01=RevB and 0x0A=RevC.
1683 */
1684
1685 /*
1686 * The original AD1848/CS4248 has just 15 indirect registers. This means
1687 * that I0 and I16 should return the same value (etc.).
1688 * However this doesn't work with CS4248. Actually it seems to be impossible
1689 * to detect if the chip is a CS4231 or CS4248.
1690 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1691 * with CS4231.
1692 */
1693
1694 /*
1695 * OPTi 82C930 has mode2 control bit in another place. This test will fail
1696 * with it. Accept this situation as a possible indication of this chip.
1697 */
1698
1699 DDB(printk("ad1848_detect() - step F\n"));
1700 ad_write(devc, 12, 0); /* Mode2=disabled */
1701
1702 for (i = 0; i < 16; i++)
1703 {
1704 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1705 {
1706 DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1707 if (!ad1847_flag)
1708 optiC930 = 1;
1709 break;
1710 }
1711 }
1712
1713 /*
1714 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1715 * The bit 0x80 is always 1 in CS4248 and CS4231.
1716 */
1717
1718 DDB(printk("ad1848_detect() - step G\n"));
1719
1720 if (ad_flags && *ad_flags == 400)
1721 *ad_flags = 0;
1722 else
1723 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1724
1725
1726 if (ad_flags)
1727 *ad_flags = 0;
1728
1729 tmp1 = ad_read(devc, 12);
1730 if (tmp1 & 0x80)
1731 {
1732 if (ad_flags)
1733 *ad_flags |= AD_F_CS4248;
1734
1735 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1736 }
1737 if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1738 {
1739 /*
1740 * CS4231 detected - is it?
1741 *
1742 * Verify that setting I0 doesn't change I16.
1743 */
1744
1745 DDB(printk("ad1848_detect() - step H\n"));
1746 ad_write(devc, 16, 0); /* Set I16 to known value */
1747
1748 ad_write(devc, 0, 0x45);
1749 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1750 {
1751 ad_write(devc, 0, 0xaa);
1752 if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1753 {
1754 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1755 return 0;
1756 }
1757
1758 /*
1759 * Verify that some bits of I25 are read only.
1760 */
1761
1762 DDB(printk("ad1848_detect() - step I\n"));
1763 tmp1 = ad_read(devc, 25); /* Original bits */
1764 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1765 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1766 {
1767 int id;
1768
1769 /*
1770 * It's at least CS4231
1771 */
1772
1773 devc->chip_name = "CS4231";
1774 devc->model = MD_4231;
1775
1776 /*
1777 * It could be an AD1845 or CS4231A as well.
1778 * CS4231 and AD1845 report the same revision info in I25
1779 * while the CS4231A reports different.
1780 */
1781
1782 id = ad_read(devc, 25);
1783 if ((id & 0xe7) == 0x80) /* Device busy??? */
1784 id = ad_read(devc, 25);
1785 if ((id & 0xe7) == 0x80) /* Device still busy??? */
1786 id = ad_read(devc, 25);
1787 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1788
1789 if ((id & 0xe7) == 0x80) {
1790 /*
1791 * It must be a CS4231 or AD1845. The register I23 of
1792 * CS4231 is undefined and it appears to be read only.
1793 * AD1845 uses I23 for setting sample rate. Assume
1794 * the chip is AD1845 if I23 is changeable.
1795 */
1796
1797 unsigned char tmp = ad_read(devc, 23);
1798 ad_write(devc, 23, ~tmp);
1799
1800 if (interwave)
1801 {
1802 devc->model = MD_IWAVE;
1803 devc->chip_name = "IWave";
1804 }
1805 else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
1806 {
1807 devc->chip_name = "AD1845";
1808 devc->model = MD_1845;
1809 }
1810 else if (cs4248_flag)
1811 {
1812 if (ad_flags)
1813 *ad_flags |= AD_F_CS4248;
1814 devc->chip_name = "CS4248";
1815 devc->model = MD_1848;
1816 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1817 }
1818 ad_write(devc, 23, tmp); /* Restore */
1819 }
1820 else
1821 {
1822 switch (id & 0x1f) {
1823 case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1824 {
1825 int xid;
1826 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1827 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1828 xid = inb(io_Indexed_Data(devc));
1829 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1830 switch (xid & 0x1f)
1831 {
1832 case 0x00:
1833 devc->chip_name = "CS4237B(B)";
1834 devc->model = MD_42xB;
1835 break;
1836 case 0x08:
1837 /* Seems to be a 4238 ?? */
1838 devc->chip_name = "CS4238";
1839 devc->model = MD_42xB;
1840 break;
1841 case 0x09:
1842 devc->chip_name = "CS4238B";
1843 devc->model = MD_42xB;
1844 break;
1845 case 0x0b:
1846 devc->chip_name = "CS4236B";
1847 devc->model = MD_4236;
1848 break;
1849 case 0x10:
1850 devc->chip_name = "CS4237B";
1851 devc->model = MD_42xB;
1852 break;
1853 case 0x1d:
1854 devc->chip_name = "CS4235";
1855 devc->model = MD_4235;
1856 break;
1857 case 0x1e:
1858 devc->chip_name = "CS4239";
1859 devc->model = MD_4239;
1860 break;
1861 default:
1862 printk("Chip ident is %X.\n", xid&0x1F);
1863 devc->chip_name = "CS42xx";
1864 devc->model = MD_4232;
1865 break;
1866 }
1867 }
1868 break;
1869
1870 case 2: /* CS4232/CS4232A */
1871 devc->chip_name = "CS4232";
1872 devc->model = MD_4232;
1873 break;
1874
1875 case 0:
1876 if ((id & 0xe0) == 0xa0)
1877 {
1878 devc->chip_name = "CS4231A";
1879 devc->model = MD_4231A;
1880 }
1881 else
1882 {
1883 devc->chip_name = "CS4321";
1884 devc->model = MD_4231;
1885 }
1886 break;
1887
1888 default: /* maybe */
1889 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1890 if (optiC930)
1891 {
1892 devc->chip_name = "82C930";
1893 devc->model = MD_C930;
1894 }
1895 else
1896 {
1897 devc->chip_name = "CS4231";
1898 devc->model = MD_4231;
1899 }
1900 }
1901 }
1902 }
1903 ad_write(devc, 25, tmp1); /* Restore bits */
1904
1905 DDB(printk("ad1848_detect() - step K\n"));
1906 }
1907 } else if (tmp1 == 0x0a) {
1908 /*
1909 * Is it perhaps a SoundPro CMI8330?
1910 * If so, then we should be able to change indirect registers
1911 * greater than I15 after activating MODE2, even though reading
1912 * back I12 does not show it.
1913 */
1914
1915 /*
1916 * Let's try comparing register values
1917 */
1918 for (i = 0; i < 16; i++) {
1919 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1920 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1921 soundpro = 1;
1922 devc->chip_name = "SoundPro CMI 8330";
1923 break;
1924 }
1925 }
1926 }
1927
1928 DDB(printk("ad1848_detect() - step L\n"));
1929 if (ad_flags)
1930 {
1931 if (devc->model != MD_1848)
1932 *ad_flags |= AD_F_CS4231;
1933 }
1934 DDB(printk("ad1848_detect() - Detected OK\n"));
1935
1936 if (devc->model == MD_1848 && ad1847_flag)
1937 devc->chip_name = "AD1847";
1938
1939
1940 if (sscape_flag == 1)
1941 devc->model = MD_1845_SSCAPE;
1942
1943 return 1;
1944}
1945
1946int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
1947 int dma_capture, int share_dma, int *osp, struct module *owner)
1948{
1949 /*
1950 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1951 * so that this driver doesn't need to allocate/deallocate it.
1952 * The actually used IRQ is ABS(irq).
1953 */
1954
1955 int my_dev;
1956 char dev_name[100];
1957 int e;
1958
1959 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1960
1961 ad1848_port_info *portc = NULL;
1962
1963 devc->irq = (irq > 0) ? irq : 0;
1964 devc->open_mode = 0;
1965 devc->timer_ticks = 0;
1966 devc->dma1 = dma_playback;
1967 devc->dma2 = dma_capture;
1968 devc->subtype = cfg.card_subtype;
1969 devc->audio_flags = DMA_AUTOMODE;
1970 devc->playback_dev = devc->record_dev = 0;
1971 if (name != NULL)
1972 devc->name = name;
1973
1974 if (name != NULL && name[0] != 0)
1975 sprintf(dev_name,
1976 "%s (%s)", name, devc->chip_name);
1977 else
1978 sprintf(dev_name,
1979 "Generic audio codec (%s)", devc->chip_name);
1980
1981 rename_region(ports, devc->name);
1982
1983 conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1984
1985 if (devc->model == MD_1848 || devc->model == MD_C930)
1986 devc->audio_flags |= DMA_HARDSTOP;
1987
1988 if (devc->model > MD_1848)
1989 {
1990 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1991 devc->audio_flags &= ~DMA_DUPLEX;
1992 else
1993 devc->audio_flags |= DMA_DUPLEX;
1994 }
1995
1996 portc = kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1997 if(portc==NULL) {
1998 release_region(devc->base, 4);
1999 return -1;
2000 }
2001
2002 if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
2003 dev_name,
2004 &ad1848_audio_driver,
2005 sizeof(struct audio_driver),
2006 devc->audio_flags,
2007 ad_format_mask[devc->model],
2008 devc,
2009 dma_playback,
2010 dma_capture)) < 0)
2011 {
2012 release_region(devc->base, 4);
2013 kfree(portc);
2014 return -1;
2015 }
2016
2017 audio_devs[my_dev]->portc = portc;
2018 audio_devs[my_dev]->mixer_dev = -1;
2019 if (owner)
2020 audio_devs[my_dev]->d->owner = owner;
2021 memset((char *) portc, 0, sizeof(*portc));
2022
2023 nr_ad1848_devs++;
2024
2025 ad1848_init_hw(devc);
2026
2027 if (irq > 0)
2028 {
2029 devc->dev_no = my_dev;
2030 if (request_irq(devc->irq, adintr, 0, devc->name,
2031 (void *)(long)my_dev) < 0)
2032 {
2033 printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2034 /* Don't free it either then.. */
2035 devc->irq = 0;
2036 }
2037 if (capabilities[devc->model].flags & CAP_F_TIMER)
2038 {
2039#ifndef CONFIG_SMP
2040 int x;
2041 unsigned char tmp = ad_read(devc, 16);
2042#endif
2043
2044 devc->timer_ticks = 0;
2045
2046 ad_write(devc, 21, 0x00); /* Timer MSB */
2047 ad_write(devc, 20, 0x10); /* Timer LSB */
2048#ifndef CONFIG_S…Large files files are truncated, but you can click here to view the full file