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/Documentation/PCI/pcieaer-howto.txt

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  1. The PCI Express Advanced Error Reporting Driver Guide HOWTO
  2. T. Long Nguyen <tom.l.nguyen@intel.com>
  3. Yanmin Zhang <yanmin.zhang@intel.com>
  4. 07/29/2006
  5. 1. Overview
  6. 1.1 About this guide
  7. This guide describes the basics of the PCI Express Advanced Error
  8. Reporting (AER) driver and provides information on how to use it, as
  9. well as how to enable the drivers of endpoint devices to conform with
  10. PCI Express AER driver.
  11. 1.2 Copyright Intel Corporation 2006.
  12. 1.3 What is the PCI Express AER Driver?
  13. PCI Express error signaling can occur on the PCI Express link itself
  14. or on behalf of transactions initiated on the link. PCI Express
  15. defines two error reporting paradigms: the baseline capability and
  16. the Advanced Error Reporting capability. The baseline capability is
  17. required of all PCI Express components providing a minimum defined
  18. set of error reporting requirements. Advanced Error Reporting
  19. capability is implemented with a PCI Express advanced error reporting
  20. extended capability structure providing more robust error reporting.
  21. The PCI Express AER driver provides the infrastructure to support PCI
  22. Express Advanced Error Reporting capability. The PCI Express AER
  23. driver provides three basic functions:
  24. - Gathers the comprehensive error information if errors occurred.
  25. - Reports error to the users.
  26. - Performs error recovery actions.
  27. AER driver only attaches root ports which support PCI-Express AER
  28. capability.
  29. 2. User Guide
  30. 2.1 Include the PCI Express AER Root Driver into the Linux Kernel
  31. The PCI Express AER Root driver is a Root Port service driver attached
  32. to the PCI Express Port Bus driver. If a user wants to use it, the driver
  33. has to be compiled. Option CONFIG_PCIEAER supports this capability. It
  34. depends on CONFIG_PCIEPORTBUS, so pls. set CONFIG_PCIEPORTBUS=y and
  35. CONFIG_PCIEAER = y.
  36. 2.2 Load PCI Express AER Root Driver
  37. There is a case where a system has AER support in BIOS. Enabling the AER
  38. Root driver and having AER support in BIOS may result unpredictable
  39. behavior. To avoid this conflict, a successful load of the AER Root driver
  40. requires ACPI _OSC support in the BIOS to allow the AER Root driver to
  41. request for native control of AER. See the PCI FW 3.0 Specification for
  42. details regarding OSC usage. Currently, lots of firmwares don't provide
  43. _OSC support while they use PCI Express. To support such firmwares,
  44. forceload, a parameter of type bool, could enable AER to continue to
  45. be initiated although firmwares have no _OSC support. To enable the
  46. walkaround, pls. add aerdriver.forceload=y to kernel boot parameter line
  47. when booting kernel. Note that forceload=n by default.
  48. nosourceid, another parameter of type bool, can be used when broken
  49. hardware (mostly chipsets) has root ports that cannot obtain the reporting
  50. source ID. nosourceid=n by default.
  51. 2.3 AER error output
  52. When a PCI-E AER error is captured, an error message will be outputed to
  53. console. If it's a correctable error, it is outputed as a warning.
  54. Otherwise, it is printed as an error. So users could choose different
  55. log level to filter out correctable error messages.
  56. Below shows an example.
  57. +------ PCI-Express Device Error -----+
  58. Error Severity : Uncorrected (Fatal)
  59. PCIE Bus Error type : Transaction Layer
  60. Unsupported Request : First
  61. Requester ID : 0500
  62. VendorID=8086h, DeviceID=0329h, Bus=05h, Device=00h, Function=00h
  63. TLB Header:
  64. 04000001 00200a03 05010000 00050100
  65. In the example, 'Requester ID' means the ID of the device who sends
  66. the error message to root port. Pls. refer to pci express specs for
  67. other fields.
  68. 3. Developer Guide
  69. To enable AER aware support requires a software driver to configure
  70. the AER capability structure within its device and to provide callbacks.
  71. To support AER better, developers need understand how AER does work
  72. firstly.
  73. PCI Express errors are classified into two types: correctable errors
  74. and uncorrectable errors. This classification is based on the impacts
  75. of those errors, which may result in degraded performance or function
  76. failure.
  77. Correctable errors pose no impacts on the functionality of the
  78. interface. The PCI Express protocol can recover without any software
  79. intervention or any loss of data. These errors are detected and
  80. corrected by hardware. Unlike correctable errors, uncorrectable
  81. errors impact functionality of the interface. Uncorrectable errors
  82. can cause a particular transaction or a particular PCI Express link
  83. to be unreliable. Depending on those error conditions, uncorrectable
  84. errors are further classified into non-fatal errors and fatal errors.
  85. Non-fatal errors cause the particular transaction to be unreliable,
  86. but the PCI Express link itself is fully functional. Fatal errors, on
  87. the other hand, cause the link to be unreliable.
  88. When AER is enabled, a PCI Express device will automatically send an
  89. error message to the PCIE root port above it when the device captures
  90. an error. The Root Port, upon receiving an error reporting message,
  91. internally processes and logs the error message in its PCI Express
  92. capability structure. Error information being logged includes storing
  93. the error reporting agent's requestor ID into the Error Source
  94. Identification Registers and setting the error bits of the Root Error
  95. Status Register accordingly. If AER error reporting is enabled in Root
  96. Error Command Register, the Root Port generates an interrupt if an
  97. error is detected.
  98. Note that the errors as described above are related to the PCI Express
  99. hierarchy and links. These errors do not include any device specific
  100. errors because device specific errors will still get sent directly to
  101. the device driver.
  102. 3.1 Configure the AER capability structure
  103. AER aware drivers of PCI Express component need change the device
  104. control registers to enable AER. They also could change AER registers,
  105. including mask and severity registers. Helper function
  106. pci_enable_pcie_error_reporting could be used to enable AER. See
  107. section 3.3.
  108. 3.2. Provide callbacks
  109. 3.2.1 callback reset_link to reset pci express link
  110. This callback is used to reset the pci express physical link when a
  111. fatal error happens. The root port aer service driver provides a
  112. default reset_link function, but different upstream ports might
  113. have different specifications to reset pci express link, so all
  114. upstream ports should provide their own reset_link functions.
  115. In struct pcie_port_service_driver, a new pointer, reset_link, is
  116. added.
  117. pci_ers_result_t (*reset_link) (struct pci_dev *dev);
  118. Section 3.2.2.2 provides more detailed info on when to call
  119. reset_link.
  120. 3.2.2 PCI error-recovery callbacks
  121. The PCI Express AER Root driver uses error callbacks to coordinate
  122. with downstream device drivers associated with a hierarchy in question
  123. when performing error recovery actions.
  124. Data struct pci_driver has a pointer, err_handler, to point to
  125. pci_error_handlers who consists of a couple of callback function
  126. pointers. AER driver follows the rules defined in
  127. pci-error-recovery.txt except pci express specific parts (e.g.
  128. reset_link). Pls. refer to pci-error-recovery.txt for detailed
  129. definitions of the callbacks.
  130. Below sections specify when to call the error callback functions.
  131. 3.2.2.1 Correctable errors
  132. Correctable errors pose no impacts on the functionality of
  133. the interface. The PCI Express protocol can recover without any
  134. software intervention or any loss of data. These errors do not
  135. require any recovery actions. The AER driver clears the device's
  136. correctable error status register accordingly and logs these errors.
  137. 3.2.2.2 Non-correctable (non-fatal and fatal) errors
  138. If an error message indicates a non-fatal error, performing link reset
  139. at upstream is not required. The AER driver calls error_detected(dev,
  140. pci_channel_io_normal) to all drivers associated within a hierarchy in
  141. question. for example,
  142. EndPoint<==>DownstreamPort B<==>UpstreamPort A<==>RootPort.
  143. If Upstream port A captures an AER error, the hierarchy consists of
  144. Downstream port B and EndPoint.
  145. A driver may return PCI_ERS_RESULT_CAN_RECOVER,
  146. PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on
  147. whether it can recover or the AER driver calls mmio_enabled as next.
  148. If an error message indicates a fatal error, kernel will broadcast
  149. error_detected(dev, pci_channel_io_frozen) to all drivers within
  150. a hierarchy in question. Then, performing link reset at upstream is
  151. necessary. As different kinds of devices might use different approaches
  152. to reset link, AER port service driver is required to provide the
  153. function to reset link. Firstly, kernel looks for if the upstream
  154. component has an aer driver. If it has, kernel uses the reset_link
  155. callback of the aer driver. If the upstream component has no aer driver
  156. and the port is downstream port, we will use the aer driver of the
  157. root port who reports the AER error. As for upstream ports,
  158. they should provide their own aer service drivers with reset_link
  159. function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and
  160. reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
  161. to mmio_enabled.
  162. 3.3 helper functions
  163. 3.3.1 int pci_enable_pcie_error_reporting(struct pci_dev *dev);
  164. pci_enable_pcie_error_reporting enables the device to send error
  165. messages to root port when an error is detected. Note that devices
  166. don't enable the error reporting by default, so device drivers need
  167. call this function to enable it.
  168. 3.3.2 int pci_disable_pcie_error_reporting(struct pci_dev *dev);
  169. pci_disable_pcie_error_reporting disables the device to send error
  170. messages to root port when an error is detected.
  171. 3.3.3 int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
  172. pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable
  173. error status register.
  174. 3.4 Frequent Asked Questions
  175. Q: What happens if a PCI Express device driver does not provide an
  176. error recovery handler (pci_driver->err_handler is equal to NULL)?
  177. A: The devices attached with the driver won't be recovered. If the
  178. error is fatal, kernel will print out warning messages. Please refer
  179. to section 3 for more information.
  180. Q: What happens if an upstream port service driver does not provide
  181. callback reset_link?
  182. A: Fatal error recovery will fail if the errors are reported by the
  183. upstream ports who are attached by the service driver.
  184. Q: How does this infrastructure deal with driver that is not PCI
  185. Express aware?
  186. A: This infrastructure calls the error callback functions of the
  187. driver when an error happens. But if the driver is not aware of
  188. PCI Express, the device might not report its own errors to root
  189. port.
  190. Q: What modifications will that driver need to make it compatible
  191. with the PCI Express AER Root driver?
  192. A: It could call the helper functions to enable AER in devices and
  193. cleanup uncorrectable status register. Pls. refer to section 3.3.
  194. 4. Software error injection
  195. Debugging PCIE AER error recovery code is quite difficult because it
  196. is hard to trigger real hardware errors. Software based error
  197. injection can be used to fake various kinds of PCIE errors.
  198. First you should enable PCIE AER software error injection in kernel
  199. configuration, that is, following item should be in your .config.
  200. CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m
  201. After reboot with new kernel or insert the module, a device file named
  202. /dev/aer_inject should be created.
  203. Then, you need a user space tool named aer-inject, which can be gotten
  204. from:
  205. http://www.kernel.org/pub/linux/utils/pci/aer-inject/
  206. More information about aer-inject can be found in the document comes
  207. with its source code.