/* Common header-file of the Linux driver for the Afatech 9005
 * USB1.1 DVB-T receiver.
 *
 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
 *
 * Thanks to Afatech who kindly provided information.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * see Documentation/dvb/README.dvb-usb for more information
 */
#ifndef _DVB_USB_AF9005_H_
#define _DVB_USB_AF9005_H_

#define DVB_USB_LOG_PREFIX "af9005"
#include "dvb-usb.h"

extern int dvb_usb_af9005_debug;
#define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
#define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
#define deb_rc(args...)   dprintk(dvb_usb_af9005_debug,0x04,args)
#define deb_reg(args...)  dprintk(dvb_usb_af9005_debug,0x08,args)
#define deb_i2c(args...)  dprintk(dvb_usb_af9005_debug,0x10,args)
#define deb_fw(args...)   dprintk(dvb_usb_af9005_debug,0x20,args)

extern int dvb_usb_af9005_led;

/* firmware */
#define FW_BULKOUT_SIZE 250
enum {
	FW_CONFIG,
	FW_CONFIRM,
	FW_BOOT
};

/* af9005 commands */
#define AF9005_OFDM_REG  0
#define AF9005_TUNER_REG 1

#define AF9005_REGISTER_RW     0x20
#define AF9005_REGISTER_RW_ACK 0x21

#define AF9005_CMD_OFDM_REG 0x00
#define AF9005_CMD_TUNER    0x80
#define AF9005_CMD_BURST    0x02
#define AF9005_CMD_AUTOINC  0x04
#define AF9005_CMD_READ     0x00
#define AF9005_CMD_WRITE    0x01

/* af9005 registers */
#define APO_REG_RESET					0xAEFF

#define APO_REG_I2C_RW_CAN_TUNER            0xF000
#define APO_REG_I2C_RW_SILICON_TUNER        0xF001
#define APO_REG_GPIO_RW_SILICON_TUNER       0xFFFE	/*  also for OFSM */
#define APO_REG_TRIGGER_OFSM                0xFFFF	/*  also for OFSM */

/***********************************************************************
 *  Apollo Registers from VLSI					       *
 ***********************************************************************/
#define xd_p_reg_aagc_inverted_agc	0xA000
#define	reg_aagc_inverted_agc_pos 0
#define	reg_aagc_inverted_agc_len 1
#define	reg_aagc_inverted_agc_lsb 0
#define xd_p_reg_aagc_sign_only	0xA000
#define	reg_aagc_sign_only_pos 1
#define	reg_aagc_sign_only_len 1
#define	reg_aagc_sign_only_lsb 0
#define xd_p_reg_aagc_slow_adc_en	0xA000
#define	reg_aagc_slow_adc_en_pos 2
#define	reg_aagc_slow_adc_en_len 1
#define	reg_aagc_slow_adc_en_lsb 0
#define xd_p_reg_aagc_slow_adc_scale	0xA000
#define	reg_aagc_slow_adc_scale_pos 3
#define	reg_aagc_slow_adc_scale_len 5
#define	reg_aagc_slow_adc_scale_lsb 0
#define xd_p_reg_aagc_check_slow_adc_lock	0xA001
#define	reg_aagc_check_slow_adc_lock_pos 0
#define	reg_aagc_check_slow_adc_lock_len 1
#define	reg_aagc_check_slow_adc_lock_lsb 0
#define xd_p_reg_aagc_init_control	0xA001
#define	reg_aagc_init_control_pos 1
#define	reg_aagc_init_control_len 1
#define	reg_aagc_init_control_lsb 0
#define xd_p_reg_aagc_total_gain_sel	0xA001
#define	reg_aagc_total_gain_sel_pos 2
#define	reg_aagc_total_gain_sel_len 2
#define	reg_aagc_total_gain_sel_lsb 0
#define xd_p_reg_aagc_out_inv	0xA001
#define	reg_aagc_out_inv_pos 5
#define	reg_aagc_out_inv_len 1
#define	reg_aagc_out_inv_lsb 0
#define xd_p_reg_aagc_int_en	0xA001
#define	reg_aagc_int_en_pos 6
#define	reg_aagc_int_en_len 1
#define	reg_aagc_int_en_lsb 0
#define xd_p_reg_aagc_lock_change_flag	0xA001
#define	reg_aagc_lock_change_flag_pos 7
#define	reg_aagc_lock_change_flag_len 1
#define	reg_aagc_lock_change_flag_lsb 0
#define xd_p_reg_aagc_rf_loop_bw_scale_acquire	0xA002
#define	reg_aagc_rf_loop_bw_scale_acquire_pos 0
#define	reg_aagc_rf_loop_bw_scale_acquire_len 5
#define	reg_aagc_rf_loop_bw_scale_acquire_lsb 0
#define xd_p_reg_aagc_rf_loop_bw_scale_track	0xA003
#define	reg_aagc_rf_loop_bw_scale_track_pos 0
#define	reg_aagc_rf_loop_bw_scale_track_len 5
#define	reg_aagc_rf_loop_bw_scale_track_lsb 0
#define xd_p_reg_aagc_if_loop_bw_scale_acquire	0xA004
#define	reg_aagc_if_loop_bw_scale_acquire_pos 0
#define	reg_aagc_if_loop_bw_scale_acquire_len 5
#define	reg_aagc_if_loop_bw_scale_acquire_lsb 0
#define xd_p_reg_aagc_if_loop_bw_scale_track	0xA005
#define	reg_aagc_if_loop_bw_scale_track_pos 0
#define	reg_aagc_if_loop_bw_scale_track_len 5
#define	reg_aagc_if_loop_bw_scale_track_lsb 0
#define xd_p_reg_aagc_max_rf_agc_7_0	0xA006
#define	reg_aagc_max_rf_agc_7_0_pos 0
#define	reg_aagc_max_rf_agc_7_0_len 8
#define	reg_aagc_max_rf_agc_7_0_lsb 0
#define xd_p_reg_aagc_max_rf_agc_9_8	0xA007
#define	reg_aagc_max_rf_agc_9_8_pos 0
#define	reg_aagc_max_rf_agc_9_8_len 2
#define	reg_aagc_max_rf_agc_9_8_lsb 8
#define xd_p_reg_aagc_min_rf_agc_7_0	0xA008
#define	reg_aagc_min_rf_agc_7_0_pos 0
#define	reg_aagc_min_rf_agc_7_0_len 8
#define	reg_aagc_min_rf_agc_7_0_lsb 0
#define xd_p_reg_aagc_min_rf_agc_9_8	0xA009
#define	reg_aagc_min_rf_agc_9_8_pos 0
#define	reg_aagc_min_rf_agc_9_8_len 2
#define	reg_aagc_min_rf_agc_9_8_lsb 8
#define xd_p_reg_aagc_max_if_agc_7_0	0xA00A
#define	reg_aagc_max_if_agc_7_0_pos 0
#define	reg_aagc_max_if_agc_7_0_len 8
#define	reg_aagc_max_if_agc_7_0_lsb 0
#define xd_p_reg_aagc_max_if_agc_9_8	0xA00B
#define	reg_aagc_max_if_agc_9_8_pos 0
#define	reg_aagc_max_if_agc_9_8_len 2
#define	reg_aagc_max_if_agc_9_8_lsb 8
#define xd_p_reg_aagc_min_if_agc_7_0	0xA00C
#define	reg_aagc_min_if_agc_7_0_pos 0
#define	reg_aagc_min_if_agc_7_0_len 8
#define	reg_aagc_min_if_agc_7_0_lsb 0
#define xd_p_reg_aagc_min_if_agc_9_8	0xA00D
#define	reg_aagc_min_if_agc_9_8_pos 0
#define	reg_aagc_min_if_agc_9_8_len 2
#define	reg_aagc_min_if_agc_9_8_lsb 8
#define xd_p_reg_aagc_lock_sample_scale	0xA00E
#define	reg_aagc_lock_sample_scale_pos 0
#define	reg_aagc_lock_sample_scale_len 5
#define	reg_aagc_lock_sample_scale_lsb 0
#define xd_p_reg_aagc_rf_agc_lock_scale_acquire	0xA00F
#define	reg_aagc_rf_agc_lock_scale_acquire_pos 0
#define	reg_aagc_rf_agc_lock_scale_acquire_len 3
#define	reg_aagc_rf_agc_lock_scale_acquire_lsb 0
#define xd_p_reg_aagc_rf_agc_lock_scale_track	0xA00F
#define	reg_aagc_rf_agc_lock_scale_track_pos 3
#define	reg_aagc_rf_agc_lock_scale_track_len 3
#define	reg_aagc_rf_agc_lock_scale_track_lsb 0
#define xd_p_reg_aagc_if_agc_lock_scale_acquire	0xA010
#define	reg_aagc_if_agc_lock_scale_acquire_pos 0
#define	reg_aagc_if_agc_lock_scale_acquire_len 3
#define	reg_aagc_if_agc_lock_scale_acquire_lsb 0
#define xd_p_reg_aagc_if_agc_lock_scale_track	0xA010
#define	reg_aagc_if_agc_lock_scale_track_pos 3
#define	reg_aagc_if_agc_lock_scale_track_len 3
#define	reg_aagc_if_agc_lock_scale_track_lsb 0
#define xd_p_reg_aagc_rf_top_numerator_7_0	0xA011
#define	reg_aagc_rf_top_numerator_7_0_pos 0
#define	reg_aagc_rf_top_numerator_7_0_len 8
#define	reg_aagc_rf_top_numerator_7_0_lsb 0
#define xd_p_reg_aagc_rf_top_numerator_9_8	0xA012
#define	reg_aagc_rf_top_numerator_9_8_pos 0
#define	reg_aagc_rf_top_numerator_9_8_len 2
#define	reg_aagc_rf_top_numerator_9_8_lsb 8
#define xd_p_reg_aagc_if_top_numerator_7_0	0xA013
#define	reg_aagc_if_top_numerator_7_0_pos 0
#define	reg_aagc_if_top_numerator_7_0_len 8
#define	reg_aagc_if_top_numerator_7_0_lsb 0
#define xd_p_reg_aagc_if_top_numerator_9_8	0xA014
#define	reg_aagc_if_top_numerator_9_8_pos 0
#define	reg_aagc_if_top_numerator_9_8_len 2
#define	reg_aagc_if_top_numerator_9_8_lsb 8
#define xd_p_reg_aagc_adc_out_desired_7_0	0xA015
#define	reg_aagc_adc_out_desired_7_0_pos 0
#define	reg_aagc_adc_out_desired_7_0_len 8
#define	reg_aagc_adc_out_desired_7_0_lsb 0
#define xd_p_reg_aagc_adc_out_desired_8	0xA016
#define	reg_aagc_adc_out_desired_8_pos 0
#define	reg_aagc_adc_out_desired_8_len 1
#define	reg_aagc_adc_out_desired_8_lsb 0
#define xd_p_reg_aagc_fixed_gain	0xA016
#define	reg_aagc_fixed_gain_pos 3
#define	reg_aagc_fixed_gain_len 1
#define	reg_aagc_fixed_gain_lsb 0
#define xd_p_reg_aagc_lock_count_th	0xA016
#define	reg_aagc_lock_count_th_pos 4
#define	reg_aagc_lock_count_th_len 4
#define	reg_aagc_lock_count_th_lsb 0
#define xd_p_reg_aagc_fixed_rf_agc_control_7_0	0xA017
#define	reg_aagc_fixed_rf_agc_control_7_0_pos 0
#define	reg_aagc_fixed_rf_agc_control_7_0_len 8
#define	reg_aagc_fixed_rf_agc_control_7_0_lsb 0
#define xd_p_reg_aagc_fixed_rf_agc_control_15_8	0xA018
#define	reg_aagc_fixed_rf_agc_control_15_8_pos 0
#define	reg_aagc_fixed_rf_agc_control_15_8_len 8
#define	reg_aagc_fixed_rf_agc_control_15_8_lsb 8
#define xd_p_reg_aagc_fixed_rf_agc_control_23_16	0xA019
#define	reg_aagc_fixed_rf_agc_control_23_16_pos 0
#define	reg_aagc_fixed_rf_agc_control_23_16_len 8
#define	reg_aagc_fixed_rf_agc_control_23_16_lsb 16
#define xd_p_reg_aagc_fixed_rf_agc_control_30_24	0xA01A
#define	reg_aagc_fixed_rf_agc_control_30_24_pos 0
#define	reg_aagc_fixed_rf_agc_control_30_24_len 7
#define	reg_aagc_fixed_rf_agc_control_30_24_lsb 24
#define xd_p_reg_aagc_fixed_if_agc_control_7_0	0xA01B
#define	reg_aagc_fixed_if_agc_control_7_0_pos 0
#define	reg_aagc_fixed_if_agc_control_7_0_len 8
#define	reg_aagc_fixed_if_agc_control_7_0_lsb 0
#define xd_p_reg_aagc_fixed_if_agc_control_15_8	0xA01C
#define	reg_aagc_fixed_if_agc_control_15_8_pos 0
#define	reg_aagc_fixed_if_agc_control_15_8_len 8
#define	reg_aagc_fixed_if_agc_control_15_8_lsb 8
#define xd_p_reg_aagc_fixed_if_agc_control_23_16	0xA01D
#define	reg_aagc_fixed_if_agc_control_23_16_pos 0
#define	reg_aagc_fixed_if_agc_control_23_16_len 8
#define	reg_aagc_fixed_if_agc_control_23_16_lsb 16
#define xd_p_reg_aagc_fixed_if_agc_control_30_24	0xA01E
#define	reg_aagc_fixed_if_agc_control_30_24_pos 0
#define	reg_aagc_fixed_if_agc_control_30_24_len 7
#define	reg_aagc_fixed_if_agc_control_30_24_lsb 24
#define xd_p_reg_aagc_rf_agc_unlock_numerator	0xA01F
#define	reg_aagc_rf_agc_unlock_numerator_pos 0
#define	reg_aagc_rf_agc_unlock_numerator_len 6
#define	reg_aagc_rf_agc_unlock_numerator_lsb 0
#define xd_p_reg_aagc_if_agc_unlock_numerator	0xA020
#define	reg_aagc_if_agc_unlock_numerator_pos 0
#define	reg_aagc_if_agc_unlock_numerator_len 6
#define	reg_aagc_if_agc_unlock_numerator_lsb 0
#define xd_p_reg_unplug_th	0xA021
#define	reg_unplug_th_pos 0
#define	reg_unplug_th_len 8
#define	reg_aagc_rf_x0_lsb 0
#define xd_p_reg_weak_signal_rfagc_thr 0xA022
#define	reg_weak_signal_rfagc_thr_pos 0
#define	reg_weak_signal_rfagc_thr_len 8
#define	reg_weak_signal_rfagc_thr_lsb 0
#define xd_p_reg_unplug_rf_gain_th 0xA023
#define	reg_unplug_rf_gain_th_pos 0
#define	reg_unplug_rf_gain_th_len 8
#define	reg_unplug_rf_gain_th_lsb 0
#define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
#define	reg_unplug_dtop_rf_gain_th_pos 0
#define	reg_unplug_dtop_rf_gain_th_len 8
#define	reg_unplug_dtop_rf_gain_th_lsb 0
#define xd_p_reg_unplug_dtop_if_gain_th 0xA025
#define	reg_unplug_dtop_if_gain_th_pos 0
#define	reg_unplug_dtop_if_gain_th_len 8
#define	reg_unplug_dtop_if_gain_th_lsb 0
#define xd_p_reg_top_recover_at_unplug_en 0xA026
#define	reg_top_recover_at_unplug_en_pos 0
#define	reg_top_recover_at_unplug_en_len 1
#define	reg_top_recover_at_unplug_en_lsb 0
#define xd_p_reg_aagc_rf_x6	0xA027
#define	reg_aagc_rf_x6_pos 0
#define	reg_aagc_rf_x6_len 8
#define	reg_aagc_rf_x6_lsb 0
#define xd_p_reg_aagc_rf_x7	0xA028
#define	reg_aagc_rf_x7_pos 0
#define	reg_aagc_rf_x7_len 8
#define	reg_aagc_rf_x7_lsb 0
#define xd_p_reg_aagc_rf_x8	0xA029
#define	reg_aagc_rf_x8_pos 0
#define	reg_aagc_rf_x8_len 8
#define	reg_aagc_rf_x8_lsb 0
#define xd_p_reg_aagc_rf_x9	0xA02A
#define	reg_aagc_rf_x9_pos 0
#define	reg_aagc_rf_x9_len 8
#define	reg_aagc_rf_x9_lsb 0
#define xd_p_reg_aagc_rf_x10	0xA02B
#define	reg_aagc_rf_x10_pos 0
#define	reg_aagc_rf_x10_len 8
#define	reg_aagc_rf_x10_lsb 0
#define xd_p_reg_aagc_rf_x11	0xA02C
#define	reg_aagc_rf_x11_pos 0
#define	reg_aagc_rf_x11_len 8
#define	reg_aagc_rf_x11_lsb 0
#define xd_p_reg_aagc_rf_x12	0xA02D
#define	reg_aagc_rf_x12_pos 0
#define	reg_aagc_rf_x12_len 8
#define	reg_aagc_rf_x12_lsb 0
#define xd_p_reg_aagc_rf_x13	0xA02E
#define	reg_aagc_rf_x13_pos 0
#define	reg_aagc_rf_x13_len 8
#define	reg_aagc_rf_x13_lsb 0
#define xd_p_reg_aagc_if_x0	0xA02F
#define	reg_aagc_if_x0_pos 0
#define	reg_aagc_if_x0_len 8
#define	reg_aagc_if_x0_lsb 0
#define xd_p_reg_aagc_if_x1	0xA030
#define	reg_aagc_if_x1_pos 0
#define	reg_aagc_if_x1_len 8
#define	reg_aagc_if_x1_lsb 0
#define xd_p_reg_aagc_if_x2	0xA031
#define	reg_aagc_if_x2_pos 0
#define	reg_aagc_if_x2_len 8
#define	reg_aagc_if_x2_lsb 0
#define xd_p_reg_aagc_if_x3	0xA032
#define	reg_aagc_if_x3_pos 0
#define	reg_aagc_if_x3_len 8
#define	reg_aagc_if_x3_lsb 0
#define xd_p_reg_aagc_if_x4	0xA033
#define	reg_aagc_if_x4_pos 0
#define	reg_aagc_if_x4_len 8
#define	reg_aagc_if_x4_lsb 0
#define xd_p_reg_aagc_if_x5	0xA034
#define	reg_aagc_if_x5_pos 0
#define	reg_aagc_if_x5_len 8
#define	reg_aagc_if_x5_lsb 0
#define xd_p_reg_aagc_if_x6	0xA035
#define	reg_aagc_if_x6_pos 0
#define	reg_aagc_if_x6_len 8
#define	reg_aagc_if_x6_lsb 0
#define xd_p_reg_aagc_if_x7	0xA036
#define	reg_aagc_if_x7_pos 0
#define	reg_aagc_if_x7_len 8
#define	reg_aagc_if_x7_lsb 0
#define xd_p_reg_aagc_if_x8	0xA037
#define	reg_aagc_if_x8_pos 0
#define	reg_aagc_if_x8_len 8
#define	reg_aagc_if_x8_lsb 0
#define xd_p_reg_aagc_if_x9	0xA038
#define	reg_aagc_if_x9_pos 0
#define	reg_aagc_if_x9_len 8
#define	reg_aagc_if_x9_lsb 0
#define xd_p_reg_aagc_if_x10	0xA039
#define	reg_aagc_if_x10_pos 0
#define	reg_aagc_if_x10_len 8
#define	reg_aagc_if_x10_lsb 0
#define xd_p_reg_aagc_if_x11	0xA03A
#define	reg_aagc_if_x11_pos 0
#define	reg_aagc_if_x11_len 8
#define	reg_aagc_if_x11_lsb 0
#define xd_p_reg_aagc_if_x12	0xA03B
#define	reg_aagc_if_x12_pos 0
#define	reg_aagc_if_x12_len 8
#define	reg_aagc_if_x12_lsb 0
#define xd_p_reg_aagc_if_x13	0xA03C
#define	reg_aagc_if_x13_pos 0
#define	reg_aagc_if_x13_len 8
#define	reg_aagc_if_x13_lsb 0
#define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca	0xA03D
#define	reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
#define	reg_aagc_min_rf_ctl_8bit_for_dca_len 8
#define	reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
#define xd_p_reg_aagc_min_if_ctl_8bit_for_dca	0xA03E
#define	reg_aagc_min_if_ctl_8bit_for_dca_pos 0
#define	reg_aagc_min_if_ctl_8bit_for_dca_len 8
#define	reg_aagc_min_if_ctl_8bit_for_dca_lsb 0
#define xd_r_reg_aagc_total_gain_7_0	0xA070
#define	reg_aagc_total_gain_7_0_pos 0
#define	reg_aagc_total_gain_7_0_len 8
#define	reg_aagc_total_gain_7_0_lsb 0
#define xd_r_reg_aagc_total_gain_15_8	0xA071
#define	reg_aagc_total_gain_15_8_pos 0
#define	reg_aagc_total_gain_15_8_len 8
#define	reg_aagc_total_gain_15_8_lsb 8
#define xd_p_reg_aagc_in_sat_cnt_7_0	0xA074
#define	reg_aagc_in_sat_cnt_7_0_pos 0
#define	reg_aagc_in_sat_cnt_7_0_len 8
#define	reg_aagc_in_sat_cnt_7_0_lsb 0
#define xd_p_reg_aagc_in_sat_cnt_15_8	0xA075
#define	reg_aagc_in_sat_cnt_15_8_pos 0
#define	reg_aagc_in_sat_cnt_15_8_len 8
#define	reg_aagc_in_sat_cnt_15_8_lsb 8
#define xd_p_reg_aagc_in_sat_cnt_23_16	0xA076
#define	reg_aagc_in_sat_cnt_23_16_pos 0
#define	reg_aagc_in_sat_cnt_23_16_len 8
#define	reg_aagc_in_sat_cnt_23_16_lsb 16
#define xd_p_reg_aagc_in_sat_cnt_31_24	0xA077
#define	reg_aagc_in_sat_cnt_31_24_pos 0
#define	reg_aagc_in_sat_cnt_31_24_len 8
#define	reg_aagc_in_sat_cnt_31_24_lsb 24
#define xd_r_reg_aagc_digital_rf_volt_7_0	0xA078
#define	reg_aagc_digital_rf_volt_7_0_pos 0
#define	reg_aagc_digital_rf_volt_7_0_len 8
#define	reg_aagc_digital_rf_volt_7_0_lsb 0
#define xd_r_reg_aagc_digital_rf_volt_9_8	0xA079
#define	reg_aagc_digital_rf_volt_9_8_pos 0
#define	reg_aagc_digital_rf_volt_9_8_len 2
#define	reg_aagc_digital_rf_volt_9_8_lsb 8
#define xd_r_reg_aagc_digital_if_volt_7_0	0xA07A
#define	reg_aagc_digital_if_volt_7_0_pos 0
#define	reg_aagc_digital_if_volt_7_0_len 8
#define	reg_aagc_digital_if_volt_7_0_lsb 0
#define xd_r_reg_aagc_digital_if_volt_9_8	0xA07B
#define	reg_aagc_digital_if_volt_9_8_pos 0
#define	reg_aagc_digital_if_volt_9_8_len 2
#define	reg_aagc_digital_if_volt_9_8_lsb 8
#define xd_r_reg_aagc_rf_gain	0xA07C
#define	reg_aagc_rf_gain_pos 0
#define	reg_aagc_rf_gain_len 8
#define	reg_aagc_rf_gain_lsb 0
#define xd_r_reg_aagc_if_gain	0xA07D
#define	reg_aagc_if_gain_pos 0
#define	reg_aagc_if_gain_len 8
#define	reg_aagc_if_gain_lsb 0
#define xd_p_tinr_imp_indicator	0xA080
#define	tinr_imp_indicator_pos 0
#define	tinr_imp_indicator_len 2
#define	tinr_imp_indicator_lsb 0
#define xd_p_reg_tinr_fifo_size	0xA080
#define	reg_tinr_fifo_size_pos 2
#define	reg_tinr_fifo_size_len 5
#define	reg_tinr_fifo_size_lsb 0
#define xd_p_reg_tinr_saturation_cnt_th	0xA081
#define	reg_tinr_saturation_cnt_th_pos 0
#define	reg_tinr_saturation_cnt_th_len 4
#define	reg_tinr_saturation_cnt_th_lsb 0
#define xd_p_reg_tinr_saturation_th_3_0	0xA081
#define	reg_tinr_saturation_th_3_0_pos 4
#define	reg_tinr_saturation_th_3_0_len 4
#define	reg_tinr_saturation_th_3_0_lsb 0
#define xd_p_reg_tinr_saturation_th_8_4	0xA082
#define	reg_tinr_saturation_th_8_4_pos 0
#define	reg_tinr_saturation_th_8_4_len 5
#define	reg_tinr_saturation_th_8_4_lsb 4
#define xd_p_reg_tinr_imp_duration_th_2k_7_0	0xA083
#define	reg_tinr_imp_duration_th_2k_7_0_pos 0
#define	reg_tinr_imp_duration_th_2k_7_0_len 8
#define	reg_tinr_imp_duration_th_2k_7_0_lsb 0
#define xd_p_reg_tinr_imp_duration_th_2k_8	0xA084
#define	reg_tinr_imp_duration_th_2k_8_pos 0
#define	reg_tinr_imp_duration_th_2k_8_len 1
#define	reg_tinr_imp_duration_th_2k_8_lsb 0
#define xd_p_reg_tinr_imp_duration_th_8k_7_0	0xA085
#define	reg_tinr_imp_duration_th_8k_7_0_pos 0
#define	reg_tinr_imp_duration_th_8k_7_0_len 8
#define	reg_tinr_imp_duration_th_8k_7_0_lsb 0
#define xd_p_reg_tinr_imp_duration_th_8k_10_8	0xA086
#define	reg_tinr_imp_duration_th_8k_10_8_pos 0
#define	reg_tinr_imp_duration_th_8k_10_8_len 3
#define	reg_tinr_imp_duration_th_8k_10_8_lsb 8
#define xd_p_reg_tinr_freq_ratio_6m_7_0	0xA087
#define	reg_tinr_freq_ratio_6m_7_0_pos 0
#define	reg_tinr_freq_ratio_6m_7_0_len 8
#define	reg_tinr_freq_ratio_6m_7_0_lsb 0
#define xd_p_reg_tinr_freq_ratio_6m_12_8	0xA088
#define	reg_tinr_freq_ratio_6m_12_8_pos 0
#define	reg_tinr_freq_ratio_6m_12_8_len 5
#define	reg_tinr_freq_ratio_6m_12_8_lsb 8
#define xd_p_reg_tinr_freq_ratio_7m_7_0	0xA089
#define	reg_tinr_freq_ratio_7m_7_0_pos 0
#define	reg_tinr_freq_ratio_7m_7_0_len 8
#define	reg_tinr_freq_ratio_7m_7_0_lsb 0
#define xd_p_reg_tinr_freq_ratio_7m_12_8	0xA08A
#define	reg_tinr_freq_ratio_7m_12_8_pos 0
#define	reg_tinr_freq_ratio_7m_12_8_len 5
#define	reg_tinr_freq_ratio_7m_12_8_lsb 8
#define xd_p_reg_tinr_freq_ratio_8m_7_0	0xA08B
#define	reg_tinr_freq_ratio_8m_7_0_pos 0
#define	reg_tinr_freq_ratio_8m_7_0_len 8
#define	reg_tinr_freq_ratio_8m_7_0_lsb 0
#define xd_p_reg_tinr_freq_ratio_8m_12_8	0xA08C
#define	reg_tinr_freq_ratio_8m_12_8_pos 0
#define	reg_tinr_freq_ratio_8m_12_8_len 5
#define	reg_tinr_freq_ratio_8m_12_8_lsb 8
#define xd_p_reg_tinr_imp_duration_th_low_2k	0xA08D
#define	reg_tinr_imp_duration_th_low_2k_pos 0
#define	reg_tinr_imp_duration_th_low_2k_len 8
#define	reg_tinr_imp_duration_th_low_2k_lsb 0
#define xd_p_reg_tinr_imp_duration_th_low_8k	0xA08E
#define	reg_tinr_imp_duration_th_low_8k_pos 0
#define	reg_tinr_imp_duration_th_low_8k_len 8
#define	reg_tinr_imp_duration_th_low_8k_lsb 0
#define xd_r_reg_tinr_counter_7_0	0xA090
#define	reg_tinr_counter_7_0_pos 0
#define	reg_tinr_counter_7_0_len 8
#define	reg_tinr_counter_7_0_lsb 0
#define xd_r_reg_tinr_counter_15_8	0xA091
#define	reg_tinr_counter_15_8_pos 0
#define	reg_tinr_counter_15_8_len 8
#define	reg_tinr_counter_15_8_lsb 8
#define xd_p_reg_tinr_adative_tinr_en	0xA093
#define	reg_tinr_adative_tinr_en_pos 0
#define	reg_tinr_adative_tinr_en_len 1
#define	reg_tinr_adative_tinr_en_lsb 0
#define xd_p_reg_tinr_peak_fifo_size	0xA093
#define	reg_tinr_peak_fifo_size_pos 1
#define	reg_tinr_peak_fifo_size_len 5
#define	reg_tinr_peak_fifo_size_lsb 0
#define xd_p_reg_tinr_counter_rst	0xA093
#define	reg_tinr_counter_rst_pos 6
#define	reg_tinr_counter_rst_len 1
#define	reg_tinr_counter_rst_lsb 0
#define xd_p_reg_tinr_search_period_7_0	0xA094
#define	reg_tinr_search_period_7_0_pos 0
#define	reg_tinr_search_period_7_0_len 8
#define	reg_tinr_search_period_7_0_lsb 0
#define xd_p_reg_tinr_search_period_15_8	0xA095
#define	reg_tinr_search_period_15_8_pos 0
#define	reg_tinr_search_period_15_8_len 8
#define	reg_tinr_search_period_15_8_lsb 8
#define xd_p_reg_ccifs_fcw_7_0	0xA0A0
#define	reg_ccifs_fcw_7_0_pos 0
#define	reg_ccifs_fcw_7_0_len 8
#define	reg_ccifs_fcw_7_0_lsb 0
#define xd_p_reg_ccifs_fcw_12_8	0xA0A1
#define	reg_ccifs_fcw_12_8_pos 0
#define	reg_ccifs_fcw_12_8_len 5
#define	reg_ccifs_fcw_12_8_lsb 8
#define xd_p_reg_ccifs_spec_inv	0xA0A1
#define	reg_ccifs_spec_inv_pos 5
#define	reg_ccifs_spec_inv_len 1
#define	reg_ccifs_spec_inv_lsb 0
#define xd_p_reg_gp_trigger	0xA0A2
#define	reg_gp_trigger_pos 0
#define	reg_gp_trigger_len 1
#define	reg_gp_trigger_lsb 0
#define xd_p_reg_trigger_sel	0xA0A2
#define	reg_trigger_sel_pos 1
#define	reg_trigger_sel_len 2
#define	reg_trigger_sel_lsb 0
#define xd_p_reg_debug_ofdm	0xA0A2
#define	reg_debug_ofdm_pos 3
#define	reg_debug_ofdm_len 2
#define	reg_debug_ofdm_lsb 0
#define xd_p_reg_trigger_module_sel	0xA0A3
#define	reg_trigger_module_sel_pos 0
#define	reg_trigger_module_sel_len 6
#define	reg_trigger_module_sel_lsb 0
#define xd_p_reg_trigger_set_sel	0xA0A4
#define	reg_trigger_set_sel_pos 0
#define	reg_trigger_set_sel_len 6
#define	reg_trigger_set_sel_lsb 0
#define xd_p_reg_fw_int_mask_n	0xA0A4
#define	reg_fw_int_mask_n_pos 6
#define	reg_fw_int_mask_n_len 1
#define	reg_fw_int_mask_n_lsb 0
#define xd_p_reg_debug_group	0xA0A5
#define	reg_debug_group_pos 0
#define	reg_debug_group_len 4
#define	reg_debug_group_lsb 0
#define xd_p_reg_odbg_clk_sel	0xA0A5
#define	reg_odbg_clk_sel_pos 4
#define	reg_odbg_clk_sel_len 2
#define	reg_odbg_clk_sel_lsb 0
#define xd_p_reg_ccif_sc	0xA0C0
#define	reg_ccif_sc_pos 0
#define	reg_ccif_sc_len 4
#define	reg_ccif_sc_lsb 0
#define xd_r_reg_ccif_saturate	0xA0C1
#define	reg_ccif_saturate_pos 0
#define	reg_ccif_saturate_len 2
#define	reg_ccif_saturate_lsb 0
#define xd_r_reg_antif_saturate	0xA0C1
#define	reg_antif_saturate_pos 2
#define	reg_antif_saturate_len 4
#define	reg_antif_saturate_lsb 0
#define xd_r_reg_acif_saturate	0xA0C2
#define	reg_acif_saturate_pos 0
#define	reg_acif_saturate_len 8
#define	reg_acif_saturate_lsb 0
#define xd_p_reg_tmr_timer0_threshold_7_0	0xA0C8
#define	reg_tmr_timer0_threshold_7_0_pos 0
#define	reg_tmr_timer0_threshold_7_0_len 8
#define	reg_tmr_timer0_threshold_7_0_lsb 0
#define xd_p_reg_tmr_timer0_threshold_15_8	0xA0C9
#define	reg_tmr_timer0_threshold_15_8_pos 0
#define	reg_tmr_timer0_threshold_15_8_len 8
#define	reg_tmr_timer0_threshold_15_8_lsb 8
#define xd_p_reg_tmr_timer0_enable	0xA0CA
#define	reg_tmr_timer0_enable_pos 0
#define	reg_tmr_timer0_enable_len 1
#define	reg_tmr_timer0_enable_lsb 0
#define xd_p_reg_tmr_timer0_clk_sel	0xA0CA
#define	reg_tmr_timer0_clk_sel_pos 1
#define	reg_tmr_timer0_clk_sel_len 1
#define	reg_tmr_timer0_clk_sel_lsb 0
#define xd_p_reg_tmr_timer0_int	0xA0CA
#define	reg_tmr_timer0_int_pos 2
#define	reg_tmr_timer0_int_len 1
#define	reg_tmr_timer0_int_lsb 0
#define xd_p_reg_tmr_timer0_rst	0xA0CA
#define	reg_tmr_timer0_rst_pos 3
#define	reg_tmr_timer0_rst_len 1
#define	reg_tmr_timer0_rst_lsb 0
#define xd_r_reg_tmr_timer0_count_7_0	0xA0CB
#define	reg_tmr_timer0_count_7_0_pos 0
#define	reg_tmr_timer0_count_7_0_len 8
#define	reg_tmr_timer0_count_7_0_lsb 0
#define xd_r_reg_tmr_timer0_count_15_8	0xA0CC
#define	reg_tmr_timer0_count_15_8_pos 0
#define	reg_tmr_timer0_count_15_8_len 8
#define	reg_tmr_timer0_count_15_8_lsb 8
#define xd_p_reg_suspend	0xA0CD
#define	reg_suspend_pos 0
#define	reg_suspend_len 1
#define	reg_suspend_lsb 0
#define xd_p_reg_suspend_rdy	0xA0CD
#define	reg_suspend_rdy_pos 1
#define	reg_suspend_rdy_len 1
#define	reg_suspend_rdy_lsb 0
#define xd_p_reg_resume	0xA0CD
#define	reg_resume_pos 2
#define	reg_resume_len 1
#define	reg_resume_lsb 0
#define xd_p_reg_resume_rdy	0xA0CD
#define	reg_resume_rdy_pos 3
#define	reg_resume_rdy_len 1
#define	reg_resume_rdy_lsb 0
#define xd_p_reg_fmf	0xA0CE
#define	reg_fmf_pos 0
#define	reg_fmf_len 8
#define	reg_fmf_lsb 0
#define xd_p_ccid_accumulate_num_2k_7_0	0xA100
#define	ccid_accumulate_num_2k_7_0_pos 0
#define	ccid_accumulate_num_2k_7_0_len 8
#define	ccid_accumulate_num_2k_7_0_lsb 0
#define xd_p_ccid_accumulate_num_2k_12_8	0xA101
#define	ccid_accumulate_num_2k_12_8_pos 0
#define	ccid_accumulate_num_2k_12_8_len 5
#define	ccid_accumulate_num_2k_12_8_lsb 8
#define xd_p_ccid_accumulate_num_8k_7_0	0xA102
#define	ccid_accumulate_num_8k_7_0_pos 0
#define	ccid_accumulate_num_8k_7_0_len 8
#define	ccid_accumulate_num_8k_7_0_lsb 0
#define xd_p_ccid_accumulate_num_8k_14_8	0xA103
#define	ccid_accumulate_num_8k_14_8_pos 0
#define	ccid_accumulate_num_8k_14_8_len 7
#define	ccid_accumulate_num_8k_14_8_lsb 8
#define xd_p_ccid_desired_level_0	0xA103
#define	ccid_desired_level_0_pos 7
#define	ccid_desired_level_0_len 1
#define	ccid_desired_level_0_lsb 0
#define xd_p_ccid_desired_level_8_1	0xA104
#define	ccid_desired_level_8_1_pos 0
#define	ccid_desired_level_8_1_len 8
#define	ccid_desired_level_8_1_lsb 1
#define xd_p_ccid_apply_delay	0xA105
#define	ccid_apply_delay_pos 0
#define	ccid_apply_delay_len 7
#define	ccid_apply_delay_lsb 0
#define xd_p_ccid_CCID_Threshold1	0xA106
#define	ccid_CCID_Threshold1_pos 0
#define	ccid_CCID_Threshold1_len 8
#define	ccid_CCID_Threshold1_lsb 0
#define xd_p_ccid_CCID_Threshold2	0xA107
#define	ccid_CCID_Threshold2_pos 0
#define	ccid_CCID_Threshold2_len 8
#define	ccid_CCID_Threshold2_lsb 0
#define xd_p_reg_ccid_gain_scale	0xA108
#define	reg_ccid_gain_scale_pos 0
#define	reg_ccid_gain_scale_len 4
#define	reg_ccid_gain_scale_lsb 0
#define xd_p_reg_ccid2_passband_gain_set	0xA108
#define	reg_ccid2_passband_gain_set_pos 4
#define	reg_ccid2_passband_gain_set_len 4
#define	reg_ccid2_passband_gain_set_lsb 0
#define xd_r_ccid_multiplier_7_0	0xA109
#define	ccid_multiplier_7_0_pos 0
#define	ccid_multiplier_7_0_len 8
#define	ccid_multiplier_7_0_lsb 0
#define xd_r_ccid_multiplier_15_8	0xA10A
#define	ccid_multiplier_15_8_pos 0
#define	ccid_multiplier_15_8_len 8
#define	ccid_multiplier_15_8_lsb 8
#define xd_r_ccid_right_shift_bits	0xA10B
#define	ccid_right_shift_bits_pos 0
#define	ccid_right_shift_bits_len 4
#define	ccid_right_shift_bits_lsb 0
#define xd_r_reg_ccid_sx_7_0	0xA10C
#define	reg_ccid_sx_7_0_pos 0
#define	reg_ccid_sx_7_0_len 8
#define	reg_ccid_sx_7_0_lsb 0
#define xd_r_reg_ccid_sx_15_8	0xA10D
#define	reg_ccid_sx_15_8_pos 0
#define	reg_ccid_sx_15_8_len 8
#define	reg_ccid_sx_15_8_lsb 8
#define xd_r_reg_ccid_sx_21_16	0xA10E
#define	reg_ccid_sx_21_16_pos 0
#define	reg_ccid_sx_21_16_len 6
#define	reg_ccid_sx_21_16_lsb 16
#define xd_r_reg_ccid_sy_7_0	0xA110
#define	reg_ccid_sy_7_0_pos 0
#define	reg_ccid_sy_7_0_len 8
#define	reg_ccid_sy_7_0_lsb 0
#define xd_r_reg_ccid_sy_15_8	0xA111
#define	reg_ccid_sy_15_8_pos 0
#define	reg_ccid_sy_15_8_len 8
#define	reg_ccid_sy_15_8_lsb 8
#define xd_r_reg_ccid_sy_23_16	0xA112
#define	reg_ccid_sy_23_16_pos 0
#define	reg_ccid_sy_23_16_len 8
#define	reg_ccid_sy_23_16_lsb 16
#define xd_r_reg_ccid2_sz_7_0	0xA114
#define	reg_ccid2_sz_7_0_pos 0
#define	reg_ccid2_sz_7_0_len 8
#define	reg_ccid2_sz_7_0_lsb 0
#define xd_r_reg_ccid2_sz_15_8	0xA115
#define	reg_ccid2_sz_15_8_pos 0
#define	reg_ccid2_sz_15_8_len 8
#define	reg_ccid2_sz_15_8_lsb 8
#define xd_r_reg_ccid2_sz_23_16	0xA116
#define	reg_ccid2_sz_23_16_pos 0
#define	reg_ccid2_sz_23_16_len 8
#define	reg_ccid2_sz_23_16_lsb 16
#define xd_r_reg_ccid2_sz_25_24	0xA117
#define	reg_ccid2_sz_25_24_pos 0
#define	reg_ccid2_sz_25_24_len 2
#define	reg_ccid2_sz_25_24_lsb 24
#define xd_r_reg_ccid2_sy_7_0	0xA118
#define	reg_ccid2_sy_7_0_pos 0
#define	reg_ccid2_sy_7_0_len 8
#define	reg_ccid2_sy_7_0_lsb 0
#define xd_r_reg_ccid2_sy_15_8	0xA119
#define	reg_ccid2_sy_15_8_pos 0
#define	reg_ccid2_sy_15_8_len 8
#define	reg_ccid2_sy_15_8_lsb 8
#define xd_r_reg_ccid2_sy_23_16	0xA11A
#define	reg_ccid2_sy_23_16_pos 0
#define	reg_ccid2_sy_23_16_len 8
#define	reg_ccid2_sy_23_16_lsb 16
#define xd_r_reg_ccid2_sy_25_24	0xA11B
#define	reg_ccid2_sy_25_24_pos 0
#define	reg_ccid2_sy_25_24_len 2
#define	reg_ccid2_sy_25_24_lsb 24
#define xd_p_dagc1_accumulate_num_2k_7_0	0xA120
#define	dagc1_accumulate_num_2k_7_0_pos 0
#define	dagc1_accumulate_num_2k_7_0_len 8
#define	dagc1_accumulate_num_2k_7_0_lsb 0
#define xd_p_dagc1_accumulate_num_2k_12_8	0xA121
#define	dagc1_accumulate_num_2k_12_8_pos 0
#define	dagc1_accumulate_num_2k_12_8_len 5
#define	dagc1_accumulate_num_2k_12_8_lsb 8
#define xd_p_dagc1_accumulate_num_8k_7_0	0xA122
#define	dagc1_accumulate_num_8k_7_0_pos 0
#define	dagc1_accumulate_num_8k_7_0_len 8
#define	dagc1_accumulate_num_8k_7_0_lsb 0
#define xd_p_dagc1_accumulate_num_8k_14_8	0xA123
#define	dagc1_accumulate_num_8k_14_8_pos 0
#define	dagc1_accumulate_num_8k_14_8_len 7
#define	dagc1_accumulate_num_8k_14_8_lsb 8
#define xd_p_dagc1_desired_level_0	0xA123
#define	dagc1_desired_level_0_pos 7
#define	dagc1_desired_level_0_len 1
#define	dagc1_desired_level_0_lsb 0
#define xd_p_dagc1_desired_level_8_1	0xA124
#define	dagc1_desired_level_8_1_pos 0
#define	dagc1_desired_level_8_1_len 8
#define	dagc1_desired_level_8_1_lsb 1
#define xd_p_dagc1_apply_delay	0xA125
#define	dagc1_apply_delay_pos 0
#define	dagc1_apply_delay_len 7
#define	dagc1_apply_delay_lsb 0
#define xd_p_dagc1_bypass_scale_ctl	0xA126
#define	dagc1_bypass_scale_ctl_pos 0
#define	dagc1_bypass_scale_ctl_len 2
#define	dagc1_bypass_scale_ctl_lsb 0
#define xd_p_reg_dagc1_in_sat_cnt_7_0	0xA127
#define	reg_dagc1_in_sat_cnt_7_0_pos 0
#define	reg_dagc1_in_sat_cnt_7_0_len 8
#define	reg_dagc1_in_sat_cnt_7_0_lsb 0
#define xd_p_reg_dagc1_in_sat_cnt_15_8	0xA128
#define	reg_dagc1_in_sat_cnt_15_8_pos 0
#define	reg_dagc1_in_sat_cnt_15_8_len 8
#define	reg_dagc1_in_sat_cnt_15_8_lsb 8
#define xd_p_reg_dagc1_in_sat_cnt_23_16	0xA129
#define	reg_dagc1_in_sat_cnt_23_16_pos 0
#define	reg_dagc1_in_sat_cnt_23_16_len 8
#define	reg_dagc1_in_sat_cnt_23_16_lsb 16
#define xd_p_reg_dagc1_in_sat_cnt_31_24	0xA12A
#define	reg_dagc1_in_sat_cnt_31_24_pos 0
#define	reg_dagc1_in_sat_cnt_31_24_len 8
#define	reg_dagc1_in_sat_cnt_31_24_lsb 24
#define xd_p_reg_dagc1_out_sat_cnt_7_0	0xA12B
#define	reg_dagc1_out_sat_cnt_7_0_pos 0
#define	reg_dagc1_out_sat_cnt_7_0_len 8
#define	reg_dagc1_out_sat_cnt_7_0_lsb 0
#define xd_p_reg_dagc1_out_sat_cnt_15_8	0xA12C
#define	reg_dagc1_out_sat_cnt_15_8_pos 0
#define	reg_dagc1_out_sat_cnt_15_8_len 8
#define	reg_dagc1_out_sat_cnt_15_8_lsb 8
#define xd_p_reg_dagc1_out_sat_cnt_23_16	0xA12D
#define	reg_dagc1_out_sat_cnt_23_16_pos 0
#define	reg_dagc1_out_sat_cnt_23_16_len 8
#define	reg_dagc1_out_sat_cnt_23_16_lsb 16
#define xd_p_reg_dagc1_out_sat_cnt_31_24	0xA12E
#define	reg_dagc1_out_sat_cnt_31_24_pos 0
#define	reg_dagc1_out_sat_cnt_31_24_len 8
#define	reg_dagc1_out_sat_cnt_31_24_lsb 24
#define xd_r_dagc1_multiplier_7_0	0xA136
#define	dagc1_multiplier_7_0_pos 0
#define	dagc1_multiplier_7_0_len 8
#define	dagc1_multiplier_7_0_lsb 0
#define xd_r_dagc1_multiplier_15_8	0xA137
#define	dagc1_multiplier_15_8_pos 0
#define	dagc1_multiplier_15_8_len 8
#define	dagc1_multiplier_15_8_lsb 8
#define xd_r_dagc1_right_shift_bits	0xA138
#define	dagc1_right_shift_bits_pos 0
#define	dagc1_right_shift_bits_len 4
#define	dagc1_right_shift_bits_lsb 0
#define xd_p_reg_bfs_fcw_7_0	0xA140
#define	reg_bfs_fcw_7_0_pos 0
#define	reg_bfs_fcw_7_0_len 8
#define	reg_bfs_fcw_7_0_lsb 0
#define xd_p_reg_bfs_fcw_15_8	0xA141
#define	reg_bfs_fcw_15_8_pos 0
#define	reg_bfs_fcw_15_8_len 8
#define	reg_bfs_fcw_15_8_lsb 8
#define xd_p_reg_bfs_fcw_22_16	0xA142
#define	reg_bfs_fcw_22_16_pos 0
#define	reg_bfs_fcw_22_16_len 7
#define	reg_bfs_fcw_22_16_lsb 16
#define xd_p_reg_antif_sf_7_0	0xA144
#define	reg_antif_sf_7_0_pos 0
#define	reg_antif_sf_7_0_len 8
#define	reg_antif_sf_7_0_lsb 0
#define xd_p_reg_antif_sf_11_8	0xA145
#define	reg_antif_sf_11_8_pos 0
#define	reg_antif_sf_11_8_len 4
#define	reg_antif_sf_11_8_lsb 8
#define xd_r_bfs_fcw_q_7_0	0xA150
#define	bfs_fcw_q_7_0_pos 0
#define	bfs_fcw_q_7_0_len 8
#define	bfs_fcw_q_7_0_lsb 0
#define xd_r_bfs_fcw_q_15_8	0xA151
#define	bfs_fcw_q_15_8_pos 0
#define	bfs_fcw_q_15_8_len 8
#define	bfs_fcw_q_15_8_lsb 8
#define xd_r_bfs_fcw_q_22_16	0xA152
#define	bfs_fcw_q_22_16_pos 0
#define	bfs_fcw_q_22_16_len 7
#define	bfs_fcw_q_22_16_lsb 16
#define xd_p_reg_dca_enu	0xA160
#define	reg_dca_enu_pos 0
#define	reg_dca_enu_len 1
#define	reg_dca_enu_lsb 0
#define xd_p_reg_dca_enl	0xA160
#define	reg_dca_enl_pos 1
#define	reg_dca_enl_len 1
#define	reg_dca_enl_lsb 0
#define xd_p_reg_dca_lower_chip	0xA160
#define	reg_dca_lower_chip_pos 2
#define	reg_dca_lower_chip_len 1
#define	reg_dca_lower_chip_lsb 0
#define xd_p_reg_dca_upper_chip	0xA160
#define	reg_dca_upper_chip_pos 3
#define	reg_dca_upper_chip_len 1
#define	reg_dca_upper_chip_lsb 0
#define xd_p_reg_dca_platch	0xA160
#define	reg_dca_platch_pos 4
#define	reg_dca_platch_len 1
#define	reg_dca_platch_lsb 0
#define xd_p_reg_dca_th	0xA161
#define	reg_dca_th_pos 0
#define	reg_dca_th_len 5
#define	reg_dca_th_lsb 0
#define xd_p_reg_dca_scale	0xA162
#define	reg_dca_scale_pos 0
#define	reg_dca_scale_len 4
#define	reg_dca_scale_lsb 0
#define xd_p_reg_dca_tone_7_0	0xA163
#define	reg_dca_tone_7_0_pos 0
#define	reg_dca_tone_7_0_len 8
#define	reg_dca_tone_7_0_lsb 0
#define xd_p_reg_dca_tone_12_8	0xA164
#define	reg_dca_tone_12_8_pos 0
#define	reg_dca_tone_12_8_len 5
#define	reg_dca_tone_12_8_lsb 8
#define xd_p_reg_dca_time_7_0	0xA165
#define	reg_dca_time_7_0_pos 0
#define	reg_dca_time_7_0_len 8
#define	reg_dca_time_7_0_lsb 0
#define xd_p_reg_dca_time_15_8	0xA166
#define	reg_dca_time_15_8_pos 0
#define	reg_dca_time_15_8_len 8
#define	reg_dca_time_15_8_lsb 8
#define xd_r_dcasm	0xA167
#define	dcasm_pos 0
#define	dcasm_len 3
#define	dcasm_lsb 0
#define xd_p_reg_qnt_valuew_7_0	0xA168
#define	reg_qnt_valuew_7_0_pos 0
#define	reg_qnt_valuew_7_0_len 8
#define	reg_qnt_valuew_7_0_lsb 0
#define xd_p_reg_qnt_valuew_10_8	0xA169
#define	reg_qnt_valuew_10_8_pos 0
#define	reg_qnt_valuew_10_8_len 3
#define	reg_qnt_valuew_10_8_lsb 8
#define xd_p_dca_sbx_gain_diff_7_0	0xA16A
#define	dca_sbx_gain_diff_7_0_pos 0
#define	dca_sbx_gain_diff_7_0_len 8
#define	dca_sbx_gain_diff_7_0_lsb 0
#define xd_p_dca_sbx_gain_diff_9_8	0xA16B
#define	dca_sbx_gain_diff_9_8_pos 0
#define	dca_sbx_gain_diff_9_8_len 2
#define	dca_sbx_gain_diff_9_8_lsb 8
#define xd_p_reg_dca_stand_alone	0xA16C
#define	reg_dca_stand_alone_pos 0
#define	reg_dca_stand_alone_len 1
#define	reg_dca_stand_alone_lsb 0
#define xd_p_reg_dca_upper_out_en	0xA16C
#define	reg_dca_upper_out_en_pos 1
#define	reg_dca_upper_out_en_len 1
#define	reg_dca_upper_out_en_lsb 0
#define xd_p_reg_dca_rc_en	0xA16C
#define	reg_dca_rc_en_pos 2
#define	reg_dca_rc_en_len 1
#define	reg_dca_rc_en_lsb 0
#define xd_p_reg_dca_retrain_send	0xA16C
#define	reg_dca_retrain_send_pos 3
#define	reg_dca_retrain_send_len 1
#define	reg_dca_retrain_send_lsb 0
#define xd_p_reg_dca_retrain_rec	0xA16C
#define	reg_dca_retrain_rec_pos 4
#define	reg_dca_retrain_rec_len 1
#define	reg_dca_retrain_rec_lsb 0
#define xd_p_reg_dca_api_tpsrdy	0xA16C
#define	reg_dca_api_tpsrdy_pos 5
#define	reg_dca_api_tpsrdy_len 1
#define	reg_dca_api_tpsrdy_lsb 0
#define xd_p_reg_dca_symbol_gap	0xA16D
#define	reg_dca_symbol_gap_pos 0
#define	reg_dca_symbol_gap_len 4
#define	reg_dca_symbol_gap_lsb 0
#define xd_p_reg_qnt_nfvaluew_7_0	0xA16E
#define	reg_qnt_nfvaluew_7_0_pos 0
#define	reg_qnt_nfvaluew_7_0_len 8
#define	reg_qnt_nfvaluew_7_0_lsb 0
#define xd_p_reg_qnt_nfvaluew_10_8	0xA16F
#define	reg_qnt_nfvaluew_10_8_pos 0
#define	reg_qnt_nfvaluew_10_8_len 3
#define	reg_qnt_nfvaluew_10_8_lsb 8
#define xd_p_reg_qnt_flatness_thr_7_0	0xA170
#define	reg_qnt_flatness_thr_7_0_pos 0
#define	reg_qnt_flatness_thr_7_0_len 8
#define	reg_qnt_flatness_thr_7_0_lsb 0
#define xd_p_reg_qnt_flatness_thr_9_8	0xA171
#define	reg_qnt_flatness_thr_9_8_pos 0
#define	reg_qnt_flatness_thr_9_8_len 2
#define	reg_qnt_flatness_thr_9_8_lsb 8
#define xd_p_reg_dca_tone_idx_5_0	0xA171
#define	reg_dca_tone_idx_5_0_pos 2
#define	reg_dca_tone_idx_5_0_len 6
#define	reg_dca_tone_idx_5_0_lsb 0
#define xd_p_reg_dca_tone_idx_12_6	0xA172
#define	reg_dca_tone_idx_12_6_pos 0
#define	reg_dca_tone_idx_12_6_len 7
#define	reg_dca_tone_idx_12_6_lsb 6
#define xd_p_reg_dca_data_vld	0xA173
#define	reg_dca_data_vld_pos 0
#define	reg_dca_data_vld_len 1
#define	reg_dca_data_vld_lsb 0
#define xd_p_reg_dca_read_update	0xA173
#define	reg_dca_read_update_pos 1
#define	reg_dca_read_update_len 1
#define	reg_dca_read_update_lsb 0
#define xd_r_reg_dca_data_re_5_0	0xA173
#define	reg_dca_data_re_5_0_pos 2
#define	reg_dca_data_re_5_0_len 6
#define	reg_dca_data_re_5_0_lsb 0
#define xd_r_reg_dca_data_re_10_6	0xA174
#define	reg_dca_data_re_10_6_pos 0
#define	reg_dca_data_re_10_6_len 5
#define	reg_dca_data_re_10_6_lsb 6
#define xd_r_reg_dca_data_im_7_0	0xA175
#define	reg_dca_data_im_7_0_pos 0
#define	reg_dca_data_im_7_0_len 8
#define	reg_dca_data_im_7_0_lsb 0
#define xd_r_reg_dca_data_im_10_8	0xA176
#define	reg_dca_data_im_10_8_pos 0
#define	reg_dca_data_im_10_8_len 3
#define	reg_dca_data_im_10_8_lsb 8
#define xd_r_reg_dca_data_h2_7_0	0xA178
#define	reg_dca_data_h2_7_0_pos 0
#define	reg_dca_data_h2_7_0_len 8
#define	reg_dca_data_h2_7_0_lsb 0
#define xd_r_reg_dca_data_h2_9_8	0xA179
#define	reg_dca_data_h2_9_8_pos 0
#define	reg_dca_data_h2_9_8_len 2
#define	reg_dca_data_h2_9_8_lsb 8
#define xd_p_reg_f_adc_7_0	0xA180
#define	reg_f_adc_7_0_pos 0
#define	reg_f_adc_7_0_len 8
#define	reg_f_adc_7_0_lsb 0
#define xd_p_reg_f_adc_15_8	0xA181
#define	reg_f_adc_15_8_pos 0
#define	reg_f_adc_15_8_len 8
#define	reg_f_adc_15_8_lsb 8
#define xd_p_reg_f_adc_23_16	0xA182
#define	reg_f_adc_23_16_pos 0
#define	reg_f_adc_23_16_len 8
#define	reg_f_adc_23_16_lsb 16
#define xd_r_intp_mu_7_0	0xA190
#define	intp_mu_7_0_pos 0
#define	intp_mu_7_0_len 8
#define	intp_mu_7_0_lsb 0
#define xd_r_intp_mu_15_8	0xA191
#define	intp_mu_15_8_pos 0
#define	intp_mu_15_8_len 8
#define	intp_mu_15_8_lsb 8
#define xd_r_intp_mu_19_16	0xA192
#define	intp_mu_19_16_pos 0
#define	intp_mu_19_16_len 4
#define	intp_mu_19_16_lsb 16
#define xd_p_reg_agc_rst	0xA1A0
#define	reg_agc_rst_pos 0
#define	reg_agc_rst_len 1
#define	reg_agc_rst_lsb 0
#define xd_p_rf_agc_en	0xA1A0
#define	rf_agc_en_pos 1
#define	rf_agc_en_len 1
#define	rf_agc_en_lsb 0
#define xd_p_rf_agc_dis	0xA1A0
#define	rf_agc_dis_pos 2
#define	rf_agc_dis_len 1
#define	rf_agc_dis_lsb 0
#define xd_p_if_agc_rst	0xA1A0
#define	if_agc_rst_pos 3
#define	if_agc_rst_len 1
#define	if_agc_rst_lsb 0
#define xd_p_if_agc_en	0xA1A0
#define	if_agc_en_pos 4
#define	if_agc_en_len 1
#define	if_agc_en_lsb 0
#define xd_p_if_agc_dis	0xA1A0
#define	if_agc_dis_pos 5
#define	if_agc_dis_len 1
#define	if_agc_dis_lsb 0
#define xd_p_agc_lock	0xA1A0
#define	agc_lock_pos 6
#define	agc_lock_len 1
#define	agc_lock_lsb 0
#define xd_p_reg_tinr_rst	0xA1A1
#define	reg_tinr_rst_pos 0
#define	reg_tinr_rst_len 1
#define	reg_tinr_rst_lsb 0
#define xd_p_reg_tinr_en	0xA1A1
#define	reg_tinr_en_pos 1
#define	reg_tinr_en_len 1
#define	reg_tinr_en_lsb 0
#define xd_p_reg_ccifs_en	0xA1A2
#define	reg_ccifs_en_pos 0
#define	reg_ccifs_en_len 1
#define	reg_ccifs_en_lsb 0
#define xd_p_reg_ccifs_dis	0xA1A2
#define	reg_ccifs_dis_pos 1
#define	reg_ccifs_dis_len 1
#define	reg_ccifs_dis_lsb 0
#define xd_p_reg_ccifs_rst	0xA1A2
#define	reg_ccifs_rst_pos 2
#define	reg_ccifs_rst_len 1
#define	reg_ccifs_rst_lsb 0
#define xd_p_reg_ccifs_byp	0xA1A2
#define	reg_ccifs_byp_pos 3
#define	reg_ccifs_byp_len 1
#define	reg_ccifs_byp_lsb 0
#define xd_p_reg_ccif_en	0xA1A3
#define	reg_ccif_en_pos 0
#define	reg_ccif_en_len 1
#define	reg_ccif_en_lsb 0
#define xd_p_reg_ccif_dis	0xA1A3
#define	reg_ccif_dis_pos 1
#define	reg_ccif_dis_len 1
#define	reg_ccif_dis_lsb 0
#define xd_p_reg_ccif_rst	0xA1A3
#define	reg_ccif_rst_pos 2
#define	reg_ccif_rst_len 1
#define	reg_ccif_rst_lsb 0
#define xd_p_reg_ccif_byp	0xA1A3
#define	reg_ccif_byp_pos 3
#define	reg_ccif_byp_len 1
#define	reg_ccif_byp_lsb 0
#define xd_p_dagc1_rst	0xA1A4
#define	dagc1_rst_pos 0
#define	dagc1_rst_len 1
#define	dagc1_rst_lsb 0
#define xd_p_dagc1_en	0xA1A4
#define	dagc1_en_pos 1
#define	dagc1_en_len 1
#define	dagc1_en_lsb 0
#define xd_p_dagc1_mode	0xA1A4
#define	dagc1_mode_pos 2
#define	dagc1_mode_len 2
#define	dagc1_mode_lsb 0
#define xd_p_dagc1_done	0xA1A4
#define	dagc1_done_pos 4
#define	dagc1_done_len 1
#define	dagc1_done_lsb 0
#define xd_p_ccid_rst	0xA1A5
#define	ccid_rst_pos 0
#define	ccid_rst_len 1
#define	ccid_rst_lsb 0
#define xd_p_ccid_en	0xA1A5
#define	ccid_en_pos 1
#define	ccid_en_len 1
#define	ccid_en_lsb 0
#define xd_p_ccid_mode	0xA1A5
#define	ccid_mode_pos 2
#define	ccid_mode_len 2
#define	ccid_mode_lsb 0
#define xd_p_ccid_done	0xA1A5
#define	ccid_done_pos 4
#define	ccid_done_len 1
#define	ccid_done_lsb 0
#define xd_r_ccid_deted	0xA1A5
#define	ccid_deted_pos 5
#define	ccid_deted_len 1
#define	ccid_deted_lsb 0
#define xd_p_ccid2_en	0xA1A5
#define	ccid2_en_pos 6
#define	ccid2_en_len 1
#define	ccid2_en_lsb 0
#define xd_p_ccid2_done	0xA1A5
#define	ccid2_done_pos 7
#define	ccid2_done_len 1
#define	ccid2_done_lsb 0
#define xd_p_reg_bfs_en	0xA1A6
#define	reg_bfs_en_pos 0
#define	reg_bfs_en_len 1
#define	reg_bfs_en_lsb 0
#define xd_p_reg_bfs_dis	0xA1A6
#define	reg_bfs_dis_pos 1
#define	reg_bfs_dis_len 1
#define	reg_bfs_dis_lsb 0
#define xd_p_reg_bfs_rst	0xA1A6
#define	reg_bfs_rst_pos 2
#define	reg_bfs_rst_len 1
#define	reg_bfs_rst_lsb 0
#define xd_p_reg_bfs_byp	0xA1A6
#define	reg_bfs_byp_pos 3
#define	reg_bfs_byp_len 1
#define	reg_bfs_byp_lsb 0
#define xd_p_reg_antif_en	0xA1A7
#define	reg_antif_en_pos 0
#define	reg_antif_en_len 1
#define	reg_antif_en_lsb 0
#define xd_p_reg_antif_dis	0xA1A7
#define	reg_antif_dis_pos 1
#define	reg_antif_dis_len 1
#define	reg_antif_dis_lsb 0
#define xd_p_reg_antif_rst	0xA1A7
#define	reg_antif_rst_pos 2
#define	reg_antif_rst_len 1
#define	reg_antif_rst_lsb 0
#define xd_p_reg_antif_byp	0xA1A7
#define	reg_antif_byp_pos 3
#define	reg_antif_byp_len 1
#define	reg_antif_byp_lsb 0
#define xd_p_intp_en	0xA1A8
#define	intp_en_pos 0
#define	intp_en_len 1
#define	intp_en_lsb 0
#define xd_p_intp_dis	0xA1A8
#define	intp_dis_pos 1
#define	intp_dis_len 1
#define	intp_dis_lsb 0
#define xd_p_intp_rst	0xA1A8
#define	intp_rst_pos 2
#define	intp_rst_len 1
#define	intp_rst_lsb 0
#define xd_p_intp_byp	0xA1A8
#define	intp_byp_pos 3
#define	intp_byp_len 1
#define	intp_byp_lsb 0
#define xd_p_reg_acif_en	0xA1A9
#define	reg_acif_en_pos 0
#define	reg_acif_en_len 1
#define	reg_acif_en_lsb 0
#define xd_p_reg_acif_dis	0xA1A9
#define	reg_acif_dis_pos 1
#define	reg_acif_dis_len 1
#define	reg_acif_dis_lsb 0
#define xd_p_reg_acif_rst	0xA1A9
#define	reg_acif_rst_pos 2
#define	reg_acif_rst_len 1
#define	reg_acif_rst_lsb 0
#define xd_p_reg_acif_byp	0xA1A9
#define	reg_acif_byp_pos 3
#define	reg_acif_byp_len 1
#define	reg_acif_byp_lsb 0
#define xd_p_reg_acif_sync_mode	0xA1A9
#define	reg_acif_sync_mode_pos 4
#define	reg_acif_sync_mode_len 1
#define	reg_acif_sync_mode_lsb 0
#define xd_p_dagc2_rst	0xA1AA
#define	dagc2_rst_pos 0
#define	dagc2_rst_len 1
#define	dagc2_rst_lsb 0
#define xd_p_dagc2_en	0xA1AA
#define	dagc2_en_pos 1
#define	dagc2_en_len 1
#define	dagc2_en_lsb 0
#define xd_p_dagc2_mode	0xA1AA
#define	dagc2_mode_pos 2
#define	dagc2_mode_len 2
#define	dagc2_mode_lsb 0
#define xd_p_dagc2_done	0xA1AA
#define	dagc2_done_pos 4
#define	dagc2_done_len 1
#define	dagc2_done_lsb 0
#define xd_p_reg_dca_en	0xA1AB
#define	reg_dca_en_pos 0
#define	reg_dca_en_len 1
#define	reg_dca_en_lsb 0
#define xd_p_dagc2_accumulate_num_2k_7_0	0xA1C0
#define	dagc2_accumulate_num_2k_7_0_pos 0
#define	dagc2_accumulate_num_2k_7_0_len 8
#define	dagc2_accumulate_num_2k_7_0_lsb 0
#define xd_p_dagc2_accumulate_num_2k_12_8	0xA1C1
#define	dagc2_accumulate_num_2k_12_8_pos 0
#define	dagc2_accumulate_num_2k_12_8_len 5
#define	dagc2_accumulate_num_2k_12_8_lsb 8
#define xd_p_dagc2_accumulate_num_8k_7_0	0xA1C2
#define	dagc2_accumulate_num_8k_7_0_pos 0
#define	dagc2_accumulate_num_8k_7_0_len 8
#define	dagc2_accumulate_num_8k_7_0_lsb 0
#define xd_p_dagc2_accumulate_num_8k_12_8	0xA1C3
#define	dagc2_accumulate_num_8k_12_8_pos 0
#define	dagc2_accumulate_num_8k_12_8_len 5
#define	dagc2_accumulate_num_8k_12_8_lsb 8
#define xd_p_dagc2_desired_level_2_0	0xA1C3
#define	dagc2_desired_level_2_0_pos 5
#define	dagc2_desired_level_2_0_len 3
#define	dagc2_desired_level_2_0_lsb 0
#define xd_p_dagc2_desired_level_8_3	0xA1C4
#define	dagc2_desired_level_8_3_pos 0
#define	dagc2_desired_level_8_3_len 6
#define	dagc2_desired_level_8_3_lsb 3
#define xd_p_dagc2_apply_delay	0xA1C5
#define	dagc2_apply_delay_pos 0
#define	dagc2_apply_delay_len 7
#define	dagc2_apply_delay_lsb 0
#define xd_p_dagc2_bypass_scale_ctl	0xA1C6
#define	dagc2_bypass_scale_ctl_pos 0
#define	dagc2_bypass_scale_ctl_len 3
#define	dagc2_bypass_scale_ctl_lsb 0
#define xd_p_dagc2_programmable_shift1	0xA1C7
#define	dagc2_programmable_shift1_pos 0
#define	dagc2_programmable_shift1_len 8
#define	dagc2_programmable_shift1_lsb 0
#define xd_p_dagc2_programmable_shift2	0xA1C8
#define	dagc2_programmable_shift2_pos 0
#define	dagc2_programmable_shift2_len 8
#define	dagc2_programmable_shift2_lsb 0
#define xd_p_reg_dagc2_in_sat_cnt_7_0	0xA1C9
#define	reg_dagc2_in_sat_cnt_7_0_pos 0
#define	reg_dagc2_in_sat_cnt_7_0_len 8
#define	reg_dagc2_in_sat_cnt_7_0_lsb 0
#define xd_p_reg_dagc2_in_sat_cnt_15_8	0xA1CA
#define	reg_dagc2_in_sat_cnt_15_8_pos 0
#define	reg_dagc2_in_sat_cnt_15_8_len 8
#define	reg_dagc2_in_sat_cnt_15_8_lsb 8
#define xd_p_reg_dagc2_in_sat_cnt_23_16	0xA1CB
#define	reg_dagc2_in_sat_cnt_23_16_pos 0
#define	reg_dagc2_in_sat_cnt_23_16_len 8
#define	reg_dagc2_in_sat_cnt_23_16_lsb 16
#define xd_p_reg_dagc2_in_sat_cnt_31_24	0xA1CC
#define	reg_dagc2_in_sat_cnt_31_24_pos 0
#define	reg_dagc2_in_sat_cnt_31_24_len 8
#define	reg_dagc2_in_sat_cnt_31_24_lsb 24
#define xd_p_reg_dagc2_out_sat_cnt_7_0	0xA1CD
#define	reg_dagc2_out_sat_cnt_7_0_pos 0
#define	reg_dagc2_out_sat_cnt_7_0_len 8
#define	reg_dagc2_out_sat_cnt_7_0_lsb 0
#define xd_p_reg_dagc2_out_sat_cnt_15_8	0xA1CE
#define	reg_dagc2_out_sat_cnt_15_8_pos 0
#define	reg_dagc2_out_sat_cnt_15_8_len 8
#define	reg_dagc2_out_sat_cnt_15_8_lsb 8
#define xd_p_reg_dagc2_out_sat_cnt_23_16	0xA1CF
#define	reg_dagc2_out_sat_cnt_23_16_pos 0
#define	reg_dagc2_out_sat_cnt_23_16_len 8
#define	reg_dagc2_out_sat_cnt_23_16_lsb 16
#define xd_p_reg_dagc2_out_sat_cnt_31_24	0xA1D0
#define	reg_dagc2_out_sat_cnt_31_24_pos 0
#define	reg_dagc2_out_sat_cnt_31_24_len 8
#define	reg_dagc2_out_sat_cnt_31_24_lsb 24
#define xd_r_dagc2_multiplier_7_0	0xA1D6
#define	dagc2_multiplier_7_0_pos 0
#define	dagc2_multiplier_7_0_len 8
#define	dagc2_multiplier_7_0_lsb 0
#define xd_r_dagc2_multiplier_15_8	0xA1D7
#define	dagc2_multiplier_15_8_pos 0
#define	dagc2_multiplier_15_8_len 8
#define	dagc2_multiplier_15_8_lsb 8
#define xd_r_dagc2_right_shift_bits	0xA1D8
#define	dagc2_right_shift_bits_pos 0
#define	dagc2_right_shift_bits_len 4
#define	dagc2_right_shift_bits_lsb 0
#define xd_p_cfoe_NS_coeff1_7_0	0xA200
#define	cfoe_NS_coeff1_7_0_pos 0
#define	cfoe_NS_coeff1_7_0_len 8
#define	cfoe_NS_coeff1_7_0_lsb 0
#define xd_p_cfoe_NS_coeff1_15_8	0xA201
#define	cfoe_NS_coeff1_15_8_pos 0
#define	cfoe_NS_coeff1_15_8_len 8
#define	cfoe_NS_coeff1_15_8_lsb 8
#define xd_p_cfoe_NS_coeff1_23_16	0xA202
#define	cfoe_NS_coeff1_23_16_pos 0
#define	cfoe_NS_coeff1_23_16_len 8
#define	cfoe_NS_coeff1_23_16_lsb 16
#define xd_p_cfoe_NS_coeff1_25_24	0xA203
#define	cfoe_NS_coeff1_25_24_pos 0
#define	cfoe_NS_coeff1_25_24_len 2
#define	cfoe_NS_coeff1_25_24_lsb 24
#define xd_p_cfoe_NS_coeff2_5_0	0xA203
#define	cfoe_NS_coeff2_5_0_pos 2
#define	cfoe_NS_coeff2_5_0_len 6
#define	cfoe_NS_coeff2_5_0_lsb 0
#define xd_p_cfoe_NS_coeff2_13_6	0xA204
#define	cfoe_NS_coeff2_13_6_pos 0
#define	cfoe_NS_coeff2_13_6_len 8
#define	cfoe_NS_coeff2_13_6_lsb 6
#define xd_p_cfoe_NS_coeff2_21_14	0xA205
#define	cfoe_NS_coeff2_21_14_pos 0
#define	cfoe_NS_coeff2_21_14_len 8
#define	cfoe_NS_coeff2_21_14_lsb 14
#define xd_p_cfoe_NS_coeff2_24_22	0xA206
#define	cfoe_NS_coeff2_24_22_pos 0
#define	cfoe_NS_coeff2_24_22_len 3
#define	cfoe_NS_coeff2_24_22_lsb 22
#define xd_p_cfoe_lf_c1_4_0	0xA206
#define	cfoe_lf_c1_4_0_pos 3
#define	cfoe_lf_c1_4_0_len 5
#define	cfoe_lf_c1_4_0_lsb 0
#define xd_p_cfoe_lf_c1_12_5	0xA207
#define	cfoe_lf_c1_12_5_pos 0
#define	cfoe_lf_c1_12_5_len 8
#define	cfoe_lf_c1_12_5_lsb 5
#define xd_p_cfoe_lf_c1_20_13	0xA208
#define	cfoe_lf_c1_20_13_pos 0
#define	cfoe_lf_c1_20_13_len 8
#define	cfoe_lf_c1_20_13_lsb 13
#define xd_p_cfoe_lf_c1_25_21	0xA209
#define	cfoe_lf_c1_25_21_pos 0
#define	cfoe_lf_c1_25_21_len 5
#define	cfoe_lf_c1_25_21_lsb 21
#define xd_p_cfoe_lf_c2_2_0	0xA209
#define	cfoe_lf_c2_2_0_pos 5
#define	cfoe_lf_c2_2_0_len 3
#define	cfoe_lf_c2_2_0_lsb 0
#define xd_p_cfoe_lf_c2_10_3	0xA20A
#define	cfoe_lf_c2_10_3_pos 0
#define	cfoe_lf_c2_10_3_len 8
#define	cfoe_lf_c2_10_3_lsb 3
#define xd_p_cfoe_lf_c2_18_11	0xA20B
#define	cfoe_lf_c2_18_11_pos 0
#define	cfoe_lf_c2_18_11_len 8
#define	cfoe_lf_c2_18_11_lsb 11
#define xd_p_cfoe_lf_c2_25_19	0xA20C
#define	cfoe_lf_c2_25_19_pos 0
#define	cfoe_lf_c2_25_19_len 7
#define	cfoe_lf_c2_25_19_lsb 19
#define xd_p_cfoe_ifod_7_0	0xA20D
#define	cfoe_ifod_7_0_pos 0
#define	cfoe_ifod_7_0_len 8
#define	cfoe_ifod_7_0_lsb 0
#define xd_p_cfoe_ifod_10_8	0xA20E
#define	cfoe_ifod_10_8_pos 0
#define	cfoe_ifod_10_8_len 3
#define	cfoe_ifod_10_8_lsb 8
#define xd_p_cfoe_Divg_ctr_th	0xA20E
#define	cfoe_Divg_ctr_th_pos 4
#define	cfoe_Divg_ctr_th_len 4
#define	cfoe_Divg_ctr_th_lsb 0
#define xd_p_cfoe_FOT_divg_th	0xA20F
#define	cfoe_FOT_divg_th_pos 0
#define	cfoe_FOT_divg_th_len 8
#define	cfoe_FOT_divg_th_lsb 0
#define xd_p_cfoe_FOT_cnvg_th	0xA210
#define	cfoe_FOT_cnvg_th_pos 0
#define	cfoe_FOT_cnvg_th_len 8
#define	cfoe_FOT_cnvg_th_lsb 0
#define xd_p_reg_cfoe_offset_7_0	0xA211
#define	reg_cfoe_offset_7_0_pos 0
#define	reg_cfoe_offset_7_0_len 8
#define	reg_cfoe_offset_7_0_lsb 0
#define xd_p_reg_cfoe_offset_9_8	0xA212
#define	reg_cfoe_off…