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/drivers/media/dvb/dvb-usb/af9005.h

https://bitbucket.org/abioy/linux
C Header | 3496 lines | 3429 code | 37 blank | 30 comment | 0 complexity | cef962f98f5af4cceb8a01d2fd22e738 MD5 | raw file
Possible License(s): CC-BY-SA-3.0, GPL-2.0, LGPL-2.0, AGPL-1.0

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   1/* Common header-file of the Linux driver for the Afatech 9005
   2 * USB1.1 DVB-T receiver.
   3 *
   4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
   5 *
   6 * Thanks to Afatech who kindly provided information.
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 *
  22 * see Documentation/dvb/README.dvb-usb for more information
  23 */
  24#ifndef _DVB_USB_AF9005_H_
  25#define _DVB_USB_AF9005_H_
  26
  27#define DVB_USB_LOG_PREFIX "af9005"
  28#include "dvb-usb.h"
  29
  30extern int dvb_usb_af9005_debug;
  31#define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
  32#define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
  33#define deb_rc(args...)   dprintk(dvb_usb_af9005_debug,0x04,args)
  34#define deb_reg(args...)  dprintk(dvb_usb_af9005_debug,0x08,args)
  35#define deb_i2c(args...)  dprintk(dvb_usb_af9005_debug,0x10,args)
  36#define deb_fw(args...)   dprintk(dvb_usb_af9005_debug,0x20,args)
  37
  38extern int dvb_usb_af9005_led;
  39
  40/* firmware */
  41#define FW_BULKOUT_SIZE 250
  42enum {
  43	FW_CONFIG,
  44	FW_CONFIRM,
  45	FW_BOOT
  46};
  47
  48/* af9005 commands */
  49#define AF9005_OFDM_REG  0
  50#define AF9005_TUNER_REG 1
  51
  52#define AF9005_REGISTER_RW     0x20
  53#define AF9005_REGISTER_RW_ACK 0x21
  54
  55#define AF9005_CMD_OFDM_REG 0x00
  56#define AF9005_CMD_TUNER    0x80
  57#define AF9005_CMD_BURST    0x02
  58#define AF9005_CMD_AUTOINC  0x04
  59#define AF9005_CMD_READ     0x00
  60#define AF9005_CMD_WRITE    0x01
  61
  62/* af9005 registers */
  63#define APO_REG_RESET					0xAEFF
  64
  65#define APO_REG_I2C_RW_CAN_TUNER            0xF000
  66#define APO_REG_I2C_RW_SILICON_TUNER        0xF001
  67#define APO_REG_GPIO_RW_SILICON_TUNER       0xFFFE	/*  also for OFSM */
  68#define APO_REG_TRIGGER_OFSM                0xFFFF	/*  also for OFSM */
  69
  70/***********************************************************************
  71 *  Apollo Registers from VLSI					       *
  72 ***********************************************************************/
  73#define xd_p_reg_aagc_inverted_agc	0xA000
  74#define	reg_aagc_inverted_agc_pos 0
  75#define	reg_aagc_inverted_agc_len 1
  76#define	reg_aagc_inverted_agc_lsb 0
  77#define xd_p_reg_aagc_sign_only	0xA000
  78#define	reg_aagc_sign_only_pos 1
  79#define	reg_aagc_sign_only_len 1
  80#define	reg_aagc_sign_only_lsb 0
  81#define xd_p_reg_aagc_slow_adc_en	0xA000
  82#define	reg_aagc_slow_adc_en_pos 2
  83#define	reg_aagc_slow_adc_en_len 1
  84#define	reg_aagc_slow_adc_en_lsb 0
  85#define xd_p_reg_aagc_slow_adc_scale	0xA000
  86#define	reg_aagc_slow_adc_scale_pos 3
  87#define	reg_aagc_slow_adc_scale_len 5
  88#define	reg_aagc_slow_adc_scale_lsb 0
  89#define xd_p_reg_aagc_check_slow_adc_lock	0xA001
  90#define	reg_aagc_check_slow_adc_lock_pos 0
  91#define	reg_aagc_check_slow_adc_lock_len 1
  92#define	reg_aagc_check_slow_adc_lock_lsb 0
  93#define xd_p_reg_aagc_init_control	0xA001
  94#define	reg_aagc_init_control_pos 1
  95#define	reg_aagc_init_control_len 1
  96#define	reg_aagc_init_control_lsb 0
  97#define xd_p_reg_aagc_total_gain_sel	0xA001
  98#define	reg_aagc_total_gain_sel_pos 2
  99#define	reg_aagc_total_gain_sel_len 2
 100#define	reg_aagc_total_gain_sel_lsb 0
 101#define xd_p_reg_aagc_out_inv	0xA001
 102#define	reg_aagc_out_inv_pos 5
 103#define	reg_aagc_out_inv_len 1
 104#define	reg_aagc_out_inv_lsb 0
 105#define xd_p_reg_aagc_int_en	0xA001
 106#define	reg_aagc_int_en_pos 6
 107#define	reg_aagc_int_en_len 1
 108#define	reg_aagc_int_en_lsb 0
 109#define xd_p_reg_aagc_lock_change_flag	0xA001
 110#define	reg_aagc_lock_change_flag_pos 7
 111#define	reg_aagc_lock_change_flag_len 1
 112#define	reg_aagc_lock_change_flag_lsb 0
 113#define xd_p_reg_aagc_rf_loop_bw_scale_acquire	0xA002
 114#define	reg_aagc_rf_loop_bw_scale_acquire_pos 0
 115#define	reg_aagc_rf_loop_bw_scale_acquire_len 5
 116#define	reg_aagc_rf_loop_bw_scale_acquire_lsb 0
 117#define xd_p_reg_aagc_rf_loop_bw_scale_track	0xA003
 118#define	reg_aagc_rf_loop_bw_scale_track_pos 0
 119#define	reg_aagc_rf_loop_bw_scale_track_len 5
 120#define	reg_aagc_rf_loop_bw_scale_track_lsb 0
 121#define xd_p_reg_aagc_if_loop_bw_scale_acquire	0xA004
 122#define	reg_aagc_if_loop_bw_scale_acquire_pos 0
 123#define	reg_aagc_if_loop_bw_scale_acquire_len 5
 124#define	reg_aagc_if_loop_bw_scale_acquire_lsb 0
 125#define xd_p_reg_aagc_if_loop_bw_scale_track	0xA005
 126#define	reg_aagc_if_loop_bw_scale_track_pos 0
 127#define	reg_aagc_if_loop_bw_scale_track_len 5
 128#define	reg_aagc_if_loop_bw_scale_track_lsb 0
 129#define xd_p_reg_aagc_max_rf_agc_7_0	0xA006
 130#define	reg_aagc_max_rf_agc_7_0_pos 0
 131#define	reg_aagc_max_rf_agc_7_0_len 8
 132#define	reg_aagc_max_rf_agc_7_0_lsb 0
 133#define xd_p_reg_aagc_max_rf_agc_9_8	0xA007
 134#define	reg_aagc_max_rf_agc_9_8_pos 0
 135#define	reg_aagc_max_rf_agc_9_8_len 2
 136#define	reg_aagc_max_rf_agc_9_8_lsb 8
 137#define xd_p_reg_aagc_min_rf_agc_7_0	0xA008
 138#define	reg_aagc_min_rf_agc_7_0_pos 0
 139#define	reg_aagc_min_rf_agc_7_0_len 8
 140#define	reg_aagc_min_rf_agc_7_0_lsb 0
 141#define xd_p_reg_aagc_min_rf_agc_9_8	0xA009
 142#define	reg_aagc_min_rf_agc_9_8_pos 0
 143#define	reg_aagc_min_rf_agc_9_8_len 2
 144#define	reg_aagc_min_rf_agc_9_8_lsb 8
 145#define xd_p_reg_aagc_max_if_agc_7_0	0xA00A
 146#define	reg_aagc_max_if_agc_7_0_pos 0
 147#define	reg_aagc_max_if_agc_7_0_len 8
 148#define	reg_aagc_max_if_agc_7_0_lsb 0
 149#define xd_p_reg_aagc_max_if_agc_9_8	0xA00B
 150#define	reg_aagc_max_if_agc_9_8_pos 0
 151#define	reg_aagc_max_if_agc_9_8_len 2
 152#define	reg_aagc_max_if_agc_9_8_lsb 8
 153#define xd_p_reg_aagc_min_if_agc_7_0	0xA00C
 154#define	reg_aagc_min_if_agc_7_0_pos 0
 155#define	reg_aagc_min_if_agc_7_0_len 8
 156#define	reg_aagc_min_if_agc_7_0_lsb 0
 157#define xd_p_reg_aagc_min_if_agc_9_8	0xA00D
 158#define	reg_aagc_min_if_agc_9_8_pos 0
 159#define	reg_aagc_min_if_agc_9_8_len 2
 160#define	reg_aagc_min_if_agc_9_8_lsb 8
 161#define xd_p_reg_aagc_lock_sample_scale	0xA00E
 162#define	reg_aagc_lock_sample_scale_pos 0
 163#define	reg_aagc_lock_sample_scale_len 5
 164#define	reg_aagc_lock_sample_scale_lsb 0
 165#define xd_p_reg_aagc_rf_agc_lock_scale_acquire	0xA00F
 166#define	reg_aagc_rf_agc_lock_scale_acquire_pos 0
 167#define	reg_aagc_rf_agc_lock_scale_acquire_len 3
 168#define	reg_aagc_rf_agc_lock_scale_acquire_lsb 0
 169#define xd_p_reg_aagc_rf_agc_lock_scale_track	0xA00F
 170#define	reg_aagc_rf_agc_lock_scale_track_pos 3
 171#define	reg_aagc_rf_agc_lock_scale_track_len 3
 172#define	reg_aagc_rf_agc_lock_scale_track_lsb 0
 173#define xd_p_reg_aagc_if_agc_lock_scale_acquire	0xA010
 174#define	reg_aagc_if_agc_lock_scale_acquire_pos 0
 175#define	reg_aagc_if_agc_lock_scale_acquire_len 3
 176#define	reg_aagc_if_agc_lock_scale_acquire_lsb 0
 177#define xd_p_reg_aagc_if_agc_lock_scale_track	0xA010
 178#define	reg_aagc_if_agc_lock_scale_track_pos 3
 179#define	reg_aagc_if_agc_lock_scale_track_len 3
 180#define	reg_aagc_if_agc_lock_scale_track_lsb 0
 181#define xd_p_reg_aagc_rf_top_numerator_7_0	0xA011
 182#define	reg_aagc_rf_top_numerator_7_0_pos 0
 183#define	reg_aagc_rf_top_numerator_7_0_len 8
 184#define	reg_aagc_rf_top_numerator_7_0_lsb 0
 185#define xd_p_reg_aagc_rf_top_numerator_9_8	0xA012
 186#define	reg_aagc_rf_top_numerator_9_8_pos 0
 187#define	reg_aagc_rf_top_numerator_9_8_len 2
 188#define	reg_aagc_rf_top_numerator_9_8_lsb 8
 189#define xd_p_reg_aagc_if_top_numerator_7_0	0xA013
 190#define	reg_aagc_if_top_numerator_7_0_pos 0
 191#define	reg_aagc_if_top_numerator_7_0_len 8
 192#define	reg_aagc_if_top_numerator_7_0_lsb 0
 193#define xd_p_reg_aagc_if_top_numerator_9_8	0xA014
 194#define	reg_aagc_if_top_numerator_9_8_pos 0
 195#define	reg_aagc_if_top_numerator_9_8_len 2
 196#define	reg_aagc_if_top_numerator_9_8_lsb 8
 197#define xd_p_reg_aagc_adc_out_desired_7_0	0xA015
 198#define	reg_aagc_adc_out_desired_7_0_pos 0
 199#define	reg_aagc_adc_out_desired_7_0_len 8
 200#define	reg_aagc_adc_out_desired_7_0_lsb 0
 201#define xd_p_reg_aagc_adc_out_desired_8	0xA016
 202#define	reg_aagc_adc_out_desired_8_pos 0
 203#define	reg_aagc_adc_out_desired_8_len 1
 204#define	reg_aagc_adc_out_desired_8_lsb 0
 205#define xd_p_reg_aagc_fixed_gain	0xA016
 206#define	reg_aagc_fixed_gain_pos 3
 207#define	reg_aagc_fixed_gain_len 1
 208#define	reg_aagc_fixed_gain_lsb 0
 209#define xd_p_reg_aagc_lock_count_th	0xA016
 210#define	reg_aagc_lock_count_th_pos 4
 211#define	reg_aagc_lock_count_th_len 4
 212#define	reg_aagc_lock_count_th_lsb 0
 213#define xd_p_reg_aagc_fixed_rf_agc_control_7_0	0xA017
 214#define	reg_aagc_fixed_rf_agc_control_7_0_pos 0
 215#define	reg_aagc_fixed_rf_agc_control_7_0_len 8
 216#define	reg_aagc_fixed_rf_agc_control_7_0_lsb 0
 217#define xd_p_reg_aagc_fixed_rf_agc_control_15_8	0xA018
 218#define	reg_aagc_fixed_rf_agc_control_15_8_pos 0
 219#define	reg_aagc_fixed_rf_agc_control_15_8_len 8
 220#define	reg_aagc_fixed_rf_agc_control_15_8_lsb 8
 221#define xd_p_reg_aagc_fixed_rf_agc_control_23_16	0xA019
 222#define	reg_aagc_fixed_rf_agc_control_23_16_pos 0
 223#define	reg_aagc_fixed_rf_agc_control_23_16_len 8
 224#define	reg_aagc_fixed_rf_agc_control_23_16_lsb 16
 225#define xd_p_reg_aagc_fixed_rf_agc_control_30_24	0xA01A
 226#define	reg_aagc_fixed_rf_agc_control_30_24_pos 0
 227#define	reg_aagc_fixed_rf_agc_control_30_24_len 7
 228#define	reg_aagc_fixed_rf_agc_control_30_24_lsb 24
 229#define xd_p_reg_aagc_fixed_if_agc_control_7_0	0xA01B
 230#define	reg_aagc_fixed_if_agc_control_7_0_pos 0
 231#define	reg_aagc_fixed_if_agc_control_7_0_len 8
 232#define	reg_aagc_fixed_if_agc_control_7_0_lsb 0
 233#define xd_p_reg_aagc_fixed_if_agc_control_15_8	0xA01C
 234#define	reg_aagc_fixed_if_agc_control_15_8_pos 0
 235#define	reg_aagc_fixed_if_agc_control_15_8_len 8
 236#define	reg_aagc_fixed_if_agc_control_15_8_lsb 8
 237#define xd_p_reg_aagc_fixed_if_agc_control_23_16	0xA01D
 238#define	reg_aagc_fixed_if_agc_control_23_16_pos 0
 239#define	reg_aagc_fixed_if_agc_control_23_16_len 8
 240#define	reg_aagc_fixed_if_agc_control_23_16_lsb 16
 241#define xd_p_reg_aagc_fixed_if_agc_control_30_24	0xA01E
 242#define	reg_aagc_fixed_if_agc_control_30_24_pos 0
 243#define	reg_aagc_fixed_if_agc_control_30_24_len 7
 244#define	reg_aagc_fixed_if_agc_control_30_24_lsb 24
 245#define xd_p_reg_aagc_rf_agc_unlock_numerator	0xA01F
 246#define	reg_aagc_rf_agc_unlock_numerator_pos 0
 247#define	reg_aagc_rf_agc_unlock_numerator_len 6
 248#define	reg_aagc_rf_agc_unlock_numerator_lsb 0
 249#define xd_p_reg_aagc_if_agc_unlock_numerator	0xA020
 250#define	reg_aagc_if_agc_unlock_numerator_pos 0
 251#define	reg_aagc_if_agc_unlock_numerator_len 6
 252#define	reg_aagc_if_agc_unlock_numerator_lsb 0
 253#define xd_p_reg_unplug_th	0xA021
 254#define	reg_unplug_th_pos 0
 255#define	reg_unplug_th_len 8
 256#define	reg_aagc_rf_x0_lsb 0
 257#define xd_p_reg_weak_signal_rfagc_thr 0xA022
 258#define	reg_weak_signal_rfagc_thr_pos 0
 259#define	reg_weak_signal_rfagc_thr_len 8
 260#define	reg_weak_signal_rfagc_thr_lsb 0
 261#define xd_p_reg_unplug_rf_gain_th 0xA023
 262#define	reg_unplug_rf_gain_th_pos 0
 263#define	reg_unplug_rf_gain_th_len 8
 264#define	reg_unplug_rf_gain_th_lsb 0
 265#define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
 266#define	reg_unplug_dtop_rf_gain_th_pos 0
 267#define	reg_unplug_dtop_rf_gain_th_len 8
 268#define	reg_unplug_dtop_rf_gain_th_lsb 0
 269#define xd_p_reg_unplug_dtop_if_gain_th 0xA025
 270#define	reg_unplug_dtop_if_gain_th_pos 0
 271#define	reg_unplug_dtop_if_gain_th_len 8
 272#define	reg_unplug_dtop_if_gain_th_lsb 0
 273#define xd_p_reg_top_recover_at_unplug_en 0xA026
 274#define	reg_top_recover_at_unplug_en_pos 0
 275#define	reg_top_recover_at_unplug_en_len 1
 276#define	reg_top_recover_at_unplug_en_lsb 0
 277#define xd_p_reg_aagc_rf_x6	0xA027
 278#define	reg_aagc_rf_x6_pos 0
 279#define	reg_aagc_rf_x6_len 8
 280#define	reg_aagc_rf_x6_lsb 0
 281#define xd_p_reg_aagc_rf_x7	0xA028
 282#define	reg_aagc_rf_x7_pos 0
 283#define	reg_aagc_rf_x7_len 8
 284#define	reg_aagc_rf_x7_lsb 0
 285#define xd_p_reg_aagc_rf_x8	0xA029
 286#define	reg_aagc_rf_x8_pos 0
 287#define	reg_aagc_rf_x8_len 8
 288#define	reg_aagc_rf_x8_lsb 0
 289#define xd_p_reg_aagc_rf_x9	0xA02A
 290#define	reg_aagc_rf_x9_pos 0
 291#define	reg_aagc_rf_x9_len 8
 292#define	reg_aagc_rf_x9_lsb 0
 293#define xd_p_reg_aagc_rf_x10	0xA02B
 294#define	reg_aagc_rf_x10_pos 0
 295#define	reg_aagc_rf_x10_len 8
 296#define	reg_aagc_rf_x10_lsb 0
 297#define xd_p_reg_aagc_rf_x11	0xA02C
 298#define	reg_aagc_rf_x11_pos 0
 299#define	reg_aagc_rf_x11_len 8
 300#define	reg_aagc_rf_x11_lsb 0
 301#define xd_p_reg_aagc_rf_x12	0xA02D
 302#define	reg_aagc_rf_x12_pos 0
 303#define	reg_aagc_rf_x12_len 8
 304#define	reg_aagc_rf_x12_lsb 0
 305#define xd_p_reg_aagc_rf_x13	0xA02E
 306#define	reg_aagc_rf_x13_pos 0
 307#define	reg_aagc_rf_x13_len 8
 308#define	reg_aagc_rf_x13_lsb 0
 309#define xd_p_reg_aagc_if_x0	0xA02F
 310#define	reg_aagc_if_x0_pos 0
 311#define	reg_aagc_if_x0_len 8
 312#define	reg_aagc_if_x0_lsb 0
 313#define xd_p_reg_aagc_if_x1	0xA030
 314#define	reg_aagc_if_x1_pos 0
 315#define	reg_aagc_if_x1_len 8
 316#define	reg_aagc_if_x1_lsb 0
 317#define xd_p_reg_aagc_if_x2	0xA031
 318#define	reg_aagc_if_x2_pos 0
 319#define	reg_aagc_if_x2_len 8
 320#define	reg_aagc_if_x2_lsb 0
 321#define xd_p_reg_aagc_if_x3	0xA032
 322#define	reg_aagc_if_x3_pos 0
 323#define	reg_aagc_if_x3_len 8
 324#define	reg_aagc_if_x3_lsb 0
 325#define xd_p_reg_aagc_if_x4	0xA033
 326#define	reg_aagc_if_x4_pos 0
 327#define	reg_aagc_if_x4_len 8
 328#define	reg_aagc_if_x4_lsb 0
 329#define xd_p_reg_aagc_if_x5	0xA034
 330#define	reg_aagc_if_x5_pos 0
 331#define	reg_aagc_if_x5_len 8
 332#define	reg_aagc_if_x5_lsb 0
 333#define xd_p_reg_aagc_if_x6	0xA035
 334#define	reg_aagc_if_x6_pos 0
 335#define	reg_aagc_if_x6_len 8
 336#define	reg_aagc_if_x6_lsb 0
 337#define xd_p_reg_aagc_if_x7	0xA036
 338#define	reg_aagc_if_x7_pos 0
 339#define	reg_aagc_if_x7_len 8
 340#define	reg_aagc_if_x7_lsb 0
 341#define xd_p_reg_aagc_if_x8	0xA037
 342#define	reg_aagc_if_x8_pos 0
 343#define	reg_aagc_if_x8_len 8
 344#define	reg_aagc_if_x8_lsb 0
 345#define xd_p_reg_aagc_if_x9	0xA038
 346#define	reg_aagc_if_x9_pos 0
 347#define	reg_aagc_if_x9_len 8
 348#define	reg_aagc_if_x9_lsb 0
 349#define xd_p_reg_aagc_if_x10	0xA039
 350#define	reg_aagc_if_x10_pos 0
 351#define	reg_aagc_if_x10_len 8
 352#define	reg_aagc_if_x10_lsb 0
 353#define xd_p_reg_aagc_if_x11	0xA03A
 354#define	reg_aagc_if_x11_pos 0
 355#define	reg_aagc_if_x11_len 8
 356#define	reg_aagc_if_x11_lsb 0
 357#define xd_p_reg_aagc_if_x12	0xA03B
 358#define	reg_aagc_if_x12_pos 0
 359#define	reg_aagc_if_x12_len 8
 360#define	reg_aagc_if_x12_lsb 0
 361#define xd_p_reg_aagc_if_x13	0xA03C
 362#define	reg_aagc_if_x13_pos 0
 363#define	reg_aagc_if_x13_len 8
 364#define	reg_aagc_if_x13_lsb 0
 365#define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca	0xA03D
 366#define	reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
 367#define	reg_aagc_min_rf_ctl_8bit_for_dca_len 8
 368#define	reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
 369#define xd_p_reg_aagc_min_if_ctl_8bit_for_dca	0xA03E
 370#define	reg_aagc_min_if_ctl_8bit_for_dca_pos 0
 371#define	reg_aagc_min_if_ctl_8bit_for_dca_len 8
 372#define	reg_aagc_min_if_ctl_8bit_for_dca_lsb 0
 373#define xd_r_reg_aagc_total_gain_7_0	0xA070
 374#define	reg_aagc_total_gain_7_0_pos 0
 375#define	reg_aagc_total_gain_7_0_len 8
 376#define	reg_aagc_total_gain_7_0_lsb 0
 377#define xd_r_reg_aagc_total_gain_15_8	0xA071
 378#define	reg_aagc_total_gain_15_8_pos 0
 379#define	reg_aagc_total_gain_15_8_len 8
 380#define	reg_aagc_total_gain_15_8_lsb 8
 381#define xd_p_reg_aagc_in_sat_cnt_7_0	0xA074
 382#define	reg_aagc_in_sat_cnt_7_0_pos 0
 383#define	reg_aagc_in_sat_cnt_7_0_len 8
 384#define	reg_aagc_in_sat_cnt_7_0_lsb 0
 385#define xd_p_reg_aagc_in_sat_cnt_15_8	0xA075
 386#define	reg_aagc_in_sat_cnt_15_8_pos 0
 387#define	reg_aagc_in_sat_cnt_15_8_len 8
 388#define	reg_aagc_in_sat_cnt_15_8_lsb 8
 389#define xd_p_reg_aagc_in_sat_cnt_23_16	0xA076
 390#define	reg_aagc_in_sat_cnt_23_16_pos 0
 391#define	reg_aagc_in_sat_cnt_23_16_len 8
 392#define	reg_aagc_in_sat_cnt_23_16_lsb 16
 393#define xd_p_reg_aagc_in_sat_cnt_31_24	0xA077
 394#define	reg_aagc_in_sat_cnt_31_24_pos 0
 395#define	reg_aagc_in_sat_cnt_31_24_len 8
 396#define	reg_aagc_in_sat_cnt_31_24_lsb 24
 397#define xd_r_reg_aagc_digital_rf_volt_7_0	0xA078
 398#define	reg_aagc_digital_rf_volt_7_0_pos 0
 399#define	reg_aagc_digital_rf_volt_7_0_len 8
 400#define	reg_aagc_digital_rf_volt_7_0_lsb 0
 401#define xd_r_reg_aagc_digital_rf_volt_9_8	0xA079
 402#define	reg_aagc_digital_rf_volt_9_8_pos 0
 403#define	reg_aagc_digital_rf_volt_9_8_len 2
 404#define	reg_aagc_digital_rf_volt_9_8_lsb 8
 405#define xd_r_reg_aagc_digital_if_volt_7_0	0xA07A
 406#define	reg_aagc_digital_if_volt_7_0_pos 0
 407#define	reg_aagc_digital_if_volt_7_0_len 8
 408#define	reg_aagc_digital_if_volt_7_0_lsb 0
 409#define xd_r_reg_aagc_digital_if_volt_9_8	0xA07B
 410#define	reg_aagc_digital_if_volt_9_8_pos 0
 411#define	reg_aagc_digital_if_volt_9_8_len 2
 412#define	reg_aagc_digital_if_volt_9_8_lsb 8
 413#define xd_r_reg_aagc_rf_gain	0xA07C
 414#define	reg_aagc_rf_gain_pos 0
 415#define	reg_aagc_rf_gain_len 8
 416#define	reg_aagc_rf_gain_lsb 0
 417#define xd_r_reg_aagc_if_gain	0xA07D
 418#define	reg_aagc_if_gain_pos 0
 419#define	reg_aagc_if_gain_len 8
 420#define	reg_aagc_if_gain_lsb 0
 421#define xd_p_tinr_imp_indicator	0xA080
 422#define	tinr_imp_indicator_pos 0
 423#define	tinr_imp_indicator_len 2
 424#define	tinr_imp_indicator_lsb 0
 425#define xd_p_reg_tinr_fifo_size	0xA080
 426#define	reg_tinr_fifo_size_pos 2
 427#define	reg_tinr_fifo_size_len 5
 428#define	reg_tinr_fifo_size_lsb 0
 429#define xd_p_reg_tinr_saturation_cnt_th	0xA081
 430#define	reg_tinr_saturation_cnt_th_pos 0
 431#define	reg_tinr_saturation_cnt_th_len 4
 432#define	reg_tinr_saturation_cnt_th_lsb 0
 433#define xd_p_reg_tinr_saturation_th_3_0	0xA081
 434#define	reg_tinr_saturation_th_3_0_pos 4
 435#define	reg_tinr_saturation_th_3_0_len 4
 436#define	reg_tinr_saturation_th_3_0_lsb 0
 437#define xd_p_reg_tinr_saturation_th_8_4	0xA082
 438#define	reg_tinr_saturation_th_8_4_pos 0
 439#define	reg_tinr_saturation_th_8_4_len 5
 440#define	reg_tinr_saturation_th_8_4_lsb 4
 441#define xd_p_reg_tinr_imp_duration_th_2k_7_0	0xA083
 442#define	reg_tinr_imp_duration_th_2k_7_0_pos 0
 443#define	reg_tinr_imp_duration_th_2k_7_0_len 8
 444#define	reg_tinr_imp_duration_th_2k_7_0_lsb 0
 445#define xd_p_reg_tinr_imp_duration_th_2k_8	0xA084
 446#define	reg_tinr_imp_duration_th_2k_8_pos 0
 447#define	reg_tinr_imp_duration_th_2k_8_len 1
 448#define	reg_tinr_imp_duration_th_2k_8_lsb 0
 449#define xd_p_reg_tinr_imp_duration_th_8k_7_0	0xA085
 450#define	reg_tinr_imp_duration_th_8k_7_0_pos 0
 451#define	reg_tinr_imp_duration_th_8k_7_0_len 8
 452#define	reg_tinr_imp_duration_th_8k_7_0_lsb 0
 453#define xd_p_reg_tinr_imp_duration_th_8k_10_8	0xA086
 454#define	reg_tinr_imp_duration_th_8k_10_8_pos 0
 455#define	reg_tinr_imp_duration_th_8k_10_8_len 3
 456#define	reg_tinr_imp_duration_th_8k_10_8_lsb 8
 457#define xd_p_reg_tinr_freq_ratio_6m_7_0	0xA087
 458#define	reg_tinr_freq_ratio_6m_7_0_pos 0
 459#define	reg_tinr_freq_ratio_6m_7_0_len 8
 460#define	reg_tinr_freq_ratio_6m_7_0_lsb 0
 461#define xd_p_reg_tinr_freq_ratio_6m_12_8	0xA088
 462#define	reg_tinr_freq_ratio_6m_12_8_pos 0
 463#define	reg_tinr_freq_ratio_6m_12_8_len 5
 464#define	reg_tinr_freq_ratio_6m_12_8_lsb 8
 465#define xd_p_reg_tinr_freq_ratio_7m_7_0	0xA089
 466#define	reg_tinr_freq_ratio_7m_7_0_pos 0
 467#define	reg_tinr_freq_ratio_7m_7_0_len 8
 468#define	reg_tinr_freq_ratio_7m_7_0_lsb 0
 469#define xd_p_reg_tinr_freq_ratio_7m_12_8	0xA08A
 470#define	reg_tinr_freq_ratio_7m_12_8_pos 0
 471#define	reg_tinr_freq_ratio_7m_12_8_len 5
 472#define	reg_tinr_freq_ratio_7m_12_8_lsb 8
 473#define xd_p_reg_tinr_freq_ratio_8m_7_0	0xA08B
 474#define	reg_tinr_freq_ratio_8m_7_0_pos 0
 475#define	reg_tinr_freq_ratio_8m_7_0_len 8
 476#define	reg_tinr_freq_ratio_8m_7_0_lsb 0
 477#define xd_p_reg_tinr_freq_ratio_8m_12_8	0xA08C
 478#define	reg_tinr_freq_ratio_8m_12_8_pos 0
 479#define	reg_tinr_freq_ratio_8m_12_8_len 5
 480#define	reg_tinr_freq_ratio_8m_12_8_lsb 8
 481#define xd_p_reg_tinr_imp_duration_th_low_2k	0xA08D
 482#define	reg_tinr_imp_duration_th_low_2k_pos 0
 483#define	reg_tinr_imp_duration_th_low_2k_len 8
 484#define	reg_tinr_imp_duration_th_low_2k_lsb 0
 485#define xd_p_reg_tinr_imp_duration_th_low_8k	0xA08E
 486#define	reg_tinr_imp_duration_th_low_8k_pos 0
 487#define	reg_tinr_imp_duration_th_low_8k_len 8
 488#define	reg_tinr_imp_duration_th_low_8k_lsb 0
 489#define xd_r_reg_tinr_counter_7_0	0xA090
 490#define	reg_tinr_counter_7_0_pos 0
 491#define	reg_tinr_counter_7_0_len 8
 492#define	reg_tinr_counter_7_0_lsb 0
 493#define xd_r_reg_tinr_counter_15_8	0xA091
 494#define	reg_tinr_counter_15_8_pos 0
 495#define	reg_tinr_counter_15_8_len 8
 496#define	reg_tinr_counter_15_8_lsb 8
 497#define xd_p_reg_tinr_adative_tinr_en	0xA093
 498#define	reg_tinr_adative_tinr_en_pos 0
 499#define	reg_tinr_adative_tinr_en_len 1
 500#define	reg_tinr_adative_tinr_en_lsb 0
 501#define xd_p_reg_tinr_peak_fifo_size	0xA093
 502#define	reg_tinr_peak_fifo_size_pos 1
 503#define	reg_tinr_peak_fifo_size_len 5
 504#define	reg_tinr_peak_fifo_size_lsb 0
 505#define xd_p_reg_tinr_counter_rst	0xA093
 506#define	reg_tinr_counter_rst_pos 6
 507#define	reg_tinr_counter_rst_len 1
 508#define	reg_tinr_counter_rst_lsb 0
 509#define xd_p_reg_tinr_search_period_7_0	0xA094
 510#define	reg_tinr_search_period_7_0_pos 0
 511#define	reg_tinr_search_period_7_0_len 8
 512#define	reg_tinr_search_period_7_0_lsb 0
 513#define xd_p_reg_tinr_search_period_15_8	0xA095
 514#define	reg_tinr_search_period_15_8_pos 0
 515#define	reg_tinr_search_period_15_8_len 8
 516#define	reg_tinr_search_period_15_8_lsb 8
 517#define xd_p_reg_ccifs_fcw_7_0	0xA0A0
 518#define	reg_ccifs_fcw_7_0_pos 0
 519#define	reg_ccifs_fcw_7_0_len 8
 520#define	reg_ccifs_fcw_7_0_lsb 0
 521#define xd_p_reg_ccifs_fcw_12_8	0xA0A1
 522#define	reg_ccifs_fcw_12_8_pos 0
 523#define	reg_ccifs_fcw_12_8_len 5
 524#define	reg_ccifs_fcw_12_8_lsb 8
 525#define xd_p_reg_ccifs_spec_inv	0xA0A1
 526#define	reg_ccifs_spec_inv_pos 5
 527#define	reg_ccifs_spec_inv_len 1
 528#define	reg_ccifs_spec_inv_lsb 0
 529#define xd_p_reg_gp_trigger	0xA0A2
 530#define	reg_gp_trigger_pos 0
 531#define	reg_gp_trigger_len 1
 532#define	reg_gp_trigger_lsb 0
 533#define xd_p_reg_trigger_sel	0xA0A2
 534#define	reg_trigger_sel_pos 1
 535#define	reg_trigger_sel_len 2
 536#define	reg_trigger_sel_lsb 0
 537#define xd_p_reg_debug_ofdm	0xA0A2
 538#define	reg_debug_ofdm_pos 3
 539#define	reg_debug_ofdm_len 2
 540#define	reg_debug_ofdm_lsb 0
 541#define xd_p_reg_trigger_module_sel	0xA0A3
 542#define	reg_trigger_module_sel_pos 0
 543#define	reg_trigger_module_sel_len 6
 544#define	reg_trigger_module_sel_lsb 0
 545#define xd_p_reg_trigger_set_sel	0xA0A4
 546#define	reg_trigger_set_sel_pos 0
 547#define	reg_trigger_set_sel_len 6
 548#define	reg_trigger_set_sel_lsb 0
 549#define xd_p_reg_fw_int_mask_n	0xA0A4
 550#define	reg_fw_int_mask_n_pos 6
 551#define	reg_fw_int_mask_n_len 1
 552#define	reg_fw_int_mask_n_lsb 0
 553#define xd_p_reg_debug_group	0xA0A5
 554#define	reg_debug_group_pos 0
 555#define	reg_debug_group_len 4
 556#define	reg_debug_group_lsb 0
 557#define xd_p_reg_odbg_clk_sel	0xA0A5
 558#define	reg_odbg_clk_sel_pos 4
 559#define	reg_odbg_clk_sel_len 2
 560#define	reg_odbg_clk_sel_lsb 0
 561#define xd_p_reg_ccif_sc	0xA0C0
 562#define	reg_ccif_sc_pos 0
 563#define	reg_ccif_sc_len 4
 564#define	reg_ccif_sc_lsb 0
 565#define xd_r_reg_ccif_saturate	0xA0C1
 566#define	reg_ccif_saturate_pos 0
 567#define	reg_ccif_saturate_len 2
 568#define	reg_ccif_saturate_lsb 0
 569#define xd_r_reg_antif_saturate	0xA0C1
 570#define	reg_antif_saturate_pos 2
 571#define	reg_antif_saturate_len 4
 572#define	reg_antif_saturate_lsb 0
 573#define xd_r_reg_acif_saturate	0xA0C2
 574#define	reg_acif_saturate_pos 0
 575#define	reg_acif_saturate_len 8
 576#define	reg_acif_saturate_lsb 0
 577#define xd_p_reg_tmr_timer0_threshold_7_0	0xA0C8
 578#define	reg_tmr_timer0_threshold_7_0_pos 0
 579#define	reg_tmr_timer0_threshold_7_0_len 8
 580#define	reg_tmr_timer0_threshold_7_0_lsb 0
 581#define xd_p_reg_tmr_timer0_threshold_15_8	0xA0C9
 582#define	reg_tmr_timer0_threshold_15_8_pos 0
 583#define	reg_tmr_timer0_threshold_15_8_len 8
 584#define	reg_tmr_timer0_threshold_15_8_lsb 8
 585#define xd_p_reg_tmr_timer0_enable	0xA0CA
 586#define	reg_tmr_timer0_enable_pos 0
 587#define	reg_tmr_timer0_enable_len 1
 588#define	reg_tmr_timer0_enable_lsb 0
 589#define xd_p_reg_tmr_timer0_clk_sel	0xA0CA
 590#define	reg_tmr_timer0_clk_sel_pos 1
 591#define	reg_tmr_timer0_clk_sel_len 1
 592#define	reg_tmr_timer0_clk_sel_lsb 0
 593#define xd_p_reg_tmr_timer0_int	0xA0CA
 594#define	reg_tmr_timer0_int_pos 2
 595#define	reg_tmr_timer0_int_len 1
 596#define	reg_tmr_timer0_int_lsb 0
 597#define xd_p_reg_tmr_timer0_rst	0xA0CA
 598#define	reg_tmr_timer0_rst_pos 3
 599#define	reg_tmr_timer0_rst_len 1
 600#define	reg_tmr_timer0_rst_lsb 0
 601#define xd_r_reg_tmr_timer0_count_7_0	0xA0CB
 602#define	reg_tmr_timer0_count_7_0_pos 0
 603#define	reg_tmr_timer0_count_7_0_len 8
 604#define	reg_tmr_timer0_count_7_0_lsb 0
 605#define xd_r_reg_tmr_timer0_count_15_8	0xA0CC
 606#define	reg_tmr_timer0_count_15_8_pos 0
 607#define	reg_tmr_timer0_count_15_8_len 8
 608#define	reg_tmr_timer0_count_15_8_lsb 8
 609#define xd_p_reg_suspend	0xA0CD
 610#define	reg_suspend_pos 0
 611#define	reg_suspend_len 1
 612#define	reg_suspend_lsb 0
 613#define xd_p_reg_suspend_rdy	0xA0CD
 614#define	reg_suspend_rdy_pos 1
 615#define	reg_suspend_rdy_len 1
 616#define	reg_suspend_rdy_lsb 0
 617#define xd_p_reg_resume	0xA0CD
 618#define	reg_resume_pos 2
 619#define	reg_resume_len 1
 620#define	reg_resume_lsb 0
 621#define xd_p_reg_resume_rdy	0xA0CD
 622#define	reg_resume_rdy_pos 3
 623#define	reg_resume_rdy_len 1
 624#define	reg_resume_rdy_lsb 0
 625#define xd_p_reg_fmf	0xA0CE
 626#define	reg_fmf_pos 0
 627#define	reg_fmf_len 8
 628#define	reg_fmf_lsb 0
 629#define xd_p_ccid_accumulate_num_2k_7_0	0xA100
 630#define	ccid_accumulate_num_2k_7_0_pos 0
 631#define	ccid_accumulate_num_2k_7_0_len 8
 632#define	ccid_accumulate_num_2k_7_0_lsb 0
 633#define xd_p_ccid_accumulate_num_2k_12_8	0xA101
 634#define	ccid_accumulate_num_2k_12_8_pos 0
 635#define	ccid_accumulate_num_2k_12_8_len 5
 636#define	ccid_accumulate_num_2k_12_8_lsb 8
 637#define xd_p_ccid_accumulate_num_8k_7_0	0xA102
 638#define	ccid_accumulate_num_8k_7_0_pos 0
 639#define	ccid_accumulate_num_8k_7_0_len 8
 640#define	ccid_accumulate_num_8k_7_0_lsb 0
 641#define xd_p_ccid_accumulate_num_8k_14_8	0xA103
 642#define	ccid_accumulate_num_8k_14_8_pos 0
 643#define	ccid_accumulate_num_8k_14_8_len 7
 644#define	ccid_accumulate_num_8k_14_8_lsb 8
 645#define xd_p_ccid_desired_level_0	0xA103
 646#define	ccid_desired_level_0_pos 7
 647#define	ccid_desired_level_0_len 1
 648#define	ccid_desired_level_0_lsb 0
 649#define xd_p_ccid_desired_level_8_1	0xA104
 650#define	ccid_desired_level_8_1_pos 0
 651#define	ccid_desired_level_8_1_len 8
 652#define	ccid_desired_level_8_1_lsb 1
 653#define xd_p_ccid_apply_delay	0xA105
 654#define	ccid_apply_delay_pos 0
 655#define	ccid_apply_delay_len 7
 656#define	ccid_apply_delay_lsb 0
 657#define xd_p_ccid_CCID_Threshold1	0xA106
 658#define	ccid_CCID_Threshold1_pos 0
 659#define	ccid_CCID_Threshold1_len 8
 660#define	ccid_CCID_Threshold1_lsb 0
 661#define xd_p_ccid_CCID_Threshold2	0xA107
 662#define	ccid_CCID_Threshold2_pos 0
 663#define	ccid_CCID_Threshold2_len 8
 664#define	ccid_CCID_Threshold2_lsb 0
 665#define xd_p_reg_ccid_gain_scale	0xA108
 666#define	reg_ccid_gain_scale_pos 0
 667#define	reg_ccid_gain_scale_len 4
 668#define	reg_ccid_gain_scale_lsb 0
 669#define xd_p_reg_ccid2_passband_gain_set	0xA108
 670#define	reg_ccid2_passband_gain_set_pos 4
 671#define	reg_ccid2_passband_gain_set_len 4
 672#define	reg_ccid2_passband_gain_set_lsb 0
 673#define xd_r_ccid_multiplier_7_0	0xA109
 674#define	ccid_multiplier_7_0_pos 0
 675#define	ccid_multiplier_7_0_len 8
 676#define	ccid_multiplier_7_0_lsb 0
 677#define xd_r_ccid_multiplier_15_8	0xA10A
 678#define	ccid_multiplier_15_8_pos 0
 679#define	ccid_multiplier_15_8_len 8
 680#define	ccid_multiplier_15_8_lsb 8
 681#define xd_r_ccid_right_shift_bits	0xA10B
 682#define	ccid_right_shift_bits_pos 0
 683#define	ccid_right_shift_bits_len 4
 684#define	ccid_right_shift_bits_lsb 0
 685#define xd_r_reg_ccid_sx_7_0	0xA10C
 686#define	reg_ccid_sx_7_0_pos 0
 687#define	reg_ccid_sx_7_0_len 8
 688#define	reg_ccid_sx_7_0_lsb 0
 689#define xd_r_reg_ccid_sx_15_8	0xA10D
 690#define	reg_ccid_sx_15_8_pos 0
 691#define	reg_ccid_sx_15_8_len 8
 692#define	reg_ccid_sx_15_8_lsb 8
 693#define xd_r_reg_ccid_sx_21_16	0xA10E
 694#define	reg_ccid_sx_21_16_pos 0
 695#define	reg_ccid_sx_21_16_len 6
 696#define	reg_ccid_sx_21_16_lsb 16
 697#define xd_r_reg_ccid_sy_7_0	0xA110
 698#define	reg_ccid_sy_7_0_pos 0
 699#define	reg_ccid_sy_7_0_len 8
 700#define	reg_ccid_sy_7_0_lsb 0
 701#define xd_r_reg_ccid_sy_15_8	0xA111
 702#define	reg_ccid_sy_15_8_pos 0
 703#define	reg_ccid_sy_15_8_len 8
 704#define	reg_ccid_sy_15_8_lsb 8
 705#define xd_r_reg_ccid_sy_23_16	0xA112
 706#define	reg_ccid_sy_23_16_pos 0
 707#define	reg_ccid_sy_23_16_len 8
 708#define	reg_ccid_sy_23_16_lsb 16
 709#define xd_r_reg_ccid2_sz_7_0	0xA114
 710#define	reg_ccid2_sz_7_0_pos 0
 711#define	reg_ccid2_sz_7_0_len 8
 712#define	reg_ccid2_sz_7_0_lsb 0
 713#define xd_r_reg_ccid2_sz_15_8	0xA115
 714#define	reg_ccid2_sz_15_8_pos 0
 715#define	reg_ccid2_sz_15_8_len 8
 716#define	reg_ccid2_sz_15_8_lsb 8
 717#define xd_r_reg_ccid2_sz_23_16	0xA116
 718#define	reg_ccid2_sz_23_16_pos 0
 719#define	reg_ccid2_sz_23_16_len 8
 720#define	reg_ccid2_sz_23_16_lsb 16
 721#define xd_r_reg_ccid2_sz_25_24	0xA117
 722#define	reg_ccid2_sz_25_24_pos 0
 723#define	reg_ccid2_sz_25_24_len 2
 724#define	reg_ccid2_sz_25_24_lsb 24
 725#define xd_r_reg_ccid2_sy_7_0	0xA118
 726#define	reg_ccid2_sy_7_0_pos 0
 727#define	reg_ccid2_sy_7_0_len 8
 728#define	reg_ccid2_sy_7_0_lsb 0
 729#define xd_r_reg_ccid2_sy_15_8	0xA119
 730#define	reg_ccid2_sy_15_8_pos 0
 731#define	reg_ccid2_sy_15_8_len 8
 732#define	reg_ccid2_sy_15_8_lsb 8
 733#define xd_r_reg_ccid2_sy_23_16	0xA11A
 734#define	reg_ccid2_sy_23_16_pos 0
 735#define	reg_ccid2_sy_23_16_len 8
 736#define	reg_ccid2_sy_23_16_lsb 16
 737#define xd_r_reg_ccid2_sy_25_24	0xA11B
 738#define	reg_ccid2_sy_25_24_pos 0
 739#define	reg_ccid2_sy_25_24_len 2
 740#define	reg_ccid2_sy_25_24_lsb 24
 741#define xd_p_dagc1_accumulate_num_2k_7_0	0xA120
 742#define	dagc1_accumulate_num_2k_7_0_pos 0
 743#define	dagc1_accumulate_num_2k_7_0_len 8
 744#define	dagc1_accumulate_num_2k_7_0_lsb 0
 745#define xd_p_dagc1_accumulate_num_2k_12_8	0xA121
 746#define	dagc1_accumulate_num_2k_12_8_pos 0
 747#define	dagc1_accumulate_num_2k_12_8_len 5
 748#define	dagc1_accumulate_num_2k_12_8_lsb 8
 749#define xd_p_dagc1_accumulate_num_8k_7_0	0xA122
 750#define	dagc1_accumulate_num_8k_7_0_pos 0
 751#define	dagc1_accumulate_num_8k_7_0_len 8
 752#define	dagc1_accumulate_num_8k_7_0_lsb 0
 753#define xd_p_dagc1_accumulate_num_8k_14_8	0xA123
 754#define	dagc1_accumulate_num_8k_14_8_pos 0
 755#define	dagc1_accumulate_num_8k_14_8_len 7
 756#define	dagc1_accumulate_num_8k_14_8_lsb 8
 757#define xd_p_dagc1_desired_level_0	0xA123
 758#define	dagc1_desired_level_0_pos 7
 759#define	dagc1_desired_level_0_len 1
 760#define	dagc1_desired_level_0_lsb 0
 761#define xd_p_dagc1_desired_level_8_1	0xA124
 762#define	dagc1_desired_level_8_1_pos 0
 763#define	dagc1_desired_level_8_1_len 8
 764#define	dagc1_desired_level_8_1_lsb 1
 765#define xd_p_dagc1_apply_delay	0xA125
 766#define	dagc1_apply_delay_pos 0
 767#define	dagc1_apply_delay_len 7
 768#define	dagc1_apply_delay_lsb 0
 769#define xd_p_dagc1_bypass_scale_ctl	0xA126
 770#define	dagc1_bypass_scale_ctl_pos 0
 771#define	dagc1_bypass_scale_ctl_len 2
 772#define	dagc1_bypass_scale_ctl_lsb 0
 773#define xd_p_reg_dagc1_in_sat_cnt_7_0	0xA127
 774#define	reg_dagc1_in_sat_cnt_7_0_pos 0
 775#define	reg_dagc1_in_sat_cnt_7_0_len 8
 776#define	reg_dagc1_in_sat_cnt_7_0_lsb 0
 777#define xd_p_reg_dagc1_in_sat_cnt_15_8	0xA128
 778#define	reg_dagc1_in_sat_cnt_15_8_pos 0
 779#define	reg_dagc1_in_sat_cnt_15_8_len 8
 780#define	reg_dagc1_in_sat_cnt_15_8_lsb 8
 781#define xd_p_reg_dagc1_in_sat_cnt_23_16	0xA129
 782#define	reg_dagc1_in_sat_cnt_23_16_pos 0
 783#define	reg_dagc1_in_sat_cnt_23_16_len 8
 784#define	reg_dagc1_in_sat_cnt_23_16_lsb 16
 785#define xd_p_reg_dagc1_in_sat_cnt_31_24	0xA12A
 786#define	reg_dagc1_in_sat_cnt_31_24_pos 0
 787#define	reg_dagc1_in_sat_cnt_31_24_len 8
 788#define	reg_dagc1_in_sat_cnt_31_24_lsb 24
 789#define xd_p_reg_dagc1_out_sat_cnt_7_0	0xA12B
 790#define	reg_dagc1_out_sat_cnt_7_0_pos 0
 791#define	reg_dagc1_out_sat_cnt_7_0_len 8
 792#define	reg_dagc1_out_sat_cnt_7_0_lsb 0
 793#define xd_p_reg_dagc1_out_sat_cnt_15_8	0xA12C
 794#define	reg_dagc1_out_sat_cnt_15_8_pos 0
 795#define	reg_dagc1_out_sat_cnt_15_8_len 8
 796#define	reg_dagc1_out_sat_cnt_15_8_lsb 8
 797#define xd_p_reg_dagc1_out_sat_cnt_23_16	0xA12D
 798#define	reg_dagc1_out_sat_cnt_23_16_pos 0
 799#define	reg_dagc1_out_sat_cnt_23_16_len 8
 800#define	reg_dagc1_out_sat_cnt_23_16_lsb 16
 801#define xd_p_reg_dagc1_out_sat_cnt_31_24	0xA12E
 802#define	reg_dagc1_out_sat_cnt_31_24_pos 0
 803#define	reg_dagc1_out_sat_cnt_31_24_len 8
 804#define	reg_dagc1_out_sat_cnt_31_24_lsb 24
 805#define xd_r_dagc1_multiplier_7_0	0xA136
 806#define	dagc1_multiplier_7_0_pos 0
 807#define	dagc1_multiplier_7_0_len 8
 808#define	dagc1_multiplier_7_0_lsb 0
 809#define xd_r_dagc1_multiplier_15_8	0xA137
 810#define	dagc1_multiplier_15_8_pos 0
 811#define	dagc1_multiplier_15_8_len 8
 812#define	dagc1_multiplier_15_8_lsb 8
 813#define xd_r_dagc1_right_shift_bits	0xA138
 814#define	dagc1_right_shift_bits_pos 0
 815#define	dagc1_right_shift_bits_len 4
 816#define	dagc1_right_shift_bits_lsb 0
 817#define xd_p_reg_bfs_fcw_7_0	0xA140
 818#define	reg_bfs_fcw_7_0_pos 0
 819#define	reg_bfs_fcw_7_0_len 8
 820#define	reg_bfs_fcw_7_0_lsb 0
 821#define xd_p_reg_bfs_fcw_15_8	0xA141
 822#define	reg_bfs_fcw_15_8_pos 0
 823#define	reg_bfs_fcw_15_8_len 8
 824#define	reg_bfs_fcw_15_8_lsb 8
 825#define xd_p_reg_bfs_fcw_22_16	0xA142
 826#define	reg_bfs_fcw_22_16_pos 0
 827#define	reg_bfs_fcw_22_16_len 7
 828#define	reg_bfs_fcw_22_16_lsb 16
 829#define xd_p_reg_antif_sf_7_0	0xA144
 830#define	reg_antif_sf_7_0_pos 0
 831#define	reg_antif_sf_7_0_len 8
 832#define	reg_antif_sf_7_0_lsb 0
 833#define xd_p_reg_antif_sf_11_8	0xA145
 834#define	reg_antif_sf_11_8_pos 0
 835#define	reg_antif_sf_11_8_len 4
 836#define	reg_antif_sf_11_8_lsb 8
 837#define xd_r_bfs_fcw_q_7_0	0xA150
 838#define	bfs_fcw_q_7_0_pos 0
 839#define	bfs_fcw_q_7_0_len 8
 840#define	bfs_fcw_q_7_0_lsb 0
 841#define xd_r_bfs_fcw_q_15_8	0xA151
 842#define	bfs_fcw_q_15_8_pos 0
 843#define	bfs_fcw_q_15_8_len 8
 844#define	bfs_fcw_q_15_8_lsb 8
 845#define xd_r_bfs_fcw_q_22_16	0xA152
 846#define	bfs_fcw_q_22_16_pos 0
 847#define	bfs_fcw_q_22_16_len 7
 848#define	bfs_fcw_q_22_16_lsb 16
 849#define xd_p_reg_dca_enu	0xA160
 850#define	reg_dca_enu_pos 0
 851#define	reg_dca_enu_len 1
 852#define	reg_dca_enu_lsb 0
 853#define xd_p_reg_dca_enl	0xA160
 854#define	reg_dca_enl_pos 1
 855#define	reg_dca_enl_len 1
 856#define	reg_dca_enl_lsb 0
 857#define xd_p_reg_dca_lower_chip	0xA160
 858#define	reg_dca_lower_chip_pos 2
 859#define	reg_dca_lower_chip_len 1
 860#define	reg_dca_lower_chip_lsb 0
 861#define xd_p_reg_dca_upper_chip	0xA160
 862#define	reg_dca_upper_chip_pos 3
 863#define	reg_dca_upper_chip_len 1
 864#define	reg_dca_upper_chip_lsb 0
 865#define xd_p_reg_dca_platch	0xA160
 866#define	reg_dca_platch_pos 4
 867#define	reg_dca_platch_len 1
 868#define	reg_dca_platch_lsb 0
 869#define xd_p_reg_dca_th	0xA161
 870#define	reg_dca_th_pos 0
 871#define	reg_dca_th_len 5
 872#define	reg_dca_th_lsb 0
 873#define xd_p_reg_dca_scale	0xA162
 874#define	reg_dca_scale_pos 0
 875#define	reg_dca_scale_len 4
 876#define	reg_dca_scale_lsb 0
 877#define xd_p_reg_dca_tone_7_0	0xA163
 878#define	reg_dca_tone_7_0_pos 0
 879#define	reg_dca_tone_7_0_len 8
 880#define	reg_dca_tone_7_0_lsb 0
 881#define xd_p_reg_dca_tone_12_8	0xA164
 882#define	reg_dca_tone_12_8_pos 0
 883#define	reg_dca_tone_12_8_len 5
 884#define	reg_dca_tone_12_8_lsb 8
 885#define xd_p_reg_dca_time_7_0	0xA165
 886#define	reg_dca_time_7_0_pos 0
 887#define	reg_dca_time_7_0_len 8
 888#define	reg_dca_time_7_0_lsb 0
 889#define xd_p_reg_dca_time_15_8	0xA166
 890#define	reg_dca_time_15_8_pos 0
 891#define	reg_dca_time_15_8_len 8
 892#define	reg_dca_time_15_8_lsb 8
 893#define xd_r_dcasm	0xA167
 894#define	dcasm_pos 0
 895#define	dcasm_len 3
 896#define	dcasm_lsb 0
 897#define xd_p_reg_qnt_valuew_7_0	0xA168
 898#define	reg_qnt_valuew_7_0_pos 0
 899#define	reg_qnt_valuew_7_0_len 8
 900#define	reg_qnt_valuew_7_0_lsb 0
 901#define xd_p_reg_qnt_valuew_10_8	0xA169
 902#define	reg_qnt_valuew_10_8_pos 0
 903#define	reg_qnt_valuew_10_8_len 3
 904#define	reg_qnt_valuew_10_8_lsb 8
 905#define xd_p_dca_sbx_gain_diff_7_0	0xA16A
 906#define	dca_sbx_gain_diff_7_0_pos 0
 907#define	dca_sbx_gain_diff_7_0_len 8
 908#define	dca_sbx_gain_diff_7_0_lsb 0
 909#define xd_p_dca_sbx_gain_diff_9_8	0xA16B
 910#define	dca_sbx_gain_diff_9_8_pos 0
 911#define	dca_sbx_gain_diff_9_8_len 2
 912#define	dca_sbx_gain_diff_9_8_lsb 8
 913#define xd_p_reg_dca_stand_alone	0xA16C
 914#define	reg_dca_stand_alone_pos 0
 915#define	reg_dca_stand_alone_len 1
 916#define	reg_dca_stand_alone_lsb 0
 917#define xd_p_reg_dca_upper_out_en	0xA16C
 918#define	reg_dca_upper_out_en_pos 1
 919#define	reg_dca_upper_out_en_len 1
 920#define	reg_dca_upper_out_en_lsb 0
 921#define xd_p_reg_dca_rc_en	0xA16C
 922#define	reg_dca_rc_en_pos 2
 923#define	reg_dca_rc_en_len 1
 924#define	reg_dca_rc_en_lsb 0
 925#define xd_p_reg_dca_retrain_send	0xA16C
 926#define	reg_dca_retrain_send_pos 3
 927#define	reg_dca_retrain_send_len 1
 928#define	reg_dca_retrain_send_lsb 0
 929#define xd_p_reg_dca_retrain_rec	0xA16C
 930#define	reg_dca_retrain_rec_pos 4
 931#define	reg_dca_retrain_rec_len 1
 932#define	reg_dca_retrain_rec_lsb 0
 933#define xd_p_reg_dca_api_tpsrdy	0xA16C
 934#define	reg_dca_api_tpsrdy_pos 5
 935#define	reg_dca_api_tpsrdy_len 1
 936#define	reg_dca_api_tpsrdy_lsb 0
 937#define xd_p_reg_dca_symbol_gap	0xA16D
 938#define	reg_dca_symbol_gap_pos 0
 939#define	reg_dca_symbol_gap_len 4
 940#define	reg_dca_symbol_gap_lsb 0
 941#define xd_p_reg_qnt_nfvaluew_7_0	0xA16E
 942#define	reg_qnt_nfvaluew_7_0_pos 0
 943#define	reg_qnt_nfvaluew_7_0_len 8
 944#define	reg_qnt_nfvaluew_7_0_lsb 0
 945#define xd_p_reg_qnt_nfvaluew_10_8	0xA16F
 946#define	reg_qnt_nfvaluew_10_8_pos 0
 947#define	reg_qnt_nfvaluew_10_8_len 3
 948#define	reg_qnt_nfvaluew_10_8_lsb 8
 949#define xd_p_reg_qnt_flatness_thr_7_0	0xA170
 950#define	reg_qnt_flatness_thr_7_0_pos 0
 951#define	reg_qnt_flatness_thr_7_0_len 8
 952#define	reg_qnt_flatness_thr_7_0_lsb 0
 953#define xd_p_reg_qnt_flatness_thr_9_8	0xA171
 954#define	reg_qnt_flatness_thr_9_8_pos 0
 955#define	reg_qnt_flatness_thr_9_8_len 2
 956#define	reg_qnt_flatness_thr_9_8_lsb 8
 957#define xd_p_reg_dca_tone_idx_5_0	0xA171
 958#define	reg_dca_tone_idx_5_0_pos 2
 959#define	reg_dca_tone_idx_5_0_len 6
 960#define	reg_dca_tone_idx_5_0_lsb 0
 961#define xd_p_reg_dca_tone_idx_12_6	0xA172
 962#define	reg_dca_tone_idx_12_6_pos 0
 963#define	reg_dca_tone_idx_12_6_len 7
 964#define	reg_dca_tone_idx_12_6_lsb 6
 965#define xd_p_reg_dca_data_vld	0xA173
 966#define	reg_dca_data_vld_pos 0
 967#define	reg_dca_data_vld_len 1
 968#define	reg_dca_data_vld_lsb 0
 969#define xd_p_reg_dca_read_update	0xA173
 970#define	reg_dca_read_update_pos 1
 971#define	reg_dca_read_update_len 1
 972#define	reg_dca_read_update_lsb 0
 973#define xd_r_reg_dca_data_re_5_0	0xA173
 974#define	reg_dca_data_re_5_0_pos 2
 975#define	reg_dca_data_re_5_0_len 6
 976#define	reg_dca_data_re_5_0_lsb 0
 977#define xd_r_reg_dca_data_re_10_6	0xA174
 978#define	reg_dca_data_re_10_6_pos 0
 979#define	reg_dca_data_re_10_6_len 5
 980#define	reg_dca_data_re_10_6_lsb 6
 981#define xd_r_reg_dca_data_im_7_0	0xA175
 982#define	reg_dca_data_im_7_0_pos 0
 983#define	reg_dca_data_im_7_0_len 8
 984#define	reg_dca_data_im_7_0_lsb 0
 985#define xd_r_reg_dca_data_im_10_8	0xA176
 986#define	reg_dca_data_im_10_8_pos 0
 987#define	reg_dca_data_im_10_8_len 3
 988#define	reg_dca_data_im_10_8_lsb 8
 989#define xd_r_reg_dca_data_h2_7_0	0xA178
 990#define	reg_dca_data_h2_7_0_pos 0
 991#define	reg_dca_data_h2_7_0_len 8
 992#define	reg_dca_data_h2_7_0_lsb 0
 993#define xd_r_reg_dca_data_h2_9_8	0xA179
 994#define	reg_dca_data_h2_9_8_pos 0
 995#define	reg_dca_data_h2_9_8_len 2
 996#define	reg_dca_data_h2_9_8_lsb 8
 997#define xd_p_reg_f_adc_7_0	0xA180
 998#define	reg_f_adc_7_0_pos 0
 999#define	reg_f_adc_7_0_len 8
1000#define	reg_f_adc_7_0_lsb 0
1001#define xd_p_reg_f_adc_15_8	0xA181
1002#define	reg_f_adc_15_8_pos 0
1003#define	reg_f_adc_15_8_len 8
1004#define	reg_f_adc_15_8_lsb 8
1005#define xd_p_reg_f_adc_23_16	0xA182
1006#define	reg_f_adc_23_16_pos 0
1007#define	reg_f_adc_23_16_len 8
1008#define	reg_f_adc_23_16_lsb 16
1009#define xd_r_intp_mu_7_0	0xA190
1010#define	intp_mu_7_0_pos 0
1011#define	intp_mu_7_0_len 8
1012#define	intp_mu_7_0_lsb 0
1013#define xd_r_intp_mu_15_8	0xA191
1014#define	intp_mu_15_8_pos 0
1015#define	intp_mu_15_8_len 8
1016#define	intp_mu_15_8_lsb 8
1017#define xd_r_intp_mu_19_16	0xA192
1018#define	intp_mu_19_16_pos 0
1019#define	intp_mu_19_16_len 4
1020#define	intp_mu_19_16_lsb 16
1021#define xd_p_reg_agc_rst	0xA1A0
1022#define	reg_agc_rst_pos 0
1023#define	reg_agc_rst_len 1
1024#define	reg_agc_rst_lsb 0
1025#define xd_p_rf_agc_en	0xA1A0
1026#define	rf_agc_en_pos 1
1027#define	rf_agc_en_len 1
1028#define	rf_agc_en_lsb 0
1029#define xd_p_rf_agc_dis	0xA1A0
1030#define	rf_agc_dis_pos 2
1031#define	rf_agc_dis_len 1
1032#define	rf_agc_dis_lsb 0
1033#define xd_p_if_agc_rst	0xA1A0
1034#define	if_agc_rst_pos 3
1035#define	if_agc_rst_len 1
1036#define	if_agc_rst_lsb 0
1037#define xd_p_if_agc_en	0xA1A0
1038#define	if_agc_en_pos 4
1039#define	if_agc_en_len 1
1040#define	if_agc_en_lsb 0
1041#define xd_p_if_agc_dis	0xA1A0
1042#define	if_agc_dis_pos 5
1043#define	if_agc_dis_len 1
1044#define	if_agc_dis_lsb 0
1045#define xd_p_agc_lock	0xA1A0
1046#define	agc_lock_pos 6
1047#define	agc_lock_len 1
1048#define	agc_lock_lsb 0
1049#define xd_p_reg_tinr_rst	0xA1A1
1050#define	reg_tinr_rst_pos 0
1051#define	reg_tinr_rst_len 1
1052#define	reg_tinr_rst_lsb 0
1053#define xd_p_reg_tinr_en	0xA1A1
1054#define	reg_tinr_en_pos 1
1055#define	reg_tinr_en_len 1
1056#define	reg_tinr_en_lsb 0
1057#define xd_p_reg_ccifs_en	0xA1A2
1058#define	reg_ccifs_en_pos 0
1059#define	reg_ccifs_en_len 1
1060#define	reg_ccifs_en_lsb 0
1061#define xd_p_reg_ccifs_dis	0xA1A2
1062#define	reg_ccifs_dis_pos 1
1063#define	reg_ccifs_dis_len 1
1064#define	reg_ccifs_dis_lsb 0
1065#define xd_p_reg_ccifs_rst	0xA1A2
1066#define	reg_ccifs_rst_pos 2
1067#define	reg_ccifs_rst_len 1
1068#define	reg_ccifs_rst_lsb 0
1069#define xd_p_reg_ccifs_byp	0xA1A2
1070#define	reg_ccifs_byp_pos 3
1071#define	reg_ccifs_byp_len 1
1072#define	reg_ccifs_byp_lsb 0
1073#define xd_p_reg_ccif_en	0xA1A3
1074#define	reg_ccif_en_pos 0
1075#define	reg_ccif_en_len 1
1076#define	reg_ccif_en_lsb 0
1077#define xd_p_reg_ccif_dis	0xA1A3
1078#define	reg_ccif_dis_pos 1
1079#define	reg_ccif_dis_len 1
1080#define	reg_ccif_dis_lsb 0
1081#define xd_p_reg_ccif_rst	0xA1A3
1082#define	reg_ccif_rst_pos 2
1083#define	reg_ccif_rst_len 1
1084#define	reg_ccif_rst_lsb 0
1085#define xd_p_reg_ccif_byp	0xA1A3
1086#define	reg_ccif_byp_pos 3
1087#define	reg_ccif_byp_len 1
1088#define	reg_ccif_byp_lsb 0
1089#define xd_p_dagc1_rst	0xA1A4
1090#define	dagc1_rst_pos 0
1091#define	dagc1_rst_len 1
1092#define	dagc1_rst_lsb 0
1093#define xd_p_dagc1_en	0xA1A4
1094#define	dagc1_en_pos 1
1095#define	dagc1_en_len 1
1096#define	dagc1_en_lsb 0
1097#define xd_p_dagc1_mode	0xA1A4
1098#define	dagc1_mode_pos 2
1099#define	dagc1_mode_len 2
1100#define	dagc1_mode_lsb 0
1101#define xd_p_dagc1_done	0xA1A4
1102#define	dagc1_done_pos 4
1103#define	dagc1_done_len 1
1104#define	dagc1_done_lsb 0
1105#define xd_p_ccid_rst	0xA1A5
1106#define	ccid_rst_pos 0
1107#define	ccid_rst_len 1
1108#define	ccid_rst_lsb 0
1109#define xd_p_ccid_en	0xA1A5
1110#define	ccid_en_pos 1
1111#define	ccid_en_len 1
1112#define	ccid_en_lsb 0
1113#define xd_p_ccid_mode	0xA1A5
1114#define	ccid_mode_pos 2
1115#define	ccid_mode_len 2
1116#define	ccid_mode_lsb 0
1117#define xd_p_ccid_done	0xA1A5
1118#define	ccid_done_pos 4
1119#define	ccid_done_len 1
1120#define	ccid_done_lsb 0
1121#define xd_r_ccid_deted	0xA1A5
1122#define	ccid_deted_pos 5
1123#define	ccid_deted_len 1
1124#define	ccid_deted_lsb 0
1125#define xd_p_ccid2_en	0xA1A5
1126#define	ccid2_en_pos 6
1127#define	ccid2_en_len 1
1128#define	ccid2_en_lsb 0
1129#define xd_p_ccid2_done	0xA1A5
1130#define	ccid2_done_pos 7
1131#define	ccid2_done_len 1
1132#define	ccid2_done_lsb 0
1133#define xd_p_reg_bfs_en	0xA1A6
1134#define	reg_bfs_en_pos 0
1135#define	reg_bfs_en_len 1
1136#define	reg_bfs_en_lsb 0
1137#define xd_p_reg_bfs_dis	0xA1A6
1138#define	reg_bfs_dis_pos 1
1139#define	reg_bfs_dis_len 1
1140#define	reg_bfs_dis_lsb 0
1141#define xd_p_reg_bfs_rst	0xA1A6
1142#define	reg_bfs_rst_pos 2
1143#define	reg_bfs_rst_len 1
1144#define	reg_bfs_rst_lsb 0
1145#define xd_p_reg_bfs_byp	0xA1A6
1146#define	reg_bfs_byp_pos 3
1147#define	reg_bfs_byp_len 1
1148#define	reg_bfs_byp_lsb 0
1149#define xd_p_reg_antif_en	0xA1A7
1150#define	reg_antif_en_pos 0
1151#define	reg_antif_en_len 1
1152#define	reg_antif_en_lsb 0
1153#define xd_p_reg_antif_dis	0xA1A7
1154#define	reg_antif_dis_pos 1
1155#define	reg_antif_dis_len 1
1156#define	reg_antif_dis_lsb 0
1157#define xd_p_reg_antif_rst	0xA1A7
1158#define	reg_antif_rst_pos 2
1159#define	reg_antif_rst_len 1
1160#define	reg_antif_rst_lsb 0
1161#define xd_p_reg_antif_byp	0xA1A7
1162#define	reg_antif_byp_pos 3
1163#define	reg_antif_byp_len 1
1164#define	reg_antif_byp_lsb 0
1165#define xd_p_intp_en	0xA1A8
1166#define	intp_en_pos 0
1167#define	intp_en_len 1
1168#define	intp_en_lsb 0
1169#define xd_p_intp_dis	0xA1A8
1170#define	intp_dis_pos 1
1171#define	intp_dis_len 1
1172#define	intp_dis_lsb 0
1173#define xd_p_intp_rst	0xA1A8
1174#define	intp_rst_pos 2
1175#define	intp_rst_len 1
1176#define	intp_rst_lsb 0
1177#define xd_p_intp_byp	0xA1A8
1178#define	intp_byp_pos 3
1179#define	intp_byp_len 1
1180#define	intp_byp_lsb 0
1181#define xd_p_reg_acif_en	0xA1A9
1182#define	reg_acif_en_pos 0
1183#define	reg_acif_en_len 1
1184#define	reg_acif_en_lsb 0
1185#define xd_p_reg_acif_dis	0xA1A9
1186#define	reg_acif_dis_pos 1
1187#define	reg_acif_dis_len 1
1188#define	reg_acif_dis_lsb 0
1189#define xd_p_reg_acif_rst	0xA1A9
1190#define	reg_acif_rst_pos 2
1191#define	reg_acif_rst_len 1
1192#define	reg_acif_rst_lsb 0
1193#define xd_p_reg_acif_byp	0xA1A9
1194#define	reg_acif_byp_pos 3
1195#define	reg_acif_byp_len 1
1196#define	reg_acif_byp_lsb 0
1197#define xd_p_reg_acif_sync_mode	0xA1A9
1198#define	reg_acif_sync_mode_pos 4
1199#define	reg_acif_sync_mode_len 1
1200#define	reg_acif_sync_mode_lsb 0
1201#define xd_p_dagc2_rst	0xA1AA
1202#define	dagc2_rst_pos 0
1203#define	dagc2_rst_len 1
1204#define	dagc2_rst_lsb 0
1205#define xd_p_dagc2_en	0xA1AA
1206#define	dagc2_en_pos 1
1207#define	dagc2_en_len 1
1208#define	dagc2_en_lsb 0
1209#define xd_p_dagc2_mode	0xA1AA
1210#define	dagc2_mode_pos 2
1211#define	dagc2_mode_len 2
1212#define	dagc2_mode_lsb 0
1213#define xd_p_dagc2_done	0xA1AA
1214#define	dagc2_done_pos 4
1215#define	dagc2_done_len 1
1216#define	dagc2_done_lsb 0
1217#define xd_p_reg_dca_en	0xA1AB
1218#define	reg_dca_en_pos 0
1219#define	reg_dca_en_len 1
1220#define	reg_dca_en_lsb 0
1221#define xd_p_dagc2_accumulate_num_2k_7_0	0xA1C0
1222#define	dagc2_accumulate_num_2k_7_0_pos 0
1223#define	dagc2_accumulate_num_2k_7_0_len 8
1224#define	dagc2_accumulate_num_2k_7_0_lsb 0
1225#define xd_p_dagc2_accumulate_num_2k_12_8	0xA1C1
1226#define	dagc2_accumulate_num_2k_12_8_pos 0
1227#define	dagc2_accumulate_num_2k_12_8_len 5
1228#define	dagc2_accumulate_num_2k_12_8_lsb 8
1229#define xd_p_dagc2_accumulate_num_8k_7_0	0xA1C2
1230#define	dagc2_accumulate_num_8k_7_0_pos 0
1231#define	dagc2_accumulate_num_8k_7_0_len 8
1232#define	dagc2_accumulate_num_8k_7_0_lsb 0
1233#define xd_p_dagc2_accumulate_num_8k_12_8	0xA1C3
1234#define	dagc2_accumulate_num_8k_12_8_pos 0
1235#define	dagc2_accumulate_num_8k_12_8_len 5
1236#define	dagc2_accumulate_num_8k_12_8_lsb 8
1237#define xd_p_dagc2_desired_level_2_0	0xA1C3
1238#define	dagc2_desired_level_2_0_pos 5
1239#define	dagc2_desired_level_2_0_len 3
1240#define	dagc2_desired_level_2_0_lsb 0
1241#define xd_p_dagc2_desired_level_8_3	0xA1C4
1242#define	dagc2_desired_level_8_3_pos 0
1243#define	dagc2_desired_level_8_3_len 6
1244#define	dagc2_desired_level_8_3_lsb 3
1245#define xd_p_dagc2_apply_delay	0xA1C5
1246#define	dagc2_apply_delay_pos 0
1247#define	dagc2_apply_delay_len 7
1248#define	dagc2_apply_delay_lsb 0
1249#define xd_p_dagc2_bypass_scale_ctl	0xA1C6
1250#define	dagc2_bypass_scale_ctl_pos 0
1251#define	dagc2_bypass_scale_ctl_len 3
1252#define	dagc2_bypass_scale_ctl_lsb 0
1253#define xd_p_dagc2_programmable_shift1	0xA1C7
1254#define	dagc2_programmable_shift1_pos 0
1255#define	dagc2_programmable_shift1_len 8
1256#define	dagc2_programmable_shift1_lsb 0
1257#define xd_p_dagc2_programmable_shift2	0xA1C8
1258#define	dagc2_programmable_shift2_pos 0
1259#define	dagc2_programmable_shift2_len 8
1260#define	dagc2_programmable_shift2_lsb 0
1261#define xd_p_reg_dagc2_in_sat_cnt_7_0	0xA1C9
1262#define	reg_dagc2_in_sat_cnt_7_0_pos 0
1263#define	reg_dagc2_in_sat_cnt_7_0_len 8
1264#define	reg_dagc2_in_sat_cnt_7_0_lsb 0
1265#define xd_p_reg_dagc2_in_sat_cnt_15_8	0xA1CA
1266#define	reg_dagc2_in_sat_cnt_15_8_pos 0
1267#define	reg_dagc2_in_sat_cnt_15_8_len 8
1268#define	reg_dagc2_in_sat_cnt_15_8_lsb 8
1269#define xd_p_reg_dagc2_in_sat_cnt_23_16	0xA1CB
1270#define	reg_dagc2_in_sat_cnt_23_16_pos 0
1271#define	reg_dagc2_in_sat_cnt_23_16_len 8
1272#define	reg_dagc2_in_sat_cnt_23_16_lsb 16
1273#define xd_p_reg_dagc2_in_sat_cnt_31_24	0xA1CC
1274#define	reg_dagc2_in_sat_cnt_31_24_pos 0
1275#define	reg_dagc2_in_sat_cnt_31_24_len 8
1276#define	reg_dagc2_in_sat_cnt_31_24_lsb 24
1277#define xd_p_reg_dagc2_out_sat_cnt_7_0	0xA1CD
1278#define	reg_dagc2_out_sat_cnt_7_0_pos 0
1279#define	reg_dagc2_out_sat_cnt_7_0_len 8
1280#define	reg_dagc2_out_sat_cnt_7_0_lsb 0
1281#define xd_p_reg_dagc2_out_sat_cnt_15_8	0xA1CE
1282#define	reg_dagc2_out_sat_cnt_15_8_pos 0
1283#define	reg_dagc2_out_sat_cnt_15_8_len 8
1284#define	reg_dagc2_out_sat_cnt_15_8_lsb 8
1285#define xd_p_reg_dagc2_out_sat_cnt_23_16	0xA1CF
1286#define	reg_dagc2_out_sat_cnt_23_16_pos 0
1287#define	reg_dagc2_out_sat_cnt_23_16_len 8
1288#define	reg_dagc2_out_sat_cnt_23_16_lsb 16
1289#define xd_p_reg_dagc2_out_sat_cnt_31_24	0xA1D0
1290#define	reg_dagc2_out_sat_cnt_31_24_pos 0
1291#define	reg_dagc2_out_sat_cnt_31_24_len 8
1292#define	reg_dagc2_out_sat_cnt_31_24_lsb 24
1293#define xd_r_dagc2_multiplier_7_0	0xA1D6
1294#define	dagc2_multiplier_7_0_pos 0
1295#define	dagc2_multiplier_7_0_len 8
1296#define	dagc2_multiplier_7_0_lsb 0
1297#define xd_r_dagc2_multiplier_15_8	0xA1D7
1298#define	dagc2_multiplier_15_8_pos 0
1299#define	dagc2_multiplier_15_8_len 8
1300#define	dagc2_multiplier_15_8_lsb 8
1301#define xd_r_dagc2_right_shift_bits	0xA1D8
1302#define	dagc2_right_shift_bits_pos 0
1303#define	dagc2_right_shift_bits_len 4
1304#define	dagc2_right_shift_bits_lsb 0
1305#define xd_p_cfoe_NS_coeff1_7_0	0xA200
1306#define	cfoe_NS_coeff1_7_0_pos 0
1307#define	cfoe_NS_coeff1_7_0_len 8
1308#define	cfoe_NS_coeff1_7_0_lsb 0
1309#define xd_p_cfoe_NS_coeff1_15_8	0xA201
1310#define	cfoe_NS_coeff1_15_8_pos 0
1311#define	cfoe_NS_coeff1_15_8_len 8
1312#define	cfoe_NS_coeff1_15_8_lsb 8
1313#define xd_p_cfoe_NS_coeff1_23_16	0xA202
1314#define	cfoe_NS_coeff1_23_16_pos 0
1315#define	cfoe_NS_coeff1_23_16_len 8
1316#define	cfoe_NS_coeff1_23_16_lsb 16
1317#define xd_p_cfoe_NS_coeff1_25_24	0xA203
1318#define	cfoe_NS_coeff1_25_24_pos 0
1319#define	cfoe_NS_coeff1_25_24_len 2
1320#define	cfoe_NS_coeff1_25_24_lsb 24
1321#define xd_p_cfoe_NS_coeff2_5_0	0xA203
1322#define	cfoe_NS_coeff2_5_0_pos 2
1323#define	cfoe_NS_coeff2_5_0_len 6
1324#define	cfoe_NS_coeff2_5_0_lsb 0
1325#define xd_p_cfoe_NS_coeff2_13_6	0xA204
1326#define	cfoe_NS_coeff2_13_6_pos 0
1327#define	cfoe_NS_coeff2_13_6_len 8
1328#define	cfoe_NS_coeff2_13_6_lsb 6
1329#define xd_p_cfoe_NS_coeff2_21_14	0xA205
1330#define	cfoe_NS_coeff2_21_14_pos 0
1331#define	cfoe_NS_coeff2_21_14_len 8
1332#define	cfoe_NS_coeff2_21_14_lsb 14
1333#define xd_p_cfoe_NS_coeff2_24_22	0xA206
1334#define	cfoe_NS_coeff2_24_22_pos 0
1335#define	cfoe_NS_coeff2_24_22_len 3
1336#define	cfoe_NS_coeff2_24_22_lsb 22
1337#define xd_p_cfoe_lf_c1_4_0	0xA206
1338#define	cfoe_lf_c1_4_0_pos 3
1339#define	cfoe_lf_c1_4_0_len 5
1340#define	cfoe_lf_c1_4_0_lsb 0
1341#define xd_p_cfoe_lf_c1_12_5	0xA207
1342#define	cfoe_lf_c1_12_5_pos 0
1343#define	cfoe_lf_c1_12_5_len 8
1344#define	cfoe_lf_c1_12_5_lsb 5
1345#define xd_p_cfoe_lf_c1_20_13	0xA208
1346#define	cfoe_lf_c1_20_13_pos 0
1347#define	cfoe_lf_c1_20_13_len 8
1348#define	cfoe_lf_c1_20_13_lsb 13
1349#define xd_p_cfoe_lf_c1_25_21	0xA209
1350#define	cfoe_lf_c1_25_21_pos 0
1351#define	cfoe_lf_c1_25_21_len 5
1352#define	cfoe_lf_c1_25_21_lsb 21
1353#define xd_p_cfoe_lf_c2_2_0	0xA209
1354#define	cfoe_lf_c2_2_0_pos 5
1355#define	cfoe_lf_c2_2_0_len 3
1356#define	cfoe_lf_c2_2_0_lsb 0
1357#define xd_p_cfoe_lf_c2_10_3	0xA20A
1358#define	cfoe_lf_c2_10_3_pos 0
1359#define	cfoe_lf_c2_10_3_len 8
1360#define	cfoe_lf_c2_10_3_lsb 3
1361#define xd_p_cfoe_lf_c2_18_11	0xA20B
1362#define	cfoe_lf_c2_18_11_pos 0
1363#define	cfoe_lf_c2_18_11_len 8
1364#define	cfoe_lf_c2_18_11_lsb 11
1365#define xd_p_cfoe_lf_c2_25_19	0xA20C
1366#define	cfoe_lf_c2_25_19_pos 0
1367#define	cfoe_lf_c2_25_19_len 7
1368#define	cfoe_lf_c2_25_19_lsb 19
1369#define xd_p_cfoe_ifod_7_0	0xA20D
1370#define	cfoe_ifod_7_0_pos 0
1371#define	cfoe_ifod_7_0_len 8
1372#define	cfoe_ifod_7_0_lsb 0
1373#define xd_p_cfoe_ifod_10_8	0xA20E
1374#define	cfoe_ifod_10_8_pos 0
1375#define	cfoe_ifod_10_8_len 3
1376#define	cfoe_ifod_10_8_lsb 8
1377#define xd_p_cfoe_Divg_ctr_th	0xA20E
1378#define	cfoe_Divg_ctr_th_pos 4
1379#define	cfoe_Divg_ctr_th_len 4
1380#define	cfoe_Divg_ctr_th_lsb 0
1381#define xd_p_cfoe_FOT_divg_th	0xA20F
1382#define	cfoe_FOT_divg_th_pos 0
1383#define	cfoe_FOT_divg_th_len 8
1384#define	cfoe_FOT_divg_th_lsb 0
1385#define xd_p_cfoe_FOT_cnvg_th	0xA210
1386#define	cfoe_FOT_cnvg_th_pos 0
1387#define	cfoe_FOT_cnvg_th_len 8
1388#define	cfoe_FOT_cnvg_th_lsb 0
1389#define xd_p_reg_cfoe_offset_7_0	0xA211
1390#define	reg_cfoe_offset_7_0_pos 0
1391#define	reg_cfoe_offset_7_0_len 8
1392#define	reg_cfoe_offset_7_0_lsb 0
1393#define xd_p_reg_cfoe_offset_9_8	0xA212
1394#define	reg_cfoe_off…

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