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/drivers/crypto/hifn_795x.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 2800 lines | 2182 code | 455 blank | 163 comment | 234 complexity | 4fedb8f2c231bee5c77cc311a41d5cdf MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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  1. /*
  2. * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/moduleparam.h>
  22. #include <linux/mod_devicetable.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/slab.h>
  26. #include <linux/delay.h>
  27. #include <linux/mm.h>
  28. #include <linux/dma-mapping.h>
  29. #include <linux/scatterlist.h>
  30. #include <linux/highmem.h>
  31. #include <linux/crypto.h>
  32. #include <linux/hw_random.h>
  33. #include <linux/ktime.h>
  34. #include <crypto/algapi.h>
  35. #include <crypto/des.h>
  36. #include <asm/kmap_types.h>
  37. //#define HIFN_DEBUG
  38. #ifdef HIFN_DEBUG
  39. #define dprintk(f, a...) printk(f, ##a)
  40. #else
  41. #define dprintk(f, a...) do {} while (0)
  42. #endif
  43. static char hifn_pll_ref[sizeof("extNNN")] = "ext";
  44. module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
  45. MODULE_PARM_DESC(hifn_pll_ref,
  46. "PLL reference clock (pci[freq] or ext[freq], default ext)");
  47. static atomic_t hifn_dev_number;
  48. #define ACRYPTO_OP_DECRYPT 0
  49. #define ACRYPTO_OP_ENCRYPT 1
  50. #define ACRYPTO_OP_HMAC 2
  51. #define ACRYPTO_OP_RNG 3
  52. #define ACRYPTO_MODE_ECB 0
  53. #define ACRYPTO_MODE_CBC 1
  54. #define ACRYPTO_MODE_CFB 2
  55. #define ACRYPTO_MODE_OFB 3
  56. #define ACRYPTO_TYPE_AES_128 0
  57. #define ACRYPTO_TYPE_AES_192 1
  58. #define ACRYPTO_TYPE_AES_256 2
  59. #define ACRYPTO_TYPE_3DES 3
  60. #define ACRYPTO_TYPE_DES 4
  61. #define PCI_VENDOR_ID_HIFN 0x13A3
  62. #define PCI_DEVICE_ID_HIFN_7955 0x0020
  63. #define PCI_DEVICE_ID_HIFN_7956 0x001d
  64. /* I/O region sizes */
  65. #define HIFN_BAR0_SIZE 0x1000
  66. #define HIFN_BAR1_SIZE 0x2000
  67. #define HIFN_BAR2_SIZE 0x8000
  68. /* DMA registres */
  69. #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
  70. #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
  71. #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
  72. #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
  73. #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
  74. #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
  75. #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
  76. #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
  77. #define HIFN_CHIP_ID 0x98 /* Chip ID */
  78. /*
  79. * Processing Unit Registers (offset from BASEREG0)
  80. */
  81. #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
  82. #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
  83. #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
  84. #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
  85. #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
  86. #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
  87. #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
  88. #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
  89. #define HIFN_0_SPACESIZE 0x20 /* Register space size */
  90. /* Processing Unit Control Register (HIFN_0_PUCTRL) */
  91. #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
  92. #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
  93. #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
  94. #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
  95. #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
  96. /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
  97. #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
  98. #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
  99. #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
  100. #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
  101. #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
  102. #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
  103. #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
  104. #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
  105. #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
  106. #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
  107. /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
  108. #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
  109. #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
  110. #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
  111. #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
  112. #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
  113. #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
  114. #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
  115. #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
  116. #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
  117. #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
  118. #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
  119. #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
  120. #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
  121. #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
  122. #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
  123. #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
  124. #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
  125. #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
  126. #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
  127. #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
  128. #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
  129. #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
  130. #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
  131. /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
  132. #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
  133. #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
  134. #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
  135. #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
  136. #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
  137. #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
  138. #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
  139. #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
  140. #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
  141. #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
  142. /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
  143. #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
  144. #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
  145. #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
  146. #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
  147. #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
  148. #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
  149. #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
  150. #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
  151. #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
  152. #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
  153. #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
  154. #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
  155. #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
  156. #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
  157. #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
  158. #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
  159. #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
  160. /* FIFO Status Register (HIFN_0_FIFOSTAT) */
  161. #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
  162. #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
  163. /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
  164. #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
  165. /*
  166. * DMA Interface Registers (offset from BASEREG1)
  167. */
  168. #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
  169. #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
  170. #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
  171. #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
  172. #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
  173. #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
  174. #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
  175. #define HIFN_1_PLL 0x4c /* 795x: PLL config */
  176. #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
  177. #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
  178. #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
  179. #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
  180. #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
  181. #define HIFN_1_REVID 0x98 /* Revision ID */
  182. #define HIFN_1_UNLOCK_SECRET1 0xf4
  183. #define HIFN_1_UNLOCK_SECRET2 0xfc
  184. #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
  185. #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
  186. #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
  187. #define HIFN_1_PUB_OP 0x308 /* Public Operand */
  188. #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
  189. #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
  190. #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
  191. #define HIFN_1_RNG_DATA 0x318 /* RNG data */
  192. #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
  193. #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
  194. /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
  195. #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
  196. #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
  197. #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
  198. #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
  199. #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
  200. #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
  201. #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
  202. #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
  203. #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
  204. #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
  205. #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
  206. #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
  207. #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
  208. #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
  209. #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
  210. #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
  211. #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
  212. #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
  213. #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
  214. #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
  215. #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
  216. #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
  217. #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
  218. #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
  219. #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
  220. #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
  221. #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
  222. #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
  223. #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
  224. #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
  225. #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
  226. #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
  227. #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
  228. #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
  229. #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
  230. #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
  231. #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
  232. #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
  233. /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
  234. #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
  235. #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
  236. #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
  237. #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
  238. #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
  239. #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
  240. #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
  241. #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
  242. #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
  243. #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
  244. #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
  245. #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
  246. #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
  247. #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
  248. #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
  249. #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
  250. #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
  251. #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
  252. #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
  253. #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
  254. #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
  255. #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
  256. /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
  257. #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
  258. #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
  259. #define HIFN_DMACNFG_UNLOCK 0x00000800
  260. #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
  261. #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
  262. #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
  263. #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
  264. #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
  265. /* PLL configuration register */
  266. #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */
  267. #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */
  268. #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */
  269. #define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */
  270. #define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */
  271. #define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */
  272. #define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */
  273. #define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */
  274. #define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */
  275. #define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */
  276. #define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */
  277. #define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */
  278. #define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */
  279. #define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */
  280. #define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */
  281. #define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */
  282. #define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */
  283. #define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */
  284. /* Public key reset register (HIFN_1_PUB_RESET) */
  285. #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
  286. /* Public base address register (HIFN_1_PUB_BASE) */
  287. #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
  288. /* Public operand length register (HIFN_1_PUB_OPLEN) */
  289. #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
  290. #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
  291. #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
  292. #define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */
  293. #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
  294. #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
  295. /* Public operation register (HIFN_1_PUB_OP) */
  296. #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
  297. #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
  298. #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
  299. #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
  300. #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
  301. #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
  302. #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
  303. #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
  304. #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
  305. #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
  306. #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
  307. #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
  308. #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
  309. #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
  310. #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
  311. #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
  312. #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
  313. #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
  314. #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
  315. #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
  316. /* Public status register (HIFN_1_PUB_STATUS) */
  317. #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
  318. #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
  319. /* Public interrupt enable register (HIFN_1_PUB_IEN) */
  320. #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
  321. /* Random number generator config register (HIFN_1_RNG_CONFIG) */
  322. #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
  323. #define HIFN_NAMESIZE 32
  324. #define HIFN_MAX_RESULT_ORDER 5
  325. #define HIFN_D_CMD_RSIZE 24*1
  326. #define HIFN_D_SRC_RSIZE 80*1
  327. #define HIFN_D_DST_RSIZE 80*1
  328. #define HIFN_D_RES_RSIZE 24*1
  329. #define HIFN_D_DST_DALIGN 4
  330. #define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1)
  331. #define AES_MIN_KEY_SIZE 16
  332. #define AES_MAX_KEY_SIZE 32
  333. #define HIFN_DES_KEY_LENGTH 8
  334. #define HIFN_3DES_KEY_LENGTH 24
  335. #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
  336. #define HIFN_IV_LENGTH 8
  337. #define HIFN_AES_IV_LENGTH 16
  338. #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
  339. #define HIFN_MAC_KEY_LENGTH 64
  340. #define HIFN_MD5_LENGTH 16
  341. #define HIFN_SHA1_LENGTH 20
  342. #define HIFN_MAC_TRUNC_LENGTH 12
  343. #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
  344. #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
  345. #define HIFN_USED_RESULT 12
  346. struct hifn_desc
  347. {
  348. volatile __le32 l;
  349. volatile __le32 p;
  350. };
  351. struct hifn_dma {
  352. struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
  353. struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
  354. struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
  355. struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
  356. u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
  357. u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
  358. /*
  359. * Our current positions for insertion and removal from the descriptor
  360. * rings.
  361. */
  362. volatile int cmdi, srci, dsti, resi;
  363. volatile int cmdu, srcu, dstu, resu;
  364. int cmdk, srck, dstk, resk;
  365. };
  366. #define HIFN_FLAG_CMD_BUSY (1<<0)
  367. #define HIFN_FLAG_SRC_BUSY (1<<1)
  368. #define HIFN_FLAG_DST_BUSY (1<<2)
  369. #define HIFN_FLAG_RES_BUSY (1<<3)
  370. #define HIFN_FLAG_OLD_KEY (1<<4)
  371. #define HIFN_DEFAULT_ACTIVE_NUM 5
  372. struct hifn_device
  373. {
  374. char name[HIFN_NAMESIZE];
  375. int irq;
  376. struct pci_dev *pdev;
  377. void __iomem *bar[3];
  378. void *desc_virt;
  379. dma_addr_t desc_dma;
  380. u32 dmareg;
  381. void *sa[HIFN_D_RES_RSIZE];
  382. spinlock_t lock;
  383. u32 flags;
  384. int active, started;
  385. struct delayed_work work;
  386. unsigned long reset;
  387. unsigned long success;
  388. unsigned long prev_success;
  389. u8 snum;
  390. struct tasklet_struct tasklet;
  391. struct crypto_queue queue;
  392. struct list_head alg_list;
  393. unsigned int pk_clk_freq;
  394. #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
  395. unsigned int rng_wait_time;
  396. ktime_t rngtime;
  397. struct hwrng rng;
  398. #endif
  399. };
  400. #define HIFN_D_LENGTH 0x0000ffff
  401. #define HIFN_D_NOINVALID 0x01000000
  402. #define HIFN_D_MASKDONEIRQ 0x02000000
  403. #define HIFN_D_DESTOVER 0x04000000
  404. #define HIFN_D_OVER 0x08000000
  405. #define HIFN_D_LAST 0x20000000
  406. #define HIFN_D_JUMP 0x40000000
  407. #define HIFN_D_VALID 0x80000000
  408. struct hifn_base_command
  409. {
  410. volatile __le16 masks;
  411. volatile __le16 session_num;
  412. volatile __le16 total_source_count;
  413. volatile __le16 total_dest_count;
  414. };
  415. #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
  416. #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
  417. #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
  418. #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
  419. #define HIFN_BASE_CMD_DECODE 0x2000
  420. #define HIFN_BASE_CMD_SRCLEN_M 0xc000
  421. #define HIFN_BASE_CMD_SRCLEN_S 14
  422. #define HIFN_BASE_CMD_DSTLEN_M 0x3000
  423. #define HIFN_BASE_CMD_DSTLEN_S 12
  424. #define HIFN_BASE_CMD_LENMASK_HI 0x30000
  425. #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
  426. /*
  427. * Structure to help build up the command data structure.
  428. */
  429. struct hifn_crypt_command
  430. {
  431. volatile __le16 masks;
  432. volatile __le16 header_skip;
  433. volatile __le16 source_count;
  434. volatile __le16 reserved;
  435. };
  436. #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
  437. #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
  438. #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
  439. #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
  440. #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
  441. #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
  442. #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
  443. #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
  444. #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
  445. #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
  446. #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
  447. #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
  448. #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
  449. #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
  450. #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
  451. #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
  452. #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
  453. #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
  454. #define HIFN_CRYPT_CMD_SRCLEN_S 14
  455. /*
  456. * Structure to help build up the command data structure.
  457. */
  458. struct hifn_mac_command
  459. {
  460. volatile __le16 masks;
  461. volatile __le16 header_skip;
  462. volatile __le16 source_count;
  463. volatile __le16 reserved;
  464. };
  465. #define HIFN_MAC_CMD_ALG_MASK 0x0001
  466. #define HIFN_MAC_CMD_ALG_SHA1 0x0000
  467. #define HIFN_MAC_CMD_ALG_MD5 0x0001
  468. #define HIFN_MAC_CMD_MODE_MASK 0x000c
  469. #define HIFN_MAC_CMD_MODE_HMAC 0x0000
  470. #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
  471. #define HIFN_MAC_CMD_MODE_HASH 0x0008
  472. #define HIFN_MAC_CMD_MODE_FULL 0x0004
  473. #define HIFN_MAC_CMD_TRUNC 0x0010
  474. #define HIFN_MAC_CMD_RESULT 0x0020
  475. #define HIFN_MAC_CMD_APPEND 0x0040
  476. #define HIFN_MAC_CMD_SRCLEN_M 0xc000
  477. #define HIFN_MAC_CMD_SRCLEN_S 14
  478. /*
  479. * MAC POS IPsec initiates authentication after encryption on encodes
  480. * and before decryption on decodes.
  481. */
  482. #define HIFN_MAC_CMD_POS_IPSEC 0x0200
  483. #define HIFN_MAC_CMD_NEW_KEY 0x0800
  484. struct hifn_comp_command
  485. {
  486. volatile __le16 masks;
  487. volatile __le16 header_skip;
  488. volatile __le16 source_count;
  489. volatile __le16 reserved;
  490. };
  491. #define HIFN_COMP_CMD_SRCLEN_M 0xc000
  492. #define HIFN_COMP_CMD_SRCLEN_S 14
  493. #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
  494. #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
  495. #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
  496. #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
  497. #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
  498. #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
  499. #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
  500. #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
  501. struct hifn_base_result
  502. {
  503. volatile __le16 flags;
  504. volatile __le16 session;
  505. volatile __le16 src_cnt; /* 15:0 of source count */
  506. volatile __le16 dst_cnt; /* 15:0 of dest count */
  507. };
  508. #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
  509. #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
  510. #define HIFN_BASE_RES_SRCLEN_S 14
  511. #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
  512. #define HIFN_BASE_RES_DSTLEN_S 12
  513. struct hifn_comp_result
  514. {
  515. volatile __le16 flags;
  516. volatile __le16 crc;
  517. };
  518. #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
  519. #define HIFN_COMP_RES_LCB_S 8
  520. #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
  521. #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
  522. #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
  523. struct hifn_mac_result
  524. {
  525. volatile __le16 flags;
  526. volatile __le16 reserved;
  527. /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
  528. };
  529. #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
  530. #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
  531. struct hifn_crypt_result
  532. {
  533. volatile __le16 flags;
  534. volatile __le16 reserved;
  535. };
  536. #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
  537. #ifndef HIFN_POLL_FREQUENCY
  538. #define HIFN_POLL_FREQUENCY 0x1
  539. #endif
  540. #ifndef HIFN_POLL_SCALAR
  541. #define HIFN_POLL_SCALAR 0x0
  542. #endif
  543. #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
  544. #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
  545. struct hifn_crypto_alg
  546. {
  547. struct list_head entry;
  548. struct crypto_alg alg;
  549. struct hifn_device *dev;
  550. };
  551. #define ASYNC_SCATTERLIST_CACHE 16
  552. #define ASYNC_FLAGS_MISALIGNED (1<<0)
  553. struct hifn_cipher_walk
  554. {
  555. struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
  556. u32 flags;
  557. int num;
  558. };
  559. struct hifn_context
  560. {
  561. u8 key[HIFN_MAX_CRYPT_KEY_LENGTH];
  562. struct hifn_device *dev;
  563. unsigned int keysize;
  564. };
  565. struct hifn_request_context
  566. {
  567. u8 *iv;
  568. unsigned int ivsize;
  569. u8 op, type, mode, unused;
  570. struct hifn_cipher_walk walk;
  571. };
  572. #define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg)
  573. static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
  574. {
  575. u32 ret;
  576. ret = readl(dev->bar[0] + reg);
  577. return ret;
  578. }
  579. static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
  580. {
  581. u32 ret;
  582. ret = readl(dev->bar[1] + reg);
  583. return ret;
  584. }
  585. static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
  586. {
  587. writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
  588. }
  589. static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
  590. {
  591. writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
  592. }
  593. static void hifn_wait_puc(struct hifn_device *dev)
  594. {
  595. int i;
  596. u32 ret;
  597. for (i=10000; i > 0; --i) {
  598. ret = hifn_read_0(dev, HIFN_0_PUCTRL);
  599. if (!(ret & HIFN_PUCTRL_RESET))
  600. break;
  601. udelay(1);
  602. }
  603. if (!i)
  604. dprintk("%s: Failed to reset PUC unit.\n", dev->name);
  605. }
  606. static void hifn_reset_puc(struct hifn_device *dev)
  607. {
  608. hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
  609. hifn_wait_puc(dev);
  610. }
  611. static void hifn_stop_device(struct hifn_device *dev)
  612. {
  613. hifn_write_1(dev, HIFN_1_DMA_CSR,
  614. HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
  615. HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
  616. hifn_write_0(dev, HIFN_0_PUIER, 0);
  617. hifn_write_1(dev, HIFN_1_DMA_IER, 0);
  618. }
  619. static void hifn_reset_dma(struct hifn_device *dev, int full)
  620. {
  621. hifn_stop_device(dev);
  622. /*
  623. * Setting poll frequency and others to 0.
  624. */
  625. hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
  626. HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
  627. mdelay(1);
  628. /*
  629. * Reset DMA.
  630. */
  631. if (full) {
  632. hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
  633. mdelay(1);
  634. } else {
  635. hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
  636. HIFN_DMACNFG_MSTRESET);
  637. hifn_reset_puc(dev);
  638. }
  639. hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
  640. HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
  641. hifn_reset_puc(dev);
  642. }
  643. static u32 hifn_next_signature(u_int32_t a, u_int cnt)
  644. {
  645. int i;
  646. u32 v;
  647. for (i = 0; i < cnt; i++) {
  648. /* get the parity */
  649. v = a & 0x80080125;
  650. v ^= v >> 16;
  651. v ^= v >> 8;
  652. v ^= v >> 4;
  653. v ^= v >> 2;
  654. v ^= v >> 1;
  655. a = (v & 1) ^ (a << 1);
  656. }
  657. return a;
  658. }
  659. static struct pci2id {
  660. u_short pci_vendor;
  661. u_short pci_prod;
  662. char card_id[13];
  663. } pci2id[] = {
  664. {
  665. PCI_VENDOR_ID_HIFN,
  666. PCI_DEVICE_ID_HIFN_7955,
  667. { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  668. 0x00, 0x00, 0x00, 0x00, 0x00 }
  669. },
  670. {
  671. PCI_VENDOR_ID_HIFN,
  672. PCI_DEVICE_ID_HIFN_7956,
  673. { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  674. 0x00, 0x00, 0x00, 0x00, 0x00 }
  675. }
  676. };
  677. #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
  678. static int hifn_rng_data_present(struct hwrng *rng, int wait)
  679. {
  680. struct hifn_device *dev = (struct hifn_device *)rng->priv;
  681. s64 nsec;
  682. nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
  683. nsec -= dev->rng_wait_time;
  684. if (nsec <= 0)
  685. return 1;
  686. if (!wait)
  687. return 0;
  688. ndelay(nsec);
  689. return 1;
  690. }
  691. static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
  692. {
  693. struct hifn_device *dev = (struct hifn_device *)rng->priv;
  694. *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
  695. dev->rngtime = ktime_get();
  696. return 4;
  697. }
  698. static int hifn_register_rng(struct hifn_device *dev)
  699. {
  700. /*
  701. * We must wait at least 256 Pk_clk cycles between two reads of the rng.
  702. */
  703. dev->rng_wait_time = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) *
  704. 256;
  705. dev->rng.name = dev->name;
  706. dev->rng.data_present = hifn_rng_data_present,
  707. dev->rng.data_read = hifn_rng_data_read,
  708. dev->rng.priv = (unsigned long)dev;
  709. return hwrng_register(&dev->rng);
  710. }
  711. static void hifn_unregister_rng(struct hifn_device *dev)
  712. {
  713. hwrng_unregister(&dev->rng);
  714. }
  715. #else
  716. #define hifn_register_rng(dev) 0
  717. #define hifn_unregister_rng(dev)
  718. #endif
  719. static int hifn_init_pubrng(struct hifn_device *dev)
  720. {
  721. int i;
  722. hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
  723. HIFN_PUBRST_RESET);
  724. for (i=100; i > 0; --i) {
  725. mdelay(1);
  726. if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
  727. break;
  728. }
  729. if (!i)
  730. dprintk("Chip %s: Failed to initialise public key engine.\n",
  731. dev->name);
  732. else {
  733. hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
  734. dev->dmareg |= HIFN_DMAIER_PUBDONE;
  735. hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
  736. dprintk("Chip %s: Public key engine has been successfully "
  737. "initialised.\n", dev->name);
  738. }
  739. /*
  740. * Enable RNG engine.
  741. */
  742. hifn_write_1(dev, HIFN_1_RNG_CONFIG,
  743. hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
  744. dprintk("Chip %s: RNG engine has been successfully initialised.\n",
  745. dev->name);
  746. #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
  747. /* First value must be discarded */
  748. hifn_read_1(dev, HIFN_1_RNG_DATA);
  749. dev->rngtime = ktime_get();
  750. #endif
  751. return 0;
  752. }
  753. static int hifn_enable_crypto(struct hifn_device *dev)
  754. {
  755. u32 dmacfg, addr;
  756. char *offtbl = NULL;
  757. int i;
  758. for (i = 0; i < ARRAY_SIZE(pci2id); i++) {
  759. if (pci2id[i].pci_vendor == dev->pdev->vendor &&
  760. pci2id[i].pci_prod == dev->pdev->device) {
  761. offtbl = pci2id[i].card_id;
  762. break;
  763. }
  764. }
  765. if (offtbl == NULL) {
  766. dprintk("Chip %s: Unknown card!\n", dev->name);
  767. return -ENODEV;
  768. }
  769. dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
  770. hifn_write_1(dev, HIFN_1_DMA_CNFG,
  771. HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
  772. HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
  773. mdelay(1);
  774. addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
  775. mdelay(1);
  776. hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
  777. mdelay(1);
  778. for (i=0; i<12; ++i) {
  779. addr = hifn_next_signature(addr, offtbl[i] + 0x101);
  780. hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
  781. mdelay(1);
  782. }
  783. hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
  784. dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev));
  785. return 0;
  786. }
  787. static void hifn_init_dma(struct hifn_device *dev)
  788. {
  789. struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
  790. u32 dptr = dev->desc_dma;
  791. int i;
  792. for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
  793. dma->cmdr[i].p = __cpu_to_le32(dptr +
  794. offsetof(struct hifn_dma, command_bufs[i][0]));
  795. for (i=0; i<HIFN_D_RES_RSIZE; ++i)
  796. dma->resr[i].p = __cpu_to_le32(dptr +
  797. offsetof(struct hifn_dma, result_bufs[i][0]));
  798. /*
  799. * Setup LAST descriptors.
  800. */
  801. dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
  802. offsetof(struct hifn_dma, cmdr[0]));
  803. dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
  804. offsetof(struct hifn_dma, srcr[0]));
  805. dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
  806. offsetof(struct hifn_dma, dstr[0]));
  807. dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
  808. offsetof(struct hifn_dma, resr[0]));
  809. dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
  810. dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
  811. dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
  812. }
  813. /*
  814. * Initialize the PLL. We need to know the frequency of the reference clock
  815. * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
  816. * allows us to operate without the risk of overclocking the chip. If it
  817. * actually uses 33MHz, the chip will operate at half the speed, this can be
  818. * overriden by specifying the frequency as module parameter (pci33).
  819. *
  820. * Unfortunately the PCI clock is not very suitable since the HIFN needs a
  821. * stable clock and the PCI clock frequency may vary, so the default is the
  822. * external clock. There is no way to find out its frequency, we default to
  823. * 66MHz since according to Mike Ham of HiFn, almost every board in existence
  824. * has an external crystal populated at 66MHz.
  825. */
  826. static void hifn_init_pll(struct hifn_device *dev)
  827. {
  828. unsigned int freq, m;
  829. u32 pllcfg;
  830. pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
  831. if (strncmp(hifn_pll_ref, "ext", 3) == 0)
  832. pllcfg |= HIFN_PLL_REF_CLK_PLL;
  833. else
  834. pllcfg |= HIFN_PLL_REF_CLK_HBI;
  835. if (hifn_pll_ref[3] != '\0')
  836. freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
  837. else {
  838. freq = 66;
  839. printk(KERN_INFO "hifn795x: assuming %uMHz clock speed, "
  840. "override with hifn_pll_ref=%.3s<frequency>\n",
  841. freq, hifn_pll_ref);
  842. }
  843. m = HIFN_PLL_FCK_MAX / freq;
  844. pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
  845. if (m <= 8)
  846. pllcfg |= HIFN_PLL_IS_1_8;
  847. else
  848. pllcfg |= HIFN_PLL_IS_9_12;
  849. /* Select clock source and enable clock bypass */
  850. hifn_write_1(dev, HIFN_1_PLL, pllcfg |
  851. HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
  852. /* Let the chip lock to the input clock */
  853. mdelay(10);
  854. /* Disable clock bypass */
  855. hifn_write_1(dev, HIFN_1_PLL, pllcfg |
  856. HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
  857. /* Switch the engines to the PLL */
  858. hifn_write_1(dev, HIFN_1_PLL, pllcfg |
  859. HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
  860. /*
  861. * The Fpk_clk runs at half the total speed. Its frequency is needed to
  862. * calculate the minimum time between two reads of the rng. Since 33MHz
  863. * is actually 33.333... we overestimate the frequency here, resulting
  864. * in slightly larger intervals.
  865. */
  866. dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
  867. }
  868. static void hifn_init_registers(struct hifn_device *dev)
  869. {
  870. u32 dptr = dev->desc_dma;
  871. /* Initialization magic... */
  872. hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
  873. hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
  874. hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
  875. /* write all 4 ring address registers */
  876. hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
  877. offsetof(struct hifn_dma, cmdr[0]));
  878. hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
  879. offsetof(struct hifn_dma, srcr[0]));
  880. hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
  881. offsetof(struct hifn_dma, dstr[0]));
  882. hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
  883. offsetof(struct hifn_dma, resr[0]));
  884. mdelay(2);
  885. #if 0
  886. hifn_write_1(dev, HIFN_1_DMA_CSR,
  887. HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
  888. HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
  889. HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
  890. HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
  891. HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
  892. HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
  893. HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
  894. HIFN_DMACSR_S_WAIT |
  895. HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
  896. HIFN_DMACSR_C_WAIT |
  897. HIFN_DMACSR_ENGINE |
  898. HIFN_DMACSR_PUBDONE);
  899. #else
  900. hifn_write_1(dev, HIFN_1_DMA_CSR,
  901. HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
  902. HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
  903. HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
  904. HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
  905. HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
  906. HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
  907. HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
  908. HIFN_DMACSR_S_WAIT |
  909. HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
  910. HIFN_DMACSR_C_WAIT |
  911. HIFN_DMACSR_ENGINE |
  912. HIFN_DMACSR_PUBDONE);
  913. #endif
  914. hifn_read_1(dev, HIFN_1_DMA_CSR);
  915. dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
  916. HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
  917. HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
  918. HIFN_DMAIER_ENGINE;
  919. dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
  920. hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
  921. hifn_read_1(dev, HIFN_1_DMA_IER);
  922. #if 0
  923. hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
  924. HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
  925. HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
  926. HIFN_PUCNFG_DRAM);
  927. #else
  928. hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
  929. #endif
  930. hifn_init_pll(dev);
  931. hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
  932. hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
  933. HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
  934. ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
  935. ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
  936. }
  937. static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
  938. unsigned dlen, unsigned slen, u16 mask, u8 snum)
  939. {
  940. struct hifn_base_command *base_cmd;
  941. u8 *buf_pos = buf;
  942. base_cmd = (struct hifn_base_command *)buf_pos;
  943. base_cmd->masks = __cpu_to_le16(mask);
  944. base_cmd->total_source_count =
  945. __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
  946. base_cmd->total_dest_count =
  947. __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
  948. dlen >>= 16;
  949. slen >>= 16;
  950. base_cmd->session_num = __cpu_to_le16(snum |
  951. ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
  952. ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
  953. return sizeof(struct hifn_base_command);
  954. }
  955. static int hifn_setup_crypto_command(struct hifn_device *dev,
  956. u8 *buf, unsigned dlen, unsigned slen,
  957. u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
  958. {
  959. struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
  960. struct hifn_crypt_command *cry_cmd;
  961. u8 *buf_pos = buf;
  962. u16 cmd_len;
  963. cry_cmd = (struct hifn_crypt_command *)buf_pos;
  964. cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
  965. dlen >>= 16;
  966. cry_cmd->masks = __cpu_to_le16(mode |
  967. ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
  968. HIFN_CRYPT_CMD_SRCLEN_M));
  969. cry_cmd->header_skip = 0;
  970. cry_cmd->reserved = 0;
  971. buf_pos += sizeof(struct hifn_crypt_command);
  972. dma->cmdu++;
  973. if (dma->cmdu > 1) {
  974. dev->dmareg |= HIFN_DMAIER_C_WAIT;
  975. hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
  976. }
  977. if (keylen) {
  978. memcpy(buf_pos, key, keylen);
  979. buf_pos += keylen;
  980. }
  981. if (ivsize) {
  982. memcpy(buf_pos, iv, ivsize);
  983. buf_pos += ivsize;
  984. }
  985. cmd_len = buf_pos - buf;
  986. return cmd_len;
  987. }
  988. static int hifn_setup_cmd_desc(struct hifn_device *dev,
  989. struct hifn_context *ctx, struct hifn_request_context *rctx,
  990. void *priv, unsigned int nbytes)
  991. {
  992. struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
  993. int cmd_len, sa_idx;
  994. u8 *buf, *buf_pos;
  995. u16 mask;
  996. sa_idx = dma->cmdi;
  997. buf_pos = buf = dma->command_bufs[dma->cmdi];
  998. mask = 0;
  999. switch (rctx->op) {
  1000. case ACRYPTO_OP_DECRYPT:
  1001. mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
  1002. break;
  1003. case ACRYPTO_OP_ENCRYPT:
  1004. mask = HIFN_BASE_CMD_CRYPT;
  1005. break;
  1006. case ACRYPTO_OP_HMAC:
  1007. mask = HIFN_BASE_CMD_MAC;
  1008. break;
  1009. default:
  1010. goto err_out;
  1011. }
  1012. buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
  1013. nbytes, mask, dev->snum);
  1014. if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) {
  1015. u16 md = 0;
  1016. if (ctx->keysize)
  1017. md |= HIFN_CRYPT_CMD_NEW_KEY;
  1018. if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB)
  1019. md |= HIFN_CRYPT_CMD_NEW_IV;
  1020. switch (rctx->mode) {
  1021. case ACRYPTO_MODE_ECB:
  1022. md |= HIFN_CRYPT_CMD_MODE_ECB;
  1023. break;
  1024. case ACRYPTO_MODE_CBC:
  1025. md |= HIFN_CRYPT_CMD_MODE_CBC;
  1026. break;
  1027. case ACRYPTO_MODE_CFB:
  1028. md |= HIFN_CRYPT_CMD_MODE_CFB;
  1029. break;
  1030. case ACRYPTO_MODE_OFB:
  1031. md |= HIFN_CRYPT_CMD_MODE_OFB;
  1032. break;
  1033. default:
  1034. goto err_out;
  1035. }
  1036. switch (rctx->type) {
  1037. case ACRYPTO_TYPE_AES_128:
  1038. if (ctx->keysize != 16)
  1039. goto err_out;
  1040. md |= HIFN_CRYPT_CMD_KSZ_128 |
  1041. HIFN_CRYPT_CMD_ALG_AES;
  1042. break;
  1043. case ACRYPTO_TYPE_AES_192:
  1044. if (ctx->keysize != 24)
  1045. goto err_out;
  1046. md |= HIFN_CRYPT_CMD_KSZ_192 |
  1047. HIFN_CRYPT_CMD_ALG_AES;
  1048. break;
  1049. case ACRYPTO_TYPE_AES_256:
  1050. if (ctx->keysize != 32)
  1051. goto err_out;
  1052. md |= HIFN_CRYPT_CMD_KSZ_256 |
  1053. HIFN_CRYPT_CMD_ALG_AES;
  1054. break;
  1055. case ACRYPTO_TYPE_3DES:
  1056. if (ctx->keysize != 24)
  1057. goto err_out;
  1058. md |= HIFN_CRYPT_CMD_ALG_3DES;
  1059. break;
  1060. case ACRYPTO_TYPE_DES:
  1061. if (ctx->keysize != 8)
  1062. goto err_out;
  1063. md |= HIFN_CRYPT_CMD_ALG_DES;
  1064. break;
  1065. default:
  1066. goto err_out;
  1067. }
  1068. buf_pos += hifn_setup_crypto_command(dev, buf_pos,
  1069. nbytes, nbytes, ctx->key, ctx->keysize,
  1070. rctx->iv, rctx->ivsize, md);
  1071. }
  1072. dev->sa[sa_idx] = priv;
  1073. dev->started++;
  1074. cmd_len = buf_pos - buf;
  1075. dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
  1076. HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
  1077. if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
  1078. dma->cmdr[dma->cmdi].l = __cpu_to_le32(
  1079. HIFN_D_VALID | HIFN_D_LAST |
  1080. HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
  1081. dma->cmdi = 0;
  1082. } else
  1083. dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
  1084. if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
  1085. hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
  1086. dev->flags |= HIFN_FLAG_CMD_BUSY;
  1087. }
  1088. return 0;
  1089. err_out:
  1090. return -EINVAL;
  1091. }
  1092. static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
  1093. unsigned int offset, unsigned int size, int last)
  1094. {
  1095. struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
  1096. int idx;
  1097. dma_addr_t addr;
  1098. addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
  1099. idx = dma->srci;
  1100. dma->srcr[idx].p = __cpu_to_le32(addr);
  1101. dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
  1102. HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
  1103. if (++idx == HIFN_D_SRC_RSIZE) {
  1104. dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
  1105. HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
  1106. (last ? HIFN_D_LAST : 0));
  1107. idx = 0;
  1108. }
  1109. dma->srci = idx;
  1110. dma->srcu++;
  1111. if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
  1112. hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
  1113. dev->flags |= HIFN_FLAG_SRC_BUSY;
  1114. }
  1115. return size;
  1116. }
  1117. static void hifn_setup_res_desc(struct hifn_device *dev)
  1118. {
  1119. struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
  1120. dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
  1121. HIFN_D_VALID | HIFN_D_LAST);
  1122. /*
  1123. * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
  1124. * HIFN_D_LAST);
  1125. */
  1126. if (++dma->resi == HIFN_D_RES_RSIZE) {
  1127. dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
  1128. HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
  1129. dma->resi = 0;
  1130. }
  1131. dma->resu++;
  1132. if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
  1133. hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
  1134. dev->flags |= HIFN_FLAG_RES_BUSY;
  1135. }
  1136. }
  1137. static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
  1138. unsigned offset, unsigned size, int last)
  1139. {
  1140. struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
  1141. int idx;
  1142. dma_addr_t addr;
  1143. addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
  1144. idx = dma->dsti;
  1145. dma->dstr[idx].p = __cpu_to_le32(addr);
  1146. dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
  1147. HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
  1148. if (++idx == HIFN_D_DST_RSIZE) {
  1149. dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
  1150. HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
  1151. (last ? HIFN_D_LAST : 0));
  1152. idx = 0;
  1153. }
  1154. dma->dsti = idx;
  1155. dma->dstu++;
  1156. if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
  1157. hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
  1158. dev->flags |= HIFN_FLAG_DST_BUSY;
  1159. }
  1160. }
  1161. static int hifn_setup_dma(struct hifn_device *dev,
  1162. struct hifn_context *ctx, struct hifn_request_context *rctx,
  1163. struct scatterlist *src, struct scatterlist *dst,
  1164. unsigned int nbytes, void *priv)
  1165. {
  1166. struct scatterlist *t;
  1167. struct page *spage, *dpage;
  1168. unsigned int soff, doff;
  1169. unsigned int n, len;
  1170. n = nbytes;
  1171. while (n) {
  1172. spage = sg_page(src);
  1173. soff = src->offset;
  1174. len = min(src->length, n);
  1175. hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);
  1176. src++;
  1177. n -= len;
  1178. }
  1179. t = &rctx->walk.cache[0];
  1180. n = nbytes;
  1181. while (n) {
  1182. if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
  1183. BUG_ON(!sg_page(t));
  1184. dpage = sg_page(t);
  1185. doff = 0;
  1186. len = t->length;
  1187. } else {
  1188. BUG_ON(!sg_page(dst));
  1189. dpage = sg_page(dst);
  1190. doff = dst->offset;
  1191. len = dst->length;
  1192. }
  1193. len = min(len, n);
  1194. hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);
  1195. dst++;
  1196. t++;
  1197. n -= len;
  1198. }
  1199. hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes);
  1200. hifn_setup_res_desc(dev);
  1201. return 0;
  1202. }
  1203. static int hifn_cipher_walk_init(struct hifn_cipher_walk *w,
  1204. int num, gfp_t gfp_flags)
  1205. {
  1206. int i;
  1207. num = min(ASYNC_SCATTERLIST_CACHE, num);
  1208. sg_init_table(w->cache, num);
  1209. w->num = 0;
  1210. for (i=0; i<num; ++i) {
  1211. struct page *page = alloc_page(gfp_flags);
  1212. struct scatterlist *s;
  1213. if (!page)
  1214. break;
  1215. s = &w->cache[i];
  1216. sg_set_page(s, page, PAGE_SIZE, 0);
  1217. w->num++;
  1218. }
  1219. return i;
  1220. }
  1221. static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w)
  1222. {
  1223. int i;
  1224. for (i=0; i<w->num; ++i) {
  1225. struct scatterlist *s = &w->cache[i];
  1226. __free_page(sg_page(s));
  1227. s->length = 0;
  1228. }
  1229. w->num = 0;
  1230. }
  1231. static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst,
  1232. unsigned int size, unsigned int *nbytesp)
  1233. {
  1234. unsigned int copy, drest = *drestp, nbytes = *nbytesp;
  1235. int idx = 0;
  1236. if (drest < size || size > nbytes)
  1237. return -EINVAL;
  1238. while (size) {
  1239. copy = min3(drest, size, dst->length);
  1240. size -= copy;
  1241. drest -= copy;
  1242. nbytes -= copy;
  1243. dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
  1244. __func__, copy, size, drest, nbytes);
  1245. dst++;
  1246. idx++;
  1247. }
  1248. *nbytesp = nbytes;
  1249. *drestp = drest;
  1250. return idx;
  1251. }
  1252. static int hifn_cipher_walk(struct ablkcipher_request *req,
  1253. struct hifn_cipher_walk *w)
  1254. {
  1255. struct scatterlist *dst, *t;
  1256. unsigned int nbytes = req->nbytes, offset, copy, diff;
  1257. int idx, tidx, err;
  1258. tidx = idx = 0;
  1259. offset = 0;
  1260. while (nbytes) {
  1261. if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
  1262. return -EINVAL;
  1263. dst = &req->dst[idx];
  1264. dprintk("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
  1265. __func__, dst->length, dst->offset, offset, nbytes);
  1266. if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
  1267. !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
  1268. offset) {
  1269. unsigned slen = min(dst->length - offset, nbytes);
  1270. unsigned dlen = PAGE_SIZE;
  1271. t = &w->cache[idx];
  1272. err = ablkcipher_add(&dlen, dst, slen, &nbytes);
  1273. if (err < 0)
  1274. return err;
  1275. idx += err;
  1276. copy = slen & ~(HIFN_D_DST_DALIGN - 1);
  1277. diff = slen & (HIFN_D_DST_DALIGN - 1);
  1278. if (dlen < nbytes) {
  1279. /*
  1280. * Destination page does not have enough space
  1281. * to put there additional blocksized chunk,
  1282. * so we mark that page as containing only
  1283. * blocksize aligned chunks:
  1284. * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
  1285. * and increase number of bytes to be processed
  1286. * in next chunk:
  1287. * nbytes += diff;
  1288. */
  1289. nbytes += diff;
  1290. /*
  1291. * Temporary of course...
  1292. * Kick author if you will catch this one.
  1293. */
  1294. printk(KERN_ERR "%s: dlen: %u, nbytes: %u,"
  1295. "slen: %u, offset: %u.\n",
  1296. __func__, dlen, nbytes, slen, offset);
  1297. printk(KERN_ERR "%s: please contact author to fix this "
  1298. "issue, generally you should not catch "
  1299. "this path under any condition but who "
  1300. "knows how did you use crypto code.\n"
  1301. "Thank you.\n", __func__);
  1302. BUG();
  1303. } else {
  1304. copy += diff + nbytes;
  1305. dst = &req->dst[idx];
  1306. err = ablkcipher_add(&dlen, dst, nbytes, &nbytes);
  1307. if (err < 0)
  1308. return err;
  1309. idx += err;
  1310. }
  1311. t->length = copy;
  1312. t->offset = offset;
  1313. } else {
  1314. nbytes -= min(dst->length, nbytes);
  1315. idx++;
  1316. }
  1317. tidx++;
  1318. }
  1319. return tidx;
  1320. }
  1321. static int hifn_setup_session(struct ablkcipher_request *req)
  1322. {
  1323. struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
  1324. struct hifn_request_context *rctx = ablkcipher_request_ctx(req);
  1325. struct hifn_device *dev = ctx->dev;
  1326. unsigned long dlen, flags;
  1327. unsigned int nbytes = req->nbytes, idx = 0;
  1328. int err = -EINVAL, sg_num;
  1329. struct scatterlist *dst;
  1330. if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB)
  1331. goto err_out_exit;
  1332. rctx->walk.flags = 0;
  1333. while (nbytes) {
  1334. dst = &req->dst[idx];
  1335. dlen = min(dst->length, nbytes);
  1336. if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
  1337. !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
  1338. rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
  1339. nbytes -= dlen;
  1340. idx++;
  1341. }
  1342. if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
  1343. err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC);
  1344. if (err < 0)
  1345. return err;
  1346. }
  1347. sg_num = hifn_cipher_walk(req, &rctx->walk);
  1348. if (sg_num < 0) {
  1349. err = sg_num;
  1350. goto err_out_exit;
  1351. }
  1352. spin_lock_irqsave(&dev->lock, flags);
  1353. if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
  1354. err = -EAGAIN;
  1355. goto err_out;
  1356. }
  1357. err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req);
  1358. if (err)
  1359. goto err_out;
  1360. dev->snum++;
  1361. dev->active = HIFN_DEFAULT_ACTIVE_NUM;
  1362. spin_unlock_irqrestore(&dev->lock, flags);
  1363. return 0;
  1364. err_out:
  1365. spin_unlock_irqrestore(&dev->lock, flags);
  1366. err_out_exit:
  1367. if (err) {
  1368. printk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
  1369. "type: %u, err: %d.\n",
  1370. dev->name, rctx->iv, rctx->ivsize,
  1371. ctx->key, ctx->keysize,
  1372. rctx->mode, rctx->op, rctx->type, err);
  1373. }
  1374. return err;
  1375. }
  1376. static int hifn_test(struct hifn_device *dev, int encdec, u8 snum)
  1377. {
  1378. int n, err;
  1379. u8 src[16];
  1380. struct hifn_context ctx;
  1381. struct hifn_request_context rctx;
  1382. u8 fips_aes_ecb_from_zero[16] = {
  1383. 0x66, 0xE9, 0x4B, 0xD4,
  1384. 0x

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